Method for manufacturing array substrate and array substrate

Abstract

The application provides a preparation method of an array substrate and the array substrate. The preparation method comprises the following steps: providing a substrate; forming a metal oxide semiconductor layer, a hydrogen blocking layer and a hydrogen-containing layer on the substrate; wherein the hydrogen blocking layer is located between the metal oxide semiconductor layer and the hydrogen-containing layer; the step of forming the hydrogen blocking layer comprises the following steps: forming a metal layer; oxidizing part of the metal layer and reserving the rest of the metal layer; wherein the oxidized metal layer forms the hydrogen blocking layer, and the reserved metal layer corresponds to the metal oxide semiconductor layer and respectively forms a gate layer and an active layer of a metal oxide thin film transistor. The hydrogen blocking layer is used for blocking hydrogen in the hydrogen-containing layer from diffusing into the active layer of the MO thin film transistor. Therefore, the preparation method of the array substrate and the array substrate provided by the application can improve the reliability of the metal oxide thin film transistor, thereby improving the reliability of the array substrate.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display panels, and in particular to a preparation method of an array substrate and the array substrate. BACKGROUND

[0002] In a display panel, a low temperature polycrystalline oxide (LTPO) technology can be used to manufacture a pixel driving circuit in a driving backplane. The LTPO technology is to use a low temperature polycrystalline (LTPS) thin film transistor (TFT) and a metal oxide (MO) thin film transistor as functional tubes in the pixel driving circuit at the same time. The LTPO combines the advantages of the two types of transistors, which helps the display panel to improve resolution, reduce power consumption, and the like.

[0003] In the related art, an array substrate can include a low temperature polycrystalline silicon thin film transistor and a metal oxide thin film transistor. The low temperature polycrystalline silicon thin film transistor can be used as a driving TFT, which has a high mobility, can reduce a driving voltage, and can achieve a high refresh rate and a high resolution. The metal oxide thin film transistor can be used as a switching TFT, which has a small leakage current, can keep a display panel at a low frame rate to have a good display effect, and can reduce power consumption of the display panel.

[0004] However, the metal oxide thin film transistor has low reliability, which leads to low reliability of the array substrate. SUMMARY

[0005] In view of the above problems, the embodiments of the present application provide a preparation method of an array substrate and the array substrate, which can improve the reliability of the metal oxide thin film transistor, and thus improve the reliability of the array substrate.

[0006] To achieve the above object, the embodiments of the present application provide the following technical solutions.

[0007] A first aspect of the embodiments of the present application provides a preparation method of an array substrate, comprising:

[0008] providing a substrate;

[0009] forming a metal oxide semiconductor layer, a hydrogen blocking layer, and a hydrogen containing layer on the substrate; the hydrogen blocking layer is located between the metal oxide semiconductor layer and the hydrogen containing layer;

[0010] The step of forming the hydrogen blocking layer comprises:

[0011] forming a metal layer;

[0012] oxidizing part of the metal layer, and leaving the rest of the metal layer; wherein the metal layer subjected to the oxidation forms a hydrogen barrier layer, and at least part of the metal layer left forms a gate layer and an active layer of a metal-oxide thin film transistor, respectively, and the projections of the gate layer and the active layer on the substrate at least partially overlap with the projection of the metal-oxide semiconductor layer on the substrate.

[0013] The preparation method of the array substrate provided by the embodiments of the present application sets a hydrogen barrier layer between the hydrogen-containing layer and the active layer of the MO thin film transistor, and the hydrogen barrier layer is used to block the diffusion of hydrogen in the hydrogen-containing layer into the active layer of the MO thin film transistor, so as to improve the reliability of the MO thin film transistor and the array substrate. In the process of preparing the hydrogen barrier layer, the gate layer of the MO thin film transistor and the hydrogen barrier layer are prepared in the same process by forming a metal layer and oxidizing part of the metal layer, so that the preparation process can be simplified. In addition, the hydrogen barrier layer and the gate layer are connected to form a complete film layer, and the complete film layer has high stability and good hydrogen blocking effect.

[0014] In a possible implementation, the hydrogen-containing layer is located on the side of the metal-oxide semiconductor layer close to the substrate, and the hydrogen-containing layer comprises a low-temperature polysilicon semiconductor layer.

[0015] The step of forming the metal-oxide semiconductor layer, the hydrogen barrier layer and the hydrogen-containing layer on the substrate specifically comprises:

[0016] The low-temperature polysilicon semiconductor layer is formed on the substrate.

[0017] The hydrogen barrier layer is formed on the side of the low-temperature polysilicon semiconductor layer away from the substrate.

[0018] The metal-oxide semiconductor layer is formed on the side of the hydrogen barrier layer away from the substrate.

[0019] In this way, the hydrogen in the low-temperature polysilicon semiconductor layer can be prevented from entering the metal-oxide semiconductor layer, so as to improve the reliability of the MO thin film transistor and the array substrate.

[0020] In a possible implementation, a capacitor is further formed on the substrate, and the gate layer of the metal-oxide thin film transistor comprises a bottom gate layer, and the bottom gate layer is located on the side of the metal-oxide semiconductor layer close to the substrate.

[0021] The metal layer left forms the bottom gate layer.

[0022] The reserved metal layer can form one of the electrode layers of the capacitor, and the electrode layer of the capacitor is electrically insulated from the bottom gate layer; or the reserved metal layer can form the gate layer of the low-temperature polysilicon thin film transistor, and the gate layer of the low-temperature polysilicon thin film transistor is electrically insulated from the bottom gate layer; or the reserved metal layer can form the gate layer of the low-temperature polysilicon thin film transistor and one of the electrode layers of the capacitor, and the gate layer of the low-temperature polysilicon thin film transistor, the electrode layer of the capacitor and the bottom gate layer are all electrically insulated.

[0023] In this way, the manufacturing process can be simplified, and the thickness of the array substrate can be reduced.

[0024] In a possible implementation, the hydrogen-containing layer is located on a side of the metal oxide semiconductor layer away from the substrate, and the hydrogen-containing layer comprises an interlayer dielectric layer;

[0025] In the step of forming the metal oxide semiconductor layer, the hydrogen barrier layer and the hydrogen-containing layer on the substrate, the step specifically comprises:

[0026] The metal oxide semiconductor layer is formed on the substrate;

[0027] The hydrogen barrier layer is formed on a side of the metal oxide semiconductor layer away from the substrate;

[0028] The interlayer dielectric layer is formed on a side of the hydrogen barrier layer away from the substrate.

[0029] In this way, the hydrogen in the interlayer dielectric layer can be prevented from entering the metal oxide semiconductor layer, so that the reliability of the MO thin film transistor and the array substrate can be improved.

[0030] In a possible implementation, the substrate further comprises a capacitor, and the gate layer of the metal oxide thin film transistor comprises a top gate layer, and the top gate layer is located on a side of the metal oxide semiconductor layer away from the substrate;

[0031] The reserved metal layer forms the top gate layer;

[0032] The reserved metal layer can form one of the electrode layers of the capacitor, and the electrode layer of the capacitor is electrically insulated from the top gate layer.

[0033] In this way, the manufacturing process can be simplified, and the thickness of the array substrate can be reduced.

[0034] In a possible implementation, the hydrogen-containing layer comprises a low-temperature polysilicon semiconductor layer and an interlayer dielectric layer, the low-temperature polysilicon semiconductor layer is located on a side of the metal oxide semiconductor layer close to the substrate, and the interlayer dielectric layer is located on a side of the metal oxide semiconductor layer away from the substrate;

[0035] The hydrogen barrier layer comprises a first hydrogen barrier layer and a second hydrogen barrier layer, the first hydrogen barrier layer is located between the metal oxide semiconductor layer and the low-temperature polysilicon semiconductor layer, and the second hydrogen barrier layer is located between the metal oxide semiconductor layer and the interlayer dielectric layer.

[0036] The step of forming the metal oxide semiconductor layer, the hydrogen barrier layer and the hydrogen-containing layer on the substrate specifically comprises:

[0037] forming the low-temperature polysilicon semiconductor layer on the substrate;

[0038] forming the first hydrogen barrier layer on a side of the low-temperature polysilicon semiconductor layer away from the substrate;

[0039] forming the metal oxide semiconductor layer on a side of the first hydrogen barrier layer away from the substrate;

[0040] forming the second hydrogen barrier layer on a side of the metal oxide semiconductor layer away from the substrate;

[0041] forming the interlayer dielectric layer on a side of the second hydrogen barrier layer away from the substrate.

[0042] In this way, the hydrogen in the low-temperature polysilicon semiconductor layer and the interlayer dielectric layer can be prevented from entering the metal oxide semiconductor layer, so as to improve the reliability of the MO thin film transistor and the array substrate.

[0043] In a possible implementation, the substrate further has a capacitor formed thereon, and the gate layer of the metal oxide thin film transistor comprises a bottom gate layer and a top gate layer, the bottom gate layer is located on a side of the metal oxide semiconductor layer close to the substrate, and the top gate layer is located on a side of the metal oxide semiconductor layer away from the substrate;

[0044] In the first hydrogen barrier layer, the remaining metal layer forms the bottom gate layer;

[0045] It can be implemented that, in the first hydrogen barrier layer, the remaining metal layer forms a first electrode layer of the capacitor, the first electrode layer is electrically insulated from the bottom gate layer; or, the remaining metal layer forms a gate layer of a low-temperature polysilicon thin film transistor, the gate layer of the low-temperature polysilicon thin film transistor is electrically insulated from the bottom gate layer; or, the remaining metal layer forms the gate layer of the low-temperature polysilicon thin film transistor and the first electrode layer of the capacitor, the gate layer of the low-temperature polysilicon thin film transistor, the first electrode layer and the bottom gate layer are all electrically insulated;

[0046] In the second hydrogen barrier layer, the remaining metal layer forms the top gate layer;

[0047] It can be implemented that, in the second hydrogen barrier layer, the remaining metal layer forms a second electrode layer of the capacitor, the second electrode layer is electrically insulated from the top gate layer.

[0048] In this way, the preparation process can be simplified, and the thickness of the array substrate can be reduced.

[0049] In a possible implementation, the thickness of the reserved metal layer is equal to the thickness of the hydrogen-blocking layer.

[0050] In this way, the thickness of the reserved metal layer does not need to be adjusted in the oxidation process, and the manufacturing process is relatively simple.

[0051] In a possible implementation, the thickness of the reserved metal layer is less than the thickness of the hydrogen-blocking layer; the hydrogen-blocking layer includes a first thickness region and a second thickness region along the thickness direction of the hydrogen-blocking layer, and the first thickness region is located on a side of the second thickness region away from the substrate.

[0052] The reserved metal layer is located in the first thickness region, and the thickness of the reserved metal layer is equal to the thickness of the hydrogen-blocking layer in the first thickness region.

[0053] Alternatively, the reserved metal layer is located in the second thickness region, and the thickness of the reserved metal layer is equal to the thickness of the hydrogen-blocking layer in the second thickness region.

[0054] In this way, the part of the hydrogen-blocking layer located opposite to the reserved metal layer along the thickness direction of the hydrogen-blocking layer can protect and insulate the reserved metal layer.

[0055] A second aspect of the embodiment of the present application provides an array substrate, including a substrate, a metal oxide semiconductor layer, a hydrogen-blocking layer, and a hydrogen-containing layer are sequentially arranged on the substrate, and the hydrogen-blocking layer is located between the metal oxide semiconductor layer and the hydrogen-containing layer.

[0056] The metal oxide semiconductor layer forms an active layer of a metal oxide thin film transistor, the hydrogen-blocking layer is of the same layer and material as a gate layer of the metal oxide thin film transistor, and a projection of the metal oxide semiconductor layer on the substrate at least partially overlaps a projection of the gate layer of the metal oxide thin film transistor on the substrate.

[0057] The array substrate provided by the embodiment of the present application sets the hydrogen-blocking layer between the hydrogen-containing layer and the active layer of the MO thin film transistor, and the hydrogen-blocking layer is used to block the hydrogen in the hydrogen-containing layer from diffusing into the active layer of the MO thin film transistor, so as to improve the reliability of the MO thin film transistor and the array substrate. When the hydrogen-blocking layer is manufactured, the gate layer of the MO thin film transistor and the hydrogen-blocking layer are manufactured in the same process by forming a metal layer and performing oxidation treatment on part of the metal layer, so as to simplify the manufacturing process. In addition, the hydrogen-blocking layer and the gate layer are connected, and form a complete film layer, the complete film layer has good structural stability and good hydrogen blocking effect.

[0058] In a possible implementation, the hydrogen-containing layer is located on a side of the metal oxide semiconductor layer close to the substrate, and the hydrogen-containing layer includes a low-temperature polysilicon semiconductor layer.

[0059] And / or, the hydrogen-containing layer is located on a side of the metal-oxide semiconductor layer away from the substrate, and the hydrogen-containing layer comprises an interlayer dielectric layer.

[0060] In this way, the hydrogen-blocking layer is used to block the diffusion of hydrogen in the low-temperature polysilicon semiconductor layer and / or the interlayer dielectric layer into the active layer of the MO thin film transistor, so as to improve the reliability of the MO thin film transistor and the array substrate.

[0061] The configuration of the present application and other inventive purposes and benefits will be more apparent and easy to understand through the description of the preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0062] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiment or prior art description will be simply introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0063] Figure 1 The flow chart of the preparation method of the array substrate provided by the embodiments of the present application;

[0064] Figure 2 The structural schematic diagram after completing step S10 provided by the embodiments of the present application;

[0065] Figure 3 The structural schematic diagram after completing step S20 provided by the embodiments of the present application;

[0066] Figure 4 The structural schematic diagram of a stack layer provided by the embodiments of the present application;

[0067] Figure 5 The structural schematic diagram of another stack layer provided by the embodiments of the present application;

[0068] Figure 6 The structural schematic diagram of a first buffer layer provided by the embodiments of the present application;

[0069] Figure 7 The flow chart of forming a hydrogen-blocking layer provided by the embodiments of the present application;

[0070] Figure 8 The structural schematic diagram after completing step S2201 provided by the embodiments of the present application;

[0071] Figure 9 The structural schematic diagram after completing step S2202 provided by the embodiments of the present application;

[0072] Figure 10 The structural schematic diagram of a hydrogen-blocking layer provided by the embodiments of the present application;

[0073] Figure 11 Another structure diagram of a hydrogen barrier layer provided for an embodiment of the present application;

[0074] Figure 12 A structure diagram of an array substrate provided for an embodiment of the present application;

[0075] Figure 13 A flow chart of step S20 provided for an embodiment of the present application;

[0076] Figure 14 A structure diagram after step S211 provided for an embodiment of the present application is completed;

[0077] Figure 15 A structure diagram of a second gate insulating layer provided for an embodiment of the present application;

[0078] Figure 16 A structure diagram after step S212 provided for an embodiment of the present application is completed;

[0079] Figure 17 A structure diagram after step S213 provided for an embodiment of the present application is completed;

[0080] Figure 18 Another structure diagram of an array substrate provided for an embodiment of the present application;

[0081] Figure 19 Another flow chart of step S20 provided for an embodiment of the present application;

[0082] Figure 20 A structure diagram after step S221 provided for an embodiment of the present application is completed;

[0083] Figure 21 A structure diagram of a first gate insulating layer provided for an embodiment of the present application;

[0084] Figure 22 A structure diagram after step S222 provided for an embodiment of the present application is completed;

[0085] Figure 23 A structure diagram after step S223 provided for an embodiment of the present application is completed;

[0086] Figure 24 Another structure diagram of an array substrate provided for an embodiment of the present application;

[0087] Figure 25 Another structure diagram of an array substrate provided for an embodiment of the present application;

[0088] Figure 26Another flowchart of step S20 provided for the embodiments of the present application;

[0089] Figure 27 A structural schematic diagram after step S234 is completed provided for the embodiments of the present application;

[0090] Figure 28 A structural schematic diagram after step S235 is completed provided for the embodiments of the present application.

[0091] Legend of reference signs:

[0092] 100: MO thin film transistor; 200: LTPS thin film transistor;

[0093] 300: capacitor; 400a: stack layer;

[0094] 410: substrate; 420: hydrogen barrier layer;

[0095] 421: first thickness area; 422: second thickness area;

[0096] 423: first hydrogen barrier layer; 424: second hydrogen barrier layer;

[0097] 425: metal layer; 440: first active layer;

[0098] 450: hydrogen-containing layer; 451: second active layer;

[0099] 452: interlayer dielectric layer; 460: first gate layer;

[0100] 461: top gate layer; 462: bottom gate layer;

[0101] 463: second gate layer; 470: electrode layer;

[0102] 480: source-drain electrode; 491: first gate insulating layer;

[0103] 492: second gate insulating layer; 493: first buffer layer;

[0104] 494: second buffer layer. DETAILED DESCRIPTION

[0105] The inventors have found, through long-term research, that in the related art, an array substrate using an LTPO technology can include an LTPS thin film transistor and an MO thin film transistor. An active layer in the MO thin film transistor is relatively sensitive to hydrogen content. Higher hydrogen content can cause the active layer to exhibit a conductorization effect, thereby reducing the electrical stability of the MO thin film transistor.

[0106] However, in order to improve the electrical performance of the LTPS thin film transistor, the active layer of the LTPS thin film transistor needs to be doped with hydrogen to passivate defects in the polycrystalline silicon grains, between the grain boundaries, and at the polycrystalline silicon and gate insulating layer. In addition, the hydrogen content in the interlayer dielectric layer in the array substrate is also relatively high. The processing temperature in the film plating process and the annealing process in the preparation of the MO thin film transistor is relatively high, which is easy to cause the hydrogen in the interlayer dielectric layer and the active layer of the LTPS thin film transistor to diffuse into the active layer of the MO thin film transistor, resulting in the conductorization of the active layer in the MO thin film transistor, thereby reducing the reliability of the MO thin film transistor and the array substrate, and even possibly causing the array substrate to fail.

[0107] Based on the above problems, the embodiments of the present application provide a preparation method of an array substrate and an array substrate. A hydrogen blocking layer is arranged between a hydrogen-containing layer and an active layer of an MO thin film transistor. The hydrogen blocking layer is used to block the diffusion of hydrogen in the hydrogen-containing layer into the active layer of the MO thin film transistor, so as to improve the reliability of the MO thin film transistor and the array substrate. In the preparation of the hydrogen blocking layer, a metal layer is formed and part of the metal layer is subjected to oxidation treatment, so that the gate layer of the MO thin film transistor and the hydrogen blocking layer are prepared in the same process, which can simplify the preparation process. In addition, the hydrogen blocking layer is connected with the gate layer to form a complete film layer. The complete film layer has good structural stability and good hydrogen blocking effect.

[0108] To make the objectives, technical solutions, and superiorities of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in connection with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0109] As shown in FIG. 1, the embodiments of the present application provide a preparation method of an array substrate, which can include the following steps. Figure 1

[0110] S10: providing a substrate.

[0111] As shown in FIG. 1, the embodiments of the present application provide a preparation method of an array substrate, which can include the following steps. Figure 2 As shown in FIG. 1, first, a substrate 410 is formed. The substrate 410 can provide support for other structural film layers prepared on the substrate 410.

[0112] In some examples, the substrate 410 can be a rigid substrate, and specifically can be a glass substrate or other rigid substrate. In other examples, the substrate 410 can also be a flexible substrate. The material of the substrate 410 can include at least one of polyimide, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyarylate, and polyethersulfone. ​

[0113] This application uses a flexible substrate 410 as an example for illustration.

[0114] The substrate 410 can be a single-layer structure or a multi-layer structure.

[0115] For example, substrate 410 may include a first flexible substrate and a first barrier layer stacked sequentially; alternatively, substrate 410 may include a first flexible substrate, a first barrier layer, and a second flexible substrate stacked sequentially; or alternatively, substrate 410 may include a first flexible substrate, a first barrier layer, a second flexible substrate, and a second barrier layer stacked sequentially. The materials of the first barrier layer and the second barrier layer may be silicon oxide, silicon nitride, silicon oxynitride, etc., used to prevent substances such as water vapor and oxygen from entering the transistor on substrate 410 and affecting the performance of the transistor.

[0116] S20: A metal oxide semiconductor layer, a hydrogen barrier layer, and a hydrogen-containing layer are formed on the substrate.

[0117] like Figure 3 As shown, a stacked layer 400a is formed on the substrate 410.

[0118] like Figure 4 and Figure 5 As shown, the stacked layer 400a may include multiple layers of film stacked together. In this embodiment, the multiple layers of film may include a metal oxide semiconductor layer, a hydrogen barrier layer 420, and a hydrogen-containing layer 450.

[0119] Among them, the hydrogen-containing layer 450 is a film layer with a high hydrogen content. The metal oxide semiconductor layer serves as the first active layer 440 of the MO thin film transistor, and the metal oxide semiconductor layer can be formed of indium gallium zinc oxide (IGZO).

[0120] The hydrogen barrier layer 420 is located between the first active layer 440 and the hydrogen-containing layer 450, thereby reducing hydrogen diffusion from the hydrogen-containing layer 450 to the first active layer 440, so as to improve the reliability of MO thin film transistors and array substrates.

[0121] like Figure 6 As shown, before fabricating the stacked layer 400a on the substrate 410, a first buffer layer 493 can be formed on the substrate 410. The first buffer layer 493 is used to isolate the substrate 410 and the film layer above the substrate 410, preventing impurities in the substrate 410 from entering the film layer above the substrate 410 and thus affecting the performance of the array substrate. In addition, it can also reduce the impact of high temperature on the substrate 410 in subsequent high-temperature processes.

[0122] In the step of forming the hydrogen barrier layer in S20, such as Figure 7 As shown, it can specifically include:

[0123] S2201: Forming a metal layer.

[0124] like Figure 8 As shown, a metal layer 425 is formed. The metal layer 425 can be made of an easily oxidizable metal, such as aluminum (Al), hafnium (Ha), tantalum (Ta), titanium (Ti), etc. The metal layer 425 can be formed by methods such as vapor deposition and sputtering.

[0125] S2202: Partial oxidation treatment of the metal layer, retaining the remaining metal layer.

[0126] Specifically, photoresist can be coated on the metal layer 425, exposed using a photomask, and then developed to form a photoresist retention area and a photoresist removal area. In the photoresist removal area, the metal layer 425 is exposed after development; in the photoresist retention area, the photoresist continues to cover the metal layer 425, thus preventing the covered metal layer 425 from oxidizing.

[0127] like Figure 9 As shown, the metal layer 425 is then oxidized, forming a metal oxide, i.e., a hydrogen barrier layer 420, in the photoresist removal area. At this point, the metal layer 425 in the photoresist retention area is retained and not oxidized. The photoresist in the retention area is stripped to expose the retained metal layer 425, thereby forming the gate layer of the MO thin-film transistor, i.e., the first gate layer 460. The first gate layer 460 of the MO thin-film transistor corresponds to the first active layer 440, and the orthographic projection of the first gate layer 460 onto the substrate 410 at least partially overlaps with the orthographic projection of the first active layer 440 onto the substrate. In this way, both the hydrogen barrier layer 420 and the first gate layer 460 are formed simultaneously, simplifying the fabrication process of the MO thin-film transistor. Furthermore, both the hydrogen barrier layer 420 and the first gate layer 460 have a hydrogen-blocking effect; they are connected together to form a complete film layer. A complete film layer has good structural stability and a good hydrogen-blocking effect.

[0128] The oxidation process for metal layer 425 can be oxygen ion bombardment, anodizing, etc.

[0129] In some examples, such as Figure 9 As shown, the thickness of the retained metal layer 425 is equal to the thickness of the hydrogen barrier layer 420. For example, the thickness of the first gate layer 460 is equal to the thickness of the hydrogen barrier layer 420. In this way, it is not necessary to control the thickness of the retained metal layer 425 during the oxidation process, which improves operability and simplifies the process.

[0130] In other examples, such as Figure 10 and Figure 11As shown, the thickness of the retained metal layer 425 is less than the thickness of the hydrogen barrier layer 420. Along the thickness direction of the metal layer 425, the hydrogen barrier layer 420 includes a first thickness region 421 and a second thickness region 422. The first thickness region 421 is located on the side of the second thickness region 422 away from the substrate 410, and the retained metal layer 425 is located in one of the first thickness region 421 and the second thickness region 422. That is, during the oxidation treatment of the metal layer 425, a portion of the metal layer 425 in the photoresist retention area along the thickness direction is oxidized to form the hydrogen barrier layer 420. In this way, the hydrogen barrier layer 420 isolates the retained metal layer 425 from other film layers, providing insulation and protection for the retained metal layer 425.

[0131] This application mainly uses the metal layer 425 in the reserved area to form the first gate layer 460 as an example for illustration.

[0132] Optional, such as Figure 10 As shown, the retained metal layer 425 forms a first gate layer 460, which is located in a first thickness region 421, and the thickness of the first gate layer 460 is equal to the thickness of the hydrogen barrier layer 420 in the first thickness region 421. At this time, the first gate layer 460 is located on the side of the hydrogen barrier layer 420 facing away from the substrate 410.

[0133] In specific implementation, a metal layer 425 of the second thickness region 422 is formed, and the metal layer 425 of the second thickness region 422 is oxidized to form a hydrogen barrier layer 420 of the second thickness region 422. Then, a metal layer 425 of the first thickness region 421 is formed on the side of the hydrogen barrier layer 420 of the second thickness region 422 facing away from the substrate 410. Through processes such as photoresist coating, exposure, development, oxidation treatment, and photoresist stripping, the metal layer 425 of the first thickness region 421 is partially oxidized. The metal layer 425 of the first thickness region 421 in the photoresist removal area forms the hydrogen barrier layer 420 of the first thickness region 421, and the metal layer 425 of the first thickness region 421 in the photoresist retention area forms the first gate layer 460. In this way, the hydrogen barrier layer 420 of the second thickness region 422 provides insulation and protection for the first gate layer 460.

[0134] Optional, such as Figure 11 As shown, the retained metal layer 425 forms a first gate layer 460, which is located in the second thickness region 422, and the thickness of the first gate layer 460 is equal to the thickness of the hydrogen barrier layer 420 in the second thickness region 422. At this time, the first gate layer 460 is located on the side of the hydrogen barrier layer 420 facing the substrate 410.

[0135] In one implementation, the metal layer 425 of the second thickness region 422 is first formed, and then the metal layer 425 of the second thickness region 422 is partially oxidized through coating photoresist, exposure, development, oxidation treatment, and photoresist stripping, etc. The metal layer 425 of the second thickness region 422 in the photoresist removal region forms the hydrogen barrier layer 420 of the second thickness region 422, and the metal layer 425 of the second thickness region 422 in the photoresist retention region forms the first gate layer 460. The metal layer 425 of the first thickness region 421 is formed on the side of the hydrogen barrier layer 420 of the second thickness region 422 and the first gate layer 460 away from the substrate 410. The thickness of the oxidized metal layer 425 is controlled by controlling the parameters of the oxidation process (for example, the oxidation time and bombardment power are controlled when the oxygen ion bombardment oxidation process is used), i.e., only the metal layer 425 in the first thickness region 421 is oxidized to form the hydrogen barrier layer 420 of the first thickness region 421. In this way, the hydrogen barrier layer 420 of the first thickness region 421 insulates and protects the first gate layer 460.

[0136] In another implementation, the metal layer 425 including the first thickness region 421 and the second thickness region 422 is formed, and the metal layer 425 of the first thickness region 421 is oxidized to form the hydrogen barrier layer 420 of the first thickness region 421. At this time, the thickness of the oxidized metal layer 425 needs to be controlled, and only the metal layer 425 in the first thickness region 421 is oxidized. Then, the metal layer 425 of the second thickness region 422 is continuously partially oxidized through coating photoresist, exposure, development, oxidation treatment, and photoresist stripping, etc. The metal layer 425 of the second thickness region 422 in the photoresist removal region forms the hydrogen barrier layer 420 of the second thickness region 422, and the metal layer 425 of the second thickness region 422 in the photoresist retention region forms the first gate layer 460.

[0137] It should be noted that, as shown in FIG. 1, the array substrate in the embodiment of the present application can include the MO thin film transistor 100, or both the MO thin film transistor 100 and the LTPS thin film transistor 200. Figure 12

[0138] In the array substrate, a capacitor 300 can also be included. The capacitor 300 includes two electrode layers 470 (i.e., a first electrode layer and a second electrode layer) oppositely arranged along the thickness direction of the array substrate, and an insulating medium layer of the capacitor 300 located between the two electrode layers 470. Here, the "oppositely arranged" can mean that the orthographic projections of the first electrode layer and the second electrode layer on the substrate 410 at least partially overlap.

[0139] The following describes three implementations of the stack layer 400a in the embodiment of the present application in detail.

[0140] ​In the first implementation of the stack layer 400a, the stack layer 400a includes a hydrogen-containing layer 450, a hydrogen-blocking layer 420 and a first active layer 440 which are sequentially stacked on the substrate 410. The hydrogen-blocking layer 420 is located on the side of the hydrogen-containing layer 450 away from the substrate 410, and the first active layer 440 is located on the side of the hydrogen-blocking layer 420 away from the substrate 410.

[0141] The hydrogen-containing layer 450 can be a low-temperature polysilicon semiconductor layer, which serves as a second active layer 451 of the LTPS thin film transistor 200.

[0142] S20: In the step of forming a metal oxide semiconductor layer, a hydrogen-blocking layer and a hydrogen-containing layer on a substrate, as shown in Figure 13 , the step can specifically include:

[0143] S211: Forming a low-temperature polysilicon semiconductor layer on a substrate.

[0144] Specifically, as shown in Figure 14 , an amorphous silicon film is deposited on the substrate 410, and then the amorphous silicon film is converted into a polysilicon film by a quasi-molecular laser annealing process, and the polysilicon film is patterned to form the second active layer 451. Since the temperature of the quasi-molecular laser annealing process is high, in order to avoid the influence on the MO thin film transistor 100, the preparation of the second active layer 451 can be prior to the MO thin film transistor 100.

[0145] As shown in Figure 15 , after the second active layer 451 is formed, a second gate insulating layer 492 can also be formed on the side of the second active layer 451 away from the substrate 410.

[0146] Before the second active layer 451 is formed, that is, before the stack layer 400a is formed, a first buffer layer 493 can also be formed first to avoid impurities in the substrate 410 from entering the second active layer 451.

[0147] S212: Forming a hydrogen-blocking layer on the side of the low-temperature polysilicon semiconductor layer away from the substrate.

[0148] As shown in Figure 16 , the hydrogen-blocking layer 420 is formed on the side of the second active layer 451 away from the substrate 410.

[0149] In specific implementation, a metal layer 425 can be deposited on the side of the second gate insulating layer 492 away from the substrate 410, and part of the metal layer 425 is oxidized to form the hydrogen-blocking layer 420, which is used to block the diffusion of hydrogen in the second active layer 451 in the direction away from the substrate 410, so as to enter the first active layer 440 above.

[0150] In this process, while forming the hydrogen barrier layer 420, the retained metal layer 425 can be used to form the first gate layer 460. This simplifies the fabrication process and reduces the thickness of the array substrate.

[0151] Optionally, the retained metal layer 425 can also form one of the electrode layers 470 of the capacitor 300. In this way, it is not necessary to fabricate the electrode layer 470 separately, which simplifies the fabrication process and reduces the thickness of the array substrate.

[0152] Optionally, the retained metal layer 425 can also form the second gate layer 463 of the LTPS thin-film transistor 200. This eliminates the need to fabricate the second gate layer 463 separately, simplifying the fabrication process and reducing the thickness of the array substrate.

[0153] It should be noted that the retained metal layer 425 can form the first gate layer 460, and can also form at least one of the electrode layer 470 and the second gate layer 463 of the capacitor 300. The first gate layer 460, the electrode layer 470 of the capacitor 300, and the second gate layer 463 are all electrically insulated from each other.

[0154] S213: A metal oxide semiconductor layer is formed on the side of the hydrogen barrier layer away from the substrate.

[0155] like Figure 17 As shown, a first active layer 440 is formed on the side of the hydrogen barrier layer 420 away from the substrate 410. Since the hydrogen barrier layer 420 is located between the first active layer 440 and the second active layer 451, it can reduce the diffusion of hydrogen from the second active layer 451 into the first active layer 440, thereby improving the reliability of the MO thin film transistor 100 and the array substrate.

[0156] It is understandable that, before forming the first active layer 440, a second buffer layer 494 can be formed on the side of the hydrogen barrier layer 420 away from the substrate 410. The second buffer layer 494 can isolate the first gate layer 460 and the first active layer 440.

[0157] like Figure 12 and Figure 18 As shown, after forming the first active layer 440, a first gate insulating layer 491, an interlayer dielectric layer 452, and a source / drain layer can be sequentially formed on the first active layer 440. The source / drain electrodes 480 of the LTPS thin-film transistor 200 and the source / drain electrodes 480 of the MO thin-film transistor 100 can be formed simultaneously from the source / drain layer. This simplifies the fabrication process and reduces the thickness of the array substrate.

[0158] Optional, such as Figure 24As shown, an electrode layer 470 of capacitor 300 can also be formed in the same layer and material as the source / drain layer, that is, the source / drain electrodes 480 of LTPS thin-film transistor 200, the source / drain electrodes 480 of MO thin-film transistor 100, and an electrode layer 470 of capacitor 300 are fabricated simultaneously. This simplifies the fabrication process and reduces the thickness of the array substrate. Alternatively, the electrode layer 470 of capacitor 300 can also be fabricated separately.

[0159] It should be noted that the MO thin-film transistor 100 can be a bottom-gate structure, a top-gate structure, or a dual-gate structure.

[0160] Understandably, continue to refer to Figure 18 The first gate layer 460 may include a top gate layer 461 and / or a bottom gate layer 462, with the top gate layer 461 located on the side of the first active layer 440 away from the substrate 410 and the bottom gate layer 462 located on the side of the first active layer 440 facing the substrate 410.

[0161] In the implementation of the MO thin film transistor 100 as a dual-gate structure, before forming the interlayer dielectric layer 452, a top gate layer 461 can also be formed on the side of the first gate insulating layer 491 facing away from the substrate 410.

[0162] Optionally, one electrode layer 470 of capacitor 300 can be formed simultaneously with the top gate layer 461. This simplifies the fabrication process and reduces the thickness of the array substrate.

[0163] like Figure 18 As shown, in the implementation where the thickness of the retained metal layer 425 is less than the thickness of the hydrogen barrier layer 420, if the retained metal layer 425 is located on the side of the hydrogen barrier layer 420 facing the substrate 410, then the hydrogen barrier layer 420 can act as the insulating dielectric layer of the capacitor 300. Since capacitance = dielectric constant * area of ​​the two electrode layers facing each other / (4πk * distance between the two electrode layers), and the dielectric constant is inversely proportional to the area of ​​the two electrode layers 470, the hydrogen barrier layer 420 has a higher dielectric constant, thereby reducing the area of ​​the electrode layer 470. When this array substrate is applied to a display panel, it is beneficial to improve the resolution of the display panel. Alternatively, if the retained metal layer 425 is located on the side of the hydrogen barrier layer 420 away from the substrate 410, the hydrogen barrier layer 420 can replace the second gate insulating layer 492 to isolate the second active layer 451 and the second gate layer 463. In this way, there is no need to set the second gate insulating layer 492, which simplifies the fabrication process and reduces the thickness of the array substrate.

[0164] In the second implementation of the stack layer 400a, the stack layer 400a comprises a first active layer 440, a hydrogen barrier layer 420 and a hydrogen-containing layer 450 which are sequentially stacked on the substrate 410, i.e. the hydrogen barrier layer 420 is located on the side of the first active layer 440 away from the substrate 410, and the hydrogen-containing layer 450 is located on the side of the hydrogen barrier layer 420 away from the substrate 410.

[0165] The hydrogen-containing layer 450 can be an interlayer dielectric layer 452, and the material of the interlayer dielectric layer 452 can be silicon nitride.

[0166] S20: In the step of forming the metal oxide semiconductor layer, the hydrogen barrier layer and the hydrogen-containing layer on the substrate, as shown in Figure 19 , the step can specifically include:

[0167] S221: Forming the metal oxide semiconductor layer on the substrate.

[0168] In a specific implementation, as shown in Figure 20 , a metal oxide semiconductor thin film is deposited on the substrate 410, and the metal oxide semiconductor thin film is patterned to form the metal oxide semiconductor layer, i.e. the first active layer 440.

[0169] As shown in Figure 21 , after the first active layer 440 is formed, the first gate insulating layer 491 can be formed.

[0170] S222: Forming the hydrogen barrier layer on the side of the metal oxide semiconductor layer away from the substrate.

[0171] As shown in Figure 22 , the hydrogen barrier layer 420 is formed on the side of the first active layer 440 away from the substrate 410.

[0172] In a specific implementation, the metal layer 425 can be deposited on the side of the first gate insulating layer 491 away from the substrate 410, and part of the metal layer 425 is oxidized to form the hydrogen barrier layer 420, which is used to prevent the hydrogen in the hydrogen-containing layer 450 located on the side of the hydrogen barrier layer 420 away from the first active layer 440 from entering the first active layer 440 below.

[0173] The remaining metal layer 425 can form the top gate layer 461 in the first gate electrode layer 460. In this way, the top gate layer 461 and the hydrogen barrier layer 420 are prepared at the same time, which can simplify the preparation process and reduce the thickness of the array substrate.

[0174] Optionally, the remaining metal layer 425 can also form one of the electrode layers 470 of the capacitor 300, and the electrode layer 470 of the capacitor 300 is electrically insulated from the top gate layer 461. In this way, one of the electrode layers 470 of the capacitor 300, the hydrogen barrier layer 420 and the top gate layer 461 are prepared at the same time, which can simplify the preparation process and reduce the thickness of the array substrate.

[0175] S223: Forming an interlayer dielectric layer on the side of the hydrogen barrier layer away from the substrate.

[0176] As shown in FIG. 4B, an interlayer dielectric layer 452 is formed on the side of the hydrogen barrier layer 420 away from the substrate 410. Since the hydrogen barrier layer 420 is located between the first active layer 440 and the interlayer dielectric layer 452, the hydrogen diffusing from the interlayer dielectric layer 452 into the first active layer 440 can be reduced, so as to improve the reliability of the MO thin film transistor 100 and the array substrate. Figure 23

[0177] Then, the source / drain electrode 480 of the MO thin film transistor 100 is formed on the side of the interlayer dielectric layer 452 away from the substrate 410.

[0178] In some embodiments, as shown in FIG. 4A and FIG. 4B, the second active layer 451 of the LTPS thin film transistor 200 can be formed before the MO thin film transistor 100. Figure 24 Figure 25

[0179] Specifically, the second active layer 451, the second gate insulating layer 492, the second gate layer 463, the second buffer layer 494, the first active layer 440, the first gate insulating layer 491, the hydrogen barrier layer 420, the interlayer dielectric layer 452 and the source / drain layer are sequentially formed on the substrate 410.

[0180] In this way, the process can be simplified, and the thickness of the array substrate can be reduced.

[0181] In this way, the process can be simplified, and the thickness of the array substrate can be reduced.

[0182] In this way, the process can be simplified, and the thickness of the array substrate can be reduced.

[0183] In this way, the process can be simplified, and the thickness of the array substrate can be reduced.

[0184] In this way, the process can be simplified, and the thickness of the array substrate can be reduced.

[0185] ​​​Optionally, the electrode layer 470 of the capacitor 300 can also be prepared separately, for example, the electrode layer 470 of the capacitor is arranged on the side of the second buffer layer 494 facing away from the substrate 410.

[0186] It can be understood that the two electrode layers 470 of the capacitor 300 can be any of the electrode layers 470 described above, and the embodiments of the present application do not limit this.

[0187] Continuing to refer to Figure 25 In the implementation where the thickness of the remaining metal layer 425 is less than the thickness of the hydrogen blocking layer 420, if the remaining metal layer 425 is located on the side of the hydrogen blocking layer 420 facing the substrate 410. For example, the remaining metal layer 425 can form one electrode layer 470 of the capacitor 300, and the source-drain layer is formed of the same material as the other electrode layer 470 of the capacitor 300. In this way, the hydrogen blocking layer 420 can act as the insulating medium layer of the capacitor 300, and the dielectric constant of the hydrogen blocking layer 420 is high, so that the area of the electrode layer 470 can be reduced (the principle has been described, and will not be repeated here), and the array substrate is applied to the display panel, which is beneficial to improve the resolution of the display panel. Alternatively, the remaining metal layer 425 is located on the side of the hydrogen blocking layer 420 facing away from the substrate 410, and the hydrogen blocking layer 420 can replace the first gate insulating layer 491 for isolating the first active layer 440 and the top gate layer 461. In addition, the hydrogen blocking layer 420 can also act as the insulating medium layer of the capacitor 300, as long as the two electrode layers 470 of the capacitor 300 are arranged on the two sides of the hydrogen blocking layer 420, so that the area of the electrode layer 470 can be reduced, and the array substrate is applied to the display panel, which is beneficial to improve the resolution of the display panel.

[0188] In the third implementation of the stack layer 400a, the hydrogen-containing layer 450 can include the second active layer 451 and the interlayer dielectric layer 452 of the LTPS thin film transistor 200. The hydrogen blocking layer 420 can include at least one of the first hydrogen blocking layer 423 and the second hydrogen blocking layer 424. In the above two implementations of the stack layer 400a, a single hydrogen blocking layer 420 has been described, and in this implementation, two hydrogen blocking layers 420 are described.

[0189] The stack layer 400a includes the second active layer 451, the first hydrogen blocking layer 423, the first active layer 440, the second hydrogen blocking layer 424, and the interlayer dielectric layer 452 which are sequentially stacked on the substrate 410.

[0190] S20: In the step of forming a metal oxide semiconductor layer, a hydrogen blocking layer and a hydrogen-containing layer on a substrate, as shown in Figure 26 , specifically can include:

[0191] S231: Forming a low-temperature polysilicon semiconductor layer on a substrate.

[0192] In specific implementation, such as Figure 14 As shown, an amorphous silicon thin film is deposited on a substrate 410, and then the amorphous silicon thin film is converted into a polycrystalline silicon thin film by an excimer laser annealing process. The polycrystalline silicon thin film is then patterned to form a low-temperature polycrystalline silicon semiconductor layer, namely the second active layer 451 of the LTPS thin film transistor 200.

[0193] like Figure 15 As shown, after the second active layer 451 is formed, a second gate insulating layer 492 can also be formed on the side of the second active layer 451 away from the substrate 410.

[0194] S232: A first hydrogen barrier layer is formed on the side of the low-temperature polycrystalline silicon semiconductor layer away from the substrate.

[0195] like Figure 16 and Figure 27 As shown, a hydrogen barrier layer 420, i.e., a first hydrogen barrier layer 423, is formed on the side of the second active layer 451 away from the substrate 410.

[0196] In a specific implementation, a first hydrogen barrier layer 423 can be formed on the side of the second gate insulating layer 492 away from the substrate 410.

[0197] In addition, while forming the first hydrogen barrier layer 423, the retained metal layer 425 can be used to form the first gate layer 460, i.e., the bottom gate layer 462. This simplifies the fabrication process and reduces the thickness of the array substrate.

[0198] Optionally, while forming the first hydrogen barrier layer 423, the retained metal layer 425 can also simultaneously form at least one of the electrode layers 470 and the second gate layer 463 of the capacitor 300. The principle is the same as in the above embodiment and will not be repeated here.

[0199] S233: A metal oxide semiconductor layer is formed on the side of the first hydrogen barrier layer away from the substrate.

[0200] like Figure 17 As shown, a first active layer 440 of the MO thin film transistor 100 is formed on the side of the hydrogen barrier layer 420 away from the substrate 410. Since the first hydrogen barrier layer 423 is located between the first active layer 440 and the second active layer 451, it can reduce the diffusion of hydrogen from the second active layer 451 into the first active layer 440, thereby improving the reliability of the MO thin film transistor 100 and the array substrate.

[0201] Before forming the first active layer 440, a second buffer layer 494 may be formed on the side of the first hydrogen barrier layer 423 away from the substrate 410.

[0202] S234: A second hydrogen barrier layer is formed on the side of the metal oxide semiconductor layer away from the substrate.

[0203] As shown in FIG. 4B, the second hydrogen barrier layer 424 is formed on the side of the first active layer 440 away from the substrate 410. Figure 27

[0204] In addition, the remaining metal layer 425 can form the first gate layer 460, i.e. the top gate layer 461, while the second hydrogen barrier layer 424 is formed. In this way, the manufacturing process can be simplified and the thickness of the array substrate can be reduced.

[0205] Optionally, the remaining metal layer 425 can also form one of the electrode layers 470 of the capacitor 300 while the second hydrogen barrier layer 424 is formed. In this way, the manufacturing process can be simplified and the thickness of the array substrate can be reduced.

[0206] S235: Forming an interlayer dielectric layer on the side of the second hydrogen barrier layer away from the substrate.

[0207] As shown in FIG. 4B, the second hydrogen barrier layer 424 is formed on the side of the first active layer 440 away from the substrate 410. Figure 28 As shown in FIG. 4B, the second hydrogen barrier layer 424 is formed on the side of the first active layer 440 away from the substrate 410.

[0208] Then, a source-drain layer is formed on the side of the interlayer dielectric layer 452 away from the substrate 410, which can form at least one of the source-drain electrodes 480 of the MO thin film transistor 100 and the source-drain electrodes 480 of the LTPS thin film transistor 200. In addition, the source-drain layer can also be arranged in the same layer and material as one of the electrode layers 470 of the capacitor 300.

[0209] It can be understood that the two electrode layers 470 of the capacitor 300 are any two of the above-mentioned electrode layers 470, and the present application does not limit the comparison.

[0210] In the implementation where the thickness of the remaining metal layer 425 is less than the thickness of the hydrogen barrier layer 420, for the first hydrogen barrier layer 423, the remaining metal layer 425 can be located on the side of the first hydrogen barrier layer 423 facing the substrate 410, or the remaining metal layer 425 can be located on the side of the first hydrogen barrier layer 423 away from the substrate 410. For the second hydrogen barrier layer 424, the remaining metal layer 425 can be located on the side of the second hydrogen barrier layer 424 facing the substrate 410, or the remaining metal layer 425 can be located on the side of the second hydrogen barrier layer 424 away from the substrate 410. The principle has been described in the above embodiments and will not be repeated here.

[0211] ​It is understandable that the source and drain 480 of the MO thin film transistor 100 are electrically connected to the first active layer 440 through a connection hole, and the source and drain 480 of the LTPS thin film transistor 200 are also electrically connected to the second active layer 451 through a connection hole.

[0212] In some embodiments, after the LTPS thin film transistor 200 and MO thin film transistor 100 are fabricated, a passivation layer, a planarization layer, etc., can be formed on the side of the LTPS thin film transistor 200 and MO thin film transistor 100 away from the substrate 410.

[0213] The materials of the passivation layer, the first gate insulating layer 491, the second gate insulating layer 492, the interlayer dielectric layer 452, the first buffer layer 493, and the second buffer layer 494 can be silicon nitride, silicon oxynitride, silicon oxide, or various novel organic insulating materials, or metal oxides with high dielectric constants such as aluminum oxide and tantalum oxide.

[0214] The electrode layer 470 of the capacitor 300, signal traces, source and drain electrodes 480, etc. in the array substrate can be made of silver, copper, aluminum, molybdenum or alloy, or a multilayer structure formed by metal and transparent conductive oxide.

[0215] This application also provides an array substrate, which is prepared by the array substrate preparation method described in the above embodiments.

[0216] The array substrate can be used in a display panel, which may include a light-emitting layer, an encapsulation layer, a polarizer, a touch layer, and a cover plate, etc., which are stacked on the array substrate in sequence. This application does not limit this.

[0217] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for fabricating an array substrate, characterized in that, include: Provide substrate; A metal oxide semiconductor layer, a hydrogen barrier layer, and a hydrogen-containing layer are formed on the substrate; wherein the hydrogen barrier layer is located between the metal oxide semiconductor layer and the hydrogen-containing layer. The step of forming the hydrogen barrier layer includes: Form a metal layer; The metal layer is partially oxidized, while the remaining portion of the metal layer is retained. The oxidized metal layer forms the hydrogen barrier layer. At least a portion of the retained metal layer has its orthogonal projection onto the substrate at least partially overlapping the orthogonal projection of the metal oxide semiconductor layer onto the substrate. The retained metal layer forms the gate layer of a metal oxide thin-film transistor, and the metal oxide semiconductor layer forms the active layer. The gate layer and the hydrogen barrier layer are formed in the same process, and the gate layer is connected to the hydrogen barrier layer. The thickness of the retained metal layer is equal to the thickness of the hydrogen barrier layer; Alternatively, the thickness of the retained metal layer is less than the thickness of the hydrogen barrier layer; wherein, along the thickness direction of the hydrogen barrier layer, the hydrogen barrier layer includes a first thickness region and a second thickness region, the first thickness region being located on the side of the second thickness region away from the substrate; The retained metal layer is located in the first thickness region, and the thickness of the retained metal layer is equal to the thickness of the hydrogen barrier layer in the first thickness region; or, the retained metal layer is located in the second thickness region, and the thickness of the retained metal layer is equal to the thickness of the hydrogen barrier layer in the second thickness region.

2. The method for fabricating an array substrate according to claim 1, characterized in that, The hydrogen-containing layer is located on the side of the metal oxide semiconductor layer closer to the substrate, and the hydrogen-containing layer includes a low-temperature polycrystalline silicon semiconductor layer; The steps of forming a metal oxide semiconductor layer, a hydrogen barrier layer, and a hydrogen-containing layer on the substrate specifically include: The low-temperature polycrystalline silicon semiconductor layer is formed on the substrate; The hydrogen barrier layer is formed on the side of the low-temperature polycrystalline silicon semiconductor layer away from the substrate; The metal oxide semiconductor layer is formed on the side of the hydrogen barrier layer away from the substrate.

3. The method for fabricating an array substrate according to claim 2, characterized in that, A capacitor is also formed on the substrate, and the gate layer of the metal oxide thin film transistor includes a bottom gate layer, which is located on the side of the metal oxide semiconductor layer close to the substrate. The retained metal layer forms the bottom gate layer.

4. The method for fabricating an array substrate according to claim 3, characterized in that, The retained metal layer forms one of the electrode layers of the capacitor, and the electrode layer of the capacitor is electrically insulated from the bottom gate layer; or, the retained metal layer forms the gate layer of a low-temperature polycrystalline silicon thin-film transistor, and the gate layer of the low-temperature polycrystalline silicon thin-film transistor is electrically insulated from the bottom gate layer; or, the retained metal layer forms both the gate layer of the low-temperature polycrystalline silicon thin-film transistor and one of the electrode layers of the capacitor, and the gate layer of the low-temperature polycrystalline silicon thin-film transistor, the electrode layer of the capacitor, and the bottom gate layer are all electrically insulated from each other.

5. The method for fabricating an array substrate according to claim 1, characterized in that, The hydrogen-containing layer is located on the side of the metal oxide semiconductor layer away from the substrate, and the hydrogen-containing layer includes an interlayer dielectric layer; The steps of forming a metal oxide semiconductor layer, a hydrogen barrier layer, and a hydrogen-containing layer on the substrate specifically include: A metal oxide semiconductor layer is formed on the substrate; The hydrogen barrier layer is formed on the side of the metal oxide semiconductor layer away from the substrate; The interlayer dielectric layer is formed on the side of the hydrogen barrier layer away from the substrate.

6. The method for fabricating an array substrate according to claim 5, characterized in that, A capacitor is also formed on the substrate, and the gate layer of the metal oxide thin film transistor includes a top gate layer, which is located on the side of the metal oxide semiconductor layer away from the substrate. The retained metal layer forms the top gate layer.

7. The method for fabricating an array substrate according to claim 6, characterized in that, The retained metal layer forms one of the electrode layers of the capacitor, and the electrode layer of the capacitor is electrically insulated from the top gate layer.

8. The method for fabricating an array substrate according to claim 1, characterized in that, The hydrogen-containing layer includes a low-temperature polycrystalline silicon semiconductor layer and an interlayer dielectric layer. The low-temperature polycrystalline silicon semiconductor layer is located on the side of the metal oxide semiconductor layer closer to the substrate, and the interlayer dielectric layer is located on the side of the metal oxide semiconductor layer away from the substrate. The hydrogen barrier layer includes a first hydrogen barrier layer and a second hydrogen barrier layer. The first hydrogen barrier layer is located between the metal oxide semiconductor layer and the low-temperature polycrystalline silicon semiconductor layer, and the second hydrogen barrier layer is located between the metal oxide semiconductor layer and the interlayer dielectric layer. The steps of forming a metal oxide semiconductor layer, a hydrogen barrier layer, and a hydrogen-containing layer on the substrate specifically include: The low-temperature polycrystalline silicon semiconductor layer is formed on the substrate; The first hydrogen barrier layer is formed on the side of the low-temperature polycrystalline silicon semiconductor layer away from the substrate; The metal oxide semiconductor layer is formed on the side of the first hydrogen barrier layer away from the substrate; A second hydrogen barrier layer is formed on the side of the metal oxide semiconductor layer away from the substrate; The interlayer dielectric layer is formed on the side of the second hydrogen barrier layer away from the substrate.

9. The method for fabricating an array substrate according to claim 8, characterized in that, A capacitor is also formed on the substrate. The gate layer of the metal oxide thin film transistor includes a bottom gate layer and a top gate layer. The bottom gate layer is located on the side of the metal oxide semiconductor layer closer to the substrate, and the top gate layer is located on the side of the metal oxide semiconductor layer away from the substrate. In the first hydrogen barrier layer, the retained metal layer forms the bottom gate layer.

10. The method for fabricating an array substrate according to claim 9, characterized in that, The metal layer retained in the first hydrogen barrier layer forms the first electrode layer of the capacitor, and the first electrode layer is electrically insulated from the bottom gate layer; or, the retained metal layer forms the gate layer of a low-temperature polycrystalline silicon thin-film transistor, and the gate layer of the low-temperature polycrystalline silicon thin-film transistor is electrically insulated from the bottom gate layer; or, the retained metal layer forms both the gate layer of the low-temperature polycrystalline silicon thin-film transistor and the first electrode layer of the capacitor, and the gate layer, the first electrode layer, and the bottom gate layer of the low-temperature polycrystalline silicon thin-film transistor are all electrically insulated. In the second hydrogen barrier layer, the retained metal layer forms the top gate layer.

11. The method for fabricating an array substrate according to claim 10, characterized in that, The metal layer retained in the second hydrogen barrier layer forms the second electrode layer of the capacitor, and the second electrode layer is electrically insulated from the top gate layer.

12. An array substrate, manufactured according to the method of claim 1, characterized in that, Includes a substrate, on which a metal oxide semiconductor layer, a hydrogen barrier layer and a hydrogen-containing layer are stacked, wherein the hydrogen barrier layer is located between the metal oxide semiconductor layer and the hydrogen-containing layer; The metal oxide semiconductor layer forms the active layer of the metal oxide thin film transistor, and the hydrogen barrier layer is of the same layer and material as the gate layer of the metal oxide thin film transistor. The orthogonal projection of the metal oxide semiconductor layer on the substrate at least partially overlaps with the orthogonal projection of the gate layer of the metal oxide thin film transistor on the substrate.

13. The array substrate according to claim 12, characterized in that, The hydrogen-containing layer is located on the side of the metal oxide semiconductor layer closer to the substrate, and the hydrogen-containing layer includes a low-temperature polycrystalline silicon semiconductor layer; And / or, the hydrogen-containing layer is located on the side of the metal oxide semiconductor layer away from the substrate, and the hydrogen-containing layer includes an interlayer dielectric layer.

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