Metal oxide thin film transistor array substrate, manufacturing method thereof and display panel

Abstract

A metal oxide thin film transistor array substrate, a manufacturing method thereof and a display panel, comprising: a substrate; a source electrode, a drain electrode and a light-shielding barrier layer on the substrate; a first insulating layer covering the source electrode, the drain electrode and the light-shielding barrier layer, the first insulating layer being formed with a first contact hole and a second contact hole; a common electrode, a first conductor part, a second conductor part and a semiconductor active layer formed by etching and patterning a metal oxide semiconductor layer on the first insulating layer, the first conductor part being filled into the first contact hole and being in conductive contact with the source electrode, the second conductor part being filled into the second contact hole and being in conductive contact with the drain electrode; and a second insulating layer, a third insulating layer, a gate electrode and a pixel electrode, wherein a third contact hole is provided through the second insulating layer and the first insulating layer, the gate electrode is filled into the third contact hole and is in conductive contact with the light-shielding barrier layer, a fourth contact hole is provided through the third insulating layer and the second insulating layer, and the pixel electrode is filled into the fourth contact hole and is in conductive contact with the second conductor part.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a metal oxide thin-film transistor array substrate, its fabrication method, and a display panel. Background Technology

[0002] With the development of the information age, as a human-machine interface application, the display screen has increasingly higher requirements for various specifications. Due to the limited performance of amorphous silicon (a-Si) driving devices, it is necessary to replace them with devices made of high electron mobility materials to meet product performance specifications.

[0003] Metal oxide semiconductors (MOS) offer advantages over amorphous silicon, including higher electron mobility, lower leakage current, and compatibility with most device fabrication processes. Common metal oxide materials include indium gallium zinc oxide (IGZO). Due to their high mobility, MOS devices are frequently used in high-end, high-specification products.

[0004] Depending on the position of the gate relative to the active semiconductor layer, existing metal-oxide-semiconductor transistors (MOS-TFTs) are divided into two architectures: bottom gate and top gate. In the existing bottom gate MOS-TFT architecture, there is only a very thin silicon oxide (SiOx) layer on the IGZO channel. The silicon oxide layer has poor film quality, and during wet etching processes, the etchant can seep from the silicon oxide layer into the semiconductor layer, etching the semiconductor and causing switching failure. The existing top gate MOS-TFT architecture can better protect the channel, increase the channel carrier concentration, and reduce trace loading. However, it is more complex to design and has more film layers. For example, our company's N1605T IGZO top gate architecture product, including the planarization layer (OC) and the third metal layer (M3), ultimately requires 11 etching processes and a total of 13 film layers, resulting in higher costs. Furthermore, more film layers also lead to higher defect rates, reducing the product's competitive advantage.

[0005] In existing MOS-TFTs, whether top-gate or bottom-gate architectures, a layer of silicon oxide needs to be deposited on the IGZO semiconductor layer to protect the channel from H ions. Except for the channel, the IGZO in other locations needs to be made conductive. Existing technologies protect the channel by coating a photoresist on the silicon oxide layer or by directly using the gate metal layer as a mask. The remaining areas are over-etched by dry etching of the silicon oxide layer, followed by hydrogenation treatment to make the exposed areas of IGZO other than the channel conductive.

[0006] Then, the IGZO conductor and the silicon oxide layer are etched in one process. In order to etch the silicon oxide layer cleanly, over-etching is required. The over-etching amount is smaller in areas with thick silicon oxide film and larger in areas with thin film, which will lead to uneven over-etching of IGZO. Severe over-etching of IGZO will cause its characteristics to change, resulting in poor semiconductor switching function or even failure. Summary of the Invention

[0007] The purpose of this invention is to provide a metal oxide thin film transistor array substrate and its fabrication method, in order to solve the problems of existing MOS-TFTs having more film layers, more complex processes, higher costs, and the current use of dry etching processes to directly etch onto IGZO, which combines IGZO conductor formation with dry etching processes, making it impossible to effectively control the amount of IGZO over-etching, which can easily lead to semiconductor failure.

[0008] This invention provides a metal oxide thin-film transistor array substrate, comprising:

[0009] Substrate;

[0010] The source, drain, and light-shielding barrier layer are formed on the substrate by etching and patterning a first metal layer. The source and drain are spaced apart, and the light-shielding barrier layer is spaced apart from both the source and drain.

[0011] A first insulating layer covering the source electrode, the drain electrode, and the light-shielding layer, wherein a first contact hole is formed through the first insulating layer at a position corresponding to the source electrode, and a second contact hole is formed through the first insulating layer at a position corresponding to the drain electrode;

[0012] A common electrode, a first conductor portion, a second conductor portion, and a semiconductor active layer are formed on the first insulating layer by etching and patterning a metal oxide semiconductor layer. The common electrode, the first conductor portion, and the second conductor portion are made into conductors after etching and forming. The semiconductor active layer remains a semiconductor. The semiconductor active layer is connected between the first conductor portion and the second conductor portion. The first conductor portion is filled into the first contact hole and makes conductive contact with the source electrode. The second conductor portion is filled into the second contact hole and makes conductive contact with the drain electrode.

[0013] A second insulating layer covering the common electrode, the first conductor portion, the second conductor portion, and the semiconductor active layer has a third contact hole formed at a position corresponding to the light-shielding layer, penetrating the second insulating layer and the first insulating layer;

[0014] A gate formed by etching a second metal layer on the second insulating layer is filled into the third contact hole and makes conductive contact with the light-shielding barrier layer.

[0015] The third insulating layer covering the gate has a fourth contact hole formed at a position corresponding to the second conductor portion, penetrating the third insulating layer and the second insulating layer;

[0016] A pixel electrode, formed by etching a transparent conductive layer on the third insulating layer, is filled into the fourth contact hole and makes conductive contact with the second conductor portion.

[0017] Furthermore, the light-shielding layer is located between the source and the drain, and the position of the light-shielding layer corresponds to the position of the semiconductor active layer and the gate.

[0018] Furthermore, the semiconductor active layer and the light-shielding barrier layer are positioned correspondingly, and the projection of the semiconductor active layer on the substrate is within the range of the projection of the light-shielding barrier layer on the substrate.

[0019] Furthermore, the gate is stacked directly above the light-shielding layer, the active semiconductor layer is sandwiched between the light-shielding layer and the gate, and the projection of the gate on the substrate overlaps with the projection of the light-shielding layer on the substrate.

[0020] Furthermore, after being etched and patterned, the first metal layer also forms a data line, and the source electrode is connected to the data line or the source electrode is part of the data line; after being etched and patterned, the second metal layer also forms a scan line, and the gate electrode is connected to the scan line or the gate electrode is part of the scan line.

[0021] This invention also provides a method for fabricating a metal oxide thin-film transistor array substrate, comprising:

[0022] A first metal layer is formed on a substrate, and the first metal layer is etched and patterned so that the first metal layer forms a source, a drain and a light-shielding barrier layer after etching. The source and the drain are spaced apart, and the light-shielding barrier layer is spaced apart from both the source and the drain.

[0023] A first insulating layer covering the source, the drain and the light-shielding layer is formed on the substrate, and the first insulating layer is etched and patterned so that a first contact hole is formed at the position corresponding to the source and a second contact hole is formed at the position corresponding to the drain after the first insulating layer is etched.

[0024] A metal oxide semiconductor layer is formed on the first insulating layer, and the metal oxide semiconductor layer fills the first contact hole and the second contact hole. Then, a photoresist layer is coated on the metal oxide semiconductor layer.

[0025] The photoresist layer is exposed and developed using a halftone mask to leave a first photoresist pattern and a second photoresist pattern on the photoresist layer. Other areas where no photoresist is left are exposed to the metal oxide semiconductor layer. The thickness of the first photoresist pattern is greater than the thickness of the second photoresist pattern. The first photoresist pattern corresponds to the position of the semiconductor active layer, and the second photoresist pattern corresponds to the positions of the first conductor portion, the second conductor portion, and the common electrode.

[0026] Using the first photoresist pattern and the second photoresist pattern as a mask, the metal oxide semiconductor layer is etched and patterned to remove the portion of the metal oxide semiconductor layer not covered by the photoresist, so that the metal oxide semiconductor layer forms a first semiconductor pattern and a second semiconductor pattern that are spaced apart after etching, wherein the first semiconductor pattern corresponds to the common electrode, and the second semiconductor pattern corresponds to the first conductor portion, the second conductor portion and the channel position.

[0027] The second photoresist pattern is removed by photoresist ashing, but the first photoresist pattern is still covered at the channel position, so that the first semiconductor pattern is exposed, and at the same time, the two ends of the second semiconductor pattern that are not covered by photoresist are also exposed.

[0028] Using the first photoresist pattern as a shield, the exposed areas of the first semiconductor pattern and the second semiconductor pattern are conductiveized, so that the first semiconductor pattern is conductiveized to form a common electrode, and the exposed two ends of the second semiconductor pattern are conductiveized to form a first conductive portion and a second conductive portion, respectively. The portion of the second semiconductor pattern located directly below the first photoresist pattern remains a semiconductor and forms a semiconductor active layer. The semiconductor active layer is connected between the first conductive portion and the second conductive portion. The first conductive portion is filled into the first contact hole and makes conductive contact with the source electrode, and the second conductive portion is filled into the second contact hole and makes conductive contact with the drain electrode.

[0029] After forming the common electrode, the first conductor portion, the second conductor portion, and the semiconductor active layer, the first photoresist pattern is removed;

[0030] A second insulating layer is formed on the first insulating layer, covering the common electrode, the first conductor portion, the second conductor portion and the semiconductor active layer, and the second insulating layer and the first insulating layer are simultaneously etched and patterned, and a third contact hole is formed at a position corresponding to the light-shielding layer, penetrating the second insulating layer and the first insulating layer;

[0031] A second metal layer is formed on the second insulating layer, and the second metal layer is etched and patterned so that the second metal layer forms a gate after etching. The gate is filled into the third contact hole and makes conductive contact with the light-shielding barrier layer.

[0032] A third insulating layer covering the gate is formed on the second insulating layer, and the third insulating layer and the second insulating layer are simultaneously etched and patterned to form a fourth contact hole penetrating the third insulating layer and the second insulating layer at a position corresponding to the second conductor portion;

[0033] A transparent conductive layer is formed on the third insulating layer, and the transparent conductive layer is etched and patterned so that the transparent conductive layer forms a pixel electrode after etching. The pixel electrode fills the fourth contact hole and makes conductive contact with the second conductor portion.

[0034] Furthermore, the light-shielding layer is located between the source and the drain, and the position of the light-shielding layer corresponds to the position of the semiconductor active layer and the gate.

[0035] Furthermore, the active semiconductor layer is positioned corresponding to the light-shielding barrier layer, and the projection of the active semiconductor layer on the substrate is within the range of the projection of the light-shielding barrier layer on the substrate; the gate is stacked directly above the light-shielding barrier layer, the active semiconductor layer is sandwiched between the light-shielding barrier layer and the gate, and the projection of the gate on the substrate overlaps with the projection of the light-shielding barrier layer on the substrate.

[0036] Furthermore, during the etching patterning of the first metal layer, a data line is also formed simultaneously, and the source electrode is connected to the data line or the source electrode is part of the data line; during the etching patterning of the second metal layer, a scan line is also formed simultaneously, and the gate electrode is connected to the scan line or the gate electrode is part of the scan line.

[0037] This invention also provides a display panel comprising the aforementioned metal oxide thin-film transistor array substrate.

[0038] The metal oxide thin-film transistor array substrate and its fabrication method provided in this invention eliminate the need for a metal layer and an insulating layer by integrating the light-shielding barrier layer with the source and drain electrodes into a single layer; and by integrating the common electrode with the semiconductor active layer into a single layer, eliminating the need for a transparent conductive layer for fabricating the common electrode and an insulating layer; moreover, this architecture eliminates the need for a planarization layer (OC) and a third metal layer (M3). Therefore, a top-gate metal oxide thin-film transistor array substrate can be fabricated based on seven masks, improving the film layer structure of the existing MOS-TFT top-gate architecture, transforming the complex top-gate architecture into a seven-etching process with a total of seven film layers, resulting in a simpler process, lower manufacturing cost, and higher production efficiency.

[0039] In the above architecture, the source and drain are fabricated on the bottom layer, and the upper active semiconductor layer is connected to the source and drain through contact holes etched in the first insulating layer. When performing conductor-enhancing processing on the semiconductor pattern after etching the metal-oxide-semiconductor (MOS) layer, there is no need to dry-etch the insulating layer; only the process conditions for conductor-enhancing the semiconductor pattern need to be considered. By separating the dry etching of the insulating layer and the conductor-enhancing process, the process of dry-etching the insulating layer to the MOS semiconductor is avoided. This better protects the characteristics of the MOS semiconductor and prevents uncontrollable over-etching due to uneven film thickness, which could lead to semiconductor failure.

[0040] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0041] Figure 1 This is a partial planar structure schematic diagram of the metal oxide thin-film transistor array substrate in an embodiment of the present invention;

[0042] Figures 2a to 2l for Figure 1 A schematic diagram of the combined cross-sectional structure along lines AA and BB during the fabrication process of a metal oxide thin-film transistor array substrate.

[0043] Figures 3a to 3h for Figure 1 A schematic diagram of the planar structure of the fabrication process of a metal oxide thin-film transistor array substrate. Detailed Implementation

[0044] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the specific embodiments, structures, features, and effects of the present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments:

[0045] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the accompanying drawings. Through the description of the specific embodiments, a more in-depth and specific understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the present invention.

[0046] Figure 1 This is a partial planar structural diagram of the metal oxide thin-film transistor array substrate in an embodiment of the present invention. Please refer to... Figure 1 This invention provides a metal oxide thin-film transistor array substrate, comprising:

[0047] Substrate 10;

[0048] A data line 111, a source 112, a drain 113, and a light-shielding layer 114 are formed on the substrate 10 by etching and patterning a first metal layer 11. The source 112 and the drain 113 are spaced apart, and the light-shielding layer 114 is also spaced apart from both the source 112 and the drain 113, meaning that the light-shielding layer 114 is not connected to either the source 112 or the drain 113. Specifically, the source 112 is connected to the data line 111 or the source 112 is part of the data line 111. The light-shielding layer 114 is located between the source 112 and the drain 113, and the position of the light-shielding layer 114 corresponds to the position of the semiconductor active layer 134 and the gate 152.

[0049] A first insulating layer 12 covers the data line 111, source 112, drain 113 and light-shielding layer 114. The first insulating layer 12 has a first contact hole 121 formed through it at the position corresponding to the source 112 and a second contact hole 122 formed through it at the position corresponding to the drain 113.

[0050] A common electrode 131, a first conductor portion 132, a second conductor portion 133, and a semiconductor active layer 134 are formed on the first insulating layer 12 by etching and patterning a metal oxide semiconductor layer 13. The common electrode 131, the first conductor portion 132, and the second conductor portion 133 are made into conductors after etching. The semiconductor active layer 134 remains a semiconductor and is connected between the first conductor portion 132 and the second conductor portion 133. The first conductor portion 132 is filled into the first contact hole 121 and makes conductive contact with the source electrode 112, thereby connecting the source electrode 112 and the semiconductor active layer 134 through the first conductor portion 132. The second conductor portion 133 is filled into the second contact hole 122 and makes conductive contact with the drain electrode 113, thereby connecting the drain electrode 113 and the semiconductor active layer 134 through the second conductor portion 133. Specifically, the common electrode 131, the first conductor portion 132, and the second conductor portion 133 formed by etching can be treated with plasma. Through ion bombardment, hydrogen (H2) doping, helium (He) doping, or argon (Ar) doping, the common electrode 131, the first conductor portion 132, and the second conductor portion 133 can be made into conductors. In this embodiment, the common electrode 131, the first conductor portion 132, the second conductor portion 133, and the semiconductor active layer 134 are all made of the same metal oxide semiconductor layer 13. Specifically, the semiconductor active layer 134 corresponds to the position of the light-shielding layer 114. The projection of the semiconductor active layer 134 on the substrate 10 is within the range of the projection of the light-shielding layer 114 on the substrate 10, that is, the light-shielding layer 114 completely covers the semiconductor active layer 134. In this way, the light-shielding layer 114 can block the backlight from the backlight module from the semiconductor active layer 134, avoiding the problem of TFT device characteristic degradation caused by long-term light exposure.

[0051] The second insulating layer 14, which covers the common electrode 131, the first conductor portion 132, the second conductor portion 133, and the semiconductor active layer 134, has a third contact hole 141 formed at a position corresponding to the light-shielding layer 114, penetrating the second insulating layer 14 and the first insulating layer 12. The opening position of the third contact hole 141 is offset from the channel position.

[0052] A scan line 151 and a gate 152 are formed on the second insulating layer 14 by etching and patterning the second metal layer 15. The gate 152 is filled into the third contact hole 141 and makes conductive contact with the light-shielding layer 114. Specifically, the gate 152 is connected to the scan line 151 or the gate 152 is part of the scan line 151. In this embodiment, the gate 152 is stacked directly above the light-shielding layer 114, and the semiconductor active layer 134 is sandwiched between the light-shielding layer 114 and the gate 152. The projection of the gate 152 on the substrate 10 overlaps with the projection of the light-shielding layer 114 on the substrate 10. By connecting the gate 152 to the light-shielding layer 114, and sandwiching the semiconductor active layer 134 between the gate 152 and the light-shielding layer 114, the carrier concentration is increased, and the conductivity of the semiconductor active layer 134 is improved.

[0053] The third insulating layer 16 covering the scan line 151 and the gate 152 has a fourth contact hole 161 formed at a position corresponding to the second conductor portion 133, penetrating the third insulating layer 16 and the second insulating layer 14.

[0054] A pixel electrode 171, formed by etching and patterning a transparent conductive layer 17 on the third insulating layer 16, is inserted into the fourth contact hole 161 and makes conductive contact with the second conductor portion 133. The pixel electrode 171 and the common electrode 131 are located on different layers, separated by the third insulating layer 16 and the second insulating layer 14, with the pixel electrode 171 positioned above the common electrode 131.

[0055] In this embodiment, by integrating the light-shielding layer 114 with the source 112 and drain 113 into one layer, a metal layer and an insulating layer are eliminated; by integrating the common electrode 131 with the semiconductor active layer 134 into one layer, a transparent conductive layer 17 for fabricating the common electrode 131 and an insulating layer are eliminated; moreover, this architecture eliminates the need for a planarization layer (OC) and a third metal layer (M3). Therefore, a metal oxide thin-film transistor array substrate with a top gate architecture can be fabricated based on seven masks, improving the film layer structure of the existing MOS-TFT top gate architecture, transforming the complex top gate architecture into a seven-step etching process with a total of seven film layers, resulting in a simple process, low manufacturing cost, and high production efficiency.

[0056] In the above architecture, the source 112 and drain 113 are fabricated on the bottom layer, and the upper semiconductor active layer 134 is connected to the source 112 and drain 113 through contact holes etched in the first insulating layer 12. When performing conductor-enhancing processing on the semiconductor pattern after etching the metal-oxide-semiconductor layer 13, there is no need to dry-etch the insulating layer; only the process conditions for conductor-enhancing the semiconductor pattern need to be considered. By separating the dry etching of the insulating layer and the conductor-enhancing process, the process of dry-etching the insulating layer to the metal-oxide-semiconductor is avoided. This better protects the characteristics of the metal-oxide-semiconductor and prevents uncontrollable over-etching due to uneven film thickness, which could lead to semiconductor failure.

[0057] Figures 2a to 2l for Figure 1 A schematic diagram of the combined cross-sectional structure along lines AA and BB during the fabrication process of a metal-oxide-slim thin-film transistor array substrate. Figures 2a to 2l The portion to the left of the dashed line corresponds to the cross-sectional structure along line AA, and the portion to the right of the dashed line corresponds to the cross-sectional structure along line BB. Figures 3a to 3h for Figure 1 A schematic diagram of the planar structure of a metal-oxide-slim thin-film transistor array substrate fabrication process. (See attached diagram.) Figures 2a to 2l and Figures 3a to 3h As shown in the figure, this embodiment of the invention also provides a method for fabricating a metal oxide thin-film transistor array substrate. Specifically, the fabrication method includes:

[0058] Please refer to Figure 2a and Figure 3a A first metal layer 11 is formed on the substrate 10, and the first metal layer 11 is etched and patterned so that the first metal layer 11 forms a data line 111, a source 112, a drain 113, and a light-shielding layer 114 after etching. The source 112 is connected to the data line 111 or is part of the data line 111. The source 112 and drain 113 are spaced apart. The light-shielding layer 114 is also spaced apart from both the source 112 and drain 113, meaning the light-shielding layer 114 is not connected to either the source 112 or drain 113. Specifically, the light-shielding layer 114 is located between the source 112 and drain 113, and the position of the light-shielding layer 114 corresponds to the position of the semiconductor active layer 134 and the gate 152.

[0059] Please refer to Figure 2b and Figure 3bA first insulating layer 12 is formed on the substrate 10, covering the data line 111, source 112, drain 113, and light-shielding layer 114. The first insulating layer 12 is then etched and patterned, so that a first contact hole 121 is formed at the position corresponding to the source 112, and a second contact hole 122 is formed at the position corresponding to the drain 113. The source 112 is exposed through the first contact hole 121, and the drain 113 is exposed through the second contact hole 122.

[0060] Please refer to Figure 2c A metal oxide semiconductor layer 13 is formed on the first insulating layer 12, and the metal oxide semiconductor layer 13 fills the first contact hole 121 and the second contact hole 122. Then, a photoresist layer 20 is coated on the metal oxide semiconductor layer 13. Specifically, the material of the metal oxide semiconductor layer 13 can be indium gallium zinc oxide (IGZO) or indium zinc oxide (IZO), etc.

[0061] Please refer to Figure 2d A halftone mask 30 (HTM) is used to expose and develop the photoresist layer 20, leaving a first photoresist pattern 21 and a second photoresist pattern 22 on the photoresist layer 20. Other areas without photoresist are exposed, revealing the metal-oxide-semiconductor layer 13. The thickness of the first photoresist pattern 21 is greater than the thickness of the second photoresist pattern 22. The first photoresist pattern 21 corresponds to the position of the active semiconductor layer 134 and covers the channel position. The second photoresist pattern 22 corresponds to the positions of the first conductor portion 132, the second conductor portion 133, and the common electrode 131. The first conductor portion 132 is the conductive portion in the metal-oxide-semiconductor layer 13 that connects the active semiconductor layer 134 to the source electrode 112, and the second conductor portion 133 is the conductive portion in the metal-oxide-semiconductor layer 13 that connects the active semiconductor layer 134 to the drain electrode 113. Except for the first photoresist pattern 21 and the second photoresist pattern 22, other areas have no photoresist and expose the metal-oxide-semiconductor layer 13.

[0062] Specifically, the halftone mask 30 includes an opaque area 31, a semi-transparent area 32, and a fully transparent area 33, wherein the opaque area 31, the semi-transparent area 32, and the fully transparent area 33 correspond to the first photoresist pattern 21, the second photoresist pattern 22, and other areas where no photoresist needs to be left, respectively. In this way, after exposure and development, the photoresist layer 20 can leave the first photoresist pattern 21 and the second photoresist pattern 22, and the thickness of the first photoresist pattern 21 is greater than the thickness of the second photoresist pattern 22.

[0063] Please refer to Figure 2e and Figure 3cUsing the first photoresist pattern 21 and the second photoresist pattern 22 as a mask, the metal oxide semiconductor layer 13 is etched and patterned to remove the portion of the metal oxide semiconductor layer 13 not covered by the photoresist (i.e., the exposed area), so that the metal oxide semiconductor layer 13 forms a first semiconductor pattern 13a and a second semiconductor pattern 13b that are spaced apart from each other after etching. The first semiconductor pattern 13a corresponds to the common electrode 131, and the second semiconductor pattern 13b corresponds to the first conductor portion 132, the second conductor portion 133 and the channel position.

[0064] Please refer to Figure 2f Then, photoresist ashing is used to remove the second photoresist pattern 22, but the channel location is still covered by the first photoresist pattern 21, exposing the first semiconductor pattern 13a, and simultaneously exposing the two ends of the second semiconductor pattern 13b that are not covered by photoresist. It should be noted that during the photoresist ashing process, the first photoresist pattern 21 is also thinned, but since the first photoresist pattern 21 is thicker than the second photoresist pattern 22, the first photoresist pattern 21 still covers the channel location after thinning.

[0065] Please refer to Figure 2g and Figure 3dUsing the first photoresist pattern 21 as a shield, the exposed areas in the first semiconductor pattern 13a and the second semiconductor pattern 13b are conductiveized, so that the first semiconductor pattern 13a is conductiveized to form a common electrode 131, and the exposed two ends of the second semiconductor pattern 13b are conductiveized to form the first conductive portion 132 and the second conductive portion 133 respectively. The part of the second semiconductor pattern 13b located directly below the first photoresist pattern 21 is not conductiveized because it is shielded by the first photoresist pattern 21, and remains a semiconductor to form the active semiconductor layer 134. In this embodiment, the active semiconductor layer 134 is connected between the first conductor portion 132 and the second conductor portion 133. The first conductor portion 132 is filled into the first contact hole 121 and makes conductive contact with the source electrode 112, thereby connecting the source electrode 112 and the active semiconductor layer 134 through the first conductor portion 132. The second conductor portion 133 is filled into the second contact hole 122 and makes conductive contact with the drain electrode 113, thereby connecting the drain electrode 113 and the active semiconductor layer 134 through the second conductor portion 133. In this embodiment, the projection of the active semiconductor layer 134 on the substrate 10 is within the range of the projection of the light-shielding layer 114 on the substrate 10, that is, the light-shielding layer 114 completely covers the active semiconductor layer 134. In this way, the light-shielding layer 114 can block the backlight from the backlight module from the active semiconductor layer 134, avoiding the problem of TFT device characteristic degradation caused by long-term exposure to light. Specifically, the exposed areas of the first semiconductor pattern 13a and the second semiconductor pattern 13b can be made conductive by plasma treatment. Through ion bombardment, hydrogen (H2) doping, helium (He) doping or argon (Ar) doping, the exposed areas of the first semiconductor pattern 13a and the second semiconductor pattern 13b are made conductive, that is, the common electrode 131, the first conductive part 132 and the second conductive part 133 are made into conductors.

[0066] Please refer to Figure 2h After forming the common electrode 131, the first conductor portion 132, the second conductor portion 133, and the active semiconductor layer 134, the first photoresist pattern 21 is removed. The common electrode 131, the first conductor portion 132, the second conductor portion 133, and the active semiconductor layer 134 are all made of the same metal oxide semiconductor layer 13.

[0067] Please refer to Figure 2i and Figure 3eA second insulating layer 14 is formed on the first insulating layer 12, covering the common electrode 131, the first conductor portion 132, the second conductor portion 133, and the semiconductor active layer 134. Both the second insulating layer 14 and the first insulating layer 12 are simultaneously etched and patterned. A third contact hole 141 is formed at a position corresponding to the light-shielding layer 114, penetrating both the second insulating layer 14 and the first insulating layer 12. The light-shielding layer 114 is exposed through the third contact hole 141. The opening position of the third contact hole 141 is offset from the channel position.

[0068] Please refer to Figure 2j and Figure 3f A second metal layer 15 is formed on the second insulating layer 14, and the second metal layer 15 is etched and patterned to form a scan line 151 and a gate 152 after etching. The gate 152 is filled into the third contact hole 141 and makes conductive contact with the light-shielding layer 114. The gate 152 is connected to the scan line 151, or the gate 152 is part of the scan line 151. In this embodiment, the gate 152 is stacked directly above the light-shielding layer 114, and the projection of the gate 152 on the substrate 10 overlaps with the projection of the light-shielding layer 114 on the substrate 10. A semiconductor active layer 134 is sandwiched between the light-shielding layer 114 and the gate 152. By connecting the gate 152 to the light-shielding layer 114, the semiconductor active layer 134 is sandwiched between the gate 152 and the light-shielding layer 114, increasing the carrier concentration and improving the conductivity of the semiconductor active layer 134.

[0069] Please refer to Figure 2k and Figure 3g A third insulating layer 16 covering the scan line 151 and the gate 152 is formed on the second insulating layer 14, and the third insulating layer 16 and the second insulating layer 14 are simultaneously etched and patterned. A fourth contact hole 161 is formed at a position corresponding to the second conductor portion 133, penetrating the third insulating layer 16 and the second insulating layer 14. The second conductor portion 133 is exposed through the fourth contact hole 161.

[0070] In this embodiment, the materials of the first insulating layer 12, the second insulating layer 14 and the third insulating layer 16 may specifically be silicon oxide (SiOx), silicon nitride (SiNx) or a composite film of silicon nitride and silicon oxide, etc.

[0071] Please refer to Figure 2l and Figure 3hA transparent conductive layer 17 is formed on the third insulating layer 16, and the transparent conductive layer 17 is etched and patterned so that the transparent conductive layer 17 forms a pixel electrode 171 after etching. The pixel electrode 171 fills the fourth contact hole 161 and makes conductive contact with the second conductor portion 133. The pixel electrode 171 and the common electrode 131 are located on different layers and are separated by the third insulating layer 16 and the second insulating layer 14, with the pixel electrode 171 located above the common electrode 131. Specifically, the material of the transparent conductive layer 17 can be indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0072] Specifically, etching the film layer to create patterns mainly involves processes such as coating photoresist, exposure, development, etching, and photoresist removal. These are existing technologies and will not be elaborated upon here.

[0073] In the above process, by integrating the light-shielding layer 114 with the source 112 and drain 113 into one layer, a metal layer and an insulating layer are eliminated; by integrating the common electrode 131 with the semiconductor active layer 134 into one layer, a transparent conductive layer 17 for fabricating the common electrode 131 and an insulating layer are eliminated; moreover, this architecture eliminates the need for a planarization layer (OC) and a third metal layer (M3). Therefore, the above process can fabricate a top-gate metal oxide thin-film transistor array substrate based on seven masks, improving the film layer structure of the existing MOS-TFT top-gate architecture, transforming the complex top-gate architecture into a seven-step etching process with a total of seven film layers. The process is simple, the manufacturing cost is low, and the production efficiency is high.

[0074] In the above process, the source 112 and drain 113 are fabricated on the bottom layer, and the upper semiconductor active layer 134 is connected to the source 112 and drain 113 through contact holes etched in the first insulating layer 12. A half-tone mask is used for etching the metal-oxide-semiconductor layer 13. When performing conductor-conducting processing on the etched semiconductor pattern, there is no need to dry-etch the insulating layer; only the process conditions for conductor-conducting the semiconductor pattern need to be considered. By separating the dry etching of the insulating layer from the conductor-conducting processing of the semiconductor pattern, the process of dry etching the insulating layer to the metal-oxide-semiconductor is avoided. This better protects the characteristics of the metal-oxide-semiconductor and prevents uncontrollable over-etching due to uneven film thickness, which could lead to semiconductor failure.

[0075] The present invention also provides a display panel, comprising the aforementioned metal oxide thin-film transistor array substrate. Specifically, the display panel may be a liquid crystal display panel.

[0076] The above specific examples illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. For those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A metal oxide thin-film transistor array substrate, characterized in that, include: Substrate (10); A source electrode (112), a drain electrode (113), and a light-shielding layer (114) are formed on the substrate (10) by etching a first metal layer (11). The source electrode (112) and the drain electrode (113) are spaced apart, and the light-shielding layer (114) is spaced apart from both the source electrode (112) and the drain electrode (113). A first insulating layer (12) covers the source electrode (112), the drain electrode (113) and the light-shielding layer (114). The first insulating layer (12) has a first contact hole (121) formed through it at a position corresponding to the source electrode (112) and a second contact hole (122) formed through it at a position corresponding to the drain electrode (113). A common electrode (131), a first conductor portion (132), a second conductor portion (133), and a semiconductor active layer (134) are formed on the first insulating layer (12) by etching and patterning a metal oxide semiconductor layer (13). The common electrode (131), the first conductor portion (132), and the second conductor portion (133) are made into conductors after etching and patterning. The semiconductor active layer (134) remains a semiconductor. The semiconductor active layer (134) is connected between the first conductor portion (132) and the second conductor portion (133). The first conductor portion (132) is filled into the first contact hole (121) and makes conductive contact with the source electrode (112). The second conductor portion (133) is filled into the second contact hole (122) and makes conductive contact with the drain electrode (113). A second insulating layer (14) covering the common electrode (131), the first conductor portion (132), the second conductor portion (133) and the semiconductor active layer (134) has a third contact hole (141) formed at a position corresponding to the light-shielding layer (114) that penetrates the second insulating layer (14) and the first insulating layer (12); A gate (152) formed by etching patterning the second metal layer (15) on the second insulating layer (14) is filled in the third contact hole (141) and makes conductive contact with the light-shielding layer (114); The third insulating layer (16) covering the gate (152) has a fourth contact hole (161) formed at a position corresponding to the second conductor portion (133) that penetrates the third insulating layer (16) and the second insulating layer (14); A pixel electrode (171) is formed by etching a transparent conductive layer (17) on the third insulating layer (16). The pixel electrode (171) is filled in the fourth contact hole (161) and makes conductive contact with the second conductor portion (133).

2. The metal oxide thin-film transistor array substrate as described in claim 1, characterized in that, The light-shielding layer (114) is located between the source (112) and the drain (113), and the position of the light-shielding layer (114) corresponds to the position of the semiconductor active layer (134) and the gate (152).

3. The metal oxide thin-film transistor array substrate as described in claim 1, characterized in that, The semiconductor active layer (134) is positioned corresponding to the light-shielding layer (114), and the projection of the semiconductor active layer (134) on the substrate (10) is within the range of the projection of the light-shielding layer (114) on the substrate (10).

4. The metal oxide thin-film transistor array substrate as described in claim 1, characterized in that, The gate (152) is stacked directly above the light-shielding layer (114), and the active semiconductor layer (134) is sandwiched between the light-shielding layer (114) and the gate (152). The projection of the gate (152) on the substrate (10) overlaps with the projection of the light-shielding layer (114) on the substrate (10).

5. The metal oxide thin-film transistor array substrate as described in claim 1, characterized in that, The first metal layer (11) also forms a data line (111) after being etched and patterned, and the source electrode (112) is connected to the data line (111) or the source electrode (112) is part of the data line (111); the second metal layer (15) also forms a scan line (151) after being etched and patterned, and the gate electrode (152) is connected to the scan line (151) or the gate electrode (152) is part of the scan line (151).

6. A method for fabricating a metal oxide thin-film transistor array substrate, characterized in that, include: A first metal layer (11) is formed on a substrate (10), and the first metal layer (11) is etched and patterned so that the first metal layer (11) forms a source (112), a drain (113) and a light-shielding layer (114) after etching. The source (112) and the drain (113) are spaced apart, and the light-shielding layer (114) is spaced apart from both the source (112) and the drain (113). A first insulating layer (12) covering the source electrode (112), the drain electrode (113) and the light-shielding layer (114) is formed on the substrate (10), and the first insulating layer (12) is etched and patterned so that a first contact hole (121) is formed at the position corresponding to the source electrode (112) and a second contact hole (122) is formed at the position corresponding to the drain electrode (113) after the first insulating layer (12) is etched. A metal oxide semiconductor layer (13) is formed on the first insulating layer (12), and the metal oxide semiconductor layer (13) is filled into the first contact hole (121) and the second contact hole (122). Then, a photoresist layer (20) is coated on the metal oxide semiconductor layer (13). The photoresist layer (20) is exposed and developed using a halftone mask (30) to leave a first photoresist pattern (21) and a second photoresist pattern (22) on the photoresist layer (20). Other areas where no photoresist is left are exposed to the metal oxide semiconductor layer (13). The thickness of the first photoresist pattern (21) is greater than the thickness of the second photoresist pattern (22). The first photoresist pattern (21) corresponds to the position of the semiconductor active layer (134), and the second photoresist pattern (22) corresponds to the positions of the first conductor portion (132), the second conductor portion (133), and the common electrode (131). Using the first photoresist pattern (21) and the second photoresist pattern (22) as a mask, the metal oxide semiconductor layer (13) is etched and patterned to remove the portion of the metal oxide semiconductor layer (13) not covered by the photoresist, so that the metal oxide semiconductor layer (13) forms a first semiconductor pattern (13a) and a second semiconductor pattern (13b) spaced apart after etching, wherein the first semiconductor pattern (13a) corresponds to the common electrode (131), and the second semiconductor pattern (13b) corresponds to the first conductor portion (132), the second conductor portion (133), and the channel position; The second photoresist pattern (22) is removed by photoresist ashing, but the first photoresist pattern (21) is still covered at the channel position, so that the first semiconductor pattern (13a) is exposed, and at the same time, the two ends of the second semiconductor pattern (13b) that are not covered by photoresist are also exposed. Using the first photoresist pattern (21) as a shield, the exposed areas of the first semiconductor pattern (13a) and the second semiconductor pattern (13b) are conductiveized, so that the first semiconductor pattern (13a) is conductiveized to form a common electrode (131), and the exposed two ends of the second semiconductor pattern (13b) are conductiveized to form a first conductor portion (132) and a second conductor portion (133) respectively. The part of the second semiconductor pattern (13b) located directly below the first photoresist pattern (21) is still retained as a semiconductor and forms a semiconductor active layer (134). The semiconductor active layer (134) is connected between the first conductor portion (132) and the second conductor portion (133). The first conductor portion (132) is filled into the first contact hole (121) and makes conductive contact with the source electrode (112). The second conductor portion (133) is filled into the second contact hole (122) and makes conductive contact with the drain electrode (113). After forming the common electrode (131), the first conductor portion (132), the second conductor portion (133) and the semiconductor active layer (134), the first photoresist pattern (21) is removed; A second insulating layer (14) is formed on the first insulating layer (12) to cover the common electrode (131), the first conductor portion (132), the second conductor portion (133) and the semiconductor active layer (134), and the second insulating layer (14) and the first insulating layer (12) are simultaneously etched and patterned, and a third contact hole (141) is formed at a position corresponding to the light-shielding layer (114) to penetrate the second insulating layer (14) and the first insulating layer (12); A second metal layer (15) is formed on the second insulating layer (14), and the second metal layer (15) is etched and patterned so that the second metal layer (15) forms a gate (152) after etching. The gate (152) is filled into the third contact hole (141) and makes conductive contact with the light-shielding layer (114). A third insulating layer (16) covering the gate (152) is formed on the second insulating layer (14), and the third insulating layer (16) and the second insulating layer (14) are simultaneously etched and patterned, and a fourth contact hole (161) penetrating the third insulating layer (16) and the second insulating layer (14) is formed at a position corresponding to the second conductor portion (133); A transparent conductive layer (17) is formed on the third insulating layer (16), and the transparent conductive layer (17) is etched and patterned so that the transparent conductive layer (17) forms a pixel electrode (171) after etching. The pixel electrode (171) fills the fourth contact hole (161) and makes conductive contact with the second conductor portion (133).

7. The method for fabricating a metal oxide thin-film transistor array substrate as described in claim 6, characterized in that, The light-shielding layer (114) is located between the source (112) and the drain (113), and the position of the light-shielding layer (114) corresponds to the position of the semiconductor active layer (134) and the gate (152).

8. The method for fabricating a metal oxide thin-film transistor array substrate as described in claim 6, characterized in that, The active semiconductor layer (134) is positioned corresponding to the light-shielding layer (114). The projection of the active semiconductor layer (134) on the substrate (10) is within the range of the projection of the light-shielding layer (114) on the substrate (10). The gate (152) is stacked directly above the light-shielding layer (114). The active semiconductor layer (134) is sandwiched between the light-shielding layer (114) and the gate (152). The projection of the gate (152) on the substrate (10) overlaps with the projection of the light-shielding layer (114) on the substrate (10).

9. The method for fabricating a metal oxide thin-film transistor array substrate as described in claim 6, characterized in that, The first metal layer (11) also forms a data line (111) during etching patterning, and the source electrode (112) is connected to the data line (111) or the source electrode (112) is part of the data line (111); the second metal layer (15) also forms a scan line (151) during etching patterning, and the gate electrode (152) is connected to the scan line (151) or the gate electrode (152) is part of the scan line (151).

10. A display panel, characterized in that, Includes the metal oxide thin-film transistor array substrate as described in any one of claims 1-5.

Images