Erasable memory and method for manufacturing the same

Abstract

The present invention provides a rewritable memory, comprising a substrate, a barrier layer, a first heterojunction, a second heterojunction, a tunneling layer, a channel layer, a source electrode and a drain electrode, wherein the barrier layer is arranged on the top surface of the substrate; the first heterojunction and the second heterojunction have a unidirectional charge conduction characteristic, and the first heterojunction and the second heterojunction are respectively used for data writing operation and data erasing operation of the rewritable memory; the tunneling layer comprises a horizontal portion and a vertical portion, and the vertical portion is used to separate the first heterojunction and the second heterojunction to avoid lateral charge conduction of the first heterojunction and the second heterojunction; the channel layer is used for charge migration. Two heterojunctions are used as data writing and data erasing channels of the rewritable memory, respectively, so that data writing and data erasing of the rewritable memory are more stable and symmetrical, data erasing and data writing speeds are improved, and dynamic power consumption is reduced. The present invention also provides a method for manufacturing the rewritable memory.

Description

Technical Field

[0001] The present invention relates to the field of erasable memories, and particularly to an erasable memory and a manufacturing method thereof. Background Art

[0002] Today's mainstream storage technologies are divided into two categories: volatile storage technologies and non-volatile storage technologies. For volatile erasable memories, they mainly include static random access memory (SRAM) and dynamic random access memory (DRAM). Volatile erasable memories have a write speed in the nanosecond range, however, their data retention ability is only in the millisecond range, which makes them only applicable in limited storage areas such as caches. For non-volatile storage technologies, such as flash memory technology, its data retention ability can reach 10 years. However, the relatively slow write operation greatly limits its application in the cache field. For flash memory technology, due to the contradiction between the reduction of the thickness of the tunneling oxide layer and the charge retention ability, it results in a relatively low erase speed of the flash memory. At the same time, the charge trapping layer will share part of the voltage, which will lead to an increase in the erase voltage. On the other hand, in order to increase the charge retention ability, an insulating medium rich in deep-level defects is used as the trapping layer, which will make it difficult for charges to be erased from the trapping layer, resulting in a slow erase speed.

[0003] The invention patent with the publication number CN100570897C discloses a method for improving the data erase speed of a non-volatile erasable memory. The non-volatile erasable memory includes a substrate, a source electrode and a drain electrode formed in the substrate, and a gate electrode formed above the substrate. Among them, there are three superimposed insulating layers between the gate electrode and the substrate. The middle layer is used to trap charges, and the insulating layers on both sides are used to lock the charges in the middle layer. The method applies a negative voltage to the gate electrode and also applies a negative voltage to the substrate during the data erase process. However, the data erase speed of the erasable memory of this invention is relatively low.

[0004] Therefore, it is necessary to provide an erasable memory and a manufacturing method thereof to solve the problems existing in the above-mentioned prior art. Summary of the Invention

[0005] The purpose of the present invention is to provide an erasable memory and a manufacturing method thereof to solve the problem of slow data erase speed of the erasable memory.

[0006] To achieve the above purpose, the erasable memory of the present invention includes a substrate, a blocking layer, a first heterojunction, a second heterojunction, a tunneling layer, a channel layer, a source electrode and a drain electrode;

[0007] The substrate serves as the gate electrode of the erasable memory;

[0008] The blocking layer is disposed on the top surface of the substrate;

[0009] The first heterojunction and the second heterojunction are respectively arranged at two opposite ends of the top surface of the barrier layer, the first heterojunction and the second heterojunction have a unidirectional charge conduction characteristic, and the charge conduction direction of the first heterojunction is opposite to the charge conduction direction of the second heterojunction, and the first heterojunction and the second heterojunction are respectively used for data writing operation and data erasing operation of the erasable memory;

[0010] The tunneling layer includes a horizontal portion and a vertical portion, the horizontal portion covers the top surfaces of the first heterojunction and the second heterojunction, and the vertical portion is used to separate the first heterojunction and the second heterojunction to avoid lateral charge conduction between the first heterojunction and the second heterojunction;

[0011] The channel layer covers the top surface of the tunnel layer and is used for charge migration;

[0012] The channel layer source and the drain are respectively arranged at two opposite ends of the top surface of the channel layer.

[0013] The beneficial effects of the erasable memory of the present invention are:

[0014] The first heterojunction and the second heterojunction are respectively arranged at two opposite ends of the top surface of the barrier layer, and the first heterojunction and the second heterojunction are respectively used for data writing operation and data erasing operation of the erasable memory; by adopting the first heterojunction and the second heterojunction with unidirectional charge conduction characteristics as data writing and data erasing channels of the erasable memory, respectively, the charge conduction directions of the first heterojunction and the second heterojunction are opposite, so that the data writing and data erasing of the erasable memory are more stable and symmetrical, and the data erasing speed and data writing speed of the erasable memory are consistent, thereby improving the data erasing and data writing speed of the erasable memory; the first heterojunction and the second heterojunction are separated by the vertical part of the tunneling layer, so that the lateral charge conduction of the first heterojunction and the second heterojunction is avoided, thereby reducing the dynamic power consumption of the erasable memory.

[0015] Optionally, the first heterojunction includes a first metal oxide layer and a second metal oxide layer, the first metal oxide layer is connected to the top surface of the barrier layer, the bottom surface of the second metal oxide layer is connected to the first metal oxide layer, the top surface of the second metal oxide layer is connected to the horizontal portion, and the first metal oxide layer and the second metal oxide layer have different constituent materials.

[0016] Optionally, the second heterojunction includes a third metal oxide layer and a fourth metal oxide layer, the third metal oxide layer is connected to the top surface of the barrier layer, the bottom surface of the fourth metal oxide layer is connected to the third metal oxide layer, and the top surface of the fourth metal oxide layer is connected to the horizontal portion;

[0017] The composition materials of the third metal oxide layer and the second metal oxide layer are the same, and the composition materials of the fourth metal oxide layer and the first metal oxide layer are the same. The beneficial effect is that since both the first heterojunction and the second heterojunction have the characteristic of unidirectional charge conduction, and the composition materials of the third metal oxide layer and the second metal oxide layer are the same, and the composition materials of the fourth metal oxide layer and the first metal oxide layer are the same, the charge conduction directions of the first heterojunction and the second heterojunction are opposite, which is convenient for the first heterojunction to conduct charges to achieve the write operation of the rewritable memory, and enables the second heterojunction to conduct charges to achieve the erase operation of the rewritable memory. And it makes the data erase speed and write speed of the rewritable memory symmetric, that is, the data erase speed and data write speed of the rewritable memory are consistent. Both the first heterojunction and the second heterojunction are composed of two different metal oxide layers, which improves the data erase and write speeds of the rewritable memory.

[0018] Optionally, when the first electric field is applied to the rewritable memory, the first heterojunction is in a conducting state, the second heterojunction is in a reverse-biased cut-off state, and the charges in the channel layer pass through the tunneling layer and the second metal oxide layer and are stored in the first metal oxide layer to complete the data write operation of the rewritable memory. Wherein, the electric field direction of the first electric field points from the substrate to the channel layer. The beneficial effect is that the first electric field is applied to the rewritable memory, which is convenient for the first heterojunction to conduct charges to complete the data write operation of the rewritable memory.

[0019] Optionally, when the second electric field is applied to the rewritable memory, the second heterojunction is in a conducting state, the first heterojunction is in a reverse-biased cut-off state, and the charges in the second heterojunction pass through the tunneling layer and enter the channel layer to complete the data erase operation of the rewritable memory. Wherein, the electric field direction of the second electric field is opposite to the electric field direction of the first electric field. The beneficial effect is that the second electric field is applied to the rewritable memory, which is convenient for the second heterojunction to conduct charges to complete the data erase operation of the rewritable memory.

[0020] The present invention also provides a manufacturing method of a rewritable memory, including the steps:

[0021] S1: Provide a substrate, and deposit an insulating medium on the substrate to form a barrier layer;

[0022] S2: Form a first heterojunction in a first region on the top surface of the barrier layer, form a second heterojunction in a second region on the top surface of the barrier layer, and form a partition region between the first region and the second region;

[0023] S3: Deposit an insulating medium to form a tunneling layer, so that the tunneling layer covers the top surfaces of the first heterojunction, the second heterojunction, and the partition region to partition the first heterojunction and the second heterojunction;

[0024] S4: Form a channel layer on the top surface of the tunneling layer, and form a source electrode and a drain electrode at both ends on the top surface of the channel layer.

[0025] The beneficial effects of the manufacturing method of the erasable memory of the present invention are as follows:

[0026] In the manufacturing method of the erasable memory of the present invention, a first heterojunction and a second heterojunction are formed on the top surface of the blocking layer, and the two heterojunctions together serve as a charge storage medium, reducing the process complexity, improving the symmetry of the data erasing and data writing operations of the erasable memory, and increasing the data erasing and data writing speeds of the erasable memory; by covering the top surfaces of the first heterojunction, the second heterojunction, and the partition region with the tunneling layer to partition the first heterojunction and the second heterojunction, the lateral charge conduction between the first heterojunction and the second heterojunction is avoided, thereby reducing the dynamic power consumption of the erasable memory.

[0027] Optionally, in step S2, the step of forming a first heterojunction in a first region on the top surface of the blocking layer and forming a second heterojunction in a second region on the top surface of the blocking layer includes:

[0028] Deposit a first metal oxide on the top surface of the blocking layer to form a primary first metal oxide layer, and etch the primary first metal oxide layer to form a first metal oxide layer in the first region;

[0029] Deposit a second metal oxide on the first metal oxide layer to form a primary second metal oxide layer, and etch the primary second metal oxide layer to form a second metal oxide layer in the first region, so that the second metal oxide layer covers the first metal oxide layer.

[0030] Optionally, in step S2, the step of forming a first heterojunction in a first region on the top surface of the blocking layer and forming a second heterojunction in a second region on the top surface of the blocking layer further includes:

[0031] Deposit a third metal oxide on the top surface of the blocking layer to form a primary third metal oxide layer, and etch the primary third metal oxide layer to form a third metal oxide layer in the second region;

[0032] Deposit a fourth metal oxide on the third metal oxide layer to form a raw fourth metal oxide layer, etch the raw fourth metal oxide layer to form a fourth metal oxide layer in the second region, and make the fourth metal oxide layer cover the third metal oxide layer. The first metal oxide and the fourth metal oxide are made of the same material, and the second metal oxide and the third metal oxide are made of the same material.

[0033] Optionally, the first metal oxide includes any one of zinc oxide, indium gallium zinc oxide, indium oxide, gallium oxide, aluminum-doped zinc oxide, and tin dioxide, and the second metal oxide includes any one of nickel oxide, cuprous oxide, and aluminum-doped cuprous oxide.

[0034] Optionally, in step S2, the step of forming a partition region between the first region and the second region includes removing the material at the contact end of the first heterojunction and the second heterojunction through photolithography and etching techniques to form the partition region. Description of the Drawings

[0035] Figure 1 It is a cross-sectional view of the erasable memory according to the embodiment of the present invention;

[0036] Figure 2 It is a flowchart of the manufacturing method of the erasable memory according to the embodiment of the present invention;

[0037] Figure 3 It is a cross-sectional view of the structure formed after depositing a barrier layer according to the embodiment of the present invention;

[0038] Figure 4 In the first embodiment of the present invention Figure 3 It is a cross-sectional view of the structure formed after depositing a first metal oxide on the basis of the shown structure;

[0039] Figure 5 For Figure 4 It is a cross-sectional view of the structure formed after etching a first metal oxide layer on the basis of the shown structure;

[0040] Figure 6 For Figure 5 It is a cross-sectional view of the structure formed after depositing a second metal oxide on the basis of the shown structure;

[0041] Figure 7 For Figure 6 It is a cross-sectional view of the structure formed after etching a second metal oxide layer on the basis of the shown structure;

[0042] Figure 8 For Figure 7 It is a cross-sectional view of the structure formed after depositing a third metal oxide on the basis of the shown structure;

[0043] Figure 9 It is a cross-sectional view of the structure formed after etching the third metal oxide layer on the structure shown below; Figure 8

[0044] Figure 10 It is a cross-sectional view of the structure formed after depositing the fourth metal oxide on the structure shown below; Figure 9

[0045] Figure 11 It is a cross-sectional view of the structure formed after etching the fourth metal oxide layer on the structure shown below; Figure 10

[0046] Figure 12 This is a cross-sectional view of the structure formed after depositing the third metal oxide in the second embodiment of the present invention on the structure shown below; Figure 5

[0047] Figure 13 It is a cross-sectional view of the structure formed after etching the third metal oxide layer on the structure shown below; Figure 12

[0048] Figure 14 It is a cross-sectional view of the structure formed after depositing the second metal oxide on the structure shown below; Figure 13

[0049] Figure 15 It is a cross-sectional view of the structure formed after forming a partition region on the structure shown below; Figure 11

[0050] Figure 16 It is a cross-sectional view of the structure formed after depositing a tunneling layer on the structure shown below; Figure 15

[0051] Figure 17 It is a cross-sectional view of the structure formed after depositing a channel layer on the structure shown below; Figure 16

[0052] Figure 18 It is a cross-sectional view of the structure formed after forming a source electrode and a drain electrode on the structure shown below. Figure 17 Detailed implementation manners

[0053] ​​​​​​​​​​In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0054] In view of the problems existing in the prior art, an embodiment of the present invention provides an erasable and writable memory. Figure 1 is a cross-sectional structural diagram of an erasable memory according to an embodiment of the present invention, referring to Figure 1 The erasable memory of the present invention comprises a substrate 1, a barrier layer 2, a first heterojunction 3, a second heterojunction 4, a tunneling layer 5, a channel layer 6, a source electrode 7 and a drain electrode 8;

[0055] The substrate 1 serves as the gate of the erasable and writable memory;

[0056] The barrier layer 2 is disposed on the top surface of the substrate 1;

[0057] The first heterojunction 3 and the second heterojunction 4 are respectively arranged at two opposite ends of the top surface of the barrier layer 2, the first heterojunction 3 and the second heterojunction 4 have a unidirectional charge conduction characteristic, and the charge conduction direction of the first heterojunction 3 is opposite to the charge conduction direction of the second heterojunction 4, and the first heterojunction 3 and the second heterojunction 4 are respectively used for data writing operation and data erasing operation of the erasable memory;

[0058] The front cross-section of the tunneling layer 5 is in a "T" shape, and the tunneling layer 5 includes a horizontal portion 52 and a vertical portion 51, wherein the horizontal portion 52 covers the top surface of the first heterojunction 3 and the second heterojunction 4, and the vertical portion 51 is used to separate the first heterojunction 3 and the second heterojunction 4 to prevent lateral charge conduction between the first heterojunction 3 and the second heterojunction 4;

[0059] The channel layer 6 covers the top surface of the tunnel layer 5 and is used for charge migration;

[0060] The source electrode 7 and the drain electrode 8 of the channel layer 6 are respectively arranged at two opposite ends of the top surface of the channel layer 6 .

[0061] The advantages of the erasable memory of the present invention are:

[0062] The first heterojunction 3 and the second heterojunction 4 are respectively disposed at opposite ends of the top surface of the blocking layer 2. The first heterojunction 3 and the second heterojunction 4 are respectively used for the data writing operation and the data erasing operation of the erasable memory; by using the first heterojunction 3 and the second heterojunction 4 with the characteristic of unidirectional charge conduction as the data writing and data erasing channels of the erasable memory respectively, and the charge conduction directions of the first heterojunction 3 and the second heterojunction 4 are opposite, so that the data writing and data erasing of the erasable memory are more stable and symmetrical, the data erasing speed and the data writing speed of the erasable memory are consistent, and the data erasing and data writing speeds of the erasable memory are improved; the vertical portion 51 of the tunneling layer 5 separates the first heterojunction 3 and the second heterojunction 4, avoiding the lateral charge conduction between the first heterojunction 3 and the second heterojunction 4, thereby reducing the dynamic power consumption of the erasable memory.

[0063] As an optional implementation manner of the present invention, as Figure 1 shown, the first heterojunction 3 includes a first metal oxide layer 30 and a second metal oxide layer 31. The first metal oxide layer 30 is connected to the top surface of the blocking layer 2. The bottom surface of the second metal oxide layer 31 is connected to the first metal oxide layer 30, and the top surface of the second metal oxide layer 31 is connected to the horizontal portion 52. The materials of the first metal oxide layer 30 and the second metal oxide layer 31 are different.

[0064] As an optional implementation manner of the present invention, as Figure 1 shown, the second heterojunction 4 includes a third metal oxide layer 40 and a fourth metal oxide layer 41. The third metal oxide layer 40 is connected to the top surface of the blocking layer 2. The bottom surface of the fourth metal oxide layer 41 is connected to the third metal oxide layer 40, and the top surface of the fourth metal oxide layer 41 is connected to the horizontal portion 52;

[0065] The third metal oxide layer 40 has the same composition material as the second metal oxide layer 31, and the fourth metal oxide layer 41 has the same composition material as the first metal oxide layer 30. The advantage is that since both the first heterojunction 3 and the second heterojunction 4 have the characteristic of unidirectional charge conduction, and the third metal oxide layer 40 has the same composition material as the second metal oxide layer 31, and the fourth metal oxide layer 41 has the same composition material as the first metal oxide layer 30, the charge conduction directions of the first heterojunction 3 and the second heterojunction 4 are opposite, which is convenient for the first heterojunction 3 to conduct charge to realize the writing operation of the erasable memory, and enables the second heterojunction 4 to conduct charge to realize the erasing operation of the erasable memory; both the first heterojunction 3 and the second heterojunction 4 are composed of two different metal oxide layers, which improves the data erasing and data writing speeds of the erasable memory.

[0066] In some alternative embodiments, the first metal oxide layer 30 and the fourth metal oxide layer 41 have the same thickness, and the second metal oxide layer 31 and the third metal oxide layer 40 have the same thickness, such that the charge conduction directions of the first heterojunction 3 and the second heterojunction 4 are opposite, and the data erasure speed and the data writing speed of the erasable memory are made consistent, ensuring the symmetry of the data erasure and writing speeds, that is, the data erasure speed and the writing speed of the erasable memory are consistent.

[0067] As an alternative embodiment of the present invention, when a positive voltage is applied to the substrate 1 end of the erasable memory, the erasable memory is applied with a first electric field, and the electric field direction is from the substrate 1 to the channel layer 6. The first heterojunction 3 is in a conducting state, the second heterojunction 4 is in a reverse-biased cut-off state, and the charges in the channel layer 6 pass through the tunneling layer 5 and enter the first heterojunction 3. After the charges enter the first heterojunction 3, they longitudinally pass through the second metal oxide layer 31 and enter the first metal oxide layer 30, and after the charges enter the first metal oxide layer 30, they are stored in the first metal oxide layer 30, completing the data writing operation of the erasable memory. The advantage is that the erasable memory is applied with the first electric field, which facilitates the first heterojunction to conduct charges to complete the data writing operation of the erasable memory.

[0068] As an alternative embodiment of the present invention, when a negative voltage is applied to the substrate 1 end of the erasable memory, the erasable memory is applied with a second electric field, the electric field direction of the second electric field is opposite to the electric field direction of the first electric field, and the electric field direction of the second electric field is from the channel layer 6 to the substrate 1. The second heterojunction 4 is in a conducting state, the first heterojunction 3 is in a reverse-biased cut-off state, and the charges in the second heterojunction 4 longitudinally pass through the tunneling layer 5 and enter the channel layer 6, completing the data erasure operation of the erasable memory. The advantage is that the erasable memory is applied with the second electric field, which facilitates the second heterojunction to conduct charges to complete the data erasure operation of the erasable memory.

[0069] It should be noted that the charges in the above data writing operation and erasure operation of the erasable memory refer to negative charges.

[0070] Figure 2 is a flowchart of the manufacturing method of the erasable memory according to the embodiment of the present invention. Referring to Figure 2 the present invention also provides a manufacturing method of an erasable memory, including the steps of:

[0071] S1: Provide a substrate, and deposit an insulating medium on the substrate to form a barrier layer;

[0072] S2: Form a first heterojunction in a first region on the top surface of the barrier layer, form a second heterojunction in a second region on the top surface of the barrier layer, and form a partition region between the first region and the second region;

[0073] S3: Deposit an insulating dielectric to form a tunneling layer, so that the tunneling layer covers the top surface of the first heterojunction, the top surface of the second heterojunction, and the partition region, to partition the first heterojunction and the second heterojunction;

[0074] S4: Form a channel layer on the top surface of the tunneling layer, and form a source electrode and a drain electrode at both ends on the top surface of the channel layer.

[0075] In some alternative embodiments, the substrate 1 is any one of a low-resistance silicon substrate, a silicon-on-insulator substrate, a tantalum nitride substrate, a silicon dioxide substrate, a silicon substrate, and a titanium nitride substrate.

[0076] In some alternative embodiments, the present invention selects a low-resistance silicon substrate as the substrate 1.

[0077] Figure 3 It is a cross-sectional view of the structure formed after depositing the barrier layer for the embodiment of the present invention.

[0078] In some alternative embodiments, referring to Figure 3 , the step of depositing an insulating dielectric material on the substrate in step S1 to form the barrier layer is specifically to deposit the barrier layer 2 on the top surface of the substrate 1 by atomic layer deposition technology.

[0079] In some alternative embodiments, the material of the barrier layer 2 is silicon oxide (SiO 2 ), hafnium dioxide (HfO 2 ), tantalum pentoxide (Ta 2 O 5 ), titanium dioxide (TiO 2 ), or a laminated combination of any one or more of hafnium zirconium oxide (HfZrO 4 ).

[0080] In some alternative embodiments, the present invention is not limited to forming the barrier layer 2 on the substrate 1 by atomic layer deposition technology, and the barrier layer 2 can also be formed by any one of chemical vapor deposition technology, physical vapor deposition technology, pulsed laser deposition technology, and electron beam evaporation technology.

[0081] In the first embodiment of the present invention, in step S2, the step of forming a first heterojunction in the first region on the top surface of the barrier layer and forming a second heterojunction in the second region on the top surface of the barrier layer includes:

[0082] Deposit a first metal oxide on the top surface of the barrier layer to form a primary first metal oxide layer, and etch the primary first metal oxide layer to form a first metal oxide layer in the first region;

[0083] Deposit a second metal oxide on the first metal oxide layer to form a primary second metal oxide layer, etch the primary second metal oxide layer to form a second metal oxide layer in the first region, and cause the second metal oxide layer to cover the first metal oxide layer.

[0084] In step S2, the step of forming a first heterojunction in a first region on the top surface of the barrier layer and forming a second heterojunction in a second region on the top surface of the barrier layer further includes:

[0085] Deposit a third metal oxide on the top surface of the barrier layer to form a primary third metal oxide layer, and etch the primary third metal oxide layer to form a third metal oxide layer in the second region;

[0086] Deposit a fourth metal oxide on the third metal oxide layer to form a primary fourth metal oxide layer, etch the primary fourth metal oxide layer to form a fourth metal oxide layer in the second region, and cause the fourth metal oxide layer to cover the third metal oxide layer. The first metal oxide and the fourth metal oxide are made of the same material, and the second metal oxide and the third metal oxide are made of the same material.

[0087] Specifically, the steps of forming the first heterojunction and the second heterojunction are as follows:

[0088] S201: Form a first metal oxide layer;

[0089] S202: Form a second metal oxide layer;

[0090] S203: Form a third metal oxide layer;

[0091] S204: Form a fourth metal oxide layer.

[0092] Figure 4 This is a cross-sectional view of the structure formed after depositing a first metal oxide on the basis of the structure shown in Figure 3 the first embodiment of the present invention; Figure 5 This is Figure 4 a cross-sectional view of the structure formed after etching the first metal oxide layer on the basis of the structure shown in.

[0093] In some alternative embodiments, referring to Figure 4 and Figure 5 , the step of forming the first metal oxide layer in step S201 includes:

[0094] Deposit a first metal oxide on the top surface of the barrier layer 2 by atomic layer deposition technology to form a primary first metal oxide layer 301, and the pattern formed after depositing the primary first metal oxide layer 301 is as shown in Figure 4 ;

[0095] Etch the original first metal oxide layer 301 through photolithography and etching techniques to form the first metal oxide layer 30 in the first region, and the formed pattern is as Figure 5 .

[0096] In some specific embodiments of the present invention, after depositing and forming the original first metal oxide layer 301 on the barrier layer 2, spin-coat photoresist on the top surface of the original first metal oxide layer 301, and form a photoresist pattern for defining the shape of the original first metal oxide layer 301 through a photolithography process including exposure and development; use the photoresist as a mask, and etch the original first metal oxide layer 301 by any one of dry etching, ion milling etching, plasma etching, reactive ion etching, laser ablation, inductively coupled plasma etching, and wet etching using an etchant solution to obtain the first metal oxide layer 30 located in the first region.

[0097] Figure 6 For Figure 5 a cross-sectional view of the structure formed after depositing a second metal oxide on the basis of the structure shown; Figure 7 For Figure 6 a cross-sectional view of the structure formed after etching out the second metal oxide layer on the basis of the structure shown.

[0098] In some alternative embodiments, referring to Figure 6 and Figure 7 , the step of forming the second metal oxide layer in step S202 includes:

[0099] Deposit a second metal oxide on the upper surface of the first metal oxide layer 30 and the upper surface of the barrier layer 2 through atomic layer deposition technology to form the original second metal oxide layer 311, and the formed pattern is as Figure 6 ;

[0100] Etch the original second metal oxide layer 311 through photolithography and etching techniques to form the second metal oxide layer 31 in the first region, and make the second metal oxide layer 31 cover the first metal oxide layer 30, and the formed pattern is as Figure 7 .

[0101] The specific steps of forming the second metal oxide layer 31 in step S202 may refer to the specific steps of forming the first metal oxide layer 30, which will not be elaborated here.

[0102] Figure 8 For Figure 7 a cross-sectional view of the structure formed after depositing a third metal oxide on the basis of the structure shown; Figure 9 For Figure 8 a cross-sectional view of the structure formed after etching out the third metal oxide layer on the basis of the structure shown.

[0103] In some alternative embodiments, referring toFigure 8 and Figure 9 In the step S203 of forming the third metal oxide layer, the steps include:

[0104] Depositing a third metal oxide on the top surfaces of the barrier layer 2 and the second metal oxide layer 31 by atomic layer deposition technology to form a primary third metal oxide layer 401, and the formed pattern is as shown in Figure 8 ;

[0105] Etching the primary third metal oxide layer 401 by photolithography and etching technologies to form a third metal oxide layer 40 in the second region, and the formed pattern is as shown in Figure 9 .

[0106] Figure 10 is a cross-sectional view of the structure formed after depositing a fourth metal oxide on the basis of the structure shown in Figure 9 ; Figure 11 is a cross-sectional view of the structure formed after etching the fourth metal oxide layer on the basis of the structure shown in Figure 10 .

[0107] In some alternative embodiments, referring to Figure 10 and Figure 11 the steps of forming the fourth metal oxide layer in the step S204 include:

[0108] Depositing a fourth metal oxide on the second metal oxide layer 31 and the third metal oxide layer 40 by atomic layer deposition technology to form a primary fourth metal oxide layer 411, and the formed pattern is as shown in Figure 10 ;

[0109] Etching the primary fourth metal oxide layer 411 by photolithography and etching technologies to form a fourth metal oxide layer 41 in the second region, and the fourth metal oxide layer 41 covers the third metal oxide layer 40, and the formed pattern is as shown in Figure 11 . Wherein, the first metal oxide and the fourth metal oxide are made of the same material, and the second metal oxide and the third metal oxide are made of the same material.

[0110] In the second embodiment of the present invention, the steps of forming the first heterojunction 3 and the second heterojunction 4 are:

[0111] S211: Forming a first metal oxide layer;

[0112] S212: Forming a third metal oxide layer;

[0113] S213: Forming a second metal oxide layer;

[0114] S214: Forming a fourth metal oxide layer.

[0115] In some alternative embodiments, referring to Figure 4and Figure 5 In the step S211 of forming the first metal oxide layer, the steps include:

[0116] Depositing a first metal oxide on the barrier layer 2 by atomic layer deposition technology to form a primary first metal oxide layer 301, and the formed pattern is as shown in Figure 4 ;

[0117] Etching the primary first metal oxide layer 301 by photolithography and etching technologies to form a first metal oxide layer 30 in the first region, and the formed pattern is as shown in Figure 5 .

[0118] Figure 12 FIG. is a cross-sectional view of the structure formed after depositing a third metal oxide on the structure shown in Figure 5 for the second embodiment of the present invention; Figure 13 FIG. is a cross-sectional view of the structure formed after etching out the third metal oxide layer on the structure shown in Figure 12 for the second embodiment of the present invention.

[0119] In some alternative embodiments, referring to Figure 12 and Figure 13 the steps of forming the third metal oxide layer in the step S212 include:

[0120] Depositing a third metal oxide on the barrier layer 2 and the first metal oxide layer 30 by atomic layer deposition technology to form a primary third metal oxide layer 401, and the formed pattern is as shown in Figure 12 ;

[0121] Etching the primary third metal oxide layer 401 by photolithography and etching technologies to form a third metal oxide layer 40 in the second region, and the formed pattern is as shown in Figure 13 .

[0122] Figure 14 FIG. is a cross-sectional view of the structure formed after depositing a second metal oxide on the structure shown in Figure 13 for some alternative embodiments.

[0123] In some alternative embodiments, referring to Figure 14 and Figure 9 the steps of forming the second metal oxide layer in the step S213 include:

[0124] Depositing a second metal oxide on the first metal oxide layer 30 and the third metal oxide layer 40 by atomic layer deposition technology to form a primary second metal oxide layer 311, and the formed pattern is as shown in Figure 14 ;

[0125] Etching the primary second metal oxide layer 311 by photolithography and etching technologies to form a second metal oxide layer 31 in the first region, and the formed pattern is as shown inFigure 9 。

[0126] In some alternative embodiments, with reference to Figure 10 and Figure 11 , the step of forming the fourth metal oxide layer in step S214 includes:

[0127] With reference to Figure 10 , deposit a fourth metal oxide on the second metal oxide layer 31 and the third metal oxide layer 40 by atomic layer deposition technology to form a primary fourth metal oxide layer 411, and the formed pattern is as shown in Figure 10 ;

[0128] Etch the primary fourth metal oxide layer 411 by photolithography and etching techniques to form a fourth metal oxide layer 41 in the second region, and the formed pattern is as shown in Figure 11 .

[0129] As an alternative embodiment of the present invention, the first metal oxide and the fourth metal oxide include any one of zinc oxide (ZnO), indium gallium zinc oxide (IGZO), indium oxide (In 2 O 3 ), gallium oxide (Ga 2 O 3 ), aluminum-doped zinc oxide (AlZnO), and tin dioxide (SnO 2 ) having electron-conducting properties.

[0130] The second metal oxide and the third metal oxide include any one of nickel oxide (NiO), cuprous oxide (Cu 2 O), aluminum-doped cuprous oxide (CuAlO 2 ), and stannous oxide (SnO) having hole-conducting properties.

[0131] Figure 15 It is a schematic diagram after the first heterojunction and the second heterojunction of the embodiment of the present invention form a partition region.

[0132] In some alternative embodiments, with reference to Figure 15 , in step S2, the specific steps of forming a partition region between the first region and the second region include:

[0133] Remove the material at the contact end of the first heterojunction 3 and the second heterojunction 4 by photolithography and etching techniques. Specifically, take the top surface of the second metal oxide layer 31 and the top surface of the fourth metal oxide layer 41 as the etching starting surface, and take the top surface of the barrier layer 2 as the etching end surface, and etch a part of the second metal oxide layer 31, a part of the fourth metal oxide layer 41, a part of the first metal oxide layer 30, and a part of the third metal oxide layer 40 at the contact end of the two heterojunctions to form a partition region.

[0134] In some embodiments, the present invention may select zinc oxide (ZnO) as the constituent material of the first metal oxide layer 30 and the second metal oxide layer 31, and may select nickel oxide (NiO) as the constituent material of the second metal oxide layer 31 and the third metal oxide layer 40.

[0135] Figure 16 For Figure 15 A cross-sectional view of the structure formed after depositing a tunneling layer on the structure shown.

[0136] In some alternative embodiments, referring to Figure 16 , the step S3 of depositing an insulating medium to form a tunneling layer to cover the top surface of the first heterojunction, the top surface of the second heterojunction, and the partition region to partition the first heterojunction and the second heterojunction includes:

[0137] Depositing an insulating medium on the top surfaces of the first heterojunction 3 and the second heterojunction 4 by atomic layer deposition technology to form an insulating medium layer, such that the insulating medium layer covers the top surfaces of the first heterojunction 3 and the second heterojunction 4, and a part of the insulating medium layer completely fills the partition region to form the above-mentioned tunneling layer 5, and the formed pattern is as shown in Figure 16 .

[0138] Referring to Figure 16 , the positive cross-sectional shape of the tunneling layer 5 is in a "T" shape. The tunneling layer 5 includes a horizontal portion 52 and a vertical portion 51. The horizontal portion 52 covers the top surfaces of the second metal oxide layer 31 and the fourth metal oxide layer 41, and the vertical portion 51 is inserted into the partition region to partition the first heterojunction 3 and the second heterojunction 4, and the shape of the vertical portion 51 is the same as the shape of the partition region.

[0139] It should be added that the present invention is not limited to depositing an insulating medium by atomic layer deposition technology to form the tunneling layer 5, and an insulating medium can also be deposited by any one of chemical vapor deposition, physical vapor deposition, pulsed laser deposition, and electron beam evaporation to form the tunneling layer 5.

[0140] In some embodiments of the present invention, the insulating medium that is the constituent material of the tunneling layer 5 is silicon oxide (SiO 2 ), hafnium dioxide (HfO 2 ), tantalum pentoxide (Ta 2 O 5 ), titanium dioxide (TiO 2 ), and hafnium zirconium oxide (HfZrO 4 ) or a laminated combination of any one or more of them.

[0141] Figure 17 For Figure 16 A cross-sectional view of the structure formed after depositing a channel layer on the structure shown.

[0142] In some embodiments of the present invention, referring to Figure 17 , in step S4, the specific steps of forming the channel layer on the top surface of the tunneling layer are as follows:

[0143] Deposit the channel layer 6 on the top surface of the tunneling layer 5 by physical vapor deposition process, and the formed pattern is as shown in Figure 17 .

[0144] It should be noted that the present invention is not limited to depositing the channel layer 6 by physical vapor deposition process, and the channel layer 6 can also be deposited by processes such as atomic layer deposition, pulsed laser deposition, and electron beam evaporation.

[0145] In some embodiments of the present invention, the constituent material of the channel layer 6 is any one of indium gallium zinc oxide (IGZO), indium oxide (In 2 O 3 ), gallium oxide (Ga 2 O 3 ), zinc oxide (ZnO), aluminum-doped zinc oxide (AlZnO), nickel oxide (NiO), and cuprous oxide (Cu 2 O).

[0146] Figure 18 For Figure 17 is a cross-sectional view of the structure formed after forming the source electrode and the drain electrode on the basis of the shown structure.

[0147] Referring to Figure 18 , in step S4, the specific steps of forming the source electrode and the drain electrode at both ends on the top surface of the channel layer are as follows:

[0148] Deposit a metal material on the top surface of the channel layer 6 by physical vapor deposition process. Then, etch the metal material through photolithography and etching techniques to form the source electrode 7 and the drain electrode 8, and the formed pattern is as shown in Figure 18 .

[0149] In summary, the advantages of the manufacturing method of the erasable memory of the present invention are:

[0150] A method for manufacturing a rewritable memory of the present invention forms a first heterojunction 3 in a first region on the top surface of a blocking layer 2, forms a second heterojunction 4 in a second region on the top surface of the blocking layer 2, and sets a partition region between the first heterojunction 3 and the second heterojunction 4. The first region and the second region are symmetric with respect to the partition region, so as to form the first heterojunction 3 and the second heterojunction 4 on the blocking layer 2. The two heterojunctions together serve as a charge storage medium, reducing the process complexity, improving the symmetry of data erasure and data writing operations of the rewritable memory, and increasing the data erasure and data writing speeds of the rewritable memory. The vertical portion 51 of a tunneling layer 5 partitions the first heterojunction 3 and the second heterojunction 4, avoiding the lateral charge conduction between the first heterojunction 3 and the second heterojunction 4, thereby reducing the dynamic power consumption of the rewritable memory.

[0151] Although the embodiments of the present invention have been described in detail above, it is obvious to those skilled in the art that various modifications and changes can be made to these embodiments. However, it should be understood that such modifications and changes are all within the scope and spirit of the present invention in the claims. Moreover, the present invention described herein may have other embodiments and can be implemented or realized in various ways.

Claims

1. A rewritable memory, It is characterized in that It includes a substrate, a barrier layer, a first heterojunction, a second heterojunction, a tunneling layer, a channel layer, a source electrode and a drain electrode; The substrate serves as a gate of the erasable and writable memory; The barrier layer is disposed on the top surface of the substrate; The first heterojunction and the second heterojunction are respectively arranged at two opposite ends of the top surface of the barrier layer, the first heterojunction and the second heterojunction have a unidirectional charge conduction characteristic, and the charge conduction direction of the first heterojunction is opposite to the charge conduction direction of the second heterojunction, and the first heterojunction and the second heterojunction are respectively used for data writing operation and data erasing operation of the erasable memory; The tunneling layer includes a horizontal portion and a vertical portion, the horizontal portion covers the top surfaces of the first heterojunction and the second heterojunction, and the vertical portion is used to separate the first heterojunction and the second heterojunction to avoid lateral charge conduction between the first heterojunction and the second heterojunction; The channel layer covers the top surface of the tunnel layer and is used for charge migration; The channel layer source and the drain are respectively arranged at two opposite ends of the top surface of the channel layer.

2. The erasable and writable memory according to claim 1, It is characterized in that The first heterojunction includes a first metal oxide layer and a second metal oxide layer, the first metal oxide layer is connected to the top surface of the barrier layer, the bottom surface of the second metal oxide layer is connected to the first metal oxide layer, the top surface of the second metal oxide layer is connected to the horizontal portion, and the first metal oxide layer and the second metal oxide layer have different constituent materials.

3. The erasable and writable memory as claimed in claim 2, It is characterized in that The second heterojunction includes a third metal oxide layer and a fourth metal oxide layer, the third metal oxide layer is connected to the top surface of the barrier layer, the bottom surface of the fourth metal oxide layer is connected to the third metal oxide layer, and the top surface of the fourth metal oxide layer is connected to the horizontal portion; The third metal oxide layer is made of the same material as the second metal oxide layer, and the fourth metal oxide layer is made of the same material as the first metal oxide layer.

4. The erasable and writable memory as claimed in claim 3, It is characterized in that When the first electric field is applied to the erasable and writable memory, the first heterojunction is in an on state, the second heterojunction is in a reverse-biased cut-off state, and the charges in the channel layer are stored in the first metal oxide layer after passing through the tunneling layer and the second metal oxide layer, thereby completing the data writing operation of the erasable and writable memory, wherein the electric field direction of the first electric field is from the substrate to the channel layer.

5. The erasable and writable memory as claimed in claim 4, It is characterized in that When a second electric field is applied to the erasable and writable memory, the second heterojunction is in an on state, the first heterojunction is in a reverse-biased cut-off state, and the charges in the second heterojunction pass through the tunneling layer into the channel layer, thereby completing the data erasing operation of the erasable and writable memory, wherein the electric field direction of the second electric field is opposite to that of the first electric field.

6. A manufacturing method of a rewritable memory for manufacturing the rewritable memory according to any one of claims 1 to 5, characterized in that, it includes the steps of: S1: Providing a substrate, and depositing an insulating medium on the substrate to form a barrier layer; S2: Forming a first heterojunction in a first region on the top surface of the barrier layer, forming a second heterojunction in a second region on the top surface of the barrier layer, and forming a partition region between the first region and the second region; S3: Depositing an insulating medium to form a tunneling layer, so that the tunneling layer covers the top surface of the first heterojunction, the top surface of the second heterojunction and the partition region to isolate the first heterojunction and the second heterojunction; S4: Forming a channel layer on the top surface of the tunneling layer, and forming a source electrode and a drain electrode at both ends on the top surface of the channel layer.

7. The manufacturing method according to claim 6, characterized in that, in the step S2, the steps of forming a first heterojunction in a first region on the top surface of the barrier layer and forming a second heterojunction in a second region on the top surface of the barrier layer include: Depositing a first metal oxide on the top surface of the barrier layer to form a primary first metal oxide layer, and etching the primary first metal oxide layer to form a first metal oxide layer in the first region; Depositing a second metal oxide on the first metal oxide layer to form a primary second metal oxide layer, and etching the primary second metal oxide layer to form a second metal oxide layer in the first region, so that the second metal oxide layer covers the first metal oxide layer.

8. The manufacturing method according to claim 7, characterized in that, in the step S2, the steps of forming a first heterojunction in a first region on the top surface of the barrier layer and forming a second heterojunction in a second region on the top surface of the barrier layer further include: Depositing a third metal oxide on the top surface of the barrier layer to form a primary third metal oxide layer, and etching the primary third metal oxide layer to form a third metal oxide layer in the second region; Depositing a fourth metal oxide on the third metal oxide layer to form a primary fourth metal oxide layer, and etching the primary fourth metal oxide layer to form a fourth metal oxide layer in the second region, so that the fourth metal oxide layer covers the third metal oxide layer, and the first metal oxide and the fourth metal oxide are made of the same material, and the second metal oxide and the third metal oxide are made of the same material.

9. The manufacturing method according to claim 8, characterized in that, the first metal oxide includes any one of zinc oxide, indium gallium zinc oxide, indium oxide, gallium oxide, aluminum-doped zinc oxide and tin dioxide, and the second metal oxide includes any one of nickel oxide, cuprous oxide and aluminum-doped cuprous oxide.

10. The manufacturing method according to claim 6, characterized in that, in the step S2, the step of forming a partition region between the first region and the second region includes removing the material at the contact end of the first heterojunction and the second heterojunction by photolithography and etching techniques to form the partition region.

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