A PUF unit circuit

Abstract

This invention provides a PUF (Power Activated Function) unit circuit, comprising: a process-sensitive circuit that outputs a circuit difference signal when a reset control signal is detected to be at a specified reset level; a positive feedback circuit that amplifies the circuit difference signal; a positive feedback suppression circuit that suppresses the positive feedback effect of the positive feedback circuit when a suppression signal is detected to be at a specified suppression level; and an output circuit that outputs the difference signal; wherein the positive feedback circuit is connected to the process-sensitive circuit; the positive feedback suppression circuit is connected to the positive feedback circuit; and the output circuit is connected to the positive feedback circuit.

Description

Technical Field

[0001] This invention relates to the fields of authentication, unique code identification, and key generation, and specifically to a PUF unit circuit. Background Technology

[0002] A physically unclonable function (PUF) refers to a device whose microstructure varies slightly due to unpredictable and uncontrollable random physical factors during manufacturing. This results in independent challenge-response relationships between device units in the input and output signals. Because it is impossible to clone identical device structures, this relationship is called a physically unclonable function. Technically, a PUF is implemented by a circuit, component, process, or other entity capable of generating output (such as a digital, word, or cloning-resistant function). Typically, a PUF can be generated based on the inherent physical characteristics of the device, such as the individual physical characteristics of a transistor, like its threshold voltage, which vary during manufacturing due to localized process variations. PUFs do not need to be stored within the device because they can be repeatedly generated. Cloning a device with a PUF implementation to generate the same PUF output as another device is virtually impossible.

[0003] Currently, the mainstream PUFs include SRAM PUF, Butterfly PUF, Ring-Swept PUF, and Arbitration PUF, and they are mainly used in three areas: authentication, unique identifiers, and key generation and management. For the same challenge signal and PUF, different response signals will still appear, which is a manifestation of the instability of PUFs.

[0004] Currently, the PUF mainly used in the market is a standard digital storage unit provided by foundry or other third-party manufacturers. This type of unit has a high proportion of unstable bits and is a circuit structure oriented towards storage and retrieval scenarios. When applied to PUF scenarios, the digital circuit part is required to correct errors and restore unstable bits. However, the high rate of unstable bit error correction will lead to an increase in chip area and power consumption. Summary of the Invention

[0005] This invention provides a PUF cell circuit that improves the stability, robustness, and noise tolerance of the SRAM PUF circuit, reduces the error rate of the PUF cell, and decreases the chip area and power consumption.

[0006] To achieve the above objectives, in one aspect, embodiments of the present invention provide a PUF unit circuit, including: a process-sensitive circuit that outputs a circuit difference signal when a reset control signal is detected to be at a specified reset level; a positive feedback circuit that amplifies the circuit difference signal; a positive feedback suppression circuit that suppresses the positive feedback effect of the positive feedback circuit when a suppression signal is detected to be at a specified suppression level; and an output circuit that outputs the difference signal.

[0007] The positive feedback circuit is connected to the process-sensitive circuit;

[0008] The positive feedback suppression circuit is connected to the positive feedback circuit;

[0009] The output circuit is connected to the positive feedback circuit.

[0010] Furthermore, the process-sensitive circuit includes: a first branch circuit that outputs a first branch signal when the reset control signal is detected to be at the specified reset level; and a second branch circuit that outputs a second branch signal when the reset control signal is detected to be at the specified reset level; the first branch signal and the second branch signal constitute the difference signal;

[0011] Both the first branch signal and the second branch signal are connected to the positive feedback circuit.

[0012] Furthermore, it also includes: a timing controller;

[0013] The output of the timing controller is connected to the input terminal of the suppression signal of the positive feedback suppression circuit; when the timing controller detects that the reset control signal is at the specified reset level, it sets and maintains the suppression signal at the specified suppression level for a specified delay time; after the specified delay time, it sets the suppression signal to a level state opposite to the specified suppression level.

[0014] Furthermore, the timing controller is specifically a delay repeater;

[0015] The output of the delay repeater is connected to the input terminal of the suppression signal of the positive feedback suppression circuit; the delay repeater outputs the reset control signal as the suppression signal after a delay.

[0016] Furthermore, the delay repeater includes: an even number of inverters connected in series, wherein the output port of any inverter in the series is connected to the input port of the adjacent inverter connected in series after the inverter; the input of the first inverter in the series is the reset control signal, and the output of the last inverter in the series is connected to the input of the suppression signal of the positive feedback suppression circuit.

[0017] Furthermore,

[0018] The first branch circuit includes: a first P-channel field-effect transistor and a third P-channel field-effect transistor;

[0019] The second branch circuit includes: a second P-channel MOSFET and a fourth P-channel MOSFET;

[0020] The positive feedback circuit includes: a first N-channel field-effect transistor and a fourth N-channel field-effect transistor;

[0021] The positive feedback suppression circuit includes: a third N-channel field-effect transistor and a sixth N-channel field-effect transistor;

[0022] The source of the first P-channel field-effect transistor is connected to a positive power supply;

[0023] The reset control signal is input to the gate of the first P-channel MOSFET;

[0024] The drain of the first P-channel field-effect transistor is connected to the source of the third P-channel field-effect transistor;

[0025] The drain of the third P-channel field-effect transistor is connected to the drain of the first N-channel field-effect transistor.

[0026] The drain of the third P-channel field-effect transistor is connected to the gate of the fourth N-channel field-effect transistor.

[0027] The gate of the third P-channel MOSFET is connected to the gate of the first N-channel MOSFET.

[0028] The source of the second P-channel MOSFET is connected to a positive power supply;

[0029] The reset control signal is input to the gate of the second P-channel MOSFET;

[0030] The drain of the second P-channel field-effect transistor is connected to the source of the fourth P-channel field-effect transistor;

[0031] The drain of the fourth P-channel field-effect transistor is connected to the drain of the fourth N-channel field-effect transistor.

[0032] The drain of the fourth P-channel field-effect transistor is connected to the gate of the first N-channel field-effect transistor.

[0033] The gate of the fourth P-channel field-effect transistor is connected to the gate of the fourth N-channel field-effect transistor.

[0034] The source of the first N-channel field-effect transistor is connected to the ground plane;

[0035] The source of the fourth N-channel field-effect transistor is connected to the ground plane;

[0036] The drain of the third N-channel field-effect transistor is connected to the drain of the first N-channel field-effect transistor;

[0037] The source of the third N-channel field-effect transistor is connected to the ground plane;

[0038] The suppression signal is input to the gate of the third N-channel field-effect transistor;

[0039] The drain of the sixth N-channel field-effect transistor is connected to the drain of the fourth N-channel field-effect transistor;

[0040] The source of the sixth N-channel MOSFET is connected to the ground plane;

[0041] The suppression signal is input to the gate of the sixth N-channel MOSFET.

[0042] Furthermore, the first branch circuit includes: a first P-channel field-effect transistor and a third P-channel field-effect transistor;

[0043] The second branch circuit includes: a second P-channel MOSFET and a fourth P-channel MOSFET;

[0044] The positive feedback circuit includes: a first N-channel field-effect transistor and a fourth N-channel field-effect transistor;

[0045] The positive feedback suppression circuit includes: a second N-channel field-effect transistor, a fifth N-channel field-effect transistor, a third N-channel field-effect transistor, and a sixth N-channel field-effect transistor;

[0046] The source of the first P-channel field-effect transistor is connected to a positive power supply;

[0047] The reset control signal is input to the gate of the first P-channel MOSFET;

[0048] The drain of the first P-channel field-effect transistor is connected to the source of the third P-channel field-effect transistor;

[0049] The drain of the third P-channel field-effect transistor is connected to the drain of the first N-channel field-effect transistor.

[0050] The drain of the third P-channel field-effect transistor is connected to the gate of the fourth N-channel field-effect transistor.

[0051] The gate of the third P-channel MOSFET is connected to the gate of the first N-channel MOSFET.

[0052] The source of the second P-channel MOSFET is connected to a positive power supply;

[0053] The reset control signal is input to the gate of the second P-channel MOSFET;

[0054] The drain of the second P-channel field-effect transistor is connected to the source of the fourth P-channel field-effect transistor;

[0055] The drain of the fourth P-channel field-effect transistor is connected to the drain of the fourth N-channel field-effect transistor.

[0056] The drain of the fourth P-channel field-effect transistor is connected to the gate of the first N-channel field-effect transistor.

[0057] The gate of the fourth P-channel field-effect transistor is connected to the gate of the fourth N-channel field-effect transistor.

[0058] The source of the first N-channel field-effect transistor is connected to the ground plane;

[0059] The source of the fourth N-channel field-effect transistor is connected to the ground plane;

[0060] The drain and gate of the second N-channel field-effect transistor are both connected to the drain of the first N-channel field-effect transistor;

[0061] The drain of the third N-channel field-effect transistor is connected to the source of the second N-channel field-effect transistor;

[0062] The source of the third N-channel field-effect transistor is connected to the ground plane;

[0063] The suppression signal is input to the gate of the third N-channel field-effect transistor;

[0064] The drain and gate of the fifth N-channel field-effect transistor are both connected to the drain of the fourth N-channel field-effect transistor.

[0065] The drain of the sixth N-channel field-effect transistor is connected to the source of the fifth N-channel field-effect transistor;

[0066] The source of the sixth N-channel MOSFET is connected to the ground plane;

[0067] The suppression signal is input to the gate of the sixth N-channel MOSFET.

[0068] Furthermore, the output circuit includes: a first transmission gate composed of a fifth P-channel field-effect transistor and a seventh N-channel field-effect transistor; the first transmission gate isolates the first branch signal from the external circuit of the PUF unit circuit and transmits the value of the first branch signal to the external circuit of the PUF unit circuit.

[0069] The source of the fifth P-channel field-effect transistor and the source of the seventh N-channel field-effect transistor are connected to form the input of the first transmission gate, and the input of the first transmission gate is connected to the drain of the first N-channel field-effect transistor.

[0070] The drain of the fifth P-channel field-effect transistor is connected to the drain of the seventh N-channel field-effect transistor to form the output of the first transmission gate. The output of the first transmission gate transmits the value of the first branch signal to the external circuit of the PUF unit circuit.

[0071] The gate input address selection signal of the fifth P-channel MOSFET;

[0072] The gate input address selection signal of the seventh N-channel MOSFET;

[0073] The address selection signal is used to enable or disable the output of the output circuit.

[0074] Furthermore, the output circuit also includes a second transmission gate composed of a sixth P-channel field-effect transistor and an eighth N-channel field-effect transistor; the second transmission gate isolates the second branch signal from the external circuit of the PUF unit circuit and transmits the value of the second branch signal to the external circuit of the PUF unit circuit.

[0075] The source of the sixth P-channel field-effect transistor and the source of the eighth N-channel field-effect transistor are connected to form the input of the second transmission gate, and the input of the second transmission gate is connected to the drain of the fourth N-channel field-effect transistor.

[0076] The drain of the sixth P-channel field-effect transistor is connected to the drain of the eight N-channel field-effect transistor to form the output of the second transmission gate. The output of the second transmission gate transmits the value of the second branch signal to the external circuit of the PUF unit circuit.

[0077] The address selection signal is input to the gate of the sixth P-channel MOSFET;

[0078] The address selection signal is input to the gate of the eighth N-channel MOSFET.

[0079] The above technical solution has the following beneficial effects: After the PUF unit circuit is reset, the positive feedback effect of the positive feedback circuit is weakened by the positive feedback suppression circuit within a specified delay time, and the positive feedback effect of the positive feedback circuit is restored after the above delay time. This improves the equivalent noise margin of the circuit and the accuracy of the circuit judgment, thereby obtaining considerable circuit robustness and stability, reducing the error rate of the PUF unit circuit, and the transmission gate used in the output circuit can independently transmit high and low levels while improving the overall symmetry of the circuit and improving the anti-interference capability of the circuit. Attached Figure Description

[0080] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0081] Figure 1 This is a circuit block diagram of one embodiment of the present invention;

[0082] Figure 2 This is a timing diagram of the reset control signal and the suppression signal in one embodiment of the present invention;

[0083] Figure 3 This is a schematic diagram of an inverter constituting a time delay repeater, one of the embodiments of the present invention;

[0084] Figure 4 This is a circuit diagram of a PUF unit, one of the embodiments of the present invention;

[0085] Figure 5 This is a simulation waveform diagram of a positive feedback suppression circuit according to one embodiment of the present invention;

[0086] Figure 6 This is another PUF unit circuit diagram of one embodiment of the present invention;

[0087] Figure 7 This is a simulation waveform diagram of another positive feedback suppression circuit in one embodiment of the present invention;

[0088] Figure 8 This is a schematic diagram of a single-ended output PUF unit circuit according to one embodiment of the present invention;

[0089] Figure 9 This is a block diagram of an RFID system for an application example of the PUF unit circuit, which is one embodiment of the present invention.

[0090] Figure 10 This is a key generation and usage system block diagram of another application example of the PUF unit circuit in one embodiment of the present invention;

[0091] The reference numerals in the attached figures are as follows:

[0092] P1 is the first P-channel MOSFET;

[0093] P2 is the second P-channel MOSFET;

[0094] P3 is the third P-channel MOSFET;

[0095] P4 is the fourth P-channel MOSFET;

[0096] P5 is the fifth P-channel MOSFET;

[0097] P6 is the sixth P-channel MOSFET;

[0098] N1 is the first N-channel field-effect transistor;

[0099] N2 is the second N-channel MOSFET;

[0100] N3 is the third N-channel MOSFET;

[0101] N4 is the fourth N-channel MOSFET;

[0102] N5 is the fifth N-channel MOSFET;

[0103] N6 is the sixth N-channel MOSFET;

[0104] N7 is the seventh N-channel MOSFET;

[0105] N8 is the eighth N-channel MOSFET;

[0106] V3 is the potential value of the source of the third P-channel MOSFET;

[0107] V4 is the potential value of the source of the fourth P-channel MOSFET;

[0108] V1 is the potential value of the drain electrode of the third P-channel field-effect transistor;

[0109] V2 is the potential value of the drain electrode of the fourth P-channel MOSFET;

[0110] Reset is the reset control signal;

[0111] Reset_delay is a suppression signal;

[0112] 'WL_Enable' is the address selection signal;

[0113] WL_Enable is the address selection signal;

[0114] ID is the output signal at the output port of the output circuit;

[0115] ID is the inverted output signal at the output port of the output circuit. Detailed Implementation

[0116] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0117] On the one hand, such as Figure 1 As shown, this embodiment of the invention provides a PUF unit circuit, including: a process-sensitive circuit that outputs a circuit difference signal when a reset control signal is detected to be at a specified reset level; a positive feedback circuit that amplifies the circuit difference signal; a positive feedback suppression circuit that suppresses the positive feedback effect of the positive feedback circuit when a suppression signal is detected to be at a specified suppression level; and an output circuit that outputs the difference signal.

[0118] The positive feedback circuit is connected to the process-sensitive circuit;

[0119] The positive feedback suppression circuit is connected to the positive feedback circuit;

[0120] The output circuit is connected to the positive feedback circuit.

[0121] The PUF (Programmable Array) unit circuit utilizes the physical changes that naturally occur during semiconductor manufacturing to form a process-sensitive circuit. When an input excitation signal, such as a reset control signal, is input to the process-sensitive circuit, the differences in the physical properties of the semiconductors constituting the process-sensitive circuit, as well as the differences in the manufacturing process, result in differences in the signals output by each semiconductor, thus obtaining a difference signal output by the process-sensitive circuit. For example, two branch signals can be generated by two symmetrical branch circuits, and these two branch signals constitute the difference signal. A positive feedback suppression circuit and a positive feedback circuit together form a positive feedback effect on the difference signal, thereby amplifying the difference signal. The amplified difference signal or the branch signal constituting the difference signal is output by the output circuit or read by an isolated readout circuit outside the PUF unit circuit, so that the value of the difference signal or the value of the branch signal constituting the difference signal can be detected and read by the external circuit. During PUF unit circuit reset, within a specified delay time, the suppression signal is set to a specified suppression level, weakening the positive feedback effect of the positive feedback circuit. During the positive feedback suppression period, the difference signal gradually reaches a stable difference output value under the action of weak positive feedback. After the specified delay time, the positive feedback suppression signal is set to a level opposite to the specified suppression level, thereby restoring the positive feedback effect of the positive feedback circuit and providing strong positive feedback to the difference signal output by the process-sensitive circuit, enabling the difference signal to quickly reach a stable output quantity that can be detected and read by external circuits. The output quantity can be read as an analog signal or a digital signal. The stabilization time of the output quantity can be obtained by testing and statistically analyzing batches of PUF unit circuits to obtain the maximum stabilization time, minimum stabilization time, and typical stabilization time. The timing between the reset control signal and the suppression signal can be designed by the MCU through software and output to the reset control signal and the suppression signal via the MCU's input / output ports. Alternatively, when the timing control circuit detects that the reset control signal is at the specified reset level, it sets and maintains the suppression signal at the specified suppression level for a specified delay time. After the specified delay time, the suppression signal is set to a level opposite to the specified suppression level. Alternatively, a circuit with a delay function can be used to delay the input reset control signal and output it as the suppression signal.It may also include an output circuit, which is connected to a positive feedback circuit; for example, the output circuit can be composed of a transmission gate or an inverter; the output circuit isolates the signal inside the PUF unit circuit from the circuit outside the PUF unit circuit, and transmits the signal value inside the PUF unit circuit to the external circuit of the PUF unit circuit; the output circuit can be a single-ended output or a double-ended output; for example, the output circuit can output any branch signal in the difference signal in a single-ended manner, or it can output two branch signals in the difference signal separately through a double-ended output; the symmetrical output at both ends improves the symmetry of the circuit and improves the anti-interference capability; the output circuit has the function of isolating the internal and external circuits of the PUF unit circuit and reducing interference.

[0122] The embodiments of the present invention have the following beneficial effects: after the PUF unit circuit is reset, the positive feedback effect of the positive feedback circuit is weakened by the positive feedback suppression circuit within a specified delay time, and the positive feedback effect of the positive feedback circuit is restored after the above-mentioned delay time. This improves the equivalent noise margin of the circuit and the accuracy of circuit judgment, thereby obtaining considerable circuit robustness and stability, reducing the error rate of the PUF unit circuit, and the output circuit has the function of isolating the internal and external circuits of the PUF unit circuit, thus improving the anti-interference capability of the circuit.

[0123] Furthermore, the process-sensitive circuit includes: a first branch circuit that outputs a first branch signal when the reset control signal is detected to be at the specified reset level; and a second branch circuit that outputs a second branch signal when the reset control signal is detected to be at the specified reset level; the first branch signal and the second branch signal constitute the difference signal;

[0124] Both the first branch signal and the second branch signal are connected to the positive feedback circuit.

[0125] In another embodiment, a process-sensitive circuit is constructed using two symmetrical branch circuits, namely a first branch circuit and a second branch circuit. The difference between the first and second branch signals, caused by subtle differences in the physical parameters or manufacturing processes of the circuit components in the two branch circuits, is used to realize the PUF unit circuit. Both the first and second branch circuits are connected to the positive feedback circuit. The positive feedback circuit detects the difference between the first and second branch circuits and, through positive feedback, amplifies the signal of one branch while decreasing the signal of the other, thereby increasing the difference between the first and second branch signals. In a specific circuit, the first branch signal may be amplified while the second branch signal is decreased, or vice versa; due to the subtle differences and randomness in the physical parameters or manufacturing processes of the components, the occurrence of these two scenarios in a specific circuit is random. To ensure the stability of the magnitude relationship between the first and second branch signals before the positive feedback circuit takes effect, a delay time is set after the reset control signal is valid. During this delay time, the suppression signal is set and maintained at the specified suppression level, weakening the positive feedback effect of the positive feedback circuit and preventing strong positive feedback from acting on the unstable magnitude relationship between the first and second branch signals. During the delay time, through weak positive feedback, the magnitude relationship between the first and second branch signals is stabilized, or even after the values ​​of the two signals have increased to a certain extent, the suppression signal is set to a level opposite to the specified suppression level, causing the positive feedback suppression circuit to stop its suppression effect. Strong positive feedback is then applied to the first and second branch signals, rapidly increasing the difference between them, achieving a state where the first and second branch signals can be stably read and distinguished.

[0126] Furthermore, it also includes: a timing controller;

[0127] The output of the timing controller is connected to the input terminal of the suppression signal of the positive feedback suppression circuit; when the timing controller detects that the reset control signal is at the specified reset level, it sets and maintains the suppression signal at the specified suppression level for a specified delay time; after the specified delay time, it sets the suppression signal to a level state opposite to the specified suppression level.

[0128] Furthermore, the timing controller is specifically a delay repeater;

[0129] The output of the delay repeater is connected to the input terminal of the suppression signal of the positive feedback suppression circuit; the delay repeater outputs the reset control signal as the suppression signal after a delay.

[0130] In another embodiment, a suppression signal can be generated using a reset control signal via a time-delay repeater; the input to the time-delay repeater is the reset control signal, and after a specified delay time, the output is the suppression signal; the suppression signal is input to a positive feedback suppression circuit; for example, as... Figure 2 As shown in the diagram, the waveform of the suppression signal lags behind the waveform of the reset control signal by a specified delay time. Initially, both the reset control signal and the suppression signal are high. After the reset control signal transitions to low, the reset control signal remains low and the suppression signal remains high for the specified delay time. After this specified delay time, the reset control signal continues to remain low, and the suppression signal also transitions to low. This timing sequence enables the output circuit to generate a difference signal when the reset control signal is detected to be at the specified reset level. Within the specified delay time, by setting and maintaining the suppression signal at the specified suppression level, the positive feedback suppression circuit weakens the positive feedback effect of the positive feedback circuit. After the specified delay time, by setting the suppression signal to a level opposite to the specified suppression level, the positive feedback circuit fully activates, applying strong positive feedback to the difference signal.

[0131] The embodiments of this invention have the following beneficial effects: After the PUF unit circuit is reset, the positive feedback effect of the positive feedback circuit is weakened by the positive feedback suppression circuit within a specified delay time, and the positive feedback effect of the positive feedback circuit is restored after the aforementioned delay time. This improves the equivalent noise margin of the circuit and enhances the accuracy of circuit judgment, thereby achieving considerable circuit robustness and stability, reducing the error rate of the PUF unit circuit, and the output circuit isolates the internal and external circuits of the PUF unit circuit, improving the circuit's anti-interference capability. Furthermore, the delay repeater uses the reset control signal to generate a suppression signal, and the control timing is implemented internally by the PUF unit circuit, reducing the control complexity of the PUF unit circuit and lowering the error rate.

[0132] Furthermore, the delay repeater includes: an even number of inverters connected in series, wherein the output port of any inverter in the series is connected to the input port of the adjacent inverter connected in series after the inverter; the input of the first inverter in the series is the reset control signal, and the output of the last inverter in the series is connected to the input of the suppression signal of the positive feedback suppression circuit.

[0133] In another embodiment, such as Figure 3As shown, an even number of inverters connected in series can form a delay repeater. The reset control signal is input to the first inverter in the series, the output of the first inverter is connected to the input of the second inverter, the output of the second inverter is connected to the input of the third inverter, and so on. The output signal of the last inverter serves as the reset_delay signal. An even number of inverters provides the function of signal delay output, and the specific delay time can be adjusted by setting the number of inverters.

[0134] The embodiments of this invention have the following beneficial effects: After the PUF unit circuit is reset, the positive feedback effect of the positive feedback circuit is weakened by the positive feedback suppression circuit within a specified delay time, and the positive feedback effect of the positive feedback circuit is restored after the aforementioned delay time. This improves the equivalent noise margin of the circuit and enhances the accuracy of circuit judgment, thereby achieving considerable circuit robustness and stability, reducing the error rate of the PUF unit circuit. The output circuit isolates the internal and external circuits of the PUF unit circuit, improving the circuit's anti-interference capability. Furthermore, the delay repeater uses the reset control signal to generate a suppression signal, and the control timing is implemented internally by the PUF unit circuit, reducing the control complexity of the PUF unit circuit and lowering the error rate. Using an inverter to construct the delay repeater simplifies the circuit structure and reduces circuit complexity.

[0135] Furthermore,

[0136] The first branch circuit includes: a first P-channel field-effect transistor and a third P-channel field-effect transistor;

[0137] The second branch circuit includes: a second P-channel MOSFET and a fourth P-channel MOSFET;

[0138] The positive feedback circuit includes: a first N-channel field-effect transistor and a fourth N-channel field-effect transistor;

[0139] The positive feedback suppression circuit includes: a third N-channel field-effect transistor and a sixth N-channel field-effect transistor;

[0140] The source of the first P-channel field-effect transistor is connected to a positive power supply;

[0141] The reset control signal is input to the gate of the first P-channel MOSFET;

[0142] The drain of the first P-channel field-effect transistor is connected to the source of the third P-channel field-effect transistor;

[0143] The drain of the third P-channel field-effect transistor is connected to the drain of the first N-channel field-effect transistor.

[0144] The drain of the third P-channel field-effect transistor is connected to the gate of the fourth N-channel field-effect transistor.

[0145] The gate of the third P-channel MOSFET is connected to the gate of the first N-channel MOSFET.

[0146] The source of the second P-channel MOSFET is connected to a positive power supply;

[0147] The reset control signal is input to the gate of the second P-channel MOSFET;

[0148] The drain of the second P-channel field-effect transistor is connected to the source of the fourth P-channel field-effect transistor;

[0149] The drain of the fourth P-channel field-effect transistor is connected to the drain of the fourth N-channel field-effect transistor.

[0150] The drain of the fourth P-channel field-effect transistor is connected to the gate of the first N-channel field-effect transistor.

[0151] The gate of the fourth P-channel field-effect transistor is connected to the gate of the fourth N-channel field-effect transistor.

[0152] The source of the first N-channel field-effect transistor is connected to the ground plane;

[0153] The source of the fourth N-channel field-effect transistor is connected to the ground plane;

[0154] The drain of the third N-channel field-effect transistor is connected to the drain of the first N-channel field-effect transistor;

[0155] The source of the third N-channel field-effect transistor is connected to the ground plane;

[0156] The suppression signal is input to the gate of the third N-channel field-effect transistor;

[0157] The drain of the sixth N-channel field-effect transistor is connected to the drain of the fourth N-channel field-effect transistor;

[0158] The source of the sixth N-channel MOSFET is connected to the ground plane;

[0159] The suppression signal is input to the gate of the sixth N-channel MOSFET.

[0160] In another embodiment, such as Figure 4As shown, the sources of P1 and P2 are both connected to Vdd, the positive power supply, and the conduction of P1 and P2 is controlled by the reset control signal. P1 (first P-channel MOSFET), P2 (second P-channel MOSFET), P3 (third P-channel MOSFET), and P4 (fourth P-channel MOSFET) constitute a process-sensitive circuit. That is, P1 and P2, while used to input the reset signal, also work with P3 and P4 to provide a difference signal due to parameter mismatch caused by process differences. The branches of P1 and P3 are connected to Vdd. The potential on V1 differs from the potential on V2 of branches P2 and P4. This difference stems from parameter mismatch caused by deviations in the physical structure and manufacturing process of the field-effect transistor. The difference in the rate of potential rise between V1 and V2 due to parameter mismatch is determined and distinguished by the positive feedback circuit formed by N1 (the first N-channel field-effect transistor) and N4 (the fourth N-channel field-effect transistor), generating a random identifier. N3 (the third N-channel field-effect transistor) is connected in parallel with N1, and N6 (the sixth N-channel field-effect transistor) is connected in parallel with N4. N3 and N6 constitute a positive feedback suppression circuit, such as... Figure 5 As shown, when the reset control signal is low and the reset_delay suppression signal is high, N3 causes V1 to stabilize at a lower potential, and N6 causes V2 to stabilize at a lower potential. N3 and N6 constitute a relatively strong suppression of positive feedback. During the period when the positive feedback effect of the positive feedback circuit composed of N1 and N4 is suppressed, the potential difference between V1 and V2 remains stable. When reset_delay is low, N3 and N6 no longer suppress the positive feedback effect of N1 and N4. Under the positive feedback effect of N1 and N4, the potential difference between V1 and V2 rapidly expands and reaches a stable state.

[0161] The embodiments of the present invention have the following beneficial effects: After the PUF unit circuit is reset, the positive feedback effect of the positive feedback circuit is weakened by the positive feedback suppression circuit within a specified delay time, and the positive feedback effect of the positive feedback circuit is restored after the above-mentioned delay time. This improves the equivalent noise margin of the circuit and enhances the accuracy of circuit judgment, thereby obtaining considerable circuit robustness and stability, reducing the error rate of the PUF unit circuit, and the output circuit has the function of isolating the internal and external circuits of the PUF unit circuit, improving the anti-interference capability of the circuit. Specifically, under the suppression effect of N3 and N6, the potential difference between V1 and V2 enters a stable state. In this state, the strong positive feedback effect of N1 and N4 is restored, causing the potential difference between V1 and V2 to be rapidly expanded in the stable state. This avoids applying the strong positive feedback effect of N1 and N4 during the period when the potential difference between V1 and V2 is unstable, improving the equivalent noise margin of the circuit and enhancing the accuracy of circuit judgment, thereby obtaining considerable circuit robustness and stability, and reducing the error rate of the PUF unit circuit.

[0162] Furthermore,

[0163] The first branch circuit includes: a first P-channel field-effect transistor and a third P-channel field-effect transistor;

[0164] The second branch circuit includes: a second P-channel MOSFET and a fourth P-channel MOSFET;

[0165] The positive feedback circuit includes: a first N-channel field-effect transistor and a fourth N-channel field-effect transistor;

[0166] The positive feedback suppression circuit includes: a second N-channel field-effect transistor, a fifth N-channel field-effect transistor, a third N-channel field-effect transistor, and a sixth N-channel field-effect transistor;

[0167] The source of the first P-channel field-effect transistor is connected to a positive power supply;

[0168] The reset control signal is input to the gate of the first P-channel MOSFET;

[0169] The drain of the first P-channel field-effect transistor is connected to the source of the third P-channel field-effect transistor;

[0170] The drain of the third P-channel field-effect transistor is connected to the drain of the first N-channel field-effect transistor.

[0171] The drain of the third P-channel field-effect transistor is connected to the gate of the fourth N-channel field-effect transistor.

[0172] The gate of the third P-channel MOSFET is connected to the gate of the first N-channel MOSFET.

[0173] The source of the second P-channel MOSFET is connected to a positive power supply;

[0174] The reset control signal is input to the gate of the second P-channel MOSFET;

[0175] The drain of the second P-channel field-effect transistor is connected to the source of the fourth P-channel field-effect transistor;

[0176] The drain of the fourth P-channel field-effect transistor is connected to the drain of the fourth N-channel field-effect transistor.

[0177] The drain of the fourth P-channel field-effect transistor is connected to the gate of the first N-channel field-effect transistor.

[0178] The gate of the fourth P-channel field-effect transistor is connected to the gate of the fourth N-channel field-effect transistor.

[0179] The source of the first N-channel field-effect transistor is connected to the ground plane;

[0180] The source of the fourth N-channel field-effect transistor is connected to the ground plane;

[0181] The drain and gate of the second N-channel field-effect transistor are both connected to the drain of the first N-channel field-effect transistor;

[0182] The drain of the third N-channel field-effect transistor is connected to the source of the second N-channel field-effect transistor;

[0183] The source of the third N-channel field-effect transistor is connected to the ground plane;

[0184] The suppression signal is input to the gate of the third N-channel field-effect transistor;

[0185] The drain and gate of the fifth N-channel field-effect transistor are both connected to the drain of the fourth N-channel field-effect transistor.

[0186] The drain of the sixth N-channel field-effect transistor is connected to the source of the fifth N-channel field-effect transistor;

[0187] The source of the sixth N-channel MOSFET is connected to the ground plane;

[0188] The suppression signal is input to the gate of the sixth N-channel MOSFET.

[0189] In another embodiment, such as Figure 6 As shown, the sources of P1 and P2 are both connected to Vdd, the positive power supply, and the conduction of P1 and P2 is controlled by the reset control signal. P1 (first P-channel MOSFET), P2 (second P-channel MOSFET), P3 (third P-channel MOSFET), and P4 (fourth P-channel MOSFET) constitute a process-sensitive circuit. That is, P1 and P2, while used to input the reset signal, also work with P3 and P4 to provide a difference signal due to parameter mismatch caused by process differences. The potential of the branches of P1 and P3 on V1 differs from the potential of the branches of P2 and P4 on V2. The difference stems from parameter mismatch caused by deviations in the physical structure and manufacturing process of the field-effect transistors (FETs). The difference in the rate of rise of the potentials V1 and V2 due to this parameter mismatch is determined and distinguished by the positive feedback circuit formed by N1 (the first N-channel FET) and N4 (the fourth N-channel FET), generating a random identifier. The branch formed by the series connection of N2 (the second N-channel FET) and N3 (the third N-channel FET) is then connected in parallel with N1; the branch formed by the series connection of N5 (the fifth N-channel FET) and N6 (the sixth N-channel FET) is then connected in parallel with N4. N2 and N3, as well as N5 and N6, constitute a positive feedback suppression circuit, such as... Figure 7As shown, when the reset control signal is low and the reset_delay suppression signal is high, N2 and N3 cause the potential of V1 to rise slowly, and N5 and N6 cause the potential of V2 to rise slowly, gradually widening the potential difference between V1 and V2. N2 and N3, as well as N5 and N6, constitute a weak suppression positive feedback. When reset_delay is low, N2 and N3, as well as N5 and N6, no longer suppress the positive feedback of N1 and N4. Under the positive feedback of N1 and N4, the potential difference between V1 and V2 rapidly expands and reaches a stable state. N2 connects the gate and drain, equivalent to a resistor with a resistance of 1 / gm, where the value of gm is affected by other parameters such as the gate-source voltage. N5 connects the gate and drain, equivalent to a resistor with a resistance of 1 / gm, where the value of gm is affected by other parameters such as the gate-source voltage. N2 and N5 act as loads in the circuit. N2, N3, N5, and N6, together with the delay of reset_delay relative to reset, weaken the strong positive feedback formed by N1 and N4 and restore the strong positive feedback after a delay. During this delay time, the weakened positive feedback will have more time to act on the V1 and V2 potentials, which reduces the error rate of the PUF unit to a certain extent and improves the stability and robustness of the circuit.

[0190] The embodiments of the present invention have the following beneficial effects: After the PUF unit circuit is reset, the positive feedback effect of the positive feedback circuit is weakened by the positive feedback suppression circuit within a specified delay time, and the positive feedback effect of the positive feedback circuit is restored after the above-mentioned delay time. This improves the equivalent noise margin of the circuit and enhances the accuracy of circuit judgment, thereby obtaining considerable circuit robustness and stability, reducing the error rate of the PUF unit circuit, and the output circuit has the function of isolating the internal and external circuits of the PUF unit circuit, improving the anti-interference capability of the circuit. Specifically, under the suppression effect of N2 and N3 and N5 and N6, the potential difference between V1 and V2 slowly increases to a sufficient difference value, increasing the anti-interference capability of the potential difference signal between V1 and V2. In this state, the strong positive feedback effect of N1 and N4 is restored, causing the potential difference between V1 and V2 to be rapidly expanded and stabilized, improving the equivalent noise margin of the circuit and enhancing the accuracy of circuit judgment, thereby obtaining considerable circuit robustness and stability, and reducing the error rate of the PUF unit circuit.

[0191] Furthermore, the output circuit includes: a first transmission gate composed of a fifth P-channel field-effect transistor and a seventh N-channel field-effect transistor; the first transmission gate isolates the first branch signal from the external circuit of the PUF unit circuit and transmits the value of the first branch signal to the external circuit of the PUF unit circuit.

[0192] The source of the fifth P-channel field-effect transistor and the source of the seventh N-channel field-effect transistor are connected to form the input of the first transmission gate, and the input of the first transmission gate is connected to the drain of the first N-channel field-effect transistor.

[0193] The drain of the fifth P-channel field-effect transistor is connected to the drain of the seventh N-channel field-effect transistor to form the output of the first transmission gate. The output of the first transmission gate transmits the value of the first branch signal to the external circuit of the PUF unit circuit.

[0194] The gate input address selection signal of the fifth P-channel MOSFET;

[0195] The gate input address selection signal of the seventh N-channel MOSFET;

[0196] The address selection signal is used to enable or disable the output of the output circuit.

[0197] In another embodiment, such as Figure 8 As shown, a transmission gate composed of P5 (the fifth P-channel MOSFET) and N7 (the seventh N-channel MOSFET) can be used as the output circuit. An external circuit can read the value of the first branch signal of the PUF unit circuit through the output circuit composed of P5 and N7. By enabling the output circuit with an address selection signal, the external circuit can read the value of the first branch signal of the PUF unit circuit. The output circuit composed of P5 and N7 also serves to isolate the external circuit from the internal circuitry of the PUF unit circuit.

[0198] The embodiments of the present invention have the following beneficial effects: After the PUF unit circuit is reset, the positive feedback effect of the positive feedback circuit is weakened by the positive feedback suppression circuit within a specified delay time, and the positive feedback effect of the positive feedback circuit is restored after the above-mentioned delay time. This improves the equivalent noise margin of the circuit and the accuracy of circuit judgment, thereby obtaining considerable circuit robustness and stability, reducing the error rate of the PUF unit circuit, and the single-ended output circuit has the function of isolating the internal and external circuits of the PUF unit circuit, saving circuit costs and improving the anti-interference capability of the circuit.

[0199] Furthermore, the output circuit also includes a second transmission gate composed of a sixth P-channel field-effect transistor and an eighth N-channel field-effect transistor; the second transmission gate isolates the second branch signal from the external circuit of the PUF unit circuit and transmits the value of the second branch signal to the external circuit of the PUF unit circuit.

[0200] The source of the sixth P-channel field-effect transistor and the source of the eighth N-channel field-effect transistor are connected to form the input of the second transmission gate, and the input of the second transmission gate is connected to the drain of the fourth N-channel field-effect transistor.

[0201] The drain of the sixth P-channel field-effect transistor is connected to the drain of the eight N-channel field-effect transistor to form the output of the second transmission gate. The output of the second transmission gate transmits the value of the second branch signal to the external circuit of the PUF unit circuit.

[0202] The address selection signal is input to the gate of the sixth P-channel MOSFET;

[0203] The address selection signal is input to the gate of the eighth N-channel MOSFET.

[0204] In another embodiment, such as Figure 6 As shown, a transmission gate consisting of P5 (the fifth P-channel MOSFET), N7 (the seventh N-channel MOSFET), P6 (the sixth P-channel MOSFET), and N8 (the eighth N-channel MOSFET) can be used as a two-terminal output circuit. An external circuit can read the values ​​of the first and second branch signals of the PUF unit circuit through the output circuit. By enabling the output circuit with an address selection signal, the external circuit can read the value of the second branch signal of the PUF unit circuit. Specifically, the external circuit can read either the value of the output signal (the first branch signal) or the inverted output signal (the second branch signal) as needed. The two-terminal output circuit isolates the external circuit from the internal circuitry of the PUF unit circuit, also achieving circuit symmetry and improving anti-interference capability.

[0205] The embodiments of the present invention have the following beneficial effects: After the PUF unit circuit is reset, the positive feedback effect of the positive feedback circuit is weakened by the positive feedback suppression circuit within a specified delay time, and the positive feedback effect of the positive feedback circuit is restored after the above-mentioned delay time. This improves the equivalent noise margin of the circuit and the accuracy of circuit judgment, thereby obtaining considerable circuit robustness and stability, reducing the error rate of the PUF unit circuit, and the dual-ended output circuit has the function of isolating the internal and external circuits of the PUF unit circuit, and realizing the symmetry of the circuit, thereby improving the anti-interference capability of the circuit.

[0206] The technical solutions of the present invention will be described in detail below with reference to specific application examples. For technical details not described in the implementation process, please refer to the relevant descriptions above.

[0207] like Figure 6 The diagram shown is a PUF (Pull-in-Flight) unit circuit. This circuit is constructed from 14 MOSFETs and generates a single random and stable digital bit (0 or 1) during each Reset cycle. The data bit is then transmitted through a transmission gate for data acquisition. Arranging this circuit array increases the number of data bits, thus generating a stable, unique, and random ID code. The following is a brief description of the entire circuit's operation:

[0208] After the chip is powered on, it instantly enters two working states to bring the circuit to a final stable state, and then the data bits at the specified address are selected by address selection. In the initial state, Reset and Reset_delay are set to high level, and MOSFETs N3, N6, N2, and N5 are turned on, pulling potentials V1 and V2 low. Subsequently, P3 and P4 are turned on (not fully turned on), pulling V3 and V4 low (higher potentials than V1 and V2). In the second state, Reset is set to low level, and Reset_delay changes from high level to low level after a certain delay. However, before Reset_delay becomes low level (common-mode analysis), Reset is low level, and MOSFETs P1 and P2 are turned on simultaneously, causing the potentials of V3 and V4 to rise. MOSFETs P3 and P4 are fully turned on, and the potentials of V1 and V2 rise. However, due to manufacturing process deviations, there may be parameter mismatch between P1, P2, P3, and P4, resulting in different rates of potential rise for V1 and V2. The potential difference between these two will gradually increase through the positive feedback formed by N1 and N4. When Reset_delay becomes low level, it will completely separate V1 and V2 from the strong positive feedback.

[0209] If the original circuit did not have N2 and N5 in parallel, V1 and V2 would remain at a low level during the period when Reset_delay is high. Only when Reset_delay becomes low would the positive feedback formed by N1 and N2 affect the potential difference between V1 and V2, and the positive feedback after the delay would be strong positive feedback. With N2 and N5, the strong positive feedback would only pull the potentials of V1 and V2 apart when Reset_delay becomes zero. During this delay, the weakened positive feedback would act on the potentials of V1 and V2 for more time, thus making the circuit's positive feedback discrimination more accurate, the circuit's stability and robustness more considerable, and the bit error rate generated by the circuit lower.

[0210] Next, we will introduce the roles of the MOSFETs other than P1 and P2 in this circuit:

[0211] P5, N7 and P6, N8 serve as transmission gates to transmit the bits generated by the internal core circuit, while also improving the symmetry of the circuit.

[0212] The parameter mismatch caused by manufacturing process deviations of P1, P2, P3, and P4 is distinguished by the positive feedback judgment formed by N1 and N4 based on the rate of rise of the potentials of V1 and V2, thereby generating random identifier bits.

[0213] P3 and P4 can isolate VDD to GND when the final judgment ends, thereby reducing static power consumption;

[0214] N1 and N4 form a strong positive feedback, which affects the potential difference between V1 and V2.

[0215] N2, N3, N5, and N6 work together with the delay function to weaken the strong positive feedback formed by N1 and N4 and restore the strong positive feedback after the delay period (the role of load transistors N2 and N5 is to weaken the strong positive feedback). During this delay period, the weakened positive feedback will have more time to act on the V1 and V2 potentials, which will reduce the error rate of the PUF unit to a certain extent and improve the stability and robustness of the circuit.

[0216] Figure 3 The eight inverters shown are used to add a delay to Reset_delay, providing weak positive feedback potentials V1 and V2.

[0217] The following are examples illustrating the application of the PUF circuit unit of this invention:

[0218] Application Example 1: RFID Tag

[0219] like Figure 9 As shown, the RFID system includes a computer, a reader, a reader antenna, and RFID tags;

[0220] 1) Computer: Primarily used for system data management and to enable interaction between users and data information;

[0221] 2) Reader: The reader mainly consists of a baseband circuit and a radio frequency (RF) circuit. The RF circuit consists of a transmitting circuit and a receiving circuit, and is mainly responsible for transmitting and receiving signals.

[0222] 3) Reader antenna: It interacts with the tag chip to exchange data and provides power to the tag chip at the same time;

[0223] 4) RFID Tag: Composed of a tag antenna and a tag chip (with a PUF cell array as the core). The tag antenna is used for data interaction with the reader antenna; the tag chip is the actual data carrier of the RFID system, providing core data to the computer via external circuitry from the PUF circuit module.

[0224] Application Example 2: Cryptographic Algorithms

[0225] Job description: (e.g.) Figure 10As shown, a set of keys is generated by the PUF key generator (PUF array) and sent to the ECC module. The ECC (Error Correcting Code) module corrects the error bits in the key and then sends it to the key management module. The key processed by the key management module and the data to be encrypted are encrypted in the encryption algorithm module to obtain encrypted data. The key must be kept consistent throughout this process.

[0226] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process may be rearranged without departing from the scope of this disclosure. The appended method claims provide elements of various steps in an exemplary order and are not intended to limit the scope to the specific order or hierarchy described.

[0227] In the above detailed description, various features are combined together in a single embodiment to simplify this disclosure. This approach to disclosure should not be construed as reflecting an intention that embodiments of the claimed subject matter require more features than are explicitly stated in each claim. Rather, as reflected in the appended claims, the invention is presented with fewer features than all of the features of the single disclosed embodiment. Therefore, the appended claims are hereby explicitly incorporated into the detailed description, wherein each claim stands alone as a preferred embodiment of the invention.

[0228] The disclosed embodiments have been described above to enable any person skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments without departing from the spirit and scope of this disclosure. Therefore, this disclosure is not limited to the embodiments given herein, but is consistent with the broadest scope of the principles and novel features disclosed in this application.

[0229] The foregoing description includes examples of one or more embodiments. It is certainly impossible to describe all possible combinations of components or methods in order to describe the above embodiments, but those skilled in the art will recognize that further combinations and arrangements of the various embodiments are possible. Therefore, the embodiments described herein are intended to cover all such changes, modifications, and variations that fall within the scope of the appended claims. Furthermore, the term "comprising" as used in the specification or claims is interpreted in a manner similar to the term "including," as interpreted when used as a conjunction in the claims. Additionally, the use of any term "or" in the specification of the claims is intended to mean "non-exclusive or."

[0230] Those skilled in the art will also understand that the various illustrative logical blocks, units, and steps listed in the embodiments of the present invention can be implemented by electronic hardware, computer software, or a combination of both. To clearly demonstrate the interchangeability of hardware and software, the functions of the various illustrative components, units, and steps described above have been generally described. Whether such functionality is implemented through hardware or software depends on the specific application and the overall system design requirements. Those skilled in the art can implement the described functions using various methods for each specific application, but such implementation should not be construed as exceeding the scope of protection of the embodiments of the present invention.

[0231] The various illustrative logic blocks or units described in the embodiments of this invention can be implemented or operate the described functions using a general-purpose processor, digital signal processor, application-specific integrated circuit (ASIC), field-programmable gate array or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. The general-purpose processor can be a microprocessor; alternatively, it can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented using a combination of computing devices, such as a digital signal processor and a microprocessor, multiple microprocessors, one or more microprocessors combined with a digital signal processor core, or any other similar configuration.

[0232] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A PUF cell circuit, characterized by, The PUF unit circuit comprises: a process-sensitive circuit for outputting a circuit difference signal when a reset control signal is detected to be a specified reset level; a positive feedback circuit for amplifying the circuit difference signal; a positive feedback inhibition circuit for inhibiting the positive feedback effect of the positive feedback circuit when an inhibition signal is detected to be a specified inhibition level; and an output circuit for outputting the circuit difference signal; the positive feedback circuit is connected to the process-sensitive circuit; the positive feedback inhibition circuit is connected to the positive feedback circuit; the output circuit is connected to the positive feedback circuit; the PUF unit circuit further comprises a timing controller; an output of the timing controller is connected to an input of the inhibition signal of the positive feedback inhibition circuit; the timing controller sets and maintains the inhibition signal to be the specified inhibition level for a specified delay time when the reset control signal is detected to be the specified reset level; and the timing controller sets the inhibition signal to be a level opposite to the specified inhibition level after the specified delay time. The positive feedback inhibition circuit and the positive feedback circuit together form a positive feedback effect on the circuit difference signal, thereby amplifying the circuit difference signal. Specifically, when the PUF unit circuit is reset, the positive feedback inhibition circuit weakens the positive feedback effect of the positive feedback circuit by setting the inhibition signal to be the specified inhibition level for the specified delay time. During the positive feedback inhibition, the circuit difference signal gradually reaches a stable difference output value under the weak positive feedback effect. After the specified delay time, the positive feedback effect of the positive feedback circuit is restored by setting the positive feedback inhibition signal to be a level opposite to the specified inhibition level, thereby providing strong positive feedback to the circuit difference signal output from the process-sensitive circuit, so that the circuit difference signal quickly reaches a stable output value that can be used for external circuit detection and reading.

2. The PUF cell circuit of claim 1, wherein, The process-sensitive circuit comprises a first branch circuit for outputting a first branch signal when the reset control signal is detected to be the specified reset level, and a second branch circuit for outputting a second branch signal when the reset control signal is detected to be the specified reset level; the first branch signal and the second branch signal constitute the difference signal. The first branch circuit and the second branch circuit are both connected to the positive feedback circuit.

3. The PUF cell circuit of claim 1, wherein, The timing controller is specifically a delay repeater. An output of the delay repeater is connected to an input of the inhibition signal of the positive feedback inhibition circuit; the delay repeater outputs the reset control signal as the inhibition signal after a delay.

4. The PUF cell circuit of claim 3, wherein, The delay repeater comprises: an even number of inverters connected in series, and an output port of any inverter in the series of inverters is connected to an input port of a neighboring inverter connected after the any inverter; an input of a first inverter in the series of inverters is the reset control signal, and an output of a last inverter in the series of inverters is connected to the input of the inhibition signal of the positive feedback inhibition circuit.

5. The PUF unit circuit of claim 2, wherein the first branch circuit comprises a first P-channel field effect transistor and a third P-channel field effect transistor. The second branch circuit comprises a second P-channel field effect transistor and a fourth P-channel field effect transistor; The positive feedback circuit comprises a first N-channel field effect transistor and a fourth N-channel field effect transistor; The positive feedback inhibition circuit comprises a third N-channel field effect transistor and a sixth N-channel field effect transistor; The source of the first P-channel field effect transistor is connected to a positive power supply; The gate of the first P-channel field effect transistor inputs the reset control signal; The drain of the first P-channel field effect transistor is connected to the source of the third P-channel field effect transistor; The drain of the third P-channel field effect transistor is connected to the drain of the first N-channel field effect transistor; The drain of the third P-channel field effect transistor is connected to the gate of the fourth N-channel field effect transistor; The gate of the third P-channel field effect transistor is connected to the gate of the first N-channel field effect transistor; The source of the second P-channel field effect transistor is connected to a positive power supply; The gate of the second P-channel field effect transistor inputs the reset control signal; The drain of the second P-channel field effect transistor is connected to the source of the fourth P-channel field effect transistor; The drain of the fourth P-channel field effect transistor is connected to the drain of the fourth N-channel field effect transistor; The drain of the fourth P-channel field effect transistor is connected to the gate of the first N-channel field effect transistor; The gate of the fourth P-channel field effect transistor is connected to the gate of the fourth N-channel field effect transistor; The source of the first N-channel field effect transistor is connected to a ground plane; The source of the fourth N-channel field effect transistor is connected to a ground plane; The drain of the third N-channel field effect transistor is connected to the drain of the first N-channel field effect transistor; The source of the third N-channel field effect transistor is connected to a ground plane; The gate of the third N-channel field effect transistor inputs the inhibition signal; The drain of the sixth N-channel field effect transistor is connected to the drain of the fourth N-channel field effect transistor; The source of the sixth N-channel field effect transistor is connected to a ground plane; The gate of the sixth N-channel field effect transistor inputs the inhibition signal.

6. The PUF cell circuit of claim 2, wherein The first branch circuit comprises a first P-channel field effect transistor and a third P-channel field effect transistor; The second branch circuit comprises a second P-channel field effect transistor and a fourth P-channel field effect transistor; The positive feedback circuit comprises a first N-channel field effect transistor and a fourth N-channel field effect transistor; The positive feedback inhibition circuit comprises a second N-channel field effect transistor, a fifth N-channel field effect transistor, a third N-channel field effect transistor, and a sixth N-channel field effect transistor; The source of the first P-channel field effect transistor is connected to a positive power supply; The gate of the first P-channel field effect transistor inputs the reset control signal; The drain of the first P-channel field effect transistor is connected to the source of the third P-channel field effect transistor; The drain of the third P-channel field effect transistor is connected to the drain of the first N-channel field effect transistor; The drain of the third P-channel field effect transistor is connected to the gate of the fourth N-channel field effect transistor; The gate of the third P-channel field effect transistor is connected to the gate of the first N-channel field effect transistor; The source of the second P-channel field effect transistor is connected to a positive power supply; The gate of the second P-channel field effect transistor inputs the reset control signal; The drain of the second P-channel field effect transistor is connected to the source of the fourth P-channel field effect transistor; The drain of the fourth P-channel field effect transistor is connected to the drain of the fourth N-channel field effect transistor; The drain of the fourth P-channel field effect transistor is connected to the gate of the first N-channel field effect transistor; The gate of the fourth P-channel field effect transistor is connected to the gate of the fourth N-channel field effect transistor; The source of the first N-channel field effect transistor is connected to ground; The source of the fourth N-channel field effect transistor is connected to ground; The drain and the gate of the second N-channel field effect transistor are both connected to the drain of the first N-channel field effect transistor; The drain of the third N-channel field effect transistor is connected to the source of the second N-channel field effect transistor; The source of the third N-channel field effect transistor is connected to ground; The gate of the third N-channel field effect transistor inputs the inhibit signal; The drain and the gate of the fifth N-channel field effect transistor are both connected to the drain of the fourth N-channel field effect transistor; The drain of the sixth N-channel field effect transistor is connected to the source of the fifth N-channel field effect transistor; The source of the sixth N-channel field effect transistor is connected to ground; The gate of the sixth N-channel field effect transistor inputs the inhibit signal.

7. The PUF cell circuit of claim 5 or 6, wherein, The output circuit comprises a first transmission gate composed of a fifth P-channel field effect transistor and a seventh N-channel field effect transistor; the first transmission gate isolates the first branch signal from external circuits of the PUF unit circuit and transmits the value of the first branch signal to the external circuits of the PUF unit circuit; The source of the fifth P-channel field effect transistor and the source of the seventh N-channel field effect transistor are connected to form the input of the first transmission gate, and the input of the first transmission gate is connected to the drain of the first N-channel field effect transistor; The drain of the fifth P-channel field effect transistor and the drain of the seventh N-channel field effect transistor are connected to form the output of the first transmission gate, and the output of the first transmission gate transmits the value of the first branch signal to the external circuits of the PUF unit circuit; The gate of the fifth P-channel field effect transistor inputs an address selection signal; The gate of the seventh N-channel field effect transistor inputs the address selection signal; The address selection signal is used to enable or disable the output of the output circuit.

8. The PUF unit circuit of claim 7, wherein The output circuit further comprises a second transmission gate composed of a sixth P-channel field effect transistor and an eighth N-channel field effect transistor; the second transmission gate isolates the second branch signal from external circuits of the PUF unit circuit and transmits the value of the second branch signal to the external circuits of the PUF unit circuit; The source of the sixth P-channel field effect transistor and the source of the eighth N-channel field effect transistor are connected to form the input of the second transmission gate, and the input of the second transmission gate is connected to the drain of the fourth N-channel field effect transistor; The drain of the sixth P-channel field effect transistor is connected with the drain of the eighth N-channel field effect transistor to form an output of the second transfer gate, and the output of the second transfer gate transmits a value of the second branch signal to an external circuit of the PUF unit circuit; The gate of the sixth P-channel field effect transistor inputs the address selection signal; The gate of the eighth N-channel field effect transistor inputs the address selection signal.

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