Control device and control method of control device

Abstract

The present invention provides a control device and a control method for the control device, which can reduce the load of the operation processing unit related to the processing of soft errors in the control device. The control device (100) includes an operation processing unit (10), a programmable circuit unit (20) and an abnormality notification unit (26). The programmable circuit unit (20) includes: a storage unit (21) for storing configuration data; an abnormality detection unit (22) for detecting soft errors in the storage unit (21); and an abnormality recording unit (24) for recording information on the soft errors detected by the abnormality detection unit (22). The abnormality notification unit (26) determines whether new soft error information is recorded in the abnormality recording unit (24). If it is determined that new soft error information is recorded, the operation processing unit (10) is notified of the occurrence of the new soft error.

Description

Technical Field

[0001] The present invention relates to a control device and a control method of the control device. Background Art

[0002] The machinery and equipment used in production sites are typically controlled by control devices such as programmable logic controllers (PLCs). Typically, users use information processing devices to create control programs that are executed by the control devices. These user-designed and created programs are also called user programs.

[0003] A PLC consists of functional units such as a central processing unit (CPU) and input / output (I / O) units. The I / O units input signals from external switches and sensors and output signals to external relays and actuators. These functional units are sometimes implemented using programmable circuits such as field-programmable gate arrays (FPGAs).

[0004] Programmable circuits offer the advantage of allowing users to customize their circuits. However, they also have the disadvantage of potentially causing soft errors, which can occur when information in the configuration random access memory (ConfigRAM) (hereinafter referred to as CRAM), which stores configuration data within the programmable circuit, is altered by radiation and other factors. This is particularly true when static random access memory (SRAM) is used as CRAM.

[0005] In CRAM, used areas that constitute functional units and unused areas that do not constitute functional units coexist, and soft errors can occur in either used or unused areas. If a soft error occurs in a used area, there is a possibility of malfunctioning control of the control device. In contrast, if a soft error occurs in an unused area, the likelihood of malfunctioning control of the control device is low. Therefore, Patent Document 1 discloses a control device that determines the location of a soft error based on mapping information. If the location of the soft error is within an unused area of ​​a functional unit, the control device continues operation, preventing unnecessary shutdowns.

[0006] Prior art literature

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent Publication No. 2018-128820 Summary of the Invention

[0009] Problems to be solved by the invention

[0010] However, in the conventional technology described above, once a soft error occurs, the FPGA periodically detects the error and sends an interrupt notification to the processor. Consequently, the processor must interrupt normal processing to analyze the soft error. This interruption occurs at a high frequency, ranging from a few milliseconds to tens of milliseconds, causing fluctuations in the processor's control cycle, making high-precision control difficult.

[0011] An object of one embodiment of the present invention is to reduce the load on a calculation processing unit related to soft error processing in a control device.

[0012] Technical means to solve the problem

[0013] In order to solve the above-mentioned problem, a control device according to one aspect of the present invention includes: an operation processing unit capable of executing a user program; a programmable circuit unit connected to the operation processing unit and constituting a functional unit; and an abnormality notification unit, wherein the programmable circuit unit includes: a storage unit for storing configuration data of the functional unit; an abnormality detection unit for detecting soft errors in the storage unit; and an abnormality recording unit for recording information on the soft errors detected by the abnormality detection unit, wherein the abnormality notification unit determines whether new information on the soft error is recorded in the abnormality recording unit, and if it is determined that new information on the soft error is recorded, the abnormality notification unit notifies the operation processing unit of the occurrence of the new soft error.

[0014] A control method for a control device according to one aspect of the present invention is a control method for a control device comprising the following parts: an operation processing unit capable of executing a user program; and a programmable circuit unit connected to the operation processing unit to constitute a functional unit, and the control method for the control device comprises: an abnormality detection step for detecting a soft error in a storage unit, wherein the storage unit stores configuration data of the functional unit; an abnormality recording step for recording information on the soft error detected in the abnormality detection step; and an abnormality notification step for determining whether new information on the soft error is recorded in the abnormality recording step, and if it is determined that new information on the soft error is recorded, notifying the operation processing unit of the occurrence of the new soft error.

[0015] Effects of the Invention

[0016] According to one embodiment of the present invention, the load on the arithmetic processing unit related to soft error processing in a control device can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a block diagram showing an example of the hardware configuration of the control device according to the first embodiment of the present invention.

[0018] Figure 2 To express Figure 1 A block diagram showing an example of the structure of the FPGA unit and the processor unit.

[0019] Figure 3 To express Figure 1 A diagram showing the timing of each step of a control method of a control device.

[0020] Figure 4 To express Figure 1 Flowchart of a control method of a control device.

[0021] Figure 5 This is a block diagram showing a configuration example of an FPGA unit and a processor unit in a control device according to a second embodiment of the present invention.

[0022] [Explanation of Symbols]

[0023] 10: Processor unit (calculation processing unit)

[0024] 11: ROM

[0025] 12: RAM

[0026] 13: Abnormal Analysis Department

[0027] 20: FPGA department (programmable circuit department)

[0028] 21: CRAM (storage unit)

[0029] 22: Abnormal Detection Department

[0030] 23: Abnormal reading unit

[0031] 24: Abnormal Records Department

[0032] 25, 45: Timer

[0033] 26, 46: Abnormal Notification Department

[0034] 27: First Communications IF

[0035] 28: Second communication IF

[0036] 30: I / O unit

[0037] 40: ASIC department

[0038] 47: Third Communication IF

[0039] 100: Control device

[0040] 200: Input and output machines

[0041] S1~S7, S21, S31, S41: Steps

[0042] t1, t2, t3: time DETAILED DESCRIPTION

[0043] Hereinafter, an embodiment of one aspect of the present invention (hereinafter also referred to as “this embodiment”) will be described with reference to the drawings.

[0044] [Implementation Method 1]

[0045] §1 Application

[0046] Figure 1 This is a block diagram showing an example of the hardware configuration of the control device 100 according to the first embodiment. Figure 1 An example of a scenario in which the present invention is applicable will be described. A control device 100 includes a processor unit (arithmetic processing unit) 10 and an FPGA unit (programmable circuit unit) 20. The processor unit 10 primarily performs processing related to the control and operation of the controlled object by executing user programs. The FPGA unit 20 constitutes a functional unit (functional unit) and performs specific processing on digital values ​​input from the processor unit 10.

[0047] Figure 2 To express Figure 1 The block diagram of the configuration example of the FPGA unit 20 and the processor unit 10 is shown. The processor unit 10 includes an abnormality analysis unit 13. The FPGA unit 20 includes a CRAM (storage unit) 21, an abnormality detection unit 22, an abnormality recording unit 24, and an abnormality notification unit 26. The CRAM 21 stores the configuration data of the functional unit. The abnormality detection unit 22 detects soft errors in the CRAM 21. The abnormality recording unit 24 records information on the soft errors detected by the abnormality detection unit 22. The abnormality notification unit 26 determines whether new soft error information is recorded in the abnormality recording unit 24. If it is determined that new soft error information is recorded, it interrupts and notifies the processor unit 10 of the occurrence of the new soft error.

[0048] According to this embodiment, when the abnormality notification unit 26 determines that no new soft error information has been recorded in the abnormality recording unit 24, it can terminate the processing without interrupting the notification to the processor unit 10. Therefore, the frequency of abnormality notifications to the processor unit 10 can be reduced, and the load on the processor unit 10 related to soft error processing can be reduced.

[0049] §2 Structure Example

[0050] like Figure 1 As shown, as an example, the control device 100 of Embodiment 1 is implemented using a PLC (Programmable Logic Controller). The control device 100 calculates command values ​​by executing pre-stored programs (such as system programs and user programs). The control device 100 provides the command values ​​to the controlled object (such as a motor driver) connected via the I / O (Input / Output) unit 30. Furthermore, the control device 100 obtains status values ​​from the controlled object. In other words, the control device 100 dynamically generates appropriate command values ​​by feeding back the status values ​​of the controlled object, thereby appropriately controlling the controlled object according to the situation.

[0051] The control device 100 includes a processor unit 10, an FPGA unit 20, a read-only memory (ROM) 11, a RAM 12, and an I / O unit 30. The various components within the control device 100 are connected by a bus. Examples of buses include parallel buses and serial buses such as inter-integrated circuit (I2C) and serial peripheral interfaces (SPI). The processor unit 10 performs sequential processing, while the FPGA unit 20 performs parallel processing.

[0052] The processor unit 10 includes a CPU, which mainly performs processing related to the control and operation of the control object by executing programs stored in the ROM 11 and the RAM 12. The FPGA unit 20 constitutes a functional unit and performs specific processing on the digital values ​​input from the processor unit 10. The ROM 11 stores the program for controlling the control device 100 and the data required for the operation of the program. The RAM 12 functions as a work area for the processor unit 10. The I / O unit 30 provides an interface with the control object. The input / output device 200 is a device that presents information to the user and accepts operation input from the user, such as a touch screen.

[0053] In order to form functional units that execute specific processing, the FPGA unit 20 needs to be configured by writing configuration data into the device. Generally, the FPGA unit 20 is configured immediately after power is turned on to obtain functional units that can realize the required circuit operations.

[0054] However, the FPGA unit 20 may generate soft errors, which may be caused by changes in the information in the CRAM storing the configuration data due to radiation, etc. Therefore, the FPGA unit 20 performs error detection to detect soft errors in the CRAM. The soft error detection of the FPGA unit 20 is described in detail below.

[0055] like Figure 2As shown, the processor unit 10 includes an abnormality analysis unit 13. The FPGA unit 20 includes a CRAM 21, an abnormality detection unit 22, an abnormality reading unit 23, an abnormality recording unit 24, a timer unit 25, an abnormality notification unit 26, and a first communication interface (hereinafter referred to as communication IF) 27.

[0056] When the FPGA unit 20 is started up, it reads configuration data stored in a ROM (e.g., ROM 11) external to the FPGA unit 20 and stores it in the CRAM 21 within the FPGA unit 20. The CRAM 21 storing the configuration data is used as a user circuit. Here, the CRAM 21 is, for example, an SRAM (static random access memory).

[0057] The abnormality detection unit 22 uses, for example, a cyclic redundancy check (CRC) code to detect soft errors in the CRAM 21. Specifically, the abnormality detection unit 22 calculates a CRC value based on the value of the data stored in the CRAM 21, and performs a CRC check to compare the calculated CRC value with the CRC value stored in the CRAM 21. If the calculated CRC value is inconsistent with the stored CRC value, the abnormality detection unit 22 detects a soft error in the CRAM 21. The abnormality detection unit 22 performs CRC checks on multiple frames contained in the FPGA unit 20 in sequence. If the CRC check of all frames is completed, the CRC check is performed again starting from the initial frame in a loop.

[0058] Furthermore, the abnormality detection unit 22 may not perform CRC checks on all frames contained in the FPGA unit 20 as a single unit, but may divide the frames into predetermined blocks and perform CRC checks on each of the blocks. For example, the abnormality detection unit 22 may divide the FPGA unit 20 into four blocks, namely, the block constituting functional unit A through the block constituting functional unit D, and perform CRC checks on each of the blocks.

[0059] The abnormality reading unit 23 reads the soft error information detected by the abnormality detection unit 22 and writes it to the abnormality recording unit 24. The abnormality recording unit 24 records the soft error information detected by the abnormality detection unit 22. The soft error information includes, for example, the soft error location (error address) and the soft error type. Examples of soft error types include single-bit errors and adjacent double-bit errors. The abnormality recording unit 24 includes one or more log registers and a status register as registers.

[0060] The abnormality recording unit 24 records the information of the first soft error detected in the first log register. Furthermore, for soft errors detected for the second or subsequent times, if the detected soft error information is identical to the soft error information recorded in the first log register, the information is not recorded. Only if the information is different, the soft error information is recorded in the second log register. Similarly, for soft errors detected thereafter, if the detected soft error information is identical to the soft error information recorded in the first or second log register, the information is not recorded. Only if the information is different, the soft error information is recorded in the third log register.

[0061] In this embodiment, three log registers, namely the first, second, and third log registers, are provided. However, the number of log registers is not limited to this number; two or fewer, or four or more log registers may be provided. Furthermore, in this embodiment, if the anomaly detection unit 22 detects the fourth soft error, the anomaly recording unit 24 may display a warning on the input / output device 200 urging the user to restart the device. Since the CRAM 21 is volatile memory, restarting the control device 100 eliminates the soft error in the CRAM 21.

[0062] Furthermore, the abnormality recording unit 24 may record the status of each soft error recorded in the first, second, and third log registers, as well as the number of detected soft errors, in the status register. In this specification, the status of the soft errors recorded in the first, second, and third log registers are referred to as the first, second, and third states, respectively. The first, second, and third states are initially set to "unanalyzed."

[0063] The timer unit 25 notifies the abnormality notification unit 26 of the start of the interrupt generation process every time a predetermined time has elapsed. Upon receiving the notification from the timer unit 25, the abnormality notification unit 26 determines whether new soft error information has been recorded in the abnormality recording unit 24. The abnormality notification unit 26 can periodically perform this determination based on the notification from the timer unit 25. Furthermore, if the abnormality notification unit 26 determines that new soft error information has been recorded, it interrupts and notifies the abnormality analysis unit 13 of the processor unit 10 of the occurrence of the new soft error.

[0064] The first communication IF 27 is a communication IF between the abnormality recording unit 24 in the FPGA unit 20 and the abnormality analyzing unit 13 in the processor unit 10 .

[0065] The processor unit 10 includes an abnormality analysis unit 13. Upon receiving notification of a new soft error from the abnormality notification unit 26, the abnormality analysis unit 13 analyzes the soft error information recorded in the abnormality recording unit 24 and writes the analysis of the soft error to the abnormality recording unit 24. For example, the abnormality analysis unit 13 analyzes whether the location of the soft error is within a used area storing configuration data for functional units or within an unused area not storing such configuration data. Furthermore, if the location of the soft error is within a used area, the abnormality analysis unit 13 may analyze whether the location is within a circuit portion within the used area that has already been processed for the soft error. An example of a circuit that has already been processed for the soft error is a redundant circuit.

[0066] §3 Action Examples

[0067] Figure 3 This is a diagram showing the timing of each step of the control method of the control device 100. The vertical axis represents time. Figure 3 In the example of , it is shown that a soft error occurs in CRAM21 between time t1 and time t2. Figure 3 As shown, first, at time t1, the timer unit 25 notifies the abnormality notification unit 26 of the start of the interrupt generation process. Upon receiving the notification from the timer unit 25, the abnormality notification unit 26 reads the soft error information from the abnormality recording unit 24. At this point, no new soft error is detected, so the abnormality notification unit 26 immediately terminates the process.

[0068] Furthermore, assume that a soft error occurs in CRAM 21 between time t1 and time t2. Abnormality detection unit 22 detects soft errors at regular intervals. Abnormality reading unit 23 reads information about the soft errors detected by abnormality detection unit 22 and writes it to abnormality recording unit 24. Abnormality recording unit 24 records the soft error information detected by abnormality detection unit 22 in an empty log register. Abnormality recording unit 24 writes the number of soft errors detected (the number of soft errors recorded in the log register) to the status register.

[0069] At time t2, a predetermined time has passed since time t1, the timer unit 25 notifies the abnormality notification unit 26 of the start of the interruption generation process. Upon receiving the notification from the timer unit 25, the abnormality notification unit 26 reads the soft error information from the abnormality recording unit 24. At this point, a new soft error is detected, and the abnormality notification unit 26 notifies the abnormality analysis unit 13 that an interruption is required.

[0070] Upon receiving the interruption notification from the abnormality notification unit 26, the abnormality analysis unit 13 performs an interruption process. The abnormality analysis unit 13 reads the status register and log register information from the abnormality recording unit 24 via the first communication IF 27. The abnormality analysis unit 13 analyzes the new soft error information corresponding to the "unanalyzed" state.

[0071] The abnormality analysis unit 13 analyzes whether the soft error location is included in a used area storing the configuration data of the functional unit or in an unused area storing no configuration data of the functional unit. The abnormality analysis unit 13 obtains the "used area" or "unused area" as the analysis result of the soft error location.

[0072] The abnormality analysis unit 13 writes the "used area" or "unused area" status of the analyzed soft error into the status register of the abnormality recording unit 24 via the first communication interface 27. The "used area" or "unused area" status indicates that the corresponding soft error analysis is complete. Furthermore, the abnormality analysis unit 13 continues or stops the operation of the functional unit executed by the FPGA unit 20 based on the analysis results.

[0073] Next, at time t3, a predetermined time after time t2, timer unit 25 notifies abnormality notification unit 26 of the start of the interrupt generation process. Upon receiving the notification from timer unit 25, abnormality notification unit 26 reads soft error information from abnormality recording unit 24. At this point, no new soft error has been detected, so abnormality notification unit 26 terminates processing immediately.

[0074] Figure 4 FIG. 1 is a flow chart showing a control method of the control device 100. Figure 4 As shown, when the start of the interrupt generation process is notified from the timer unit 25, the abnormality notification unit 26 reads soft error information (the number of soft error detections and the first, second, and third states) from the abnormality recording unit 24 (step S1).

[0075] Next, the abnormality notification unit 26 determines whether the first state of the abnormality recording unit 24 is unanalyzed (step S2). If the first state is unanalyzed (YES in step S2), the process proceeds to step S21, where the abnormality notification unit 26 determines that the number of soft error analyses is zero.

[0076] If the first state is not "unanalyzed" (NO in step S2), the process proceeds to step S3, where the abnormality notification unit 26 determines whether the second state of the abnormality recording unit 24 is "unanalyzed." If the second state is "unanalyzed" (YES in step S3), the process proceeds to step S31, where the abnormality notification unit 26 determines that the number of soft error analyses is 1.

[0077] If the second status is not "unanalyzed" (NO in step S3), the process proceeds to step S4, where the abnormality notification unit 26 determines whether the third status of the abnormality recording unit 24 is "unanalyzed." If the third status is "unanalyzed" (YES in step S4), the process proceeds to step S41, where the abnormality notification unit 26 determines that the number of soft error analyses is 2.

[0078] If the third state is not unanalyzed (NO in step S4), the process proceeds to step S5, where the abnormality notification unit 26 determines that the number of soft errors analyzed is 3. After step S21, S31, S41, or S5, the process proceeds to step S6, where the abnormality notification unit 26 determines whether the number of soft errors analyzed is different from the number of soft errors detected.

[0079] If the number of soft errors detected differs from the number of soft errors analyzed (YES in step S6), the abnormality notification unit 26 determines that a new soft error has occurred and records this information in the log register of the abnormality recording unit 24. Next, the abnormality notification unit 26 notifies the abnormality analysis unit 13 of the need to interrupt processing (step S7). After step S7, the process ends. If NO in step S6, the abnormality notification unit 26 does not notify the abnormality analysis unit 13 of the processor unit 10 of the need to interrupt processing, and the process ends.

[0080] [Function, effect]

[0081] As described above, according to the above configuration, when the abnormality notification unit 26 determines that information about a new soft error is recorded in the abnormality recording unit 24, it notifies the processor unit 10 of the occurrence of the new soft error. Therefore, the frequency of abnormality notifications to the processor unit 10 can be reduced, and the load on the processor unit 10 related to soft error handling can be reduced.

[0082] Furthermore, the abnormality analysis unit 13 analyzes the soft error information recorded in the abnormality recording unit 24 and writes the analysis result to the abnormality recording unit 24. Therefore, the abnormality notification unit 26 can reliably determine whether new soft error information is recorded in the abnormality recording unit 24.

[0083] Furthermore, the abnormality analysis unit 13 analyzes whether the location where the soft error occurred is within a used area storing configuration data for a functional unit or within an unused area where no configuration data is stored. Therefore, if the location where the soft error occurred is within an unused area for a functional unit, operation can be continued, thereby preventing unnecessary operational downtime.

[0084] Furthermore, the processor unit 10 performs sequential processing, and the FPGA unit 20 performs parallel processing. Therefore, the FPGA unit 20 capable of parallel processing detects soft errors and records soft error information, and thus is less likely to interfere with other processing due to these processes.

[0085] On the other hand, the processor unit 10 performs sequential processing and, upon receiving notification of a soft error, must interrupt other processing. However, when the abnormality notification unit 26 determines that new soft error information has been recorded in the abnormality recording unit 24, it notifies the processor unit 10 of the occurrence of a new soft error. This reduces the frequency of soft error notifications to the arithmetic processing unit. Therefore, even when the processor unit 10 performs sequential processing, the frequency of interrupting other processing can be reduced.

[0086] Furthermore, upon receiving notifications from the timer unit 25, the abnormality notification unit 26 periodically performs processing to determine whether new soft error information has been recorded in the abnormality recording unit 24. Therefore, the abnormality notification unit 26 can perform processing to determine whether new soft error information has been recorded without receiving notifications from the abnormality detection unit 22. Consequently, for example, the control device 100 can be implemented using an existing FPGA without modifying the processing of the abnormality detection unit 22.

[0087] Furthermore, since the FPGA unit 20 includes the abnormality notification unit 26 , it is not necessary to provide another chip such as an application specific integrated circuit (ASIC) for providing the abnormality notification unit 26 . Therefore, the structure of the control device 100 can be simplified.

[0088] [Implementation Method 2]

[0089] Hereinafter, another embodiment of the present invention will be described. In addition, for the sake of convenience, the same reference numerals are given to components having the same functions as those described in the above embodiment, and their description will not be repeated.

[0090] Figure 5 1 is a block diagram showing a configuration example of the FPGA unit 20 and the processor unit 10 in the control device 100 according to Embodiment 2. Embodiment 2 differs from Embodiment 1 in that the control device 100 further includes an ASIC unit 40 , which includes a timer unit 45 and an abnormality notification unit 46 .

[0091] Specifically, the FPGA unit 20 includes a CRAM 21 , an abnormality detection unit 22 , an abnormality reading unit 23 , an abnormality recording unit 24 , a first communication IF 27 , and a second communication IF 28 . The second communication IF 28 is an IF for communicating with the ASIC unit 40 .

[0092] ASIC unit 40 includes a timer unit 45, an abnormality notification unit 46, and a third communication interface 47. Timer unit 45 and abnormality notification unit 46 of ASIC unit 40 have the same functions as timer unit 25 and abnormality notification unit 26 of FPGA unit 20 described in Embodiment 1, respectively. Third communication interface 47 is an interface for communication between ASIC unit 40 and FPGA unit 20.

[0093] In this manner, the timer unit 45 and the abnormality notification unit 46 may be formed as a circuit separate from the FPGA unit 20 including the CRAM 21 .

[0094] §4 Variations

[0095] While the embodiments of the present invention have been described in detail, the descriptions so far are merely illustrative of the present invention in all respects. Various improvements or modifications may be made without departing from the scope of the present invention. For example, the following changes may be made.

[0096] In the second embodiment, the abnormality notification unit 46 is provided in the ASIC unit 40 , but may be provided in an FPGA unit different from the FPGA unit 20 , or may be provided in a processor unit different from the processor unit 10 .

[0097] Furthermore, the abnormality analyzer 13 may write the number of analyzed soft errors (the number of soft errors whose status is not "unanalyzed") to the status register of the abnormality recorder 24 via the first communication IF 27. The abnormality notification unit 26 may read the number of analyzed soft errors from the status register.

[0098] Furthermore, the abnormality recording unit 24 may not record the number of soft error detections in the status register. The abnormality notification unit 26 may determine the number of soft error detections based on the number of log registers in which soft errors are recorded.

[0099] 〔Summarize〕

[0100] A control device according to one aspect of the present invention includes: an operation processing unit capable of executing a user program; a programmable circuit unit connected to the operation processing unit and constituting a functional unit; and an abnormality notification unit, wherein the programmable circuit unit includes: a storage unit for storing configuration data of the functional unit; an abnormality detection unit for detecting soft errors in the storage unit; and an abnormality recording unit for recording information on the soft errors detected by the abnormality detection unit, wherein the abnormality notification unit determines whether new information on the soft error is recorded in the abnormality recording unit, and if it is determined that new information on the soft error is recorded, the abnormality notification unit notifies the operation processing unit of the occurrence of the new soft error.

[0101] According to the above configuration, when the abnormality notification unit determines that new soft error information has been recorded in the abnormality recording unit, it notifies the arithmetic processing unit of the occurrence of the new soft error, thereby reducing the frequency of abnormality notifications to the arithmetic processing unit. Consequently, the load on the arithmetic processing unit related to soft error handling can be reduced.

[0102] In the control device of the first aspect, the arithmetic processing unit may also include an abnormality analysis unit that, upon notification of the occurrence of the new soft error from the abnormality notification unit, analyzes the soft error information recorded in the abnormality recording unit and writes a message to the abnormality recording unit indicating that the soft error analysis has been completed. With this configuration, the abnormality notification unit can reliably determine whether new soft error information is recorded in the abnormality recording unit.

[0103] In the control device of the first aspect, the abnormality analysis unit may also analyze whether the location where the soft error occurred is within a used area where the configuration data of the functional unit is stored, or within an unused area where the configuration data is not stored. With this configuration, operation can be continued even if the location where the soft error occurred is within the unused area of ​​the functional unit, thereby preventing unnecessary operational stoppage.

[0104] In the control device of the aspect described above, the arithmetic processing unit may perform sequential processing, and the programmable circuit unit may perform parallel processing. According to this configuration, the programmable circuit unit capable of parallel processing performs soft error detection and soft error information recording, thereby reducing the possibility that these processes will interfere with other processes.

[0105] On the other hand, the arithmetic processing unit performs sequential processing, so if notified of a soft error, other processing must be interrupted. However, the abnormality notification unit notifies the arithmetic processing unit of the occurrence of a new soft error when it determines that new soft error information has been recorded in the abnormality recording unit. Therefore, the frequency of soft error notification to the arithmetic processing unit is low. Therefore, even when the arithmetic processing unit performs sequential processing, the frequency of interrupting other processing can be reduced.

[0106] In the control device of the first aspect, the abnormality notification unit may also periodically perform processing to determine whether new soft error information has been recorded in the abnormality recording unit. According to this configuration, the abnormality notification unit can perform processing to determine whether new soft error information has been recorded without receiving notification from the abnormality detection unit. Therefore, for example, the control device can be implemented using a commercially available FPGA without changing the processing of the abnormality detection unit.

[0107] In the control device of the first aspect, the programmable circuit unit may also include the abnormality notification unit. According to this structure, it is not necessary to provide another chip such as an ASIC (application specific integrated circuit) for the abnormality notification unit, thereby simplifying the structure of the control device.

[0108] A control method for a control device according to one aspect of the present invention is a control method for a control device comprising the following parts: an operation processing unit capable of executing a user program; and a programmable circuit unit connected to the operation processing unit to constitute a functional unit, and the control method for the control device comprises: an abnormality detection step for detecting a soft error in a storage unit, wherein the storage unit stores configuration data of the functional unit; an abnormality recording step for recording information on the soft error detected in the abnormality detection step; and an abnormality notification step for determining whether new information on the soft error is recorded in the abnormality recording step, and if it is determined that new information on the soft error is recorded, notifying the operation processing unit of the occurrence of the new soft error.

[0109] The control device of each embodiment of the present invention can also be implemented by a computer. In this case, the control device is implemented by a computer by running the computer as the various parts (software elements) included in the control device. The control program of the control device and the computer-readable recording medium recording the control program are also included in the scope of the present invention.

[0110] The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims. Embodiments obtained by appropriately combining technical means disclosed in different embodiments are also included in the technical scope of the present invention.

Claims

1. A control device, comprising: The calculation processing unit can execute the user program; A programmable circuit unit, connected to the arithmetic processing unit, constituting a functional unit; as well as Abnormal Notification Department, The programmable circuit unit comprises: A storage unit for storing configuration data of the functional unit; an abnormality detection unit that detects a soft error in the storage unit; and an abnormality recording unit, recording information of the soft error detected by the abnormality detection unit, The abnormality notification unit determines whether new information of the soft error is recorded in the abnormality recording unit according to the state of the soft error, wherein the state of the soft error indicates that the corresponding soft error analysis is completed, When the number of detected soft errors is different from the number of analyzed soft errors, the abnormality notification unit determines that the information is new soft errors, When it is determined that new information of the soft error is recorded, the occurrence of the new soft error is notified to the arithmetic processing unit.

2. The control device according to claim 1, wherein: The operation processing unit includes: The abnormality analyzing unit analyzes the information of the soft error recorded in the abnormality recording unit and writes a message indicating that the soft error has been analyzed in the abnormality recording unit when the abnormality notifying unit notifies the occurrence of the new soft error.

3. The control device according to claim 2, wherein: The abnormality analysis unit analyzes whether a location where the soft error occurs is included in a used area where the configuration data of the functional unit is stored or in an unused area where the configuration data is not stored.

4. The control device according to any one of claims 1 to 3, wherein: The arithmetic processing unit performs sequential processing, and the programmable circuit unit performs parallel processing.

5. The control device according to any one of claims 1 to 3, wherein: The abnormality notification unit periodically performs a process of determining whether new information of the soft error is recorded in the abnormality recording unit.

6. The control device according to any one of claims 1 to 3, wherein: The programmable circuit section includes the abnormality notification section.

7. A control method for a control device, the control device comprising: The calculation processing unit can execute the user program; and a programmable circuit unit connected to the arithmetic processing unit to constitute a functional unit, and the control method of the control device includes: an abnormality detection step of detecting a soft error in a storage unit that stores configuration data of the functional unit; an abnormality recording step, recording information of the soft error detected in the abnormality detecting step; and an abnormality notification step, determining whether new information of the soft error is recorded in the abnormality recording step according to the status of the soft error, wherein the status of the soft error indicates that the corresponding soft error analysis is completed, and when the number of soft errors detected is different from the number of soft errors analyzed, the abnormality notification step determines that it is new information of the soft error, and when it is determined that new information of the soft error is recorded, notifying the operation processing unit of the occurrence of the new soft error.

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