An image processing system

Abstract

The present invention relates to an image processing system, comprising a main control module constructed using the RISC-V architecture and connected to a median filter module via a bus; the median filter module synchronizes with the main control module's clock via a clock interface; the main control module sets the filter type of the median filter module via a filter selection interface, and then sends image data to the median filter module in batches via a write data interface based on a clock signal; the median filter module performs median filtering on the image data based on a filtering algorithm corresponding to the filter type. The present invention implements RISC-V-based median filtering. Due to the simplicity of the RISC-V instruction set, the median filter image processing process saves a large amount of circuitry, significantly reduces power consumption and area, and saves costs.

Description

Technical Field

[0001] The present invention relates to the technical field of image processing, and in particular to an image processing system. Background Art

[0002] As a nonlinear smoothing technology in image processing, median filtering sets the grayscale value of each pixel to the median of the grayscale values ​​of all pixels in a certain neighborhood window of the point, making the value of the pixel closer to the true value of the surrounding area, thereby eliminating isolated noise points and effectively suppressing noise.

[0003] In the prior art, median filtering of images is performed by building corresponding algorithms based on FPGAs. Although median filtering can be achieved, the cost and power consumption are very high. Summary of the Invention

[0004] In order to solve the problems of high cost and high power consumption in the prior art, the present invention provides an image processing system, which has the characteristics of lower power consumption and lower cost.

[0005] An image processing system includes: a main control module and a median filter module, wherein the main control module is constructed using a RISC-V architecture;

[0006] The main control module and the median filter module are connected via a bus;

[0007] The median filter module includes a data write interface, a clock interface and a filter selection interface;

[0008] The median filter module is synchronized with the clock of the main control module through the clock interface;

[0009] The main control module is configured to set the filter type of the median filter module through the filter selection interface, and then send the pixel value of each row to the median filter module through the write data interface based on a clock signal;

[0010] The median filtering module is used to perform median filtering on the pixel values ​​based on a filtering algorithm corresponding to the filtering type.

[0011] Furthermore, the median filter module further includes: a module enable interface and a main control enable interface;

[0012] When the signal of the module enabling interface received by the main control module is at a high level and the signal received by the main control enabling interface is at a high level, the main control module and the median filtering module are successfully connected.

[0013] Furthermore, the median filtering module further includes: a data reading interface, and the median filtering module is further configured to send the filtered pixel values ​​to the main control module via the data reading interface.

[0014] Furthermore, the median filter module further includes: a reset interface, and the median filter module is further configured to be reset when the reset interface receives a low level.

[0015] Furthermore, the median filter module further includes: an interrupt interface, and the median filter module is further configured to receive an interrupt signal from the main control module through the interrupt interface.

[0016] Furthermore, the median filter module further includes: a write enable interface, and the median filter module is further configured to start receiving the pixel value of each row when the write enable interface is at a high level.

[0017] Furthermore, the median filter module further includes: a read enable interface, and the median filter module is further configured to send the filtered pixel value to the main control module when the read enable interface is at a high level.

[0018] Furthermore, the median filter module is provided with random access memories arranged in sequence, and starting from the second random access memory, each random access memory reads the pixel value in the adjacent previous random access memory to overwrite the currently stored pixel value and then store it; the first random access memory is used to store the entire row of pixel values ​​sent by the main control module, and the new entire row of pixel values ​​overwrites the currently stored entire row of pixel values ​​for storage.

[0019] Furthermore, the median filtering module is used to perform median filtering on the pixel values ​​in the preset number of random access memories based on the filtering algorithm corresponding to the filtering type when the number of random access memories storing a whole row of pixel values ​​is the same as the preset number of filtering types.

[0020] Furthermore, the median filtering module is also used to perform median filtering on the pixel values ​​in the preset number of random access memories after completing the median filtering processing, and when the random access memories with serial numbers corresponding to the preset number have stored a new entire row of pixel values, based on the filtering algorithm corresponding to the filtering type, until the random access memories with serial numbers corresponding to the preset number no longer store new pixel values.

[0021] The present invention has the following beneficial effects: a main control module constructed using the RISC-V architecture is connected to a median filter module via a bus; the median filter module is synchronized with the main control module's clock via a clock interface; the main control module sets the filter type of the median filter module via a filter selection interface, and then sends image data in batches to the median filter module via a write data interface based on the clock signal; the median filter module performs median filtering on the image data based on a filtering algorithm corresponding to the filter type. RISC-V-based median filtering is implemented, and due to the simplicity of the RISC-V instruction set, the implementation of the median filter image processing process saves a large amount of circuitry, significantly reduces power consumption and area, and saves costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0023] Figure 1 is a schematic structural diagram of an image processing system provided according to an exemplary embodiment;

[0024] Figure 2 is a schematic diagram of an interface of a median filter module provided according to an exemplary embodiment;

[0025] Figure 3 is a diagram showing a filtering processing principle of a 3*3 filtering model provided according to an exemplary embodiment;

[0026] Figure 4 is a diagram showing a filtering processing principle of a 5*5 filtering model provided according to an exemplary embodiment;

[0027] Figure 5 is a diagram showing a filtering processing principle of a 7*7 filtering model provided according to an exemplary embodiment;

[0028] Figure 6 is a processing flow chart of median filtering provided according to an exemplary embodiment. DETAILED DESCRIPTION

[0029] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0030] Reference Figure 1 and Figure 2 As shown, an embodiment of the present invention provides an image processing system, which may include: a main control module 1 and a median filter module 3, wherein the main control module 1 is constructed using a RISC-V architecture;

[0031] The main control module 1 and the median filter module 3 are connected via a bus 2;

[0032] The median filter module 3 includes a data write interface, a clock interface and a filter selection interface;

[0033] The median filter module 3 is synchronized with the clock of the main control module 1 through the clock interface;

[0034] The main control module 1 is used to set the filter type of the median filter module 3 through the filter selection interface, and then send the pixel value of each row to the median filter module 3 through the write data interface based on the clock signal;

[0035] The median filter module 3 is used to perform median filtering on pixel values ​​based on a filtering algorithm corresponding to the filtering type.

[0036] Specifically, RISC-V is an open source instruction set architecture based on the principle of a reduced instruction set (RISC-V) architecture. It has the characteristics of being completely open source, does not have corresponding high licensing fees, and can be used completely freely and free of charge. At the same time, the RISC-V architecture is simpler than mainstream X86 and ARM architectures, with dozens of instructions in total and capable of modular design. In addition, it is also very convenient to transplant Linux and Unix systems to the RISC-V platform. Through the main control module and corresponding median filter module developed based on RISC-V, the median filter module can be connected to the main control module as an IP (processing core) through a bus structure. When there is data that needs to be processed by median filtering, the filter selection interface is first used to select the filter type through the filter selection signal, and then the median filter module 3 is shaken by the bus. After the handshake is successful, data transmission begins. After the median filter module 3 receives the data, it starts to calculate based on the filtering algorithm of the corresponding filter type and returns the calculation result to the main control module 1 through the bus, until the median calculation of the entire image is completed and the operation is terminated.

[0037] Because the main control modules designed based on the RISC-V instruction set are designed with low power consumption, low cost and small area performance requirements, and due to the simplicity of the RISC-V architecture, a large amount of circuits are saved in the design of the corresponding main control modules, which greatly reduces power consumption and area, thereby reducing the cost and difficulty of implementation.

[0038] As a feasible implementation of the above embodiment, median filtering sets the grayscale value of each pixel in the image to the median of the grayscale values ​​of all pixels within a certain neighborhood window of that pixel, making the value of that pixel closer to the surrounding true value, thereby eliminating isolated noise points and effectively suppressing noise. Therefore, the implementation of median filtering in the median filtering module can be achieved by storing the corresponding pixel values ​​in a random access memory (RAM) provided in the median filtering module and then performing the corresponding batch calculations.

[0039] A random access memory arranged in sequence is provided in the median filter module. Starting from the second random access memory, each random access memory reads the pixel value in the adjacent previous random access memory to overwrite the currently stored pixel value and then store it; the first random access memory is used to store the entire row of pixel values ​​sent by the main control module, and the new entire row of pixel values ​​overwrites the currently stored entire row of pixel values ​​for storage.

[0040] The median filtering module 3 is used to perform median filtering on the pixel values ​​in the preset number of random access memories based on the filtering algorithm corresponding to the filtering type when the number of random access memories storing the entire row of pixel values ​​is the same as the preset number of filtering types.

[0041] The median filtering module is also used to perform median filtering on the pixel values ​​in the preset number of random access memories each time a new median filtering process is completed, and when the random access memories with serial numbers corresponding to the preset number have stored a new entire row of pixel values, perform median filtering on the pixel values ​​in the preset number of random access memories based on the filtering algorithm corresponding to the filtering type until the random access memories with serial numbers corresponding to the preset number no longer store new pixel values.

[0042] Specifically, refer to Figures 3 to 5 As shown in the figure, for the median filtering algorithm, that is, g(x,y)=med{f(xk,yl),(k,l∈W)}, f(x,y), g(x,y) are the original image and the processed image respectively, and W is the two-dimensional template, that is, the corresponding filtering type, which is usually composed of processing areas such as 3x3, 5x5, and 7x7.

[0043] The main control module selects the median filter type through the filter selection interface and then uses RAM for buffering. A cache matrix of 3, 5, or 7 RAMs can be used, respectively. Data can be 8-bit wide and up to 1920 pixels deep, supporting pixel value processing for 1080P (1920x1080) images. The median filter module employs a pipelined architecture synchronized to the clock, processing one pixel per clock cycle and outputting the result in the corresponding clock cycle, accelerating computation. After receiving data transmitted via the bus, it buffers the data into RAM0. Once RAM0 has buffered a full row of image data, RAM1 begins reading data from RAM0, while RAM0 continues to buffer pixel value data from the main control module. Similarly, RAM2 reads data from RAM1 after RAM1 has buffered a full row of data. For example, in a 3x3 model, median filter computation begins after RAM2 has buffered a full row of data. In this 3x3 model, data is read from each of the three RAMs, three at a time, for comparison and computation. The calculation is performed in a hardware parallel processing mode, and finally the middle value of the matrix can be quickly obtained to replace the pixel value at the middle position of the current matrix, such as Figure 3 In the middle, it is the position of 12. The same is true for 5x5, 7x7 and other models. Figure 4 、 Figure 5 shown.

[0044] The specific processing steps are as follows:

[0045] After caching m rows of image pixel data through m RAMs;

[0046] Read m data from each RAM at a time, a total of m*m data;

[0047] Sort m*m data and calculate the median;

[0048] Replace the median data in the image with (m 2 +1) / 2;

[0049] Repeat the above steps until the data in the data matrix formed by the current RAM is calculated, that is, the median filter window calculates the pixel data;

[0050] After receiving the pixel values ​​of the entire row, the m*m data matrix is ​​constructed and the median filter calculation process is continued until the entire image is processed. The median filter algorithm is completed. Here, m can be an odd number such as 3, 5, or 7.

[0051] Reference Figure 2 As shown, in some specific embodiments of the present invention, the median filter module further includes: a module enable interface and a master enable interface;

[0052] When the signal of the module enable interface received by the main control module is at a high level and the signal received by the main control enable interface is at a high level, the main control module and the median filter module are successfully connected.

[0053] The median filter module further includes: a data reading interface, and the median filter module is further configured to send the pixel values ​​after filtering to the main control module via the data reading interface.

[0054] The median filter module further includes: a reset interface, and the median filter module is further configured to be reset when the reset interface receives a low level.

[0055] The median filter module further includes: an interrupt interface, and the median filter module is further configured to receive an interrupt signal from the main control module via the interrupt interface.

[0056] The median filter module further includes: a write enable interface, and the median filter module is further configured to start receiving the pixel value of each row when the write enable interface is at a high level.

[0057] The median filter module further includes: a read enable interface, and the median filter module is further configured to send the filtered pixel value to the main control module when the read enable interface is at a high level.

[0058] For details, refer to the table below for the names, number of bits, and corresponding transmission directions of the signals transmitted by each interface.

[0059] Table 1. Interface signal table

[0060]

[0061]

[0062] Among them, clk and rst_n are the input clock and reset signals of the clock interface and reset interface of the median module respectively, and reset is valid at low level for reset.

[0063] The ready signal is the signal sent by the module enable interface. When the median filter module is ready to receive data, the interface signal of the interface is set to 1, otherwise it is 0.

[0064] The valid signal is sent by the main control module. When the main control module needs to perform median filtering, this signal is set to 1, otherwise it is 0. When both the valid and ready signals are 1, the main control module and the median filter module reach a handshake state and can exchange data.

[0065] w_en and w_data are the corresponding signals of the write enable interface and write data interface respectively, and 8 bits of data are written in each clock cycle.

[0066] r_en and r_data are the signals of the corresponding read enable interface and read data interface respectively. After the median filter algorithm processes the pixel value, 8 bits of data are read into the main control module in each clock cycle.

[0067] intr is the signal of the interrupt interface. When the median filter module receives the interrupt control signal from the main control module, it handles the interrupt problem of the median filter module.

[0068] select is the signal of the filter selection interface, which can be used to select the median filter model configuration.

[0069] For example, when the select signal configuration is 00, the 3x3 filter model is selected, when it is 01, the 5x5 filter model is selected, and when it is 10, the 7x7 filter model is selected.

[0070] It is understood that those skilled in the art may set or reset the specific settings and expansions of the filter types according to actual application requirements, and the present invention does not impose any limitation thereto.

[0071] Reference Figure 6 As shown, the embodiment of the present invention also provides a specific implementation process of median filtering, and the specific process is as follows:

[0072] 101. The main control module determines to perform median filtering;

[0073] 102. Select filter type;

[0074] 103. Determine that data can be transmitted through a bus transmission enable signal;

[0075] 104. The median filter module receives data;

[0076] 105. The median filter module calculates the median;

[0077] 106. The calculation results are transmitted to the main control module in real time via the bus;

[0078] 107. The median calculation of the entire image is completed.

[0079] The RISC-V architecture-based master control module can connect to the median filter module via a bus by mounting the IP mode (the processing core composed of the median filter module). When data requires median filtering, the master control module first selects the filter model using the filter selection interface, then performs a handshake with the filter module via the bus. Data communication is then possible when both the ready and valid signals are 1. Data transmission then begins. After receiving the data, the median filter module begins calculations (based on the specific implementation process of the median filter described above) and returns the results to the master control module via the bus. This process continues until the median calculation of the entire image is completed.

[0080] The image processing system provided by the above-described embodiments of the present invention utilizes a main control module and a corresponding median filter module designed based on the RISC-V instruction set. Leveraging the simplicity and efficiency of the RISC-V architecture, the system saves a significant amount of circuitry in the design of the main control module and median filter module, significantly reducing power consumption and area. Furthermore, because the RISC-V architecture is open, it allows for more flexible selection of different instruction sets, thereby reducing costs.

[0081] Compared with traditional processors, the present invention can realize image preprocessing at low power consumption and low cost, while improving processing efficiency.

[0082] For simplicity of description, the aforementioned method embodiments are described as a series of actions. However, those skilled in the art should be aware that the present invention is not limited by the order of the actions described, as certain steps can be performed in other orders or simultaneously according to the present invention. Furthermore, those skilled in the art should also be aware that the embodiments described in this specification are preferred embodiments, and the actions and modules involved are not necessarily required for the present invention.

[0083] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similarities between the various embodiments can be referred to in conjunction with each other. For device embodiments, since they are generally similar to method embodiments, their description is relatively simple, and for relevant details, reference can be made to the description of the method embodiments.

[0084] The steps in the methods of the various embodiments of the present invention can be adjusted in sequence, combined, and deleted according to actual needs, and the technical features recorded in the various embodiments can be replaced or combined.

[0085] The modules and submodules in the devices and terminals of various embodiments of the present invention may be combined, divided, or deleted according to actual needs.

[0086] In the several embodiments provided herein, it should be understood that the disclosed terminals, devices, and methods can be implemented in other ways. For example, the terminal embodiments described above are merely illustrative. For example, the division of modules or submodules is merely a logical functional division. In actual implementation, other division methods may be used, such as combining or integrating multiple submodules or modules into another module, or omitting or not implementing certain features. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between devices or modules via some interface, which may be electrical, mechanical, or other forms.

[0087] The modules or submodules described as separate components may or may not be physically separate, and the components of the modules or submodules may or may not be physical modules or submodules, that is, they may be located in one place or distributed across multiple network modules or submodules. Some or all of the modules or submodules may be selected to achieve the purpose of this embodiment according to actual needs.

[0088] In addition, the functional modules or submodules in the various embodiments of the present invention may be integrated into a single processing module, or each module or submodule may exist physically separately, or two or more modules or submodules may be integrated into a single module. The aforementioned integrated modules or submodules may be implemented in the form of hardware or software functional modules or submodules.

[0089] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0090] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, software units executed by a processor, or a combination of the two. The software units may be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0091] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0092] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An image processing system, characterized in that: include: Main control module and median filter module, The main control module is constructed using the RISC-V architecture; The main control module and the median filter module are connected via a bus; The median filter module includes a data write interface, a clock interface and a filter selection interface; The median filter module is synchronized with the clock of the main control module through the clock interface; The main control module is configured to set the filter type of the median filter module through the filter selection interface, and then send the pixel value of each row to the median filter module through the write data interface based on a clock signal; The median filtering module is used to perform median filtering on the pixel values ​​based on a filtering algorithm corresponding to the filtering type, where the filtering type is a two-dimensional template consisting of 3x3, 5x5, or 7x7 processing areas.

2. The system according to claim 1, wherein: The median filter module also includes: a module enable interface and a main control enable interface; When the signal of the module enabling interface received by the main control module is at a high level and the signal received by the main control enabling interface is at a high level, the main control module and the median filtering module are successfully connected.

3. The system according to claim 1, wherein: The median filter module further includes: a data reading interface, and the median filter module is further configured to send the filtered pixel values ​​to the main control module via the data reading interface.

4. The system according to claim 1, wherein: The median filter module further includes: a reset interface, and the median filter module is further configured to be reset when the reset interface receives a low level.

5. The system according to claim 1, wherein: The median filter module further includes an interrupt interface, and the median filter module is further configured to receive an interrupt signal from the main control module through the interrupt interface.

6. The system according to claim 1, wherein: The median filter module further includes: a write enable interface, and the median filter module is further configured to start receiving the pixel value of each row when the write enable interface is at a high level.

7. The system according to claim 3, wherein: The median filter module further includes: a read enable interface, and the median filter module is further configured to send the filtered pixel value to the main control module when the read enable interface is at a high level.

8. The system according to claim 1, wherein: The median filter module is provided with random access memories arranged in sequence. Starting from the second random access memory, each random access memory reads the pixel value in the adjacent previous random access memory to overwrite the currently stored pixel value and then store it; the first random access memory is used to store the entire row of pixel values ​​sent by the main control module, and the new entire row of pixel values ​​overwrites the currently stored entire row of pixel values ​​for storage.

9. The system according to claim 8, characterized in that The median filtering module is used to perform median filtering on the pixel values ​​in the preset number of random access memories based on the filtering algorithm corresponding to the filtering type when the number of random access memories storing a whole row of pixel values ​​is the same as the preset number of filtering types.

10. The system according to claim 9, characterized in that The median filtering module is also used to perform median filtering on the pixel values ​​in the preset number of random access memories based on the filtering algorithm corresponding to the filtering type after completing the median filtering processing on the pixel values ​​in the preset number of random access memories and when the random access memories with serial numbers corresponding to the preset number have stored a new entire row of pixel values, until the random access memories with serial numbers corresponding to the preset number no longer store new pixel values.

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