A method for preparing a semiconductor structure

Abstract

The present invention provides a method for manufacturing a semiconductor structure. The method for manufacturing the semiconductor structure includes: providing a semiconductor substrate; forming a first epitaxial layer on the semiconductor substrate; forming a diffusion film on a surface of the first epitaxial layer facing away from the semiconductor substrate, the diffusion film having diffusion atoms; after forming the diffusion film, performing an annealing treatment to allow the diffusion atoms to enter the first epitaxial layer, the diffusion atoms being suitable for filling atomic vacancies in the first epitaxial layer. The present invention introduces the diffusion atoms in the diffusion film into the first epitaxial layer to fill the vacancies inside the first epitaxial layer, reduces the deep-level defects in the first epitaxial layer, achieves the purpose of improving the carrier lifetime, avoids damage to the surface of the first epitaxial layer, is convenient to implement, and reduces the production cost.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and particularly relates to a method for preparing a semiconductor structure. Background Art

[0002] 4H-SiC material has the advantages of high critical breakdown electric field, high thermal conductivity, and high electron mobility. It is an excellent material for manufacturing high-voltage, high-temperature, and high-frequency power semiconductor devices, and is also the third-generation semiconductor material with the best commercial performance and the most mature technology at present. Compared with silicon PiN diodes, when the same breakdown voltage is achieved, the SiC PiN diode can achieve a higher doping concentration in the drift region and a thinner thickness. Compared with SiC Schottky diodes, it can achieve a higher breakdown voltage and a smaller leakage current. When conducting forward, minority carriers are injected into the drift layer to generate a conductance modulation effect. The voltage drop in the drift region is no longer limited by the low doping concentration and the epitaxial thickness, which can greatly improve the current-carrying capacity of the device and reduce the specific on-resistance. Deep-level defect centers in the epitaxial layer are important factors affecting the carrier lifetime. These defect energy levels capture the corresponding carriers, resulting in a decrease in the effective carrier concentration. At the same time, surface recombination, recombination at the substrate and interface will all have an adverse impact on the carrier lifetime, thereby affecting the conductance modulation effect of the device.

[0003] The prior art usually uses ion implantation to improve the interface performance. However, using the ion implantation process will cause serious damage to the surface of the semiconductor material, and the equipment for ion implantation is expensive, making it difficult to balance the effect and cost. Summary of the Invention

[0004] Therefore, the technical problem to be solved by the present invention is to overcome the defects that when improving the carrier lifetime of the semiconductor epitaxial layer in the prior art, the ion implantation process causes serious damage to the semiconductor epitaxial layer and the equipment for ion implantation is expensive, and further provide a method for preparing a semiconductor structure.

[0005] The present invention provides a method for preparing a semiconductor structure, including: providing a semiconductor substrate; forming a first epitaxial layer on the semiconductor substrate; forming a diffusion film on a surface of the first epitaxial layer facing away from the semiconductor substrate, the diffusion film having diffusion atoms; after forming the diffusion film, performing an annealing treatment to enable the diffusion atoms to enter the first epitaxial layer, and the diffusion atoms are suitable for filling atomic vacancies in the first epitaxial layer.

[0006] Optionally, the annealing treatment includes a first heat preservation stage to an Nth heat preservation stage performed in sequence, the temperature of the kth heat preservation stage is higher than the temperature of the (k + 1)th heat preservation stage, N is an integer greater than or equal to 2, and k is an integer greater than or equal to 1 and less than or equal to N - 1.

[0007] Optionally, the annealing treatment is carried out in an inert gas atmosphere.

[0008] Optionally, the diffusion film is a carbon film; the step of forming the diffusion film includes: forming a photoresist film on the surface of the first epitaxial layer facing away from the semiconductor substrate; performing carbonization treatment on the photoresist film in a nitrogen atmosphere so that the photoresist film forms the diffusion film.

[0009] Optionally, the thickness of the photoresist film is 0.1 μm to 20 μm.

[0010] Optionally, the temperature of the carbonization treatment is 500 °C to 1000 °C, and the time of the carbonization treatment is 10 min to 60 min.

[0011] Optionally, after the step of forming a photoresist film on the surface of the first epitaxial layer facing away from the semiconductor substrate and before the step of performing carbonization treatment on the photoresist film in a nitrogen atmosphere, it further includes: performing a heat treatment on the photoresist film, the temperature of the heat treatment is 50 °C to 200 °C, and the time of the heat treatment is 1 min to 10 min.

[0012] Optionally, the diffusion film is a carbon film; N is equal to 3, the temperature of the first heat preservation stage is 1600 °C to 1800 °C, and the time of the first heat preservation stage is 30 min to 120 min; the temperature of the second heat preservation stage is 1400 °C to 1600 °C, and the time of the second heat preservation stage is 30 min to 120 min; the temperature of the third heat preservation stage is 1200 °C to 1400 °C, and the time of the third heat preservation stage is 30 min to 120 min.

[0013] Optionally, it further includes: after the step of performing the annealing treatment, removing the diffusion film; after removing the diffusion film, forming a second epitaxial layer on the surface of the first epitaxial layer facing away from the semiconductor substrate, and the conductivity type of the second epitaxial layer is opposite to that of the first epitaxial layer.

[0014] Optionally, the conductivity type of the first epitaxial layer is N-type, and the conductivity type of the second epitaxial layer is P-type.

[0015] Optionally, after the step of removing the diffusion film and before the step of forming a second epitaxial layer on the surface of the first epitaxial layer facing away from the semiconductor substrate, it further includes: passivating the dangling bonds on the surface of the first epitaxial layer facing away from the semiconductor substrate.

[0016] Optionally, the step of passivating the dangling bonds on the surface of the first epitaxial layer facing away from the semiconductor substrate includes: oxidizing the surface of the first epitaxial layer facing away from the semiconductor substrate with an oxygen-containing oxidizing gas; after the oxidation treatment, passivating the surface of the first epitaxial layer facing away from the semiconductor substrate with a nitrogen-containing gas.

[0017] Optionally, the oxygen-containing oxidizing gas includes oxygen.

[0018] Optionally, the nitrogen-containing gas includes one or a mixture of nitrogen, nitric oxide, or nitrous oxide.

[0019] Optionally, the temperature of the oxidation treatment is 1100°C to 1500°C, and the time of the oxidation treatment is 10 min to 120 min; the temperature of the surface passivation treatment is 1100°C to 1500°C, and the time of the surface passivation treatment is 20 min to 80 min.

[0020] Optionally, after the step of passivating the dangling bonds on the surface of the first epitaxial layer facing away from the semiconductor substrate and before the step of forming a second epitaxial layer on the surface of the first epitaxial layer facing away from the semiconductor substrate, it further includes: removing the oxide layer on the surface of the first epitaxial layer.

[0021] Optionally, the material of the first epitaxial layer is silicon carbide doped with N-type conductive ions.

[0022] Optionally, the doping concentration of N-type conductive ions in the first epitaxial layer is 1×10 13 atom / cm 3 ~1×10 16 atom / cm 3 .

[0023] Optionally, the thickness of the first epitaxial layer is 2 μm to 300 μm.

[0024] Optionally, the semiconductor substrate is a silicon carbide substrate.

[0025] The technical solution of the present invention has the following advantages:

[0026] The manufacturing method of the semiconductor structure provided by the technical solution of the present invention includes: providing a semiconductor substrate; forming a first epitaxial layer on the semiconductor substrate; forming a diffusion film on the surface of the first epitaxial layer facing away from the semiconductor substrate, where the diffusion film contains diffusion atoms; after forming the diffusion film, performing an annealing treatment to allow the diffusion atoms to enter the first epitaxial layer, and the diffusion atoms are suitable for filling the atomic vacancies in the first epitaxial layer. The present invention enables the diffusion atoms in the diffusion film to enter the first epitaxial layer to fill the vacancies inside the first epitaxial layer, which can reduce the deep-level defects in the first epitaxial layer and achieve the purpose of improving the carrier lifetime. Traditional ion implantation equipment is expensive, and the ion implantation process will cause serious damage to the material surface and damage the device performance. The present invention allows the diffusion atoms to enter the interior of the first epitaxial layer through diffusion by annealing treatment. The implementation method is simple, which can replace expensive ion implantation equipment, reduce production costs, and will not damage the surface of the first epitaxial layer.

[0027] Further, the annealing treatment includes a first heat preservation stage to an Nth heat preservation stage carried out in sequence. The temperature of the kth heat preservation stage is higher than that of the (k + 1)th heat preservation stage. N is an integer greater than or equal to 2, and k is an integer greater than or equal to 1 and less than or equal to N - 1. Through the annealing treatment with a stepped temperature, the deep-level defects inside the first epitaxial layer can be further reduced, and the purpose of improving the carrier lifetime in the first epitaxial layer can be achieved.

[0028] Further, passivation treatment is performed on the dangling bonds on the surface of the first epitaxial layer facing away from the semiconductor substrate. Performing passivation treatment on the surface of the first epitaxial layer can form covalent bonds with the dangling bonds on the surface of the first epitaxial layer, reduce the interface state density, thereby reducing the surface recombination rate and further improving the carrier lifetime. Description of the Drawings

[0029] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0030] Figure 1 It is the process flow chart of the manufacturing process of the semiconductor structure provided in this embodiment;

[0031] Figure 2 It is the schematic diagram of the semiconductor structure formed in this embodiment;

[0032] Figure 3 It is the schematic diagram of the carrier movement at the interface between the diffusion film and the first epitaxial layer in this embodiment;

[0033] Figure 4 Schematic diagram of a semiconductor structure formed in one embodiment. Detailed implementation manners

[0034] A method for preparing a semiconductor structure includes: injecting ions into an epitaxial layer by using an ion implantation process to fill deep-level defects in the epitaxial layer.

[0035] However, this ion implantation process in this method will cause serious damage to the surface of the semiconductor material, and the equipment for ion implantation is expensive, making it difficult to balance the effect and cost.

[0036] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0037] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present invention. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0038] In the description of the present invention, it should be noted that unless otherwise clearly specified and limited, the terms "installed", "connected", "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0039] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0040] This embodiment provides a method for preparing a semiconductor structure. The preparation flow chart is as shown in Figure 1, and the formed semiconductor structure is as Figure 2 shown, including the following steps:

[0041] Step S1: Provide a semiconductor substrate 01;

[0042] Step S2: Form a first epitaxial layer 02 on the semiconductor substrate 01;

[0043] Step S3: Form a diffusion film 03 on the surface of the first epitaxial layer 02 facing away from the semiconductor substrate 01, and diffusion atoms 04 are present in the diffusion film 03;

[0044] After forming the diffusion film 03, perform an annealing treatment to allow the diffusion atoms 04 to enter the first epitaxial layer 02, and the diffusion atoms 04 are suitable for filling atomic vacancies 05 in the first epitaxial layer 02.

[0045] The carrier movement at the interface between the diffusion film and the first epitaxial layer is as Figure 3 shown. Allowing the diffusion atoms 04 in the diffusion film 03 to enter the first epitaxial layer 02 to fill the atomic vacancies 05 inside the first epitaxial layer 02 can reduce the deep-level defects in the first epitaxial layer 02 and achieve the purpose of improving the carrier lifetime.

[0046] In this embodiment, the annealing treatment includes a first heat preservation stage to an Nth heat preservation stage performed in sequence, the temperature of the kth heat preservation stage is higher than that of the (k + 1)th heat preservation stage, N is an integer greater than or equal to 2, and k is an integer greater than or equal to 1 and less than or equal to N - 1. Through the annealing treatment with a stepped temperature, the first epitaxial layer 02 with more balanced and stable carriers can be formed, further reducing the deep-level defects inside the first epitaxial layer 02 and achieving the purpose of improving the carrier lifetime.

[0047] In this embodiment, the annealing treatment is performed in an inert gas atmosphere. The inert gas atmosphere can protect the diffusion film 03 from being oxidized.

[0048] In one embodiment, the diffusion film 03 is a carbon film; the steps of forming the diffusion film 03 include: forming a photoresist film on the surface of the first epitaxial layer 02 facing away from the semiconductor substrate 01; performing carbonization treatment on the photoresist film in a nitrogen atmosphere so that the photoresist film forms the diffusion film 03. Carbonization of the photoresist film can quickly form clusters of carbon and carbon elements on the surface of the first epitaxial layer 02, realizing carbon enrichment on the surface of the first epitaxial layer 02, and providing a carbon source for high-temperature annealing to diffuse carbon atoms into the interior of the first epitaxial layer 02. Conventional ion implantation equipment is expensive, and ion implantation will cause serious damage to the surface and damage the device performance. In this embodiment, a carbon film is obtained by carbonizing the photoresist, and then annealing treatment is used to diffuse carbon atoms into the interior of the first epitaxial layer 02. The implementation method is simple, which can replace expensive ion implantation equipment, reduce production costs, and will not cause damage to the surface. In a specific embodiment, the photoresist film is formed by a photoresist spin-coating process. The rotation speed of the photoresist spin-coating process is 1500 rpm to 5000 rpm, the temperature is 20°C to 25°C, and the thickness of the formed photoresist film is 0.1 μm to 20 μm, such as 0.1 μm, 1 μm, 5 μm, 10 μm or 20 μm. In a specific embodiment, the temperature of the carbonization treatment is 500°C to 1000°C, such as 500°C, 600°C, 800°C or 1000°C, and the time of the carbonization treatment is 10 min to 60 min, such as 10 min, 20 min, 30 min or 60 min.

[0049] In one embodiment, after the step of forming a photoresist film on the surface of the first epitaxial layer 02 facing away from the semiconductor substrate 01 and before the step of performing carbonization treatment on the photoresist film in a nitrogen atmosphere, it further includes: performing a heating treatment on the photoresist film. The temperature of the heating treatment is 50°C to 200°C, such as 50°C, 80°C, 100°C, 150°C or 200°C, and the time of the heating treatment is 1 min to 10 min, such as 1 min, 3 min, 5 min or 10 min. The purpose of the heating treatment is to densify the structure of the photoresist film before the step of carbonization treatment, which is beneficial to forming a dense carbon film after carbonization treatment.

[0050] In one embodiment, the diffusion film 03 is a carbon film; N is equal to 3, the temperature in the first heat preservation stage is 1600°C to 1800°C, such as 1600°C, 1650°C, 1700°C or 1800°C, and the time in the first heat preservation stage is 30 min to 120 min, such as 30 min, 60 min, 90 min or 120 min; the temperature in the second heat preservation stage is 1400°C to 1600°C, such as 1400°C, 1450°C, 1500°C or 1600°C, and the time in the second heat preservation stage is 30 min to 120 min, such as 30 min, 60 min, 90 min or 120 min; the temperature in the third heat preservation stage is 1200°C to 1400°C, such as 1200°C, 1250°C, 1300°C or 1400°C, and the time in the third heat preservation stage is 30 min to 120 min, such as 30 min, 60 min, 90 min or 120 min. In one embodiment, the cooling rate between different heat preservation stages is 2°C to 5°C.

[0051] In this embodiment, as Figure 4 shown, it further includes: after the step of performing the annealing treatment, removing the diffusion film 03; after removing the diffusion film 03, forming a second epitaxial layer 06 on the surface of the first epitaxial layer 02 facing away from the semiconductor substrate 01, and the conductivity type of the second epitaxial layer 06 is opposite to that of the first epitaxial layer 02. In one embodiment, the conductivity type of the first epitaxial layer 02 is N-type nitrogen doping, and the conductivity type of the second epitaxial layer 06 is P-type aluminum doping. In a specific embodiment, the methods for removing the carbon diffusion film include: introducing oxygen to remove the surface carbon film, using microwave oxygen plasma to remove the surface carbon film, dry etching to remove the surface carbon film, and wet etching to remove the surface carbon film, etc.

[0052] In this embodiment, after the step of removing the diffusion film 03 and before the step of forming the second epitaxial layer 06 on the surface of the first epitaxial layer 02 facing away from the semiconductor substrate 01, it further includes: passivating the dangling bonds on the surface of the first epitaxial layer 02 facing away from the semiconductor substrate 01.

[0053] In this embodiment, the steps of passivating the dangling bonds on the surface of the first epitaxial layer 02 facing away from the semiconductor substrate 01 include: oxidizing the surface of the first epitaxial layer 02 facing away from the semiconductor substrate 01 with an oxygen-containing oxidizing gas; after the oxidation treatment, performing surface passivation treatment on the first epitaxial layer 02 facing away from the semiconductor substrate 01 with a nitrogen-containing gas. By performing the oxidation treatment in an oxygen-containing oxidizing gas atmosphere, an oxide layer can be formed on the surface of the first epitaxial layer 02. Then, by performing the surface passivation treatment in a nitrogen-containing gas, the incomplete oxidation state at the interface between the first epitaxial layer 02 and the oxide layer can be partially eliminated, the interface state density can be reduced, and the interface quality can be improved. In a specific embodiment, the carrier lifetimes of the initially formed first epitaxial layer 02 and the first epitaxial layer 02 after annealing and passivation treatments are respectively measured by the microwave photoconductivity decay method. Since the edge quality of the first epitaxial layer 02 is poor and there are a large number of cracks, the edge thickness of 5 mm is removed before the test. The test step length of the laser beam movement during the test is 2 mm, and the test time is minimized on the basis of meeting the test accuracy. The carrier lifetime of the initially formed first epitaxial layer 02 measured by the microwave photoconductivity decay method is 1.64 μs, and the carrier lifetime of the first epitaxial layer 02 after annealing and passivation treatments measured by the microwave photoconductivity decay method is 2.07 μs. The carrier lifetime of the first epitaxial layer 02 after annealing and passivation treatments is increased by 26.2%.

[0054] In one embodiment, the oxygen-containing oxidizing gas includes oxygen. In one embodiment, the nitrogen-containing gas includes one or several mixtures of nitrogen, nitric oxide, or dinitrogen oxide, such as a mixed gas of nitrogen and nitric oxide, and the volume ratio of nitrogen to nitric oxide is (0.2 - 5):1.

[0055] In one embodiment, the temperature of the oxidation treatment is 1100°C - 1500°C, such as 1100°C, 1200°C, 1300°C, 1400°C, or 1500°C, and the time of the oxidation treatment is 10 min - 120 min, such as 10 min, 30 min, 60 min, 90 min, or 120 min; the temperature of the surface passivation treatment is 1100°C - 1500°C, such as 1100°C, 1200°C, 1300°C, 1400°C, or 1500°C, and the time of the surface passivation treatment is 20 min - 80 min, such as 20 min, 30 min, 40 min, 60 min, or 80 min.

[0056] In this embodiment, after the step of passivating the dangling bonds on the surface of the first epitaxial layer 02 facing away from the semiconductor substrate 01 and before the step of forming a second epitaxial layer 06 on the surface of the first epitaxial layer 02 facing away from the semiconductor substrate 01, it further includes: removing the oxide layer on the surface of the first epitaxial layer 02. In one embodiment, a buffered oxide etchant is used to completely etch and remove the oxide layer on the surface of the first epitaxial layer 02. The buffered oxide etchant is formed by mixing hydrofluoric acid with a mass concentration of 49% and ammonium fluoride solution with a mass concentration of 40%.

[0057] In this embodiment, the semiconductor substrate 01 is a silicon carbide substrate. In one embodiment, the resistivity of the silicon carbide substrate is 0.001 Ω·cm to 0.1 Ω·cm, and the thickness of the silicon carbide substrate is 10 μm to 1000 μm, such as 10 μm, 100 μm, 350 μm, 560 μm, 750 μm or 1000 μm. In one embodiment, before the step of forming the first epitaxial layer 02 on the semiconductor substrate 01, a cleaning process is performed on the silicon carbide substrate, including: a first cleaning process, a second cleaning process, and a third cleaning process. The first cleaning process is to mix concentrated sulfuric acid and hydrogen peroxide solution in a volume ratio of 1:4 and then clean the silicon carbide substrate. The cleaning temperature is 120°C to 280°C, and the cleaning time is 30 min. The first cleaning process can effectively remove the organic matter on the surface of the silicon carbide substrate; the second cleaning process is to mix ammonia water, hydrogen peroxide solution and water in a volume ratio of 1:1:50 and then clean the silicon carbide substrate. The cleaning temperature is 35°C to 80°C, and the cleaning time is 20 min. Then, hydrochloric acid, hydrogen peroxide solution and water are mixed in a volume ratio of 1:1:50 and the silicon carbide substrate is cleaned. The cleaning temperature is 35°C to 80°C, and the cleaning time is 20 min. The second cleaning process can further remove the organic matter, metal and residual ions on the silicon carbide substrate; the third cleaning process is to mix hydrofluoric acid and water in a volume ratio of 1:30 and then clean the silicon carbide substrate. The cleaning temperature is 10°C to 30°C. The third cleaning process can remove the oxide layer on the surface of the silicon carbide substrate.

[0058] In one embodiment, the material of the first epitaxial layer 02 is silicon carbide doped with N-type conductive ions. In a specific embodiment, the material of the first epitaxial layer 02 is nitrogen-doped N-type silicon carbide. In one embodiment, the doping concentration of N-type conductive ions in the first epitaxial layer 02 is 1×10 13 atom / cm 3 ~1×10 16 atom / cm 3 ,for example 1×10 13atoms / cm 3 、2×10 14 atoms / cm 3 、6×10 14 atoms / cm 3 、5×10 15 atoms / cm 3 or 1×10 16 atoms / cm 3 。In one embodiment, the thickness of the first epitaxial layer 02 is 2 μm to 300 μm, such as 2 μm, 30 μm, 100 μm, 180 μm, 240 μm or 300 μm.

[0059] In one embodiment, the material of the second epitaxial layer 06 is silicon carbide doped with P-type conductive ions. In a specific embodiment, the material of the second epitaxial layer 06 is aluminum-doped P-type silicon carbide. In one embodiment, the doping concentration of N-type conductive ions in the second epitaxial layer 06 is 1×10 17 atoms / cm 3 ~1×10 21 atoms / cm 3 ,such as 1×10 17 atoms / cm 3 、1×10 18 atoms / cm 3 、3×10 19 atoms / cm 3 、5×10 20 atoms / cm 3 or 1×10 21 atoms / cm 3 。In one embodiment, the thickness of the second epitaxial layer 06 is 0.2 μm to 100 μm, such as 0.2 μm, 2 μm, 15 μm, 40 μm, 70 μm or 100 μm.

[0060] Obviously, the above embodiments are merely examples given for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all implementation manners here. And the obvious changes or modifications derived therefrom are still within the protection scope of the present invention.

Claims

1. A method for preparing a semiconductor structure, characterized in that, Comprising: Providing a semiconductor substrate; Forming a first epitaxial layer on the semiconductor substrate; Forming a diffusion film on a surface of the first epitaxial layer facing away from the semiconductor substrate, the diffusion film having diffusion atoms; The diffusion film is a carbon film; The step of forming the diffusion film includes: forming a photoresist film on a surface of the first epitaxial layer facing away from the semiconductor substrate; performing a heat treatment on the photoresist film; performing a carbonization treatment on the photoresist film in a nitrogen atmosphere so that the photoresist film forms the diffusion film; After forming the diffusion film, an annealing treatment is performed to allow the diffusion atoms to enter the first epitaxial layer, and the diffusion atoms are suitable for filling atomic vacancies in the first epitaxial layer; the annealing treatment includes a first heat preservation stage to an Nth heat preservation stage performed in sequence, the temperature of the kth heat preservation stage is greater than the temperature of the (k + 1)th heat preservation stage, N is an integer greater than or equal to 2, and k is an integer greater than or equal to 1 and less than or equal to N - 1.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein, The annealing treatment is performed in an inert gas atmosphere.

3. The method for manufacturing a semiconductor structure according to claim 1, wherein The thickness of the photoresist film is 0.1 μm to 20 μm; The temperature of the carbonization treatment is 500 °C to 1000 °C, and the time of the carbonization treatment is 10 min to 60 min.

4. The method for manufacturing a semiconductor structure according to claim 3, wherein, The temperature of the heat treatment is 50 °C to 200 °C, and the time of the heat treatment is 1 min to 10 min.

5. The method for preparing a semiconductor structure according to claim 2, characterized in that, The diffusion film is a carbon film; N is equal to 3, the temperature of the first heat preservation stage is 1600 °C to 1800 °C, and the time of the first heat preservation stage is 30 min to 120 min; the temperature of the second heat preservation stage is 1400 °C to 1600 °C, and the time of the second heat preservation stage is 30 min to 120 min; the temperature of the third heat preservation stage is 1200 °C to 1400 °C, and the time of the third heat preservation stage is 30 min to 120 min.

6. The method for preparing a semiconductor structure according to claim 1, wherein, Further comprising: After the step of performing the annealing treatment, removing the diffusion film; After removing the diffusion film, forming a second epitaxial layer on a surface of the first epitaxial layer facing away from the semiconductor substrate, and the conductivity type of the second epitaxial layer is opposite to that of the first epitaxial layer; The conductivity type of the first epitaxial layer is N-type, and the conductivity type of the second epitaxial layer is P-type.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein, After the step of removing the diffusion film and before the step of forming the second epitaxial layer on a surface of the first epitaxial layer facing away from the semiconductor substrate, further comprising: passivating dangling bonds on a surface of the first epitaxial layer facing away from the semiconductor substrate.

8. The method for manufacturing a semiconductor structure according to claim 7, wherein, The step of passivating dangling bonds on a surface of the first epitaxial layer facing away from the semiconductor substrate includes: oxidizing the first epitaxial layer on a surface facing away from the semiconductor substrate with an oxygen-containing oxidizing gas; after performing the oxidation treatment, passivating the surface of the first epitaxial layer on a side facing away from the semiconductor substrate with a nitrogen-containing gas; The oxygen-containing oxidizing gas includes oxygen; The nitrogen-containing gas includes one or a mixture of nitrogen, nitric oxide, or nitrous oxide; The temperature of the oxidation treatment is 1100°C to 1500°C, and the time of the oxidation treatment is 10 min to 120 min; the temperature of the surface passivation treatment is 1100°C to 1500°C, and the time of the surface passivation treatment is 20 min to 80 min.

9. The method for preparing a semiconductor structure according to claim 8, wherein, After the step of passivating the dangling bonds on the surface of the first epitaxial layer facing away from the semiconductor substrate and before the step of forming a second epitaxial layer on the surface of the first epitaxial layer facing away from the semiconductor substrate, it further includes: removing the oxide layer on the surface of the first epitaxial layer.

10. The method for manufacturing a semiconductor structure according to claim 1, wherein, The material of the first epitaxial layer is silicon carbide doped with N-type conductive ions; The doping concentration of N-type conductive ions in the first epitaxial layer is 1×10 13 atom / cm 3 ~1×10 16 atom / cm 3 ; The thickness of the first epitaxial layer is 2 μm to 300 μm; The semiconductor substrate is a silicon carbide substrate.

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