Isolation Preparation Method for a Semiconductor Device

Abstract

The present invention provides a method for isolating and preparing a semiconductor device. The method includes: sequentially growing a high-resistivity epitaxial layer and a dielectric film layer on the surface of a substrate; etching a portion of the dielectric film layer corresponding to the active region to expose the high-resistivity epitaxial layer; etching the exposed high-resistivity epitaxial layer to a specified depth; and epitaxially growing a device layer in the etched region of the high-resistivity epitaxial layer. The present invention can set a high-resistivity epitaxial layer, etch a groove in the high-resistivity epitaxial layer, grow a device layer in the groove, and the high-resistivity epitaxial layer protects the side surface of the device layer, reducing side leakage.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device fabrication, and particularly to an isolation fabrication method for semiconductor devices. Background Art

[0002] One of the key technologies in semiconductor device fabrication is the isolation process. Currently, there are mainly two methods: mesa isolation and ion implantation isolation. Mesa isolation mainly uses Cl-based plasmas such as BCl3 and Cl2 for mesa etching. Mesa isolation is a three-dimensional process that can cause the gate metal to contact the two-dimensional electron gas on the mesa sidewall, generating a new gate leakage channel. At the same time, the mesa can cause the gate metal to be uneven, generating electric field spikes and causing device failure. In addition, the etching process can also introduce defects and reduce reliability. Ion implantation isolation uses high-energy particles to bombard and incorporate other ions such as F+, He+, B+, H+, and N+ into the active layer by destroying the lattice structure to achieve active layer isolation. Ion implantation isolation can maintain device flatness and is simple and easy to implement, but the thermal stability of the device is not good. After high temperature, some lattice damage will be repaired, resulting in a reduction in isolation effect.

[0003] To solve the above problems, the prior art has proposed using selective epitaxial growth to grow mutually isolated active regions to achieve device isolation. However, this method uses a dielectric film for side protection, which has the problem of easy leakage. Summary of the Invention

[0004] Embodiments of the present invention provide an isolation fabrication method for semiconductor devices to solve the problem of easy leakage on the side of the device in the existing selective epitaxial isolation process.

[0005] In a first aspect, embodiments of the present invention provide an isolation fabrication method for semiconductor devices, including:

[0006] Growing a high-resistivity epitaxial layer and a dielectric film layer on the surface of the substrate in sequence;

[0007] Etching a part of the dielectric film layer corresponding to the active region to expose the high-resistivity epitaxial layer;

[0008] Etching the exposed high-resistivity epitaxial layer to a specified depth;

[0009] Epitaxially growing a device layer in the etched region of the high-resistivity epitaxial layer.

[0010] In a possible implementation, the thickness of the high-resistivity epitaxial layer is greater than the thickness of the device layer;

[0011] The thickness of the device layer is the same as the specified depth.

[0012] In a possible implementation, the resistivity of the high-resistivity epitaxial layer is greater than 10 6Ohm·cm.

[0013] In a possible implementation, the material of the high-resistance epitaxial layer and the material of the device layer include the same material.

[0014] In a possible implementation, the material of the high-resistance epitaxial layer and the material of the device layer include gallium nitride.

[0015] In a possible implementation, the device layer includes a gallium nitride channel layer, an aluminum gallium nitride barrier layer, and a gallium nitride cap layer.

[0016] In a possible implementation, the substrate includes a sapphire substrate, a silicon carbide substrate, or a gallium nitride substrate.

[0017] In a possible implementation, after epitaxially growing the device layer in the etched area of the high-resistance epitaxial layer, it further includes: preparing a source electrode, a drain electrode, and a gate electrode on the surface of the device layer.

[0018] In a possible implementation, after epitaxially growing the device layer in the etched area of the high-resistance epitaxial layer, it further includes: removing the dielectric film layer.

[0019] In a second aspect, an embodiment of the present invention provides a semiconductor device, which is prepared by a method for isolating a semiconductor device as described in the first aspect of the embodiment of the present invention.

[0020] An embodiment of the present invention provides a method for isolating a semiconductor device, including: sequentially growing a high-resistance epitaxial layer and a dielectric film layer on the surface of a substrate; etching a part of the dielectric film layer corresponding to the active region to expose the high-resistance epitaxial layer; etching the exposed high-resistance epitaxial layer to a specified depth; and epitaxially growing a device layer in the etched area of the high-resistance epitaxial layer. By providing a high-resistance epitaxial layer, etching a groove in the high-resistance epitaxial layer, and growing a device layer in the groove, the high-resistance epitaxial layer protects the side surface of the device layer and reduces side leakage. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0022] Figure 1 is a flowchart of a method for isolating a semiconductor device provided by an embodiment of the present invention;

[0023] Figure 2It is a schematic diagram of the device structure after completing the steps of the preparation method in the embodiments of the present invention;

[0024] Figure 3 It is a schematic diagram of the device structure after completing the steps of the preparation method in the embodiments of the present invention;

[0025] Figure 4 It is a schematic diagram of the device structure after completing the steps of the preparation method in the embodiments of the present invention. Detailed implementation manners

[0026] In order to enable those skilled in the art to better understand this solution, the technical solutions in the embodiments of this solution will be clearly described below in conjunction with the accompanying drawings in the embodiments of this solution. Obviously, the described embodiments are some, rather than all, of the embodiments of this solution. Based on the embodiments in this solution, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the scope of protection of this solution.

[0027] The term "including" in the description and claims of this solution and the above-mentioned accompanying drawings, as well as any other variations, means "including but not limited to", and is intended to cover non-exclusive inclusion, not limited to the examples listed in the text. In addition, terms such as "first" and "second" are used to distinguish different objects, rather than to describe a specific order.

[0028] The implementation of the present invention will be described in detail below in conjunction with specific accompanying drawings:

[0029] Figure 1 It is a flowchart of an isolation preparation method for a semiconductor device provided by an embodiment of the present invention. Referring to Figure 1 , it is described in detail as follows, including:

[0030] Step S1: Sequentially grow a high-resistivity epitaxial layer 2 and a dielectric film layer 3 on the surface of the substrate 1.

[0031] In an optional embodiment, it specifically includes: cleaning the substrate 1 to remove surface contamination; placing the cleaned substrate 1 in an epitaxial furnace to grow a high-resistivity epitaxial layer 2 on the surface of the substrate 1; placing the substrate 1 with the grown high-resistivity epitaxial layer 2 in a chemical vapor deposition furnace to deposit a dielectric film layer 3 on the surface of the high-resistivity epitaxial layer 2.

[0032] In an optional embodiment, the resistivity of the high-resistivity epitaxial layer 2 is greater than 10 6 ohm·cm.

[0033] Exemplarily, the thickness range of the high-resistivity epitaxial layer 2 is from 0.1 μm to 10 μm.

[0034] Exemplarily, the material of the dielectric film layer 3 includes silicon oxide, silicon nitride or silicon oxynitride.

[0035] Exemplarily, the thickness range of the dielectric film layer 3 is from 0.01 micrometer to 0.5 micrometers.

[0036] In an alternative embodiment, the substrate 1 includes a sapphire substrate, a silicon carbide substrate, or a gallium nitride substrate.

[0037] Step S2: Etch the portion of the dielectric film layer 3 corresponding to the active region to expose the high-resistivity epitaxial layer 2;

[0038] Figure 2 is a schematic diagram of the device structure after completing step S2 of the preparation method provided by the embodiment of the present invention; refer to Figure 2 : From bottom to top are the substrate 1, the high-resistivity epitaxial layer 2, and the dielectric film layer 3 in sequence; the portion of the dielectric film layer 3 corresponding to the active region is etched to expose the corresponding region of the high-resistivity epitaxial layer 2 and the active region.

[0039] In an alternative embodiment, before etching the portion of the dielectric film layer 3 corresponding to the active region to expose the high-resistivity epitaxial layer 2, it further includes:

[0040] Coat a layer of photoresist on the surface of the dielectric film layer 3. After photolithography alignment, exposure, and development, the portion of the dielectric film layer 3 corresponding to the active region is exposed; the portion corresponding to the active region is the region where the device layer 4 needs to continue epitaxial growth.

[0041] Exemplarily, the etching method for the dielectric film layer 3 includes wet etching or dry etching.

[0042] Exemplarily, the thickness range of the photoresist is from 1 micrometer to 5 micrometers.

[0043] Step S3: Etch the exposed high-resistivity epitaxial layer 2 to a specified depth.

[0044] Figure 3 is a schematic diagram of the device structure after completing step S3 of the preparation method provided by the embodiment of the present invention; refer to Figure 3 : A groove is formed in the corresponding region of the high-resistivity epitaxial layer 2 and the active region; the depth of the groove is less than the thickness of the high-resistivity epitaxial layer 2.

[0045] After etching the exposed high-resistivity epitaxial layer 2 to a specified depth, it further includes: removing the remaining photoresist after etching to obtain an etched wafer.

[0046] Exemplarily, the etching method for the high-resistivity epitaxial layer 2 includes dry etching.

[0047] Exemplarily, the range of the specified depth is from 200 nanometers to 1000 nanometers.

[0048] Exemplarily, the method for removing photoresist includes: removing the photoresist with acetone and cleaning the surface with deionized water.

[0049] Step S4: Epitaxially grow a device layer 4 in the etched area of the high-resistivity epitaxial layer 2.

[0050] Figure 4 is a schematic diagram of the device structure after completing step S4 of the preparation method provided by an embodiment of the present invention; refer to Figure 4 :

[0051] Put the etched wafer into an epitaxial furnace, and epitaxially grow a device layer 4 on the surface of the etched area of the high-resistivity epitaxial layer 2; during the epitaxial growth process, no epitaxial layer will grow on the surface of the dielectric film layer 3, and an epitaxial layer can grow on the surface of the high-resistivity epitaxial layer 2; during the epitaxial growth process, the dielectric film layer 3 acts as a mask to form selective epitaxy.

[0052] Grow a device layer 4 in the groove formed in the area corresponding to the active region of the high-resistivity epitaxial layer 2; the high-resistivity epitaxial layer 2 protects the side surface of the device layer 4.

[0053] By providing the high-resistivity epitaxial layer 2, etching a groove in the high-resistivity epitaxial layer 2, and growing a device layer 4 in the groove, the high-resistivity epitaxial layer 2 protects the side surface of the device layer 4 and reduces side leakage.

[0054] Using the epitaxially grown high-resistivity epitaxial layer for isolation, the lattice mismatch between the high-resistivity epitaxial layer 2 and the device layer 4 is small, avoiding the problems of large lattice mismatch of the device layer 4 caused by using a dielectric film for side isolation and large side leakage caused by epitaxial growth defects on the side surface of the device layer 4.

[0055] In an optional embodiment, the device layer 4 includes a channel layer, a barrier layer, and a cap layer.

[0056] In an optional embodiment, after epitaxially growing the device layer 4 in the etched area of the high-resistivity epitaxial layer 2, it further includes: removing the dielectric film layer 3.

[0057] Exemplarily, the method for removing the dielectric film layer 3 includes wet etching with a hydrofluoric acid solution.

[0058] In an optional embodiment, the thickness of the high-resistivity epitaxial layer 2 is greater than the thickness of the device layer 4; the thickness of the device layer 4 is the same as the specified depth.

[0059] The thickness of the device layer 4 is the same as the specified depth of etching the high-resistivity epitaxial layer 2, ensuring the flatness of the device while achieving active region isolation. The final device surface is flat, which can reduce the difficulty of subsequent planarization processes and facilitate subsequent processes.

[0060] In an optional embodiment, the material of the high-resistivity epitaxial layer 2 and the material of the device layer 4 include the same material.

[0061] The high-resistance layer and the device layer 4 are homoepitaxially grown using the same material, and the lattice mismatch at the interface between the high-resistance layer and the device layer 4 is small, which can reduce surface leakage current.

[0062] In an alternative embodiment, the material of the high-resistance epitaxial layer 2 and the material of the device layer 4 include gallium nitride.

[0063] Correspondingly, in an alternative embodiment, the material of the substrate 1 includes sapphire, silicon carbide or gallium nitride; the device layer 4 includes a gallium nitride channel layer, an aluminum gallium nitride barrier layer and a gallium nitride cap layer.

[0064] In an alternative embodiment, the material of the high-resistance epitaxial layer 2 and the material of the device layer 4 include silicon carbide. Correspondingly, in an alternative embodiment, the material of the substrate 1 includes silicon carbide.

[0065] In an alternative embodiment, after epitaxially growing the device layer 4 in the etched area of the high-resistance epitaxial layer 2, it further includes: fabricating a source electrode, a drain electrode and a gate electrode on the surface of the device layer 4. Details are as follows:

[0066] Lithographically pattern the regions corresponding to the source and drain electrodes. Coat a layer of photoresist on the surface of the wafer, the thickness range of the photoresist is from 1 micron to 5 microns, and expose and develop the corresponding regions where the source and drain electrodes need to be fabricated.

[0067] Deposit metals for the source and drain electrodes. Sequentially deposit titanium, aluminum, nickel and gold on the surface of the wafer by evaporation or sputtering, where the thickness range of titanium is from 10 nm to 40 nm, the thickness range of aluminum is from 70 nm to 250 nm, the thickness range of nickel is from 25 nm to 100 nm, and the thickness range of gold is from 30 nm to 100 nm.

[0068] Lift off the metals for the source and drain electrodes. Immerse the wafer in an organic solvent after metal deposition to remove the photoresist and the excess metals deposited on the photoresist, and only retain the metal electrode parts corresponding to the source and drain electrodes. Then put the wafer into a rapid thermal annealing furnace and anneal it in a nitrogen atmosphere, the annealing temperature is 850 °C and the annealing time is 30 seconds.

[0069] Lithographically pattern the region corresponding to the gate electrode. Coat a layer of photoresist on the surface of the wafer, the thickness range of the photoresist is from 1 micron to 5 microns, and expose and develop the corresponding region where the gate electrode needs to be fabricated.

[0070] Sequentially deposit nickel, gold and nickel on the surface of the wafer by evaporation.

[0071] Then immerse the wafer in an organic solvent to remove the photoresist and the excess metals deposited on the photoresist, and only retain the metal electrode part corresponding to the gate electrode. Then put the wafer into a rapid thermal annealing furnace and anneal it in a nitrogen atmosphere, the annealing temperature is 850 °C and the annealing time is 30 seconds.

[0072] A semiconductor device provided by an embodiment of the present invention is prepared by the isolation preparation method of the above-mentioned semiconductor device provided by the embodiment of the present invention, and has the beneficial effects of the isolation preparation method of the above-mentioned semiconductor device provided by the embodiment of the present invention.

[0073] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing isolation of a semiconductor device, characterized in that, the preparation method includes: successively growing a high-resistance epitaxial layer and a dielectric film layer on the surface of a substrate; etching a part of the dielectric film layer corresponding to the active region to expose the high-resistance epitaxial layer; etching the exposed high-resistance epitaxial layer to a specified depth; Epitaxially grow a device layer in the etched area of the high-resistivity epitaxial layer; wherein, the thickness of the high-resistivity epitaxial layer is greater than the thickness of the device layer; the thickness of the device layer is the same as the specified depth; the resistivity of the high-resistivity epitaxial layer is greater than 10 6 ohm·cm; the material of the high-resistivity epitaxial layer and the material of the device layer include the same material; the high-resistivity epitaxial layer and the device layer are homoepitaxially grown using the same material.

2. The method for preparing isolation of a semiconductor device according to claim 1, characterized in that, the materials of the high-resistance epitaxial layer and the device layer include gallium nitride.

3. The method for preparing isolation of a semiconductor device according to claim 2, characterized in that, the device layer includes a gallium nitride channel layer, an aluminum gallium nitride barrier layer and a gallium nitride cap layer.

4. The method for preparing isolation of a semiconductor device according to claim 3, characterized in that, the substrate includes a sapphire substrate, a silicon carbide substrate or a gallium nitride substrate.

5. The method for preparing isolation of a semiconductor device according to any one of claims 1 to 4, characterized in that, after epitaxially growing a device layer in the etched area of the high-resistance epitaxial layer, it further includes: preparing a source electrode, a drain electrode and a gate electrode on the surface of the device layer.

6. The method for preparing isolation of a semiconductor device according to any one of claims 1 to 4, characterized in that, after epitaxially growing a device layer in the etched area of the high-resistance epitaxial layer, it further includes: removing the dielectric film layer.

7. A semiconductor device, characterized in that, it is prepared by the method for preparing isolation of a semiconductor device according to any one of claims 1 to 6.

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