Method for forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a gate cut region and device regions located on both sides of the gate cut region, a gate structure being formed on the substrate of the gate cut region and the device regions, an etching mask layer being provided on top of the gate structure; removing the etching mask layer on top of the gate structure in the gate cut region and the device regions; forming a gate structure on the substrate of the gate cut region and the device regions; forming a dielectric layer covering the sidewalls of the gate structure on the substrate of the gate cut region and the device regions; forming a hard mask layer covering the dielectric layer and the gate structure; etching the hard mask layer until the top of the gate structure in the gate cut region is exposed; removing the gate structure and the dielectric layer in the gate cut region, and forming corresponding dividing trenches in the gate cut region, so that the gate structures on different device regions are divided by the dividing trenches. This solution can improve the quality of the formed semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuits, and more particularly to a method for forming a semiconductor structure. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration. Transistors, as the most basic semiconductor devices, are currently widely used. Therefore, as the density and integration of semiconductor devices increase, the feature size of planar transistors is getting smaller and smaller.

[0003] To better adapt to the reduction of feature size, semiconductor processes are gradually transitioning from planar transistors to three-dimensional transistors with higher efficiency, such as fin field-effect transistors (FinFETs). FinFETs can improve the integration of semiconductor devices, and the gate structure of FinFETs can control the transistor channel from both sides of the fin, thereby increasing the control of the gate structure over the channel carriers of the transistor, which is beneficial to reducing leakage current and improving the short-channel effect.

[0004] However, existing semiconductor structures still have the problem of poor performance. Summary of the Invention

[0005] The problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0006] To solve the above problems, the present invention provides a method for forming a semiconductor structure, the method comprising:

[0007] Providing a substrate, the substrate comprising a gate cutting region and device regions on both sides of the gate cutting region, a gate structure being formed on the substrate of the gate cutting region and the device regions, and an etching mask layer being formed on top of the gate structure;

[0008] Removing the etching mask layer on top of the gate structure in the gate cutting region and the device regions;

[0009] Forming a dielectric layer covering the sidewalls of the gate structure on the substrate of the gate cutting region and the device regions;

[0010] Forming a hard mask layer covering the dielectric layer and the gate structure;

[0011] Etching the hard mask layer until the top of the gate structure in the gate cutting region is exposed;

[0012] Removing the gate structure and the dielectric layer in the gate cutting region, and forming corresponding dividing trenches in the gate cutting region, such that the gate structures on different device regions are divided by the dividing trenches.

[0013] Optionally, after forming the hard mask layer, the method further includes:

[0014] Forming a covering layer covering the hard mask layer;

[0015] Before etching the hard mask layer, the covering layer is also etched.

[0016] Optionally, after forming a gate structure and an offset spacer on the sidewalls of the gate structure on the substrates of the gate cutting region and the device region, the method further includes: forming source / drain doping layers on the substrates on both sides of the gate structure and the offset spacer in the device region, and forming a protective layer covering the source / drain doping layers;

[0017] After forming the dielectric layer, the dielectric layer also covers the protective layer.

[0018] Optionally, after forming a gate structure on the substrates of the gate cutting region and the device region, it further includes: forming an offset spacer on the sidewalls of the gate structure;

[0019] After forming the dielectric layer, the dielectric layer also covers the offset spacer;

[0020] When etching the hard mask layer, the top of the offset spacer on the gate cutting region is also exposed;

[0021] When removing the gate structure and the dielectric layer on the gate cutting region, the offset spacer on the gate cutting region is also removed.

[0022] Optionally, the method for removing the offset spacer on the gate cutting region includes: using more than one cycle processing technology to remove the offset spacer on the gate cutting region; each of the cycle processing technologies includes a material modification processing technology and an etching process after the material modification processing technology.

[0023] Optionally, the material modification processing technology is an ion implantation process.

[0024] Optionally, the ions implanted in the ion implantation process are H ions.

[0025] Optionally, the etching process is a plasma dry etching process.

[0026] Optionally, the number of times of performing the cycle processing technology is 10 to 60 times.

[0027] Optionally, the gate structure is a dummy gate structure or a metal gate structure.

[0028] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0029] The above solution provides a substrate, the substrate including a gate cutting area and device areas located on both sides of the gate cutting area; a gate structure is formed on the substrate in the gate cutting area and the device areas; a dielectric layer covering the sidewalls of the gate structure is formed on the substrate in the gate cutting area and the device areas; a hard mask layer covering the dielectric layer and the gate structure is formed; the hard mask layer is etched until the top of the gate structure in the gate cutting area is exposed; the gate structure and the dielectric layer in the gate cutting area are removed, and corresponding dividing trenches are formed in the gate cutting area, so that the gate structures on different device areas are divided by the dividing trenches. After forming the gate structure, the etching mask layer located on the top of the gate structure is removed in this solution, and there is no need to etch and remove the etching mask layer on the top of the gate structure after forming the dielectric layer subsequently, so the etching loss of the dielectric layer can be reduced, thereby avoiding the reduction of the height of the finally formed gate structure due to the etching loss of the dielectric layer, so the quality of the formed semiconductor structure can be improved.

[0030] Further, after forming a gate structure on the substrate in the gate cutting area and the device areas, source-drain doping layers are formed on the substrate on both sides of the gate structure in the device areas, and a protective layer covering the source-drain doping layers is formed. During the subsequent process of etching and removing the dielectric layer in the gate cutting area, the protective layer can protect the source-drain doping layers from the influence of the etching process, so the performance of the formed semiconductor structure can be improved. Description of the Drawings

[0031] Figures 1 to 4 It is a schematic diagram of a method for forming a semiconductor structure;

[0032] Figures 5 to 14 It is a schematic diagram of an intermediate structure formed by each step of a method for forming a semiconductor structure in an embodiment of the present invention. Detailed Embodiments

[0033] As can be seen from the background art, the performance of the existing semiconductor structure needs to be improved.

[0034] See Figures 1 to 4 , a method for forming a semiconductor structure, includes:

[0035] Refer to Figure 1 , a substrate 100 is provided, the substrate including a gate cutting area I and device areas II located on both sides of the gate cutting area I; a gate material layer 110 is formed on the gate cutting area I and the device areas II, and a patterned etching hard mask layer 120 located on the gate material layer 110;

[0036] Figure 2 is Figure 1 a schematic cross-sectional view along line AA on the basis. See Figure 2, using the patterned etched hard mask layer 120 as a mask to etch the gate material layer 110 to form a plurality of discrete gate structures 115; after forming the gate structures 115, a dielectric layer 130 covering the sidewalls of the gate structures 115 and the sidewalls of the etched hard mask layer 120 and a covering layer 140 covering the dielectric layer 130, the etched hard mask layer 120, and the gate structures 115 are formed on the substrate 100;

[0037] See Figure 3 , a patterned mask composite layer (not shown) is formed on the covering layer 140; using the patterned mask composite layer as a mask to etch the covering layer 140, the dielectric layer 130, and the etched hard mask layer 120 on the gate cutting area I until the top of the gate structure 115 on the gate cutting area I is exposed.

[0038] See Figure 4 , etch and remove the gate structure 115 on the gate cutting area I, and form corresponding dividing trenches 116 on the gate cutting area I, so that the gate structures 115 on different device areas II are divided by the dividing trenches 116.

[0039] In the formation process of the above semiconductor structure, in order to avoid the generation of bridge defects caused by the residue of the etched hard mask layer 120 existing on the top of the gate structure 115, generally after etching the covering layer 140, the dielectric layer 130, and the etched hard mask layer 120 on the gate cutting area I using the patterned mask composite layer as a mask, a plasma etching process is further used to remove the residual etched hard mask layer 120 on the top of the gate structure 115.

[0040] However, in the process of using the plasma etching process to remove the residual etched hard mask layer 120 on the top of the gate structure 115, the plasma etching process also acts on the dielectric layer 130 on both sides of the gate structure 115, causing etching loss of the dielectric layer 130, and the etching loss of the dielectric layer 130 will affect the height of the finally formed gate structure, reducing the performance of the formed semiconductor structure.

[0041] To solve the above problems, the technical solution in the embodiment of the present invention, after forming the gate structure, removes the etched hard mask layer, and after forming the dielectric layer, forms a hard mask layer covering the gate structure and the dielectric layer. Since the etched mask layer on the top of the gate structure has been removed after forming the gate structure and before forming the dielectric layer, there is no need to use an etching process to remove the residual etched hard mask on the top of the gate structure subsequently, so the etching loss of the dielectric layer can be avoided, and thus the performance of the formed semiconductor structure can be improved.

[0042] To make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following will describe in detail the specific embodiments of the present invention with reference to the accompanying drawings.

[0043] The following will combine Figures 5 to 14 to further describe in detail a method for forming a semiconductor structure in an embodiment of the present invention.

[0044] Referring to Figure 5 , a substrate is provided. The substrate includes a substrate 100, the substrate 100 has a gate cut region I and device regions II on both sides of the gate cut region I. A gate structure 110 is provided on the gate cut region I and the device regions II, and an etching hard mask layer 120 is provided on the top of the gate structure 110.

[0045] The substrate 100 provides a process platform for forming a semiconductor structure subsequently.

[0046] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be other types of substrates such as silicon-on-insulator substrate or germanium-on-insulator substrate. The material of the substrate can be a material suitable for process requirements or easy to integrate.

[0047] The substrate 100 includes a gate cut region I and device regions II on both sides of the gate cut region. Among them, the gate cut region I is a region for dividing the dummy gate structure 110, and the device regions II are regions for forming transistors respectively.

[0048] In this embodiment, the gate structure 110 is a dummy gate structure, occupying a spatial position for forming a metal gate structure subsequently. In other embodiments, the gate structure 110 can also be a metal gate structure.

[0049] The steps of forming the gate structure 110 include: forming a gate dielectric film on the substrate 100; forming a polysilicon film on the gate dielectric film; forming a patterned etching mask layer 120 on the polysilicon film; etching the polysilicon film and the gate dielectric film in sequence using the patterned etching mask layer 120 as a mask to form a gate dielectric layer and a dummy gate electrode layer on the gate dielectric layer, thereby forming the gate structure 110.

[0050] In this embodiment, the semiconductor structure is a fin field effect transistor, and the substrate 100 also has fins (not shown). The gate structure 110 straddles the fins and covers part of the top and part of the sidewalls of the fins. In other embodiments, the semiconductor structure is a planar transistor, and the multiple gate structures are located on the surface of the planar substrate.

[0051] Referring toFigure 6 , remove the etching mask layer 120 on the top of the gate structure 110 in the gate cutting area and the device area.

[0052] In this embodiment, a dry etching process is used to remove the etching mask layer 120 on the top of the gate structure 110. In other embodiments, a wet etching process can also be used to remove the etching mask layer 120 on the top of the gate structure 110.

[0053] Figure 7 is Figure 6 The schematic cross-sectional structure diagram along line AA on the basis of. Refer to Figure 7 , after removing the etching mask layer 120 on the top of the gate structure 110 in the gate cutting area and the device area, an offset spacer 130 located on the sidewall of the gate structure 110 is formed in the gate cutting area and the device area.

[0054] The material of the offset spacer 130 is a low dielectric constant material. The low dielectric constant material is a dielectric material with a dielectric constant less than 3.9, such as silicon nitride, silicon oxynitride, etc.

[0055] The process of forming the offset spacer 130 includes chemical vapor deposition, physical vapor deposition or atomic layer deposition process.

[0056] Refer to Figure 8 , a source / drain doping layer 140 is formed on the substrate 100 on both sides of the gate structure 110 and the offset spacer 130 in the device area, and a protective layer 150 covering the source / drain doping layer 140 is formed.

[0057] In this embodiment, after forming the offset spacer 130, a source / drain doping layer (not shown in the figure) is formed on the substrate 100 on both sides of the dummy gate structure 110. Among them, the source / drain doping layer between adjacent dummy gate structures 110 is shared by the transistors (common source area or common drain area).

[0058] The method of forming the source / drain doping layer 140 includes: selectively epitaxially growing the source / drain doping layer 140 on the substrate 100 on both sides of the gate structure 130 and the offset spacer 130.

[0059] For PMOS or P-type transistors, the material of the source / drain doping layer 140 includes SiGe doped with conductive ions, and the conductive type of the conductive ions is P-type. For NMOS or N-type fin field effect transistors, the material of the source / drain doping layer 140 includes SiC doped with conductive ions or SiP doped with conductive ions, and the conductive type of the conductive ions is N-type. In this embodiment, the material of the source / drain doping layer 140 includes SiGe doped with conductive ions.

[0060] The protective layer 150 is used to protect the source / drain doping layer 140 during the subsequent formation process of the semiconductor structure.

[0061] In this embodiment, the material of the protective layer 150 is silicon nitride.

[0062] The process for forming the protective layer 150 can be physical chemical vapor deposition process, chemical vapor deposition process, atomic layer deposition process, metal organic chemical vapor deposition process, etc.

[0063] See Figure 9 , after the protective layer 150 is formed, a dielectric layer 160 covering the sidewalls of the offset spacer 130 is formed on the protective layer 150 in the gate cut region and the device region.

[0064] The top surface of the dielectric layer 160 is flush with the top surfaces of the gate structure 110 and the offset spacer 130.

[0065] The dielectric layer 160 is used to achieve electrical isolation between different gate structures and between different semiconductor structures.

[0066] In this embodiment, the material of the dielectric layer 160 is silicon dioxide. In other embodiments, the material of the dielectric layer 160 can also be selected from one or more combinations of low-k dielectric materials (dielectric constant greater than or equal to 2.5 and less than 3.9) or ultra-low-k dielectric materials (dielectric constant less than 2.5), where the low-k dielectric materials or ultra-low-k dielectric materials include doped silicon dioxide, organic polymers, and porous materials, etc.

[0067] The dielectric layer 160 can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or furnace tube method.

[0068] See Figure 10 , after the dielectric layer 160 is formed, a hard mask layer 170 covering the dielectric layer 160, the gate structure 110, and the offset spacer 130 and a capping layer 180 covering the hard mask layer 170 are formed.

[0069] The hard mask layer 170 serves as an etch mask for etching the gate structure 110, the offset spacer 130, and the dielectric layer 160 in the gate cut region.

[0070] In this embodiment, the material of the hard mask layer 170 is silicon nitride. In other embodiments, the material of the hard mask layer 170 can also be silicon oxynitride, etc.

[0071] The process for forming the hard mask layer 170 is chemical vapor deposition process, physical vapor deposition process, atomic layer deposition process, etc.

[0072] The covering layer 180 is used as an etching mask for etching the hard mask layer 170, and during the subsequent patterning of the hard mask material layer using a patterned mask layer, it enables the patterned mask layer to be formed on a planarized surface, thereby improving the topography quality of the formed mask layer.

[0073] In this embodiment, the material of the covering layer 180 is silicon dioxide.

[0074] The covering layer 180 can be formed by processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc.

[0075] Refer to Figure 11 , etch the covering layer 180 and the hard mask layer 170 in sequence until the top of the gate structure 110 and the offset sidewall 130 on the gate cutting region I are exposed.

[0076] The steps of etching the covering layer 180 and the hard mask layer 170 may include: forming a patterned mask layer (not shown) on the covering layer 180, the patterned mask layer having an opening located on the gate cutting region; using the patterned mask layer as a mask to etch the covering layer 180 and the hard mask layer 170 on the gate cutting region in sequence until the top of the gate structure 110 and the offset sidewall 130 on the gate cutting region are exposed.

[0077] In this embodiment, the process of etching the covering layer 180 and the hard mask layer 170 on the gate cutting region using the patterned mask layer as a mask is a plasma dry etching process.

[0078] Refer to Figure 12 , etch and remove the gate structure 110 on the gate cutting region.

[0079] In this embodiment, a plasma dry etching process is used to etch and remove the gate structure 110 on the gate cutting region. In other embodiments, a wet etching process may also be used to etch and remove the gate structure 110 on the gate cutting region.

[0080] Refer to Figure 13 , after etching and removing the gate structure 110 on the gate cutting region, remove the offset sidewall 130 on the gate cutting region.

[0081] In this embodiment, more than one cycle of processing is used to remove the offset sidewall 130 on the gate cutting region. Wherein, each cycle of processing includes a material modification processing and an etching process after the material modification processing.

[0082] A material modification treatment process is performed on the offset sidewall 130 on the gate cutting region, so that the material of the offset sidewall 130 after the material modification treatment becomes more porous, so that the etching rate of the offset sidewall 130 after the material modification treatment is increased in the subsequent etching process, so as to facilitate the rapid removal of the offset sidewall 130 on the gate cutting region I, and reduce the impact of the etching process after the material modification treatment process on other film layers.

[0083] In this embodiment, the material modification treatment process is an ion modification treatment process. Specifically, the material of the offset sidewall 130 is silicon nitride. Correspondingly, the processing gas used in the ion modification treatment process is H2. The silicon nitride is made porous by H2, so that it is easier to remove in the subsequent etching process.

[0084] In this embodiment, the etching process in the cyclic treatment process is a plasma dry etching process. Specifically, the processing gases used in the plasma dry etching process include NF3, H2, and CH4.

[0085] In other embodiments, when an etch stop layer (not shown in the figure) is further formed on the substrate 100, the cyclic treatment process also acts on removing the etch stop layer with a partial thickness at the bottom of the trench formed after removing the gate structure 110 and the offset sidewall 130 on the gate cutting region. By removing the etch stop layer with the partial thickness, the presence of residues of the gate structure 110 and the offset sidewall 130 on the gate cutting region can be avoided.

[0086] See Figure 14 , after etching and removing the offset sidewall 130 on the gate cutting region, the dielectric layer 160 on the gate cutting region is etched and removed, and corresponding dividing trenches 190 are formed on the gate cutting region, so that the gate structures 110 on different device regions are divided by the dividing trenches 190.

[0087] In this embodiment, a dry etching process is used to etch and remove the dielectric layer 160 on the gate cutting region.

[0088] During the process of etching and removing the dielectric layer 160 on the gate cutting region, a part of the dielectric layer 160 on the protective layer 150 is also etched and removed. However, due to the presence of the protective layer 150, the source-drain doping layer 140 is protected from the etching process, so that the performance of the formed semiconductor structure can be improved.

[0089] It should be noted that by etching and removing the dielectric layer 160 on the gate cutting region, the gate protrusion generated during the formation of the gate structure 110 can be completely removed, so as to avoid the generation of defects caused by the residue of the gate protrusion and improve the quality of the formed semiconductor structure.

[0090] In other embodiments, when an etch stop layer is further formed on the substrate 100, during the process of etching and removing the dielectric layer 160 on the gate cutting area I, the etch stop layer with a bottom partial thickness of the dielectric layer 160 on the gate cutting area I is also etched and removed, so as to avoid the existence of residues of the dielectric layer 160 and the gate protrusion on the gate cutting area, and improve the quality of the formed semiconductor structure.

[0091] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate, the substrate including a gate cutting area and device areas on both sides of the gate cutting area, a gate structure being formed on the substrate of the gate cutting area and the device areas, and an etching mask layer being provided on top of the gate structure; Removing the etching mask layer on top of the gate structure in the gate cutting area and the device areas; Forming a dielectric layer covering the sidewalls of the gate structure on the substrate of the gate cutting area and the device areas; Forming a hard mask layer covering the dielectric layer and the gate structure; Etching the hard mask layer until the top of the gate structure in the gate cutting area is exposed; Removing the gate structure and the dielectric layer in the gate cutting area, and forming corresponding dividing trenches in the gate cutting area, such that the gate structures on different device areas are divided by the dividing trenches.

2. The method for forming a semiconductor structure according to claim 1, wherein After forming the gate structure on the substrate of the gate cutting area and the device areas, it further includes: forming source-drain doping layers on the substrate on both sides of the gate structure in the device areas, and forming a protective layer covering the source-drain doping layers; after forming the dielectric layer, the dielectric layer also covers the protective layer.

3. The method for forming a semiconductor structure according to claim 1, wherein, After forming the gate structure on the substrate of the gate cutting area and the device areas, it further includes: forming offset sidewalls on the sidewalls of the gate structure; After forming the dielectric layer, the dielectric layer also covers the offset sidewalls; When etching the hard mask layer, the top of the offset sidewalls in the gate cutting area is also exposed; When removing the gate structure and the dielectric layer in the gate cutting area, the offset sidewalls in the gate cutting area are also removed.

4. The method for forming a semiconductor structure according to claim 3, wherein, The method for removing the offset sidewalls in the gate cutting area includes: removing the offset sidewalls in the gate cutting area by using more than one cycle processing technology; each of the cycle processing technologies includes a material modification processing technology and an etching process after the material modification processing technology.

5. The method for forming a semiconductor structure according to claim 4, wherein, The material modification processing technology is an ion implantation technology.

6. The method for forming a semiconductor structure according to claim 5, wherein The ions implanted by the ion implantation technology are H ions.

7. The method for forming a semiconductor structure according to claim 4, wherein, The etching process is a plasma dry etching process.

8. The method for forming a semiconductor structure according to claim 4, wherein, The number of times of performing the cycle processing technology is 10 to 60 times.

9. The method for forming a semiconductor structure according to claim 1, wherein, After forming the hard mask layer, it further includes: forming a covering layer covering the hard mask layer; Before etching the hard mask layer, the covering layer is also etched.

10. The method for forming a semiconductor structure according to claim 1, wherein, The gate structure is a dummy gate structure or a metal gate structure.

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