Test structure and method of forming the same

Abstract

A test structure and a method for forming the same include: a substrate having a cutting path including a plurality of pixel test areas and a plurality of logic test areas, the pixel test areas and the logic test areas being alternately arranged in a first direction; a pixel test gate structure located above the pixel test areas, the pixel test gate structure extending perpendicularly to the first direction; and a logic test gate structure located above the logic test areas, the logic test gate structure extending perpendicularly to the first direction. The test structure can reduce manufacturing costs, labor, and time.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a test structure and a forming method thereof. Background Art

[0002] The image sensor consists of pixel unit circuits and logic circuits.

[0003] In the prior art, a wafer is typically provided, and a pixel region (Pixel) and a logic region (Logic) are formed in the chip region of the wafer to perform different functions. The pixel region contains pixel unit circuits, and the logic region contains logic circuits. Therefore, the pixel region and the logic region have different designs and internal structures. Due to the different designs and internal structures of the pixel region and the logic region, during the product development process, samples of the pixel region in the chip region and samples of the logic region in the chip region need to be cut separately to test the pixel region and the logic region.

[0004] However, because the samples of the pixel area and the logic area in the chip area need to be cut separately, not only a large number of trial production samples need to be provided, but also a large number of cutting operations are required. In addition, the chip area is damaged after cutting and cannot be reused, resulting in a waste of manufacturing costs, manpower, and time. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a test structure and a forming method thereof, so as to reduce manufacturing cost, manpower and time.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a test structure, including: a substrate, the cutting path of the substrate includes a plurality of pixel test areas and a plurality of logic test areas, and the pixel test areas and the logic test areas are alternately arranged in a first direction; a pixel test gate structure located on the pixel test area, and the extension direction of the pixel test gate structure is perpendicular to the first direction; and a logic test gate structure located on the logic test area, and the extension direction of the logic test gate structure is perpendicular to the first direction.

[0007] Optionally, it includes: a first gate oxide layer located on the pixel test area; a second gate oxide layer located on the logic test area and on the first gate oxide layer; a plurality of gates located on the second gate oxide layer, and the pixel test area and the logic test area respectively have the gates; and the pixel test gate structure includes: the first gate oxide layer, the second gate oxide layer located on the first gate oxide layer, and the gate located on the pixel test area, and the logic test gate structure includes: the second gate oxide layer located on the logic test area, and the gate located on the logic test area.

[0008] Optionally, it also includes: a first sidewall located on the sidewall surface of the gate located on the pixel test area; a second sidewall located on the first sidewall and the sidewall surface of the gate located on the logic test area; and the pixel test gate structure also includes: the first sidewall and the second sidewall located on the sidewall surface of the first sidewall, and the logic test gate structure also includes: the second sidewall located on the sidewall surface of the gate located on the logic test area.

[0009] Optionally, it also includes: a gate and a second sidewall surface located on the pixel test area, and a contact barrier layer on the surface of the pixel test area, wherein the contact barrier layer exposes the gate on the logic test area and the surface of the logic test area; a contact layer located on the top of the gate on the logic test area, and at least a portion of the surface of the logic test area on both sides of the logic test gate structure along the first direction.

[0010] Optionally, it also includes: an active area located in the cutting path, the active area extending along the first direction and located in the logic test area and the pixel test area, and the first gate oxide layer and the second gate oxide layer are located on the active area, and the gate spans the active area; an isolation structure, in a direction perpendicular to the first direction, the isolation structure passes through the active area between adjacent logic test areas and pixel test areas.

[0011] Optionally, it further includes: a plurality of conductive structures respectively located on the top surface of the gate of the pixel test area, the active area surface in the pixel test area on both sides of the pixel test gate structure along the first direction, and the surface of the contact layer.

[0012] Optionally, the material of the first sidewall spacer includes oxide.

[0013] Optionally, the second sidewall includes: a lower second sidewall and an upper second sidewall located on a surface of the lower second sidewall.

[0014] Optionally, the material of the lower second spacer includes oxide, and the material of the upper second spacer includes nitride.

[0015] Optionally, the contact barrier layer includes: a lower contact barrier layer and an upper contact barrier layer located on a surface of the lower contact barrier layer.

[0016] Optionally, the material of the lower contact barrier layer includes oxide, and the material of the upper contact barrier layer includes nitride.

[0017] Correspondingly, the technical solution of the present invention also provides a method for forming any of the above-mentioned test structures, including: providing a substrate, the cutting path of the substrate including a plurality of pixel test areas and a plurality of logic test areas, the pixel test areas and the logic test areas being alternately arranged in a first direction; forming a pixel test gate structure on the pixel test area, the extension direction of the pixel test gate structure being perpendicular to the first direction; forming a logic test gate structure on the logic test area, the extension direction of the logic test gate structure being perpendicular to the first direction.

[0018] Optionally, the method for forming the pixel test gate structure and the logic test gate structure includes: forming a first gate oxide layer on the pixel test area; forming a second gate oxide layer on the logic test area and on the first gate oxide layer; forming a plurality of gates on the second gate oxide layer, and the pixel test area and the logic test area respectively have the gates.

[0019] Optionally, the method for forming a first gate oxide layer on the pixel test area includes: forming a first gate oxide film on the logic test area and the pixel test area; forming a first mask layer on the pixel test area, the first mask layer exposing the first gate oxide film on the logic test area; etching the first gate oxide film using the first mask layer as a mask until the exposed first gate oxide film is removed to form the first gate oxide layer; after forming the first gate oxide layer and before forming the second gate oxide layer, removing the first mask layer.

[0020] Optionally, the method for forming the pixel test gate structure and the logic test gate structure also includes: forming a first sidewall on the sidewall surface of the gate on the pixel test area; forming a second sidewall on the first sidewall and the sidewall surface of the gate on the logic test area; and the first gate oxide layer, the second gate oxide layer located on the first gate oxide layer, the gate located on the pixel test area, the first sidewall, and the second sidewall located on the sidewall surface of the first sidewall constitute the pixel test gate structure, and the second gate oxide layer located on the logic test area, the gate located on the logic test area, and the second sidewall on the sidewall surface of the gate located on the logic test area constitute the logic test gate structure.

[0021] Optionally, the method for forming a first sidewall on the sidewall surface of the gate on the pixel test area includes: forming an initial first sidewall layer on the sidewall surface of the gate on the logic test area and the pixel test area; forming a second mask layer on the gate and the initial first sidewall layer on the pixel test area, the second mask layer exposing the initial first sidewall layer on the logic test area; etching the initial first sidewall layer using the second mask layer as a mask until the exposed initial first sidewall layer is removed to form the first sidewall; after forming the first sidewall and before forming the second sidewall, removing the second mask layer.

[0022] Optionally, the method for forming an initial first sidewall layer on the sidewall surface of the gate on the logic test area and the pixel test area includes: forming a first sidewall film on the surface of the logic test area, the surface of the pixel test area, and the surface of the gate on the logic test area and the pixel test area; etching the first sidewall film using an anisotropic etching process until the first sidewall film on the surface of the logic test area, the surface of the pixel test area, and the top surface of the gate on the logic test area and the pixel test area is removed.

[0023] Optionally, the method of forming a second sidewall on the first sidewall and the sidewall surface of the gate on the logic test area includes: forming a second sidewall film on the gate and the first sidewall surface on the pixel test area, the gate surface on the logic test area, the logic test area surface, and the pixel test area surface; etching the second sidewall film using an anisotropic etching process until the first sidewall and the gate top surface on the pixel test area, the gate top surface on the logic test area, the logic test area surface, and the second sidewall film on the pixel test area surface are removed.

[0024] Optionally, after forming the pixel test gate structure and the logic test gate structure, the method further includes: forming a contact barrier layer on the gate and the second sidewall surface on the pixel test area, and the surface of the pixel test area, wherein the contact barrier layer exposes the gate on the logic test area and the surface of the logic test area; after forming the contact barrier layer, forming a contact layer on the top of the gate on the logic test area and at least part of the surface of the logic test area on both sides of the logic test gate structure along the first direction.

[0025] Optionally, before forming the first gate oxide layer, it also includes: forming an active area and an isolation structure in the cutting road, the active area extends along the first direction and is located in the logic test area and the pixel test area, and, in a direction perpendicular to the first direction, the isolation structure passes through the active area between adjacent logic test areas and pixel test areas; the first gate oxide layer and the second gate oxide layer are located on the active area, and the gate spans the active area.

[0026] Optionally, the method further includes: after forming the contact layer, forming a plurality of conductive structures on the top surface of the gate of the pixel test area, the active area surface on both sides of the pixel test gate structure along the first direction, and the surface of the contact layer.

[0027] Optionally, the substrate also includes a chip area for forming a chip, and the method for forming the test structure also includes: forming a pixel unit circuit in the chip area, and, in the process of forming the pixel unit circuit, forming the pixel test gate structure; forming a logic circuit in the chip area, and, in the process of forming the logic circuit, forming the logic test gate structure.

[0028] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0029] The test structure provided by the technical solution of the present invention comprises, on the one hand, a substrate cutting path including a plurality of pixel test areas and a plurality of logic test areas, with the pixel test areas and the logic test areas being arranged alternately in a first direction. On the other hand, a pixel test gate structure is provided on the pixel test areas, and a logic test gate structure is provided on the logic test areas, to respectively constitute a test structure for testing pixel unit circuits and a test structure for testing logic circuits. Furthermore, the pixel test gate structure and the logic test gate structure extend in directions perpendicular to the first direction. Therefore, by cutting the alternating logic test areas and pixel test areas in the cutting path, a cut sample for testing can be obtained using a small number, or even a single sample, and a small number of cuts without damaging the pixel unit circuits and logic unit circuits in the chip area. This reduces manufacturing costs, manpower, and time. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figures 1 to 13 1 is a schematic structural diagram of each step in a method for forming a test structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] As described in the background, since samples of the pixel area and logic area of ​​the chip must be cut separately, not only a large number of trial production samples need to be provided, but also a large number of cutting operations are required. Furthermore, the chip area is damaged after cutting and cannot be reused, resulting in a waste of manufacturing costs, manpower, and time.

[0032] To address the above technical issues, the present invention provides a test structure and a method for forming the same. The test structure comprises: a substrate having a cutting path including a plurality of pixel test areas and a plurality of logic test areas, the pixel test areas and the logic test areas being alternately arranged in a first direction; a pixel test gate structure located above the pixel test areas, the pixel test gate structure extending perpendicularly to the first direction; and a logic test gate structure located above the logic test areas, the logic test gate structure extending perpendicularly to the first direction. Therefore, the test structure can reduce manufacturing costs, labor, and time.

[0033] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0034] It should be noted that the “surface” in this specification is used to describe the relative position relationship in space and is not limited to whether there is direct contact.

[0035] Figures 1 to 13 1 is a schematic structural diagram of each step in a method for forming a test structure according to an embodiment of the present invention.

[0036] Please refer to Figure 1 and Figure 2 , Figure 1 yes Figure 2 Schematic diagram of the top view of the structure, Figure 2 yes Figure 1 A schematic cross-sectional structural diagram along direction AA provides a substrate 100 .

[0037] The substrate 100 includes a plurality of chip regions (not shown), wherein the chip regions are used to form chips. The dicing streets 101 of the substrate 100 are located between adjacent chip regions.

[0038] Specifically, the chip area includes a pixel area (not shown) and a logic area (not shown), wherein the pixel area is used to form a plurality of pixel unit circuits, and the logic area is used to form a logic circuit to constitute at least a part of the chip.

[0039] After wafer-level manufacturing is completed, by cutting the cutting streets 101 , several chip regions can be separated without damaging the chips to form independent chips.

[0040] The cutting street 101 of the substrate 100 includes a plurality of pixel test regions PT and a plurality of logic test regions LT. The pixel test regions PT and the logic test regions LT are alternately arranged in a first direction X.

[0041] The pixel test area PT is used to form a test structure for testing the pixel unit circuit, and the logic test area LT is used to form a test structure for testing the logic circuit.

[0042] In this embodiment, the first direction X is the extending direction of the portion of the cutting street 101 where the dry pixel test region PT and the plurality of logic test regions LT are located.

[0043] The substrate 100 is made of a semiconductor material.

[0044] Specifically, the material of the substrate 100 in this embodiment includes silicon.

[0045] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0046] Next, a pixel unit circuit is formed in the pixel area, and a logic circuit is formed in the logic area. Furthermore, in this embodiment, during the formation of the pixel unit circuit, a test structure for testing the pixel unit circuit is formed within and on the pixel test area PT of the dicing street 101. Furthermore, during the formation of the logic circuit, a test structure for testing the logic circuit is formed within and on the logic test area LT of the dicing street 101.

[0047] In this way, the process consistency between forming the pixel unit circuit and forming the test structure for testing the pixel unit circuit is better ensured, and the process consistency between forming the logic circuit and forming the test structure for testing the logic circuit is better ensured to improve the accuracy of detection.

[0048] Specifically, in this embodiment, the subsequent process steps for forming a test structure within and on the pixel test region PT of the dicing street 101 are synchronized with at least a portion of the process steps for forming a pixel unit circuit in the pixel region. Similarly, the subsequent process steps for forming a test structure within and on the logic test region LT of the dicing street 101 are synchronized with at least a portion of the process steps for forming a logic circuit in the logic region.

[0049] Please refer to Figure 3 and Figure 4 , Figure 3 yes Figure 4 Schematic diagram of the top view of the structure, Figure 4 yes Figure 3 The cross-sectional structural diagram along the direction AA shows that an active region S and an isolation structure 110 are formed in the cutting street 101 .

[0050] The active region S extends along the first direction X and is located in the logic test region LT and the pixel test region PT.

[0051] The isolation structure 110 penetrates the active area S between adjacent logic test areas LT and pixel test areas PT in a second direction Y, and the second direction Y is perpendicular to the first direction X. In this way, isolation between adjacent logic test areas LT and pixel test areas PT is achieved.

[0052] In this embodiment, two or more independent active regions S are formed in the second direction Y to further increase the number of test structures that can be cut for testing in a sample.

[0053] In other embodiments, only one active region S is formed.

[0054] In this embodiment, the process of forming the active region S includes an ion implantation process and the like.

[0055] In this embodiment, the method for forming the isolation structure 110 includes: forming an isolation structure mask layer (not shown) on the surface of the cutting road 101, the isolation structure mask layer exposing the surface of the cutting road 101 between the adjacent logic test area LT and the pixel test area PT; etching the cutting road 101 using the isolation structure mask layer as a mask to form an isolation opening (not shown); and filling material in the isolation opening to form the isolation structure 110.

[0056] The isolation structure 110 is made of dielectric material.

[0057] The process of etching the cutting street 101 to form the isolation opening includes at least one of a wet etching process and a dry etching process, and the process of filling the material to form the isolation structure 110 includes a chemical vapor deposition process or a physical vapor deposition process.

[0058] Next, a pixel test gate structure is formed on the pixel test area PT, wherein the extending direction of the pixel test gate structure is perpendicular to the first direction X; and a logic test gate structure is formed on the logic test area LT, wherein the extending direction of the logic test gate structure is perpendicular to the first direction X. For the specific steps of forming the pixel test gate structure and the logic test gate structure, please refer to Figures 5 to 9 .

[0059] Please refer to Figure 5 , Figure 5 and Figure 4In the same viewing direction, a first gate oxide layer 121 is formed on the pixel test region PT.

[0060] Specifically, the first gate oxide layer 121 is located on the active region S.

[0061] In this embodiment, the material of the first gate oxide layer 121 includes silicon oxide.

[0062] Specifically, the method for forming the first gate oxide layer 121 includes: forming a first gate oxide film (not shown) on the logic test area LT and the pixel test area PT; forming a first mask layer (not shown) on the pixel test area PT, the first mask layer exposing the first gate oxide film on the logic test area LT; etching the first gate oxide film using the first mask layer as a mask until the exposed first gate oxide film is removed to form the first gate oxide layer 121; after forming the first gate oxide layer 121 and before forming the second gate oxide layer, removing the first mask layer.

[0063] In this embodiment, the material of the first mask layer includes photoresist, and the process of removing the first mask layer includes an ashing process.

[0064] In this embodiment, the process of forming the first gate oxide film includes a chemical vapor deposition process, a physical vapor deposition process, an oxidation process, or an atomic layer deposition process.

[0065] In this embodiment, the process of etching the first gate oxide film includes at least one of a wet etching process and a dry etching process.

[0066] Please continue to refer to Figure 5 After forming the first gate oxide layer 121 , a second gate oxide layer 122 is formed on the logic test region LT and on the first gate oxide layer 121 .

[0067] Specifically, the second gate oxide layer 122 is located on the active region S.

[0068] Thus, a thicker gate oxide layer (including the first gate oxide layer 121 and the second gate oxide layer 122 ) is formed on the pixel test region PT, and at the same time, a thinner gate oxide layer (ie, the second gate oxide layer 122 ) is formed on the logic test region LT.

[0069] In this embodiment, the material of the second gate oxide layer 122 includes silicon oxide.

[0070] In this embodiment, the process of forming the second gate oxide layer 122 includes a chemical vapor deposition process, a physical vapor deposition process, an oxidation process, or an atomic layer deposition process.

[0071] Please refer to Figure 6 , Figure 6 and Figure 5 In the same viewing direction, a plurality of gates 130 are formed on the second gate oxide layer 122 , and the pixel test area PT and the logic test area LT respectively have the gates 130 .

[0072] The gate 130 extends in the second direction Y, and crosses the active region S.

[0073] In this embodiment, the gate 130 is made of polysilicon.

[0074] In this embodiment, the method for forming the plurality of gates 130 includes: depositing a gate material layer (not shown) on the pixel test area PT and the logic test area LT; forming a plurality of independent gate mask structures (not shown), wherein the gate mask structure extends in the second direction Y and spans the active area S, and each pixel test area PT has the gate mask structure, and each logic test area LT has the gate mask junction; using the gate mask structure as a mask, etching the gate material layer until the surface of the isolation structure 110, a portion of the surface of the pixel test area PT, and a portion of the surface of the logic test area LT are exposed.

[0075] It should be noted that, according to actual conditions, the critical dimensions of the gate 130 on the pixel test region PT and the gate 130 on the logic test region LT may be different.

[0076] Please refer to Figure 7 , Figure 7 and Figure 6 In the same viewing direction, a first spacer 141 is formed on the sidewall surface of the gate 130 on the pixel test region PT.

[0077] In this embodiment, the material of the first spacer 141 includes oxide.

[0078] Specifically, the material of the first sidewall spacer 141 includes silicon oxide.

[0079] In this embodiment, the method for forming the first spacer 141 on the sidewall surface of the gate 130 on the pixel test area PT includes: forming an initial first spacer layer (not shown) on the sidewall surface of the gate 130 on the logic test area LT and the pixel test area PT; forming a second mask layer (not shown) on the gate 130 and the initial first spacer layer on the pixel test area PT, the second mask layer exposing the initial first spacer layer on the logic test area LT; etching the initial first spacer layer using the second mask layer as a mask until the exposed initial first spacer layer is removed to form the first spacer 141.

[0080] In this embodiment, the material of the second mask layer includes photoresist.

[0081] In this embodiment, the method for forming an initial first spacer layer includes: depositing a first spacer film (not shown) on the surface of the logic test area LT, the surface of the pixel test area PT, and the surface of the gate 130 on the logic test area LT and the pixel test area PT; and etching the first spacer film using an anisotropic etching process until the first spacer film on the surface of the logic test area LT, the surface of the pixel test area PT, and the top surface of the gate 130 on the logic test area LT and the pixel test area PT is removed.

[0082] In this embodiment, after forming the first sidewall spacer 141 and before subsequently forming the second sidewall spacer, the second mask layer is removed.

[0083] In this embodiment, the process of removing the second mask layer includes an ashing process.

[0084] In this embodiment, before forming the first spacer 141 , a silicon oxide film 131 is formed on the surface of the gate 130 .

[0085] In other embodiments, the silicon oxide film is not formed.

[0086] Please refer to Figure 8 and Figure 9 , Figure 8 yes Figure 9 Schematic diagram of the top view of the structure, Figure 9 yes Figure 8 1 is a schematic cross-sectional structural diagram along the direction AA, in which a second spacer 142 is formed on the first spacer 141 and the sidewall surface of the gate 130 on the logic test region LT.

[0087] Thus, the pixel test gate structure 150 and the logic test gate structure 160 are formed.

[0088] Specifically, in this embodiment, the pixel test gate structure 150 includes: a first gate oxide layer 121, a second gate oxide layer 122 located on the first gate oxide layer 121, a gate 130 located on the pixel test region PT, a first spacer 141, and a second spacer 142 located on the sidewall surface of the first spacer 141. The logic test gate structure 160 includes: a second gate oxide layer 122 located on the logic test region LT, a gate 130 located on the logic test region LT, and a second spacer 142 located on the sidewall surface of the gate 130 located on the logic test region LT.

[0089] At the same time, the pixel test gate structure 150 can have thicker sidewalls (including the first sidewall 141 and the second sidewall 142 ), and the logic test gate structure 160 can have thinner sidewalls (ie, the second sidewall 142 ).

[0090] In this embodiment, the method for forming the second spacer 142 on the first spacer 141 and the sidewall surface of the gate 130 on the logic test area LT includes: depositing a second spacer film (not shown) on the surface of the gate 130 and the first spacer 141 on the pixel test area PT, the surface of the gate 130 on the logic test area LT, the surface of the logic test area LT, and the surface of the pixel test area PT; and etching the second spacer film using an anisotropic etching process until the first spacer 141 and the top surface of the gate 130 on the pixel test area PT, the top surface of the gate 130 on the logic test area LT, the surface of the logic test area LT, and the surface of the pixel test area PT are removed.

[0091] In this embodiment, the second spacer film includes: a lower second spacer film and an upper second spacer film located on a surface of the lower second spacer film.

[0092] Correspondingly, the second sidewall includes: a lower second sidewall (not shown) and an upper second sidewall (not shown) located on the surface of the lower second sidewall.

[0093] In this embodiment, the material of the lower second spacer includes oxide, and the material of the upper second spacer includes nitride.

[0094] Specifically, the material of the lower second sidewall spacer includes silicon oxide, and the material of the upper second sidewall spacer includes silicon nitride.

[0095] Please refer to Figure 10 , Figure 10 and Figure 9 In accordance with the viewing method, a contact barrier layer 170 (SAB, Salicide Block) is formed on the surface of the gate 130 and the second sidewall 142 on the pixel test area PT, and on the surface of the pixel test area PT, and the contact barrier layer 170 exposes the gate 130 on the logic test area LT and the surface of the logic test area LT.

[0096] The contact barrier layer 170 is used to block the reaction between the metal material layer and the surface of the pixel test area PT and the surface of the gate 130 on the pixel test area PT when the contact layer is subsequently formed. Therefore, when the contact layer is subsequently formed on the logic test area LT, a contact layer is not formed on the pixel test area PT.

[0097] In this embodiment, the method for forming a contact barrier layer 170 on the surface of the gate 130 and the second sidewall 142 on the pixel test area PT includes: depositing a contact barrier film (not shown) on the surface of the pixel test area PT, the surface of the logic test area LT, and the surfaces of the gate 130 and the second sidewall 142 on the pixel test area PT and the logic test area LT; forming a third mask structure (not shown) on the pixel test area PT, the third mask structure exposing the logic test area LT; and etching the contact barrier film using the third mask structure as a mask until the logic test area LT is exposed.

[0098] In this embodiment, the contact barrier film includes a lower contact barrier film (not shown) and an upper contact barrier film (not shown) located on a surface of the lower contact barrier film.

[0099] Accordingly, the contact barrier layer 170 includes a lower contact barrier layer (not shown) and an upper contact barrier layer (not shown) located on the surface of the lower contact barrier layer.

[0100] In this embodiment, the material of the lower contact barrier layer includes oxide, and the material of the upper contact barrier layer includes nitride.

[0101] Specifically, the material of the lower contact barrier layer includes silicon oxide, and the material of the upper contact barrier layer includes silicon nitride.

[0102] Please refer to Figure 11 , Figure 11 and Figure 10 In accordance with the viewing direction, after forming the contact barrier layer 170, a contact layer 180 is formed on the top of the gate 130 on the logic test area LT and on at least part of the surface of the logic test area LT on both sides of the logic test gate structure 160 along the first direction X.

[0103] Specifically, in this embodiment, the contact layer 180 is located on the top of the gate 130 on the logic test region LT and on the surface of the active region S on both sides of the logic test gate structure 160 along the first direction X in the logic test region LT.

[0104] The contact layer 180 is used to improve the conductivity between the subsequently formed conductive structure and the gate 130 on the logic test region LT, as well as the active region S of the logic test region LT.

[0105] In this embodiment, the material of the contact layer 180 includes metal silicide.

[0106] In this embodiment, the method for forming the contact layer 180 includes: forming a third mask layer (not shown) on the logic test area LT and the pixel test area PT, wherein the third mask layer exposes a portion of the silicon oxide film 131 surface on the top surface of the gate 130 on the logic test area LT and at least a portion of the surface of the second gate oxide layer 122 on the active area S of the logic test gate structure 160 on both sides of the first direction X; etching the exposed silicon oxide film 131 and the second gate oxide layer 122 using the third mask layer as a mask until the top surface of the gate 130 is exposed. surface and the surface of the active area S; after etching the exposed silicon oxide film 131 and the second gate oxide layer 122 using the third mask layer as a mask, the third mask layer is removed; after removing the third mask layer, a metal material layer (not shown) is formed on the logic test area LT and the pixel test area PT, and the exposed top surface of the gate 130 and the surface of the active area S are in contact with the metal material layer; after forming the metal material layer, annealing treatment is performed to allow the metal material layer to react with the material of the contacted top surface of the gate 130 and the surface of the active area S to form the contact layer 180.

[0107] Since the contact barrier layer 170 is formed on the pixel test region PT, the contact layer 180 is not formed on the pixel test region PT.

[0108] Please refer to Figure 12 and Figure 13 , Figure 12 yes Figure 13 Schematic diagram of the top view of the structure, Figure 13 yes Figure 12 The cross-sectional structural diagram along direction AA shows that a plurality of conductive structures 190 are formed on the top surface of the gate 130 of the pixel test region PT, the surface of the active area S on both sides of the pixel test gate structure 150 along the first direction X, and the surface of the contact layer 180 .

[0109] In this embodiment, the conductive structure 190 is a conductive plug.

[0110] In this embodiment, the method for forming a plurality of conductive structures 190 includes: after forming the contact layer 180, forming an etch stop film 191 and a dielectric layer 192 located on the surface of the etch stop film 191 on the cutting street 101; forming a fourth mask layer on the surface of the dielectric layer 192, the fourth mask layer exposing a portion of the surface of the dielectric layer 192; using the fourth mask layer as a mask, etching the dielectric layer 192 and the etch stop film 191 until the top surface of the gate 130 of the pixel test area PT, the surface of the active area S on both sides of the pixel test gate structure 150 along the first direction X, and the surface of the contact layer 180 are exposed, and forming a plurality of contact holes (CT, not shown) in the dielectric layer 192; and depositing material in the plurality of contact holes to form a plurality of conductive structures 190.

[0111] In this embodiment, the conductive structure 190 is made of tungsten.

[0112] It should be noted that Figure 12 For ease of understanding and explanation, the etch stop film 191 , the dielectric layer 192 , the contact stop layer 170 , and the contact layer 180 are not shown.

[0113] Correspondingly, the embodiment of the present invention also provides a test structure formed by the above method, please continue to refer to Figure 12 and Figure 13 , comprising: a substrate 100, wherein a cutting street 101 of the substrate 100 comprises a plurality of pixel test areas PT and a plurality of logic test areas LT, wherein the pixel test areas PT and the logic test areas LT are alternately arranged in a first direction X; a pixel test gate structure 150 located on the pixel test areas PT, wherein an extension direction of the pixel test gate structure 150 is perpendicular to the first direction X; and a logic test gate structure 160 located on the logic test areas LT, wherein an extension direction of the logic test gate structure 160 is perpendicular to the first direction X.

[0114] In the test structure, a dicing street 101 of a substrate 100 includes a plurality of pixel test areas PT and a plurality of logic test areas LT, with the pixel test areas PT and the logic test areas LT being alternately arranged in a first direction X. Furthermore, a pixel test gate structure 150 is provided on the pixel test areas PT, and a logic test gate structure 160 is provided on the logic test areas LT, forming a test structure for testing pixel unit circuits and a test structure for testing logic circuits, respectively. Furthermore, the pixel test gate structures 150 and the logic test gate structures 160 extend perpendicular to the first direction X. Therefore, by dicing the alternating logic test areas and pixel test areas in the dicing street, a sample for testing can be obtained from a small number or even a single sample (wafer) without damaging the pixel unit circuits and logic unit circuits in the chip area. Furthermore, the number of dicing steps can be effectively reduced when dicing along the first direction X. This reduces manufacturing costs, labor, and time.

[0115] Specifically, the test structure includes: a first gate oxide layer 121 located on the pixel test area PT; a second gate oxide layer 122 located on the logic test area LT and formed on the first gate oxide layer 121; a plurality of gates 130 located on the second gate oxide layer 122, and the pixel test area PT and the logic test area LT respectively have the gates 130.

[0116] In this embodiment, the pixel test gate structure 150 includes: the first gate oxide layer 121 , a second gate oxide layer 122 located on the first gate oxide layer 121 , and a gate 130 located on the pixel test region PT.

[0117] In this embodiment, the logic test gate structure 160 includes: a second gate oxide layer 122 located on the logic test region LT, and a gate 130 located on the logic test region LT.

[0118] In this embodiment, the materials of the first gate oxide layer 121 and the second gate oxide layer 122 both include silicon oxide, and the material of the gate 130 includes polysilicon.

[0119] In this embodiment, the test structure further includes: a first spacer 141 located on the sidewall surface of the gate 130 above the pixel test region PT; and a second spacer 142 located on the first spacer 141 and on the sidewall surface of the gate 130 above the logic test region LT. Furthermore, the pixel test gate structure 150 further includes: the first spacer 141 and the second spacer 142 located on the sidewall surface of the first spacer 141. The logic test gate structure 160 further includes: the second spacer 142 located on the sidewall surface of the gate 130 above the logic test region LT. This further increases the number of structures within the test structure that can be used for testing, thereby further reducing manufacturing costs, labor, and time.

[0120] In this embodiment, the material of the first spacer 141 includes oxide.

[0121] Specifically, the material of the first sidewall spacer 141 includes silicon oxide.

[0122] In this embodiment, the second sidewall spacer includes: a lower second sidewall spacer (not shown) and an upper second sidewall spacer (not shown) located on a surface of the lower second sidewall spacer.

[0123] In this embodiment, the material of the lower second spacer includes oxide, and the material of the upper second spacer includes nitride. Specifically, the material of the lower second spacer includes silicon oxide, and the material of the upper second spacer includes silicon nitride.

[0124] In this embodiment, the test structure further includes: a contact barrier layer 170 located on the surfaces of the gate 130 and the second sidewall 142 on the pixel test region PT, and on the surface of the pixel test region PT; the contact barrier layer 170 exposes the gate 130 on the logic test region LT and the surface of the logic test region LT; and a contact layer 180 located on top of the gate 130 on the logic test region LT and on at least a portion of the surface of the logic test region LT on both sides of the logic test gate structure 160 along the first direction X. This further increases the number of structures within the test structure that can be used for testing, thereby further reducing manufacturing costs, labor, and time.

[0125] In this embodiment, the contact barrier layer 170 includes a lower contact barrier layer (not shown) and an upper contact barrier layer (not shown) located on a surface of the lower contact barrier layer. The lower contact barrier layer is made of an oxide, while the upper contact barrier layer is made of a nitride. Specifically, the lower contact barrier layer is made of silicon oxide, while the upper contact barrier layer is made of silicon nitride.

[0126] In this embodiment, the material of the contact layer 180 includes metal silicide.

[0127] In this embodiment, the test structure further includes: an active area S located within the scribe line 101, the active area S extending along the first direction X and located within the logic test area LT and the pixel test area PT; and an isolation structure 110 extending through the active area S between adjacent logic test areas LT and pixel test areas PT in the second direction Y. This further increases the number of structures within the test structure that can be used for testing, thereby further reducing manufacturing costs, labor, and time.

[0128] In this embodiment, two or more independent active regions S are formed in the second direction Y to further increase the number of test structures that can be cut for testing in a sample.

[0129] In other embodiments, only one active region S is formed.

[0130] The isolation structure 110 is made of dielectric material.

[0131] Specifically, the first gate oxide layer 121 and the second gate oxide layer 122 are both located on the active area S, the gate 130 spans the active area S, and the contact layer 180 is located on the top of the gate 130 on the logic test area LT, and on the surface of the active area S in the logic test area LT on both sides of the logic test gate structure 160 along the first direction X.

[0132] In this embodiment, the test structure further includes: a plurality of conductive structures 190 located on the top surface of the gate 130 of the pixel test region PT, the surface of the active area S within the pixel test region PT on both sides of the pixel test gate structure 150 along the first direction X, and the surface of the contact layer 180. This further increases the number of structures within the test structure that can be used for testing, thereby further reducing manufacturing costs, manpower, and time.

[0133] In this embodiment, the conductive structure 190 is a conductive plug, and the material of the conductive structure 190 includes tungsten.

[0134] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A test structure, characterized in that: include: A substrate, wherein the cutting lanes of the substrate include a plurality of pixel test areas and a plurality of logic test areas, wherein the pixel test areas and the logic test areas are alternately arranged in a first direction; a pixel test gate structure located on the pixel test area, wherein an extension direction of the pixel test gate structure is perpendicular to the first direction; a logic test gate structure located on the logic test area, wherein an extension direction of the logic test gate structure is perpendicular to the first direction; a first spacer located on a sidewall surface of the gate electrode on the pixel test area; a second spacer located on the first spacer and the sidewall surface of the gate on the logic test area; and The pixel test gate structure further includes: the first sidewall and a second sidewall located on the sidewall surface of the first sidewall, and the logic test gate structure further includes: a second sidewall located on the sidewall surface of the gate on the logic test area.

2. The test structure according to claim 1, wherein: include: a first gate oxide layer located on the pixel test area; and a second gate oxide layer located on the logic test area and on the first gate oxide layer; A plurality of gates are located on the second gate oxide layer, and the pixel test area and the logic test area respectively have the gates; and the pixel test gate structure includes: the first gate oxide layer, a second gate oxide layer located on the first gate oxide layer, and the gates located on the pixel test area; the logic test gate structure includes: the second gate oxide layer located on the logic test area, and the gates located on the logic test area.

3. The test structure according to claim 2, wherein: Also includes: a gate and a second sidewall spacer surface located on the pixel test area, and a contact barrier layer on the surface of the pixel test area, wherein the contact barrier layer exposes the gate on the logic test area and the surface of the logic test area; A contact layer is located on the top of the gate on the logic test area and on at least part of the surface of the logic test area on both sides of the logic test gate structure along the first direction.

4. The test structure according to claim 3, wherein: Also includes: an active area located within the dicing street, the active area extending along the first direction and located within the logic test area and the pixel test area, the first gate oxide layer and the second gate oxide layer being located on the active area, and the gate crossing the active area; The isolation structure penetrates the active area between the adjacent logic test area and the pixel test area in a direction perpendicular to the first direction.

5. The test structure according to claim 4, wherein: Also includes: Several conductive structures are respectively located on the top surface of the gate of the pixel test area, the active area surface of the pixel test area on both sides of the pixel test gate structure along the first direction, and the surface of the contact layer.

6. The test structure according to claim 2, wherein: The material of the first spacer includes oxide.

7. The test structure according to claim 2, wherein: The second sidewall spacer includes: a lower second sidewall spacer and an upper second sidewall spacer located on a surface of the lower second sidewall spacer.

8. The test structure according to claim 7, wherein: The material of the lower second spacer includes oxide, and the material of the upper second spacer includes nitride.

9. The test structure according to claim 3, wherein: The contact barrier layer includes a lower contact barrier layer and an upper contact barrier layer located on a surface of the lower contact barrier layer.

10. The test structure according to claim 9, wherein: The material of the lower contact barrier layer includes oxide, and the material of the upper contact barrier layer includes nitride.

11. A method for forming a test structure according to any one of claims 1 to 10, characterized in that: include: Providing a substrate, wherein a cutting street of the substrate includes a plurality of pixel test areas and a plurality of logic test areas, wherein the pixel test areas and the logic test areas are alternately arranged in a first direction; forming a pixel test gate structure on the pixel test area, wherein an extension direction of the pixel test gate structure is perpendicular to the first direction; A logic test gate structure is formed on the logic test area, and an extension direction of the logic test gate structure is perpendicular to the first direction.

12. The method for forming a test structure according to claim 11, wherein: The method for forming the pixel test gate structure and the logic test gate structure includes: forming a first gate oxide layer on the pixel test area; forming a second gate oxide layer on the logic test area and on the first gate oxide layer; forming a plurality of gates on the second gate oxide layer, and the pixel test area and the logic test area respectively have the gates.

13. The method for forming a test structure according to claim 12, wherein: The method for forming a first gate oxide layer on the pixel test area includes: forming a first gate oxide film on the logic test area and the pixel test area; forming a first mask layer on the pixel test area, wherein the first mask layer exposes the first gate oxide film on the logic test area; etching the first gate oxide film using the first mask layer as a mask until the exposed first gate oxide film is removed to form the first gate oxide layer; after forming the first gate oxide layer and before forming the second gate oxide layer, removing the first mask layer.

14. The method for forming a test structure according to claim 12, wherein: The method for forming the pixel test gate structure and the logic test gate structure also includes: forming a first sidewall on the sidewall surface of the gate on the pixel test area; forming a second sidewall on the first sidewall and the sidewall surface of the gate on the logic test area; and the first gate oxide layer, the second gate oxide layer located on the first gate oxide layer, the gate located on the pixel test area, the first sidewall, and the second sidewall located on the sidewall surface of the first sidewall constitute the pixel test gate structure, and the second gate oxide layer located on the logic test area, the gate located on the logic test area, and the second sidewall on the sidewall surface of the gate located on the logic test area constitute the logic test gate structure.

15. The method for forming a test structure according to claim 14, wherein: The method for forming a first sidewall spacer on the sidewall surface of the gate on the pixel test area includes: forming an initial first sidewall spacer layer on the sidewall surface of the gate on the logic test area and the pixel test area; forming a second mask layer on the gate and the initial first sidewall spacer layer on the pixel test area, the second mask layer exposing the initial first sidewall spacer layer on the logic test area; etching the initial first sidewall spacer layer using the second mask layer as a mask until the exposed initial first sidewall spacer layer is removed to form the first sidewall; after forming the first sidewall, and before forming the second sidewall, removing the second mask layer.

16. The method for forming a test structure according to claim 15, wherein: The method for forming an initial first spacer layer on the sidewall surface of the gate on the logic test area and the pixel test area includes: forming a first spacer film on the surface of the logic test area, the surface of the pixel test area, and the surface of the gate on the logic test area and the pixel test area; etching the first spacer film using an anisotropic etching process until the first spacer film on the surface of the logic test area, the surface of the pixel test area, and the top surface of the gate on the logic test area and the pixel test area is removed.

17. The method for forming a test structure according to claim 14, wherein: The method for forming a second sidewall on the first sidewall and the sidewall surface of the gate on the logic test area includes: forming a second sidewall film on the gate and the first sidewall surface on the pixel test area, the gate surface on the logic test area, the surface of the logic test area, and the surface of the pixel test area; etching the second sidewall film using an anisotropic etching process until the first sidewall and the top surface of the gate on the pixel test area, the top surface of the gate on the logic test area, the surface of the logic test area, and the second sidewall film on the surface of the pixel test area are removed.

18. The method for forming a test structure according to claim 14, wherein: After forming the pixel test gate structure and the logic test gate structure, it also includes: forming a contact barrier layer on the gate and the second sidewall surface on the pixel test area, and the surface of the pixel test area, the contact barrier layer exposing the gate on the logic test area and the surface of the logic test area; after forming the contact barrier layer, forming a contact layer on the top of the gate on the logic test area and at least part of the surface of the logic test area on both sides of the logic test gate structure along the first direction.

19. The method for forming a test structure according to claim 18, wherein: Before forming the first gate oxide layer, it also includes: forming an active area and an isolation structure in the cutting road, the active area extends along the first direction and is located in the logic test area and the pixel test area, and, in a direction perpendicular to the first direction, the isolation structure passes through the active area between adjacent logic test areas and pixel test areas; the first gate oxide layer and the second gate oxide layer are located on the active area, and the gate spans the active area.

20. The method for forming a test structure according to claim 19, wherein: Also includes: After forming the contact layer, a plurality of conductive structures are formed on the top surface of the gate of the pixel test area, the active area surfaces on both sides of the pixel test gate structure along the first direction, and the surface of the contact layer.

21. The method for forming a test structure according to claim 11, wherein: The substrate also includes a chip area for forming a chip, and the method for forming the test structure also includes: forming a pixel unit circuit in the chip area, and forming the pixel test gate structure in the process of forming the pixel unit circuit; forming a logic circuit in the chip area, and forming the logic test gate structure in the process of forming the logic circuit.

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