Method of manufacturing a memory and memory

Abstract

The application provides a memory manufacturing method and a memory, the memory manufacturing method comprises the following steps: providing a substrate and a bit line contact layer; forming a dummy bit line structure on the top of the bit line contact layer; forming a spacer layer on the sidewall of the dummy bit line structure and the sidewall of the bit line contact layer; forming a dielectric layer on the sidewall of the spacer layer; forming a sacrificial layer which fills the area between adjacent dummy bit line structures and covers the sidewall of the dielectric layer; after the formation of the sacrificial layer, the dummy bit line structure is removed to form a via hole which exposes the bit line contact layer; forming a bit line conductive part which fills the via hole and covers the bit line contact layer; after the formation of the bit line conductive part, the spacer layer is removed to form a gap between the dielectric layer and the bit line conductive part. In the application, the gap between the bit line conductive part and the dielectric layer can reduce the parasitic capacitance, improve the running speed of the memory and reduce the power consumption of the memory.

Description

Technical Field

[0001] This invention relates to the semiconductor field, and in particular to a method for manufacturing a memory and a memory. Background Technology

[0002] Memory is a storage component used to store programs and various data information. Random access memory (RAM) is divided into static random access memory (SRAM) and dynamic random access memory (DRAM). DRAM typically includes capacitors and transistors connected to them. The capacitors store electrical charge representing the stored information, and the transistors control the inflow and outflow of charge from the capacitors. When writing data, the word line is given a high level, the transistor conducts, and the bit line charges the capacitor. When reading data, the word line is also given a high level, the transistor conducts, the capacitor discharges, and the bit line receives the read signal.

[0003] However, as memory process nodes continue to shrink, memory performance needs to be improved. Summary of the Invention

[0004] The technical problem solved by the embodiments of the present invention is to provide a method for manufacturing a memory and a memory, so as to improve the performance of the memory.

[0005] To address the aforementioned problems, embodiments of the present invention provide a method for manufacturing a memory. The method includes: providing a substrate and a plurality of discrete bit line contact layers, wherein the substrate has a plurality of active regions, and each bit line contact layer is electrically connected to the active region; forming a pseudo bit line structure on the top of the bit line contact layer; forming a spacer layer on the sidewall of the pseudo bit line structure and the sidewall of the bit line contact layer; forming a dielectric layer on the sidewall of the spacer layer; forming a sacrificial layer that fills the region between adjacent pseudo bit line structures, and the sacrificial layer covers the sidewall of the dielectric layer; after forming the sacrificial layer, removing the pseudo bit line structure to form a via exposing the bit line contact layer; forming a bit line conductive portion that fills the via and covers the bit line contact layer; and after forming the bit line conductive portion, removing the spacer layer to form a gap between the dielectric layer and the bit line conductive portion.

[0006] In addition, the material of the spacer layer is different from the material of the dielectric layer, the pseudo-bit line structure and the sacrificial layer.

[0007] In addition, the material of the spacer layer includes silicon nitride, silicon oxide, silicon oxynitride, or silicon carbonitride.

[0008] In addition, the material of the dielectric layer includes a low dielectric constant material.

[0009] In addition, the step of forming the pseudo bit line structure includes: forming a pseudo bit line layer on the substrate, the pseudo bit line layer covering the bit line contact layer; forming a patterned mask layer on the pseudo bit line layer; and etching the pseudo bit line layer using the patterned mask layer as a mask to form the pseudo bit line structure.

[0010] Additionally, the step of forming the patterned mask layer includes: forming a plurality of discrete core portions on the pseudo-bit line layer; forming a sidewall film covering the top and sidewalls of the core portions and the pseudo-bit line layer; etching the sidewall film to form a sidewall layer located on the opposite sidewalls of the core portions; and removing the core portions, with the sidewall layer serving as the patterned mask layer.

[0011] In addition, during the process of removing the pseudo-bit line structure, the etching selectivity ratio of the material of the pseudo-bit line structure to the materials of the sacrificial layer, the dielectric layer and the spacer layer is 5-15.

[0012] In addition, the materials of the pseudo-bit line structure include silicon nitride, silicon oxynitride, or silicon carbonitride.

[0013] In addition, the material of the sacrificial layer includes silicon oxide.

[0014] In addition, the material of the dielectric layer includes a low dielectric constant material.

[0015] In addition, the step of forming the bit line conductive portion includes: forming a barrier layer at the bottom and sidewall of the through hole; and forming a conductive layer on the surface of the barrier layer that fills the through hole.

[0016] In addition, the material of the conductive layer includes one or more of ruthenium, tungsten, gold, or silver.

[0017] In addition, the material of the barrier layer includes one or both of tantalum nitride and titanium nitride.

[0018] In addition, the conductive layer and the barrier layer are also located on the top surface of the sacrificial layer; the step of forming the bit line conductive portion further includes: planarizing the bit line conductive portion and removing the conductive layer and the barrier layer that are higher than the top surface of the sacrificial layer.

[0019] In addition, after forming the gap, the method further includes: forming an insulating capping layer on top of the bit line conductive portion and the dielectric layer; removing the sacrificial layer after forming the insulating capping layer; and forming a protective layer on the surface of the dielectric layer and the insulating capping layer after removing the sacrificial layer.

[0020] In addition, in the process of removing the sacrificial layer, the etching selectivity ratio of the material of the sacrificial layer to the material of the insulating cap layer is 5-15.

[0021] This invention also provides a memory manufactured using the aforementioned manufacturing method. The memory includes: a substrate and a plurality of discrete bit line contact layers, wherein the substrate has a plurality of active regions and each bit line contact layer is electrically connected to the active region; a bit line conductive portion located on top of the bit line contact layers; a dielectric layer located around the sidewall of the bit line conductive portion; and a gap between the dielectric layer and the bit line conductive portion.

[0022] Compared with the prior art, the technical solution provided by the embodiments of the present invention has the following advantages:

[0023] In this embodiment of the invention, a pseudo bit line structure is first formed on top of the bit line contact layer, and then a sacrificial layer is filled between the pseudo bit line structures. During the removal of the pseudo bit line structure, the sacrificial layer protects the substrate. After the pseudo bit line structure is removed, vias are formed between the sacrificial layers, which can serve as filling areas for the bit line conductive parts, thereby avoiding impurities generated during the etching process to form the bit line conductive parts. In addition, the filling method ensures that the bit line conductive parts are supported by the sacrificial layer during formation, making them less prone to tilting or collapse. Furthermore, removing the spacer layer between the bit line conductive parts and the dielectric layer to form gaps reduces the parasitic capacitance of the memory. Thus, the performance of the memory is improved, for example, the memory operates at a faster speed, has a higher yield, and a longer lifespan.

[0024] In addition, the material of the spacer layer is different from that of the dielectric layer, pseudo-bit line structure and sacrificial layer. Therefore, wet etching can be used in the process of removing the spacer layer to form gaps, thereby simplifying the process and saving costs.

[0025] In addition, the dielectric layer is made of materials with low dielectric constants. Low dielectric constant materials can reduce parasitic capacitance and improve memory performance.

[0026] Furthermore, the step of forming the patterned mask layer includes: forming multiple discrete cores on the pseudo-bitline layer; forming a sidewall film covering the top and sidewalls of the cores and the pseudo-bitline layer; etching the sidewall film to form a sidewall layer opposite to the sidewalls of the core layer; and removing the cores, with the sidewall layer serving as the patterned mask layer. That is, the sidewall film is not formed by photolithography, but rather grown on the sidewalls of the cores; thus, the size of the sidewall layer is not limited by the photolithography process. By reducing the size of the sidewall layer, the size of the pseudo-bitline structure formed using the sidewall layer as a mask can be reduced, thereby reducing the size of the memory.

[0027] In addition, the step of forming the bit line conductive portion includes: forming a barrier layer at the bottom and sidewalls of the via; and forming a conductive layer on the surface of the barrier layer that fills the via. The barrier layer can block the diffusion of the conductive layer material, thereby improving the performance of the memory.

[0028] In addition, the conductive layer is made of one or more of ruthenium, tungsten, gold, or silver; ruthenium, tungsten, gold, or silver are all low-resistance materials, which can reduce the resistance of the conductive layer and thus improve the operating speed of the memory. Attached Figure Description

[0029] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments, and unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0030] Figures 1 to 16 This is a schematic diagram of the structure corresponding to each step in the manufacturing method of the memory provided in the first embodiment of the present invention;

[0031] Figure 17 This is a schematic diagram of the structure of a memory provided in the second embodiment of the present invention. Detailed Implementation

[0032] As can be seen from the background technology, the performance of existing memory technologies needs to be improved.

[0033] Analysis revealed that the main causes of the above problems include: as process nodes shrink, the spacing between bit lines becomes narrower, leading to larger parasitic capacitances between bit lines, which in turn affects memory operating speed and increases power consumption. Additionally, when forming the bit line structure using etching methods, a large amount of non-volatile impurities remain in the bit line structure; excessive impurities increase the resistance of the bit line structure, thus slowing down memory operation. Furthermore, as the width of the bit line structure becomes narrower, the bit line structure formed by etching methods is prone to tilting and collapse, thus affecting memory yield and lifespan.

[0034] To address the aforementioned problems, embodiments of the present invention provide a method for manufacturing a memory. By forming a gap between the bit line conductive portion and the dielectric layer, the parasitic capacitance of the memory is reduced. Furthermore, by filling the vias to form the bit line conductive portion, the method avoids forming the bit line conductive portion through etching, reducing the content of impurities generated by etching in the bit line conductive portion, thereby reducing the resistance of the bit line conductive portion. Additionally, the bit line conductive portion is supported by the sacrificial layer during formation, making it less prone to tilting or collapse, resulting in higher memory yield and longer lifespan.

[0035] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of the present invention to enable the reader to better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0036] The first embodiment of the present invention provides a method for manufacturing a memory. Figures 1 to 16 This is a schematic diagram of the structure corresponding to each step in the manufacturing method.

[0037] refer to Figure 1 The substrate 100 and a plurality of discrete bit line contact layers 101 are provided. The substrate 100 has a plurality of active regions 102, and each bit line contact layer 101 is electrically connected to the active region 102.

[0038] The substrate 100 is made of silicon, germanium, or other semiconductor materials.

[0039] The area between adjacent active regions 102 is filled with a first isolation layer 103, which is used to isolate multiple active regions 102. The material of the first isolation layer 103 is an insulating material, such as silicon dioxide.

[0040] In this embodiment, a portion of the bit line contact layer 101 is located within the substrate 100, while a portion is above the surface of the substrate 100. The partial embedding of the bit line contact layer 101 into the substrate 100 reduces the parasitic capacitance of the memory and improves memory performance. In other embodiments, the bit line contact layer may also be located on the substrate surface.

[0041] The material of the bit line contact layer 101 is a conductive material, such as polysilicon.

[0042] In this embodiment, a second isolation layer 104 may also be formed on the surface of the substrate 100. The second isolation layer 104 fills the area between the discrete bit line contact layers 101 and is used to isolate the multiple bit line contact layers 101; the top of the second isolation layer 104 may be flush with the top of the bit line contact layer 101.

[0043] The material of the second isolation layer 104 is an insulating material, such as silicon nitride.

[0044] Reference Figures 1 to 6 A pseudo bit line structure 117 is formed on the top of the bit line contact layer 101.

[0045] The pseudo bit line structure 117 is used to define the position and size of the subsequently formed bit line structure; that is, the size of the pseudo bit line structure 117 is the same as the size of the subsequently formed bit line structure. Since the pseudo bit line structure 117 does not need to have conductive properties, an insulating material can be used as the material for the pseudo bit line structure 117.

[0046] The steps for forming the pseudo bit line structure 117 include: forming a pseudo bit line layer 105 on a substrate 100, the pseudo bit line layer 105 covering the bit line contact layer 101; forming a patterned mask layer 115 on the pseudo bit line layer 105; and etching the pseudo bit line layer 105 using the patterned mask layer 115 as a mask to form the pseudo bit line structure 117.

[0047] Specifically, in this embodiment, the pseudo bitline structure 117 is formed using a double patterning (SADP) method. The method for forming the pseudo bitline structure 117 will be described in detail below with reference to the accompanying drawings.

[0048] refer to Figure 1 A pseudo bit line layer 105 is formed on the substrate 100, and the pseudo bit line layer 105 covers the bit line contact layer 101.

[0049] A bottom mask layer 106 and a core layer 109 are formed sequentially on the pseudo bit line layer 105. In this embodiment, the bottom mask layer 106 includes a first bottom mask layer 107 and a second bottom mask layer 108.

[0050] The first bottom mask layer 107 and the second bottom mask layer 108 are made of different materials. Specifically, the first bottom mask layer 107 can be made of silicon oxynitride, and the second bottom mask layer 108 can be made of silicon hydroxide.

[0051] It is understood that in other embodiments, the bottom mask layer may also be a single-layer structure.

[0052] In this embodiment, the core layer 109 includes a first core layer 110 and a second core layer 111. The material of the first core layer 110 includes silicon oxynitride. The material of the second core layer 111 includes silicon hydroxide.

[0053] In other embodiments, the core layer may also be a single-layer structure.

[0054] A patterned photoresist layer 112 is formed on the core layer 109.

[0055] refer to Figure 2 With a patterned photoresist layer of 112 (reference) Figure 1 Using a mask, the core layer 109 was etched (reference). Figure 1 This forms multiple separate core sections 113. Each core section 113 has a double-layer structure; however, in other embodiments, the core section may also have a single-layer structure.

[0056] After the core 113 is formed, the patterned photoresist layer 112 is removed.

[0057] refer to Figure 3 A sidewall membrane 114 is formed, covering the top and sidewalls of the core 113 and the bottom mask layer 106.

[0058] In this embodiment, the sidewall film 114 is deposited using atomic layer deposition (ALD); the sidewall film 114 formed by ALD has a more uniform thickness. In other embodiments, the sidewall film can be formed using methods such as chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0059] The material of the sidewall membrane 114 is different from that of the core 113; for example, it can be silicon oxide.

[0060] refer to Figure 4 , opposite side wall membrane 114 (reference) Figure 3 The etching process is performed to form a sidewall layer 115 located on the opposite sidewall of the core 113. Due to the etching load effect, that is, the larger the etched area, the easier it is to be etched, and the sidewall film 114 deposited on the sidewall of the core 113 (refer to...) Figure 3 It is not easily etched, thus forming the sidewall layer 115.

[0061] refer to Figure 5 Remove core part 113 (reference) Figure 4 The sidewall layer 115 serves as a patterned mask layer 115.

[0062] Using the patterned mask layer 115 as a mask, the bottom mask layer 106 is etched (reference). Figure 4 This forms a patterned bottom mask layer 116. In this embodiment, the patterned bottom mask layer 116 has a two-layer structure. In other embodiments, the patterned bottom mask layer may also be a single-layer structure.

[0063] refer to Figure 6 With a graphical bottom mask layer 116 (reference) Figure 5 Using a mask, 105 pseudo-bit line layers were etched (reference). Figure 5 This forms a pseudo bitline structure 117. After forming the pseudo bitline structure 117, the patterned bottom mask layer 116 is removed.

[0064] In this embodiment, the patterned mask layer 115 (reference) Figure 4 The pattern is passed to the pseudo bit line structure 117 through the patterned bottom mask layer 116. Therefore, the width of the pseudo bit line structure 117 is the same as the width of the patterned mask layer 115. The smaller the width of the patterned mask layer 115, the smaller the width of the pseudo bit line structure 117, and thus the smaller the size of the memory.

[0065] The materials of the pseudo-bit line structure 117 include silicon nitride, silicon oxynitride, or silicon carbonitride.

[0066] It is worth noting that in other embodiments, the pseudo-bitline structure may not be formed using a dual patterning process. For example, a single hard mask layer may be formed directly on the pseudo-bitline layer, and photolithography may be performed on the hard mask layer to form multiple discrete cores located on the pseudo-bitline layer; a sidewall film covering the top and sidewalls of the cores and the pseudo-bitline layer may be formed; the sidewall film may be etched to form a sidewall layer on the opposite sidewalls of the cores; the cores may be removed, and the sidewall layer may be a patterned mask layer. The pseudo-bitline layer may be etched using the patterned mask layer to form the pseudo-bitline structure.

[0067] refer to Figure 7 An initial spacer film 128 is formed by a deposition process. The initial spacer film 128 covers the sidewalls of the bit line contact layer 101, the sidewalls and top of the pseudo bit line structure 117, and the top of the second isolation layer 104.

[0068] An initial dielectric film 129 is formed on the surface of the initial spacer film 128 by a deposition process.

[0069] refer to Figure 8 Remove the initial spacer membrane 128 (reference) from the top of the pseudo-bit line structure 117 and the top of the second isolation layer 104. Figure 7 Thus, a spacer layer 130 is formed on the sidewall of the pseudo-position line structure 117 and the sidewall of the position line contact layer.

[0070] Remove the initial dielectric film 129 (reference) from the top of the pseudo bit line structure 117 and the top of the second isolation layer 104. Figure 7 Thus, a dielectric layer 118 is formed on the sidewall of the spacer layer 130.

[0071] During the subsequent etching process to remove the sacrificial layer, the spacer layer 130 and the dielectric layer 118 can protect the bit line conductive parts and ensure the accuracy of the morphology and size of the bit line conductive parts.

[0072] The dielectric layer 118 is made of a low dielectric constant material, which can reduce the parasitic capacitance of the memory and improve the operating speed of the memory.

[0073] refer to Figure 9 A sacrificial layer 119 is formed to fill the region between adjacent pseudo-bit line structures 117, and the sacrificial layer 119 covers the sidewall of the dielectric layer 118.

[0074] The sacrificial layer 119 also covers the surface of the second isolation layer 104.

[0075] refer to Figure 10 Remove pseudo bit line structure 117 (reference) Figure 9 This forms a through hole that exposes the bit line contact layer 101.

[0076] In this embodiment, the material of the pseudo-bit line structure 117 is different from the materials of the spacer layer 130, dielectric layer 118, and sacrificial layer 119, and the etching rate of the pseudo-bit line structure 117 is greater than that of the sacrificial layer 119, dielectric layer 118, and spacer layer 130. The etching selectivity ratio of the materials of the pseudo-bit line structure 117 to those of the sacrificial layer 119, dielectric layer 118, and spacer layer 130 is 5-15, for example, 8, 10, and 13. The pseudo-bit line structure 117 is removed by wet etching, using a hot phosphoric acid solution as the etching solvent. In other embodiments, a dry etching method can also be used to remove the pseudo-bit line structure.

[0077] refer to Figure 11 and Figure 12 A bit line conductive portion 120 is formed that fills the through-hole and covers the bit line contact layer 101.

[0078] The bit line conductive portion 120 is a conductive structure within the bit line structure. Formed using a via-filling method, the bit line conductive portion 120 is supported by the sacrificial layer 119 during its formation. Therefore, even if the width of the bit line conductive portion 120 is narrow, it is less prone to tilting or collapse. Furthermore, since no etching process is used, no etching-induced impurities remain in the bit line conductive portion 120; thereby reducing the resistance of the bit line conductive portion 120 and improving the operating speed of the memory.

[0079] The step of forming the bit line conductive portion 120 includes: forming a barrier layer 121 at the bottom and sidewall of the through hole; and forming a conductive layer 122 on the surface of the barrier layer 121 that fills the through hole.

[0080] In this embodiment, the conductive layer 122 and the barrier layer 121 formed by atomic deposition technology have more uniform thicknesses. In other embodiments, other deposition techniques may also be used.

[0081] The barrier layer 121 is made of one or both of tantalum nitride and titanium nitride. Tantalum nitride or titanium nitride is conductive and has good barrier properties, preventing the diffusion of the conductive layer 122. The conductive layer 122 is made of one or more of ruthenium, tungsten, gold, or silver. Ruthenium, tungsten, gold, or silver are all low-resistance metals, which can further reduce the resistance of the conductive layer 122 and improve the operating speed of the memory.

[0082] In other embodiments, the bit line conductive portion may also be a single-layer structure.

[0083] In this embodiment, as Figure 11 As shown, the conductive layer 122 and the barrier layer 121 are also formed on the top surface of the sacrificial layer 119, the spacer layer 130, and the dielectric layer 118; as Figure 12As shown, the conductive portion 120 of the bit line is planarized, and the conductive layer 122 and the barrier layer 121 (see reference) above the top surface of the sacrificial layer 119, the spacer layer 130 and the dielectric layer 118 are removed. Figure 11 ).

[0084] In this embodiment, chemical mechanical polishing technology is used to planarize the conductive portion 120 of the bit line.

[0085] refer to Figure 13 After forming the bit line filling portion 120, the spacer layer 130 is removed (see reference). Figure 12 This forms a gap 131 between the dielectric layer 118 and the bit line conductive portion 120.

[0086] In this embodiment, the spacer layer 130 located on the sidewall of the bit line contact layer 101 is removed. In other embodiments, the spacer layer located on the sidewall of the bit line contact layer may be retained.

[0087] The material of spacer layer 130 is different from that of dielectric layer 118 and sacrificial layer 119. The etching rate of spacer layer 130 is greater than that of dielectric layer 118 and sacrificial layer 119, and the selective etching ratio of spacer layer 130 to dielectric layer 118 and sacrificial layer 119 is 5-15. Therefore, in this embodiment, wet etching can be used to remove spacer layer 130 to form gap 131. In other embodiments, dry etching can also be used to remove spacer layer.

[0088] The material of spacer layer 130 includes silicon nitride, silicon oxide, silicon oxynitride, or silicon carbonitride.

[0089] refer to Figure 14 An insulating capping layer 123 is formed on top of the conductive portion 120 and the dielectric layer 118.

[0090] In this embodiment, the insulating capping layer 123 is also located on top of the gap 131. Because the gap 131 is narrow and elongated, no excessive insulating material will remain in the gap 131 during the process of depositing insulating material to form the insulating capping layer 123.

[0091] The insulating cover layer 123 serves as the insulating structure in the bit line structure.

[0092] In this embodiment, the insulating cover layer 123 is formed using a double patterning process (SADP), which makes the dimensions of the formed insulating cover layer 123 more precise.

[0093] refer to Figure 15 After forming the insulating capping layer 123, the sacrificial layer 119 is removed (see reference). Figure 14 ).

[0094] The etching rate of the sacrificial layer 119 is greater than that of the insulating cap layer 123, and the etching selectivity ratio between the materials of the sacrificial layer 119 and the insulating cap layer 123 is 5-15, for example, 8, 10, or 13. This high etching selectivity ensures that the insulating cap layer 123 maintains its original morphology and dimensions during the removal of the sacrificial layer 119. In this embodiment, a wet etching method is used to remove the sacrificial layer 119, and hydrofluoric acid solution is used as the etching reagent. In other embodiments, a dry etching method can also be used to remove the sacrificial layer.

[0095] refer to Figure 16 A protective layer 124 is formed on the surface of the dielectric layer 118 and the insulating capping layer 123.

[0096] In this embodiment, the protective layer 124 is also located on the surface of the second isolation layer 104.

[0097] In this embodiment, the protective layer 124 is formed using atomic layer deposition technology.

[0098] The material of the protective layer 124 includes silicon carbonitride.

[0099] In summary, the gap 131 between the bit line conductive portion 120 and the dielectric layer 118 in this embodiment can reduce parasitic capacitance, thereby improving the memory's response speed and reducing its power consumption. In addition, the bit line conductive portion 120 has low resistance, resulting in a fast memory operating speed. Furthermore, the bit line conductive portion 120 is supported by the sacrificial layer 119 during its formation, making it less prone to tilting or collapse, further improving the memory's yield and lifespan.

[0100] The second embodiment of the present invention also provides a memory that can be manufactured by the memory manufacturing method of the first embodiment. Figure 17 This is a schematic diagram of the memory structure provided in this embodiment.

[0101] refer to Figure 17 The memory includes: a substrate 200 and a plurality of discrete bit line contact layers 201, the substrate 200 having a plurality of active regions 202, and each bit line contact layer 201 being electrically connected to an active region 202; a bit line conductive portion 205 located on top of the bit line contact layer 201; a dielectric layer 208 located on the periphery of the sidewall of the bit line conductive portion 205; and a gap 211 between the dielectric layer 208 and the bit line conductive portion 205.

[0102] The memory provided in this embodiment will be described in detail below with reference to the accompanying drawings.

[0103] The active regions 202 also include a first isolation layer 203, which is used to isolate the active regions 202.

[0104] The surface of the substrate 200 also includes a second isolation layer 204, which is used to isolate the bit line contact layer 201.

[0105] The bit line conductive portion 205 further includes: a conductive layer 206 located on top of the bit line contact layer 201; and a barrier layer 207 located between the bit line contact layer 201 and the conductive layer 206, the barrier layer 207 also covering the sidewall of the conductive layer 206.

[0106] The conductive layer 206 is made of one or more of ruthenium, tungsten, gold, or silver. Ruthenium, tungsten, gold, or silver are all low-resistance metals, which can reduce the resistance of the conductive layer 206 and improve the operating speed of the memory.

[0107] The barrier layer 207 is made of a conductive material, such as tantalum nitride or titanium nitride.

[0108] The thickness of the barrier layer 207 is 2.5-6nm, for example, it can be 3nm. The barrier layer 207 of this thickness has a good ability to block the diffusion of the conductive layer 206.

[0109] The dielectric layer 208 is made of a low dielectric constant material.

[0110] An insulating capping layer 209 is located on top of the conductive part 205 and the dielectric layer 208; a protective layer 210 is located on the surface of the insulating capping layer 209 and the dielectric layer 208, and the protective layer 210 is also located on the surface of the second isolation layer 204.

[0111] In summary, the dielectric layer 208 of this embodiment uses a low dielectric constant material, which can reduce parasitic capacitance. A gap 211 exists between the bit line conductive portion 205 and the dielectric layer 208, which further reduces parasitic capacitance, improves memory operating speed, and reduces memory power consumption. Furthermore, the conductive layer 206 is made of a low-resistance material such as ruthenium, tungsten, gold, or silver; the low resistance of the conductive layer 206 results in a fast memory operating speed.

[0112] Those skilled in the art will understand that the above embodiments are specific examples of implementing the present invention, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of the present invention. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for manufacturing a memory, characterized in that, include: A substrate and a plurality of discrete bit line contact layers are provided, wherein the substrate has a plurality of active regions, and each bit line contact layer is electrically connected to the active region. A pseudo bit line structure is formed on top of the bit line contact layer; A spacer layer is formed on the sidewall of the pseudo bit line structure and the sidewall of the bit line contact layer; A dielectric layer is formed on the sidewall of the spacer layer; A sacrificial layer is formed to fill the region between adjacent pseudo-bit line structures, and the sacrificial layer covers the sidewalls of the dielectric layer; After the sacrificial layer is formed, the pseudo bit line structure is removed to form a via that exposes the bit line contact layer; A bit line conductive portion is formed that fills the through-hole and covers the bit line contact layer; After the bit line conductive portion is formed, the spacer layer is removed to form a gap between the dielectric layer and the bit line conductive portion.

2. The method for manufacturing a memory according to claim 1, characterized in that, The material of the spacer layer is different from the material of the dielectric layer, the pseudo-bit line structure, and the sacrificial layer.

3. The method for manufacturing a memory according to claim 2, characterized in that, The spacer layer is made of silicon nitride, silicon oxide, silicon oxynitride, or silicon carbonitride.

4. The method for manufacturing a memory according to claim 2, characterized in that, The dielectric layer is made of a material with a low dielectric constant.

5. The method for manufacturing a memory according to claim 1, characterized in that, The steps for forming the pseudo bit line structure include: forming a pseudo bit line layer on the substrate, the pseudo bit line layer covering the bit line contact layer; forming a patterned mask layer on the pseudo bit line layer; and etching the pseudo bit line layer using the patterned mask layer as a mask to form the pseudo bit line structure.

6. The method for manufacturing a memory according to claim 5, characterized in that, The step of forming the patterned mask layer includes: forming a plurality of discrete cores on the pseudo-bitline layer; forming a sidewall film covering the top and sidewalls of the cores and the pseudo-bitline layer; etching the sidewall film to form a sidewall layer located on the opposite sidewalls of the cores; and removing the cores, wherein the sidewall layer serves as the patterned mask layer.

7. The method for manufacturing a memory according to claim 1, characterized in that, In the process of removing the pseudo-bit line structure, the etching selectivity ratio of the material of the pseudo-bit line structure to the materials of the sacrificial layer, the dielectric layer and the spacer layer is 5-15.

8. The method for manufacturing a memory according to claim 7, characterized in that, The materials of the pseudo-position line structure include silicon nitride, silicon oxynitride, or silicon carbonitride.

9. The method for manufacturing a memory according to claim 7, characterized in that, The material of the sacrificial layer includes silicon oxide.

10. The method for manufacturing a memory according to claim 1, characterized in that, The step of forming the conductive portion of the bit line includes: forming a barrier layer at the bottom and sidewall of the through hole; and forming a conductive layer on the surface of the barrier layer that fills the through hole.

11. The method for manufacturing a memory according to claim 10, characterized in that, The conductive layer is made of one or more of ruthenium, tungsten, gold, or silver.

12. The method for manufacturing a memory according to claim 10, characterized in that, The barrier layer is made of one or both of tantalum nitride and titanium nitride.

13. The method for manufacturing a memory according to claim 10, characterized in that, The conductive layer and the barrier layer are also located on the top surface of the sacrificial layer, the spacer layer and the dielectric layer; the step of forming the bit line conductive portion further includes: planarizing the bit line conductive portion and removing the conductive layer and the barrier layer that are higher than the top surface of the sacrificial layer, the spacer layer and the dielectric layer.

14. The method for manufacturing a memory according to claim 1, characterized in that, After forming the gap, the method further includes: forming an insulating capping layer on top of the bit line conductive portion and the dielectric layer; removing the sacrificial layer after forming the insulating capping layer; and forming a protective layer on the surface of the dielectric layer and the insulating capping layer after removing the sacrificial layer.

15. The method for manufacturing a memory according to claim 14, characterized in that, In the process of removing the sacrificial layer, the etching selectivity ratio of the material of the sacrificial layer to the material of the insulating cap layer is 5-15.

16. A memory manufactured using the manufacturing method according to any one of claims 1-15, characterized in that, include: The substrate and multiple discrete bit line contact layers, wherein the substrate has multiple active regions, and each bit line contact layer is electrically connected to the active region. Bit line conductive portion, the bit line conductive portion being located on top of the bit line contact layer; A dielectric layer located on the periphery of the sidewall of the bit line conductive portion; There is a gap between the dielectric layer and the bit line conductive portion.

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