A vertically stacked complementary field effect transistor and its preparation method

Abstract

The present invention discloses a vertically stacked complementary field-effect transistor (FET) and its preparation method. The invention vertically stacks an n-type indium tin oxide field-effect transistor (ITO FET) at the bottom layer and a p-type two-dimensional material field-effect transistor at the top layer to form a complementary field-effect transistor, thereby achieving a CMOS device with low power consumption, small unit area occupation, minimal parasitic effects, and high operating speed.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a vertically stacked complementary field-effect transistor based on indium tin oxide / two-dimensional materials and a preparation method thereof. Background Art

[0002] The flat panel display industry has become one of the core pillar industries in my country's electronic information sector. Flat panel display technology can be categorized into two types based on driving methods: passive matrix driving and active matrix driving. Active matrix driving is the core method for achieving large-size, high-definition flat panel displays. Thin-film transistors (TFTs), as driving units, play a crucial role in flat panel display technology and are key to achieving high-resolution displays. As flat panel display technology evolves toward higher resolution, faster response speeds, and more flexible displays, the performance requirements for TFTs are becoming increasingly stringent. Developing a semiconductor channel material with high mobility and a high on / off ratio has become a crucial step in the development of display technology.

[0003] Indium tin oxide (ITO) is a tin-doped wide-bandgap semiconductor with a bandgap of approximately 3.5-4.3 eV. ITO films typically exhibit very high conductivity, high transmittance in the visible range, and high reflectivity in the infrared range. These properties have led to its widespread application in solar cells, thermal mirrors, anti-reflective coatings, gas sensors, and flat-panel displays. Recent research has demonstrated that ITO typically possesses a high carrier concentration. By significantly reducing the film thickness, the carrier concentration can be manipulated, achieving a transition from metallic to semiconducting properties. Furthermore, ITO's low relative dielectric constant allows ITO transistors to better overcome short-channel effects, enabling nanoscale devices with current switching ratios greater than 8, and enabling smaller individual driver units. Therefore, compared to oxide semiconductor materials such as ZnO, SnO2, In2O3, IGZO, and IGO, ITO transistors hold great potential in the development of next-generation flat-panel display technologies. Although ITO transistors have excellent performance, they are n-type transistors. The lack of p-type transistors with similar performance limits the design of low energy consumption, working speed, complementary logic circuits, etc. of flat panel display driver circuits. The channel materials of existing p-type transistors are mostly copper-based oxides, tin monoxide, NiO x However, the p-type transistors made from these materials have low mobility. The two-dimensional material monolayer tungsten diselenide (WSe2) is a rare semiconductor material with good electron and hole transport properties. Its p-type transport properties when in contact with palladium materials have attracted increasing research attention. Summary of the Invention

[0004] The purpose of the present invention is to provide a vertically stacked complementary transistor based on indium tin oxide / two-dimensional materials and a preparation method thereof, wherein by improving the structure, gate electrode, gate dielectric, etc. of the vertically stacked complementary field-effect transistor, the vertical stacking of n-type indium tin oxide field-effect transistors and p-type two-dimensional material field-effect transistors is utilized, and the two complement each other to achieve better electrical performance and smaller area occupancy than existing device structures and technologies.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] A CMOS device is a vertically stacked complementary field-effect transistor based on indium tin oxide / two-dimensional materials, wherein an n-type indium tin oxide field-effect transistor (ITO FET) is located at the bottom layer and a p-type two-dimensional material field-effect transistor is located at the top layer, and the two are vertically stacked; the gate electrodes of the two field-effect transistors are interconnected; the source electrodes or drain electrodes of the two field-effect transistors are interconnected, so that their source and drain electrodes are connected in series to form a CMOS inverter.

[0007] Preferably, the ITO FET includes a substrate, a buffer layer, a first gate electrode, a first gate dielectric layer, an ITO channel and source / drain electrodes at both ends thereof, and a second gate dielectric layer arranged in sequence from bottom to top. The substrate can be a rigid substrate, such as a silicon wafer, a glass substrate, a mica sheet, etc., or a flexible substrate, such as a polymer substrate such as PET (polyethylene terephthalate), PI (polyimide film), PMMA (polymethyl methacrylate), etc. The material of the buffer layer is preferably SiO2, SiN x and high-κ dielectric HfO2, with a typical thickness of 10-100 nm. The ITO channel layer and buffer layer are grown using thin-film fabrication techniques such as magnetron sputtering, atomic layer deposition, and electron beam evaporation. The source, drain, and gate electrodes of the ITO transistor are fabricated through a series of micro-nanofabrication processes, including spin coating of photoresist, baking, exposure, development, fixing, oxygen plasma debonding, metal evaporation, and lift-off, or through shutter mask evaporation. The gate dielectric is preferably grown using atomic layer deposition.

[0008] The two-dimensional material FET is stacked vertically with the ITO FET. Preferably, the two-dimensional material FET includes a second gate electrode, a third gate dielectric layer, a two-dimensional material channel and a source-drain electrode at both ends thereof, a fourth gate dielectric layer, and a third gate electrode sequentially arranged on the second gate dielectric layer from bottom to top. Wherein, the second gate electrode is directly prepared on the gate dielectric (i.e., the second gate dielectric layer) on the top of the ITO FET. The two-dimensional material is preferably WSe2, MoTe2, In2Se3, etc., and a single layer of WSe2 is grown on a substrate such as a silicon wafer, a mica sheet, or molten glass by chemical vapor deposition, and then directionally transferred in the vertical direction of the ITO FET. The source, drain electrode and gate electrode of the two-dimensional material transistor are prepared by a series of micro-nano processing processes or shutter mask evaporation processes such as spin coating photoresist, baking, exposure, development, fixing, oxygen plasma debonding, metal evaporation, and stripping. The gate dielectric is preferably grown by atomic layer deposition.

[0009] The first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer and the fourth gate dielectric layer are made of high-κ dielectric materials, such as HfO2, HfSiO4, Si3N4, La2O5, ZrO2, etc., and the thickness is preferably 5 to 10 nm.

[0010] The first gate electrode, the second gate electrode and the third gate electrode are connected in series, and the electrode materials are preferably Al, Au, or Pt.

[0011] The source-drain electrodes at both ends of the ITO channel and the source-drain electrodes at both ends of the two-dimensional material channel are connected in series, and the electrode materials are preferably Ni, Pt, and Cr / Pd, Pd / Au metal composite layers.

[0012] The present invention also discloses a method for preparing the above-mentioned vertically stacked complementary field-effect transistor based on indium tin oxide / two-dimensional material, comprising the following steps:

[0013] 1) Cleaning the substrate and growing a buffer layer on the substrate;

[0014] 2) sequentially forming a first gate electrode and a first gate dielectric layer on the buffer layer;

[0015] 3) preparing an ITO channel and source / drain electrodes at both ends of the ITO channel on the first gate dielectric layer;

[0016] 4) growing a second gate dielectric layer on the ITO channel and the source and drain electrodes at both ends;

[0017] 5) forming windows in the second gate dielectric layer and the first gate dielectric layer by photolithography and etching, and then preparing a second gate electrode, so that the second gate electrode and the first gate electrode are connected to each other through the window;

[0018] 6) growing a third gate dielectric layer on the second gate electrode, and forming windows connecting the upper and lower source electrodes or drain electrodes in the third gate dielectric layer and the second gate dielectric layer by photolithography and etching;

[0019] 7) transferring the two-dimensional material to a designated area on the third gate dielectric layer as a channel, and preparing source and drain electrodes at both ends thereof, wherein the source electrode or drain electrode is connected to the underlying source electrode or drain electrode through the window prepared in step 6);

[0020] 8) growing a fourth gate dielectric layer on the two-dimensional material channel and the source and drain electrodes at both ends;

[0021] 9) Forming windows in the fourth gate dielectric layer and the third gate dielectric layer by photolithography and etching, and then preparing a third gate electrode, so that the third gate electrode and the second gate electrode are connected to each other through the windows.

[0022] The present invention complements a p-type two-dimensional material FET with an n-type ITO FET, and vertically stacks the two to produce a CMOS device with low power consumption, small unit area occupation, small parasitic effects, and high operating speed. Its beneficial effects are mainly reflected in:

[0023] (1) ITO transistors can better overcome the short channel effect, realize nanoscale devices with excellent performance, and make the device occupy a smaller area.

[0024] (2) The n-type ITO transistor and the p-type two-dimensional material FET can be designed as a complementary field-effect transistor, which can achieve ultra-low power consumption of the device.

[0025] (3) ITO FET and two-dimensional material FET adopt a vertical stacking structure, which not only further reduces the device's occupied area, but also reduces the system parasitic effects and power consumption, and improves the operating speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Schematic diagram of the structure of a vertically stacked complementary field-effect transistor of indium tin oxide / tungsten diselenide, wherein: 1 is a substrate, 2 is a buffer layer, 3 is a first gate electrode, 4 is a first gate dielectric layer, 5 is a first source / drain electrode, 6 is an indium tin oxide channel, 7 is a second gate dielectric layer, 8 is a second gate electrode, 9 is a third gate dielectric layer, 10 is a tungsten diselenide channel, 11 is a second source / drain electrode, 12 is a fourth gate dielectric layer, and 13 is a third gate electrode.

[0027] Figure 2The following is a flow chart of the fabrication process for the ITO FET in a vertically stacked complementary field-effect transistor of indium tin oxide / tungsten diselenide, wherein: Step 1: Clean the silicon wafer using a standard RCA cleaning process; Step 2: Grow a buffer layer on the silicon wafer; Step 3: Prepare the gate electrode; Step 4: Form a high-κ gate dielectric layer; Step 5: Grow ITO; Step 6: Prepare source and drain electrodes; Step 7: Grow a high-κ gate dielectric layer.

[0028] Figure 3 This is a process flow chart for preparing WSe2 FET in a vertically stacked complementary field-effect transistor of indium tin oxide / tungsten diselenide, wherein: Step 8 prepares the gate electrode; Step 9 grows a high-κ gate dielectric layer; Step 10 directionally transfers WSe2 onto the high-κ gate dielectric layer prepared in Step 9 and performs patterned etching; Step 11 prepares source and drain electrodes; Step 12 grows a high-κ gate dielectric layer; Step 13 prepares the gate electrode. DETAILED DESCRIPTION

[0029] In order to make the contents of the present invention easier to understand, the technical solutions of the present invention are further described below through specific embodiments in conjunction with the accompanying drawings. However, the following embodiments are merely examples of the present invention and do not represent the scope of protection of the rights defined by the present invention. The scope of protection of the rights of the present invention shall be subject to the claims.

[0030] The preparation of ITO FET can be seen in Figure 1 and Figure 2 :

[0031] Step 1: Substrate 1 is Si(111), and particles, organic matter, oxides, etc. on the substrate are cleaned using a standard RCA cleaning process. After cleaning, the substrate is blown dry with high-purity nitrogen gas for later use.

[0032] Step 2: First, the Si(111) substrate 1 is cleaned with a solution of hydrofluoric acid: deionized water = 1:4 (volume ratio) to remove the SiO2 on the surface. Then, an atomic layer deposition system is used to grow a 20nm thick high-κ dielectric HfO2 buffer layer 2 on the surface of the substrate 1. TEMAHf and O3 are used as precursors, the growth temperature is 250℃, and then a rapid annealing furnace is used to anneal in a nitrogen atmosphere at 500℃ for 30s to reduce defects.

[0033] Step 3: Prepare the first gate electrode 3 by process steps including coating, baking, photolithography, development, metal evaporation and stripping. The specific steps include: (1) on the basis of the second step, spin-coating HMDS (hexamethyldisilazane) as an adhesion layer, the spin-coating parameters are 4000 rpm, 30 s, and baking at 95 ° C for 60 s after spin-coating; (2) first spin-coating photoresist LOR10A, the spin-coating parameters are 3000 rpm, 30 s, and baking at 150 ° C for 120 s after spin-coating; then spin-coating photoresist AZ5214, the spin-coating parameters are 4000 rpm, 30 s, and baking at 95 ° C for 90 s after spin-coating; (3) exposing for 1.7 s to pattern the metal-peeled photoresist; (4) developing: the developer is 2.38% TMAH (tetramethylammonium hydroxide), developing for 85 s to 90 s, cleaning with deionized water, and drying with N2; (5) oxygen plasma cleaning: the ratio of argon and oxygen is 4:1, 30 W, 2 min; (6) evaporating 50 nm Al; (7) Stripping metal: heating at 120°C for 30 min in NMP (N-methylpyrrolidone), washing with isopropanol, and drying with nitrogen.

[0034] Step 4: A 5nm thick layer of high-κ HfO2 was grown on the surface using an atomic layer deposition system as the first gate dielectric layer 4. TEMAHf and O3 were used as precursors at a growth temperature of 250°C. The layer was then annealed in a nitrogen atmosphere at 500°C for 30 seconds in a rapid annealing furnace to reduce defects.

[0035] Step 5: Use magnetron sputtering to grow 15nm of ITO, and use processes such as coating, baking, photolithography, development, and wet etching to prepare ITO channels 6 with a length of 10μm and a width of 50μm. The specific steps include: (1) After spin coating, the photoresist is AZ1518, which is baked at 110℃ for 70s and exposed for 4.7s. The developer is AZ351B, which is developed for 2min and fixed in deionized water for 1min; (2) Etching the ITO with an etchant of HCl:H2O=1:1 (volume ratio) for 20s; (3) De-resisting in acetone at 50℃ for 30min.

[0036] Step 6: Prepare the first source / drain electrode 5 by process steps including coating, baking, photolithography, development, metal evaporation and stripping. The specific steps include: (1) Based on the fifth step, spin-coat HMDS as an adhesion layer, with the spin-coating parameters being 4000 rpm for 30 seconds, and then bake at 95°C for 60 seconds; (2) first spin-coat LOR10A, with the spin-coating parameters being 3000 rpm for 30 seconds, and then bake at 150°C for 120 seconds; then spin-coat AZ5214, with the spin-coating parameters being 4000 rpm for 30 seconds, and then bake at 95°C for 90 seconds; (3) expose for 1.7 seconds to pattern the photoresist of the metal stripping; (4) develop: the developer is 2.38% TMAH, develop for 85 to 90 seconds, rinse with deionized water, and blow dry with N2; (5) oxygen plasma cleaning: the ratio of argon and oxygen is 4:1, 30W, 2 minutes; (6) evaporate 50nm Ni; (7) strip metal: heat at 120°C for 30 minutes in NMP, rinse with isopropyl alcohol, and blow dry with nitrogen.

[0037] Step 7: Use an atomic layer deposition system to grow a 10 nm thick high-κ dielectric HfO2 on the surface as the second gate dielectric layer 7. TEMAHf and O3 are used as precursors, and the growth temperature is 250°C.

[0038] The above seven steps complete the preparation of ITO FET.

[0039] Step 8: Before preparing the second gate electrode, the high-κ dielectric HfO2 is first etched to open a "window" (i.e., "opening the window") that is interconnected with the first gate electrode 3. The "opening the window" process includes process steps such as coating, baking, photolithography, development, and plasma etching (ICP). The specific steps include: (1) The photoresist is AZ1518, which is baked at 110°C for 70 seconds after spin coating, exposed for 4.7 seconds, and developed with AZ351B as the developer for 2 minutes, and fixed in deionized water for 1 minute; (2) ICP etching of the high-κ dielectric HfO2 to the first source / drain electrode 5, the etching gas is boron trichloride and chlorine. After etching, the resist is removed in NMP at 110°C for 30 minutes, soaked in acetone for 10 minutes, soaked in isopropyl alcohol for 10 minutes, rinsed with deionized water, and blown dry with high-purity nitrogen.

[0040] Similar to the third step, 50 nm Al is prepared as the second gate electrode 8 and forms an interconnection with the first gate electrode 3 . The specific steps include: (1) on the basis of the seventh step, spin-coating HMDS (hexamethyldisilazane) as an adhesion layer, the spin-coating parameters are 4000 rpm, 30 s, and baking at 95 ° C for 60 s after spin-coating; (2) first spin-coating photoresist LOR10A, the spin-coating parameters are 3000 rpm, 30 s, and baking at 150 ° C for 120 s after spin-coating; then spin-coating photoresist AZ5214, the spin-coating parameters are 4000 rpm, 30 s, and baking at 95 ° C for 90 s after spin-coating; (3) exposing for 1.7 s to pattern the metal-stripped photoresist; (4) developing: the developer is 2.38% TMAH (tetramethylammonium hydroxide), developing for 85 s to 90 s, cleaning with deionized water, and drying with N2; (5) oxygen plasma cleaning: the ratio of argon and oxygen is 4:1, 30 W, 2 min; (6) evaporating 50 nm Al; (7) Stripping metal: heating at 120°C for 30 min in NMP (N-methylpyrrolidone), washing with isopropanol, and drying with nitrogen.

[0041] Step 9: The same as the process in step 4, a high-κ dielectric HfO2 with a thickness of 5 nm is grown on the surface using an atomic layer deposition system as the third gate dielectric layer 9.

[0042] Before preparing WSe2 FET, the high-κ dielectric HfO2 must be etched first, that is, a "window" (i.e., "opening the window") is opened to connect the source and drain of the lower ITO FET with the source and drain of the upper WSe2 FET. The "opening the window" process includes process steps such as coating, baking, photolithography, development, and plasma etching (ICP). The specific steps include: (1) the photoresist is AZ1518, which is baked at 110℃ for 70s after spin coating, exposed for 4.7s, and developed with AZ351B for 2min, and fixed in deionized water for 1min; (2) ICP etching of the high-κ dielectric HfO2 to the first source / drain electrode 5, the etching gas is boron trichloride and chlorine. After etching, the resin is removed in NMP at 110℃ for 30min, soaked in acetone for 10min, soaked in isopropyl alcohol for 10min, rinsed with deionized water, and blown dry with high-purity nitrogen.

[0043] The preparation of WSe2 FET can be seen in Figure 1 and Figure 3 :

[0044] Step 10: Directly transfer the WSe2 grown by chemical vapor deposition to the designated area of ​​the high-κ dielectric HfO2 gate layer prepared in step 9.

[0045] Step 11: Prepare the second source-drain electrode 11 through the following process steps: coating, baking, photolithography, development, metal evaporation and stripping. The specific steps include: (1) spin coating HMDS as an adhesion layer, the spin coating parameters are 4000 rpm, 30 s, and baking at 95 ° C for 60 s after spin coating; (2) first spin coating LOR10A, the spin coating parameters are 3000 rpm, 30 s, and baking at 150 ° C for 120 s after spin coating; then spin coating AZ5214, the spin coating parameters are 4000 rpm, 30 s, and baking at 95 ° C for 90 s after spin coating; (3) exposure for 1.7 s to pattern the photoresist of the metal stripping; (4) development: the developer is 2.38% TMAH, the development is 85 s to 90 s, deionized water is cleaned, and N2 is blown dry; (5) oxygen plasma cleaning: the ratio of argon and oxygen is 4:1, 30 W, 2 min; (6) evaporation of 20 nm Pt; (7) metal stripping: heating at 120 ° C for 30 min in NMP, washing with isopropyl alcohol, and blowing dry with nitrogen. At this time, the source and drain Pt of the WSe2 FET are connected to the source and drain Ni of the ITO FET through the "window" opened in the ninth step.

[0046] Step 12: Use an atomic layer deposition system to grow a 10 nm thick high-κ dielectric HfO2 on the surface as the fourth gate dielectric 12. TEMAHf and O3 are used as precursors, and the growth temperature is 250°C.

[0047] In order to interconnect the gate electrode of ITO FET and the gate electrode of WSe2 FET, it is necessary to etch the high-κ dielectric HfO2 on the gate electrode, that is, to open a "window" (i.e., "opening the window") for the gate electrode of the lower ITO FET to connect to the gate electrode of the upper WSe2 FET. The "opening the window" process includes process steps such as coating, baking, photolithography, development, and plasma etching (ICP). The steps include: (1) the photoresist is AZ1518, which is baked at 110℃ for 70s after spin coating, exposed for 4.7s, and developed with AZ351B for 2min, and fixed in deionized water for 1min; (2) ICP etching of the high-κ dielectric HfO2 to the second gate electrode 8, the etching gas is boron trichloride and chlorine, and after etching, the resist is removed in NMP at 110℃ for 30min, soaked in acetone for 10min, soaked in isopropyl alcohol for 10min, cleaned with deionized water, and blown dry with high-purity nitrogen.

[0048] Step 13: Same as the process in step 3, prepare 50nm Al as the third gate electrode 13.

Claims

1. A CMOS device is based on a vertically stacked complementary field effect transistor of indium tin oxide / two-dimensional material, wherein: An n-type indium tin oxide field-effect transistor is located at the bottom layer, and a p-type two-dimensional material field-effect transistor is located at the upper layer, and the two are stacked vertically; the indium tin oxide field-effect transistor includes a substrate, a buffer layer, a first gate electrode, a first gate dielectric layer, an ITO channel and source-drain electrodes at both ends, and a second gate dielectric layer, which are arranged in sequence from bottom to top; the two-dimensional material field-effect transistor includes a second gate electrode, a third gate dielectric layer, a two-dimensional material channel and source-drain electrodes at both ends, a fourth gate dielectric layer, and a third gate electrode, which are arranged in sequence from bottom to top on the second gate dielectric layer; the first gate electrode, the second gate electrode, and the third gate electrode are connected in series, and the source-drain electrodes at both ends of the ITO channel and the source-drain electrodes at both ends of the two-dimensional material channel are connected in series to form a CMOS inverter.

2. The CMOS device according to claim 1, wherein The substrate is a rigid substrate or a flexible substrate.

3. The CMOS device according to claim 2, wherein: The substrate is a rigid substrate selected from silicon wafer, glass substrate, and mica sheet; or the substrate is a flexible substrate selected from the following polymer materials: PET, PI, and PMMA.

4. The CMOS device according to claim 1, wherein The buffer layer is made of SiO2, silicon nitride or HfO2, and has a thickness of 10-100 nm.

5. The CMOS device according to claim 1, wherein The two-dimensional material is WSe2, MoTe2 or In2Se3.

6. The CMOS device according to claim 1, wherein The first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer and the fourth gate dielectric layer are high Dielectric material.

7. The CMOS device according to claim 6, wherein: The high The dielectric material is selected from HfO2, HfSiO4, Si3N4, La2O5, and ZrO2.

8. The CMOS device according to claim 1, wherein: The materials of the first gate electrode, the second gate electrode and the third gate electrode are selected from Al, Au and Pt; the materials of the source and drain electrodes are selected from Ni, Pt, Cr / Pd and Pd / Au.

9. The method for preparing the CMOS device according to any one of claims 1 to 8, comprising the following steps: 1) Cleaning the substrate and growing a buffer layer on the substrate; 2) sequentially forming a first gate electrode and a first gate dielectric layer on the buffer layer; 3) Preparing an ITO channel and source / drain electrodes at both ends of the ITO channel on the first gate dielectric layer; 4) growing a second gate dielectric layer on the ITO channel and the source and drain electrodes at both ends; 5) forming windows in the second gate dielectric layer and the first gate dielectric layer by photolithography and etching, and then preparing a second gate electrode so that the second gate electrode and the first gate electrode are connected to each other through the window; 6) growing a third gate dielectric layer on the second gate electrode, and forming windows connecting the upper and lower source electrodes or drain electrodes in the third gate dielectric layer and the second gate dielectric layer by photolithography and etching; 7) Transferring the two-dimensional material to a designated area on the third gate dielectric layer as a channel, and preparing source and drain electrodes at both ends thereof, wherein the source electrode or drain electrode is connected to the underlying source electrode or drain electrode through the window prepared in step 6); 8) growing a fourth gate dielectric layer on the two-dimensional material channel and the source and drain electrodes at both ends; 9) Forming windows in the fourth gate dielectric layer and the third gate dielectric layer by photolithography and etching, and then preparing a third gate electrode, so that the third gate electrode and the second gate electrode are connected to each other through the windows.

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