ESD protection devices

Abstract

The present invention discloses an electrostatic protection device, which is formed by LDMOS, and the LDMOS includes: a first high-voltage well region doped with a second conductive type and a second high-voltage well region doped with a first conductive type; a gate structure covers the surface of a selected area of ​​the first high-voltage well region and extends above the surface of the second high-voltage well region; a source region is formed in the surface region of the first high-voltage well region outside the first side of the gate structure; a first diffusion region heavily doped with the second conductive type is also formed in the surface region of the first high-voltage well region between the second side of the source region and the first side of the gate structure; a drain region is formed in the second high-voltage well region outside the second side of the gate structure; the first diffusion region is a floating structure; a parasitic triode is formed by the source region, the first high-voltage well region including the first diffusion region, the second high-voltage well region and the drain region, and the first diffusion region is used to increase the width and concentration of the base region of the parasitic triode. The present invention can improve the holding voltage of the LDMOS after snapback occurs.

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit, and in particular to an electrostatic discharge (ESD) device. Background Art

[0002] like Figure 1 As shown, it is an application circuit diagram of an electrostatic protection device; the electrostatic protection device 102 is arranged between the input and output pads 101 and the ground. When static electricity appears in the input and output pads 101, the electrostatic protection device 102 is triggered and discharges the static electricity, thereby protecting the internal circuit 103.

[0003] Conventional high-voltage ESD devices generally use LDMOS. Figure 2 , which is a schematic diagram of the cross-sectional structure of an existing electrostatic protection device; Figure 2 The circuit 102 shown adopts a high-voltage LDMOS structure, and a body region 202 composed of a high-voltage well region of the second conductivity type and a drift region 203 composed of a high-voltage well region of the first conductivity type are formed on a semiconductor substrate such as a silicon substrate 201. A gate dielectric layer such as a gate oxide layer 204 and a polysilicon gate 205 cover the surface of the body region 202 and extend to the surface of the drift region 203. The source region 206 composed of the heavily doped region of the first conductivity type formed in the body region 202 and the first side of the polysilicon gate 205 are self-aligned, and the heavily doped region of the second conductivity type formed in the body region 202 constitutes a body region lead-out region 208, and a field oxide layer 209b is separated between the source region 206 and the body region lead-out region 208. A drain region 207 composed of a heavily doped region of the first conductivity type is formed in the drift region 203, and the drain region 207 and the polysilicon gate 205 are separated by a certain distance and a field oxide layer 209a. The field oxide layer 209c is formed outside the second side of the drain region 207. The source region 206, the body region lead-out region 208 and the polysilicon gate 205 are all connected to the source, the resistor R101 is connected between the polysilicon gate 205 and the source, and the drain region 207 is connected to the drain.

[0004] Figure 2 The LDMOS shown can be a P-type LDMOS. In this case, the first conductivity type is P-type, and the second conductivity type is N-type; the source is connected to the electrostatic terminal, and the drain is grounded.

[0005] Figure 2 The LDMOS shown can also be an N-type LDMOS. In this case, the first conductivity type is N-type, and the second conductivity type is P-type; the source is grounded, and the drain is connected to the electrostatic terminal.

[0006] Generally, the ESD capability of LDMOS itself is relatively weak. In order to improve the ESD capability and design flexibility, some deformations are usually made based on LDMOS, such as inserting the drain end of P-type LDMOS into the N+ region to form a parasitic thyristor (SCR) structure, which can greatly improve the ESD protection capability. However, the maintenance voltage (Vh) of the pure SCR structure after snapback generally does not exceed 10V, and there is a greater risk of latchup in high-voltage port applications, that is, when the power supply voltage of the high-voltage port is greater than the maintenance voltage of the SCR, latchup effect is likely to occur. Summary of the invention

[0007] The technical problem to be solved by the present invention is to provide an electrostatic protection device which can be formed by using LDMOS and can improve the maintenance voltage of LDMOS after snapback occurs, thereby reducing the risk of latch-up effect in high-voltage port applications.

[0008] In order to solve the above technical problems, the electrostatic protection device provided by the present invention is formed by LDMOS, and the LDMOS includes:

[0009] A first high-voltage well region doped with the second conductivity type and a second high-voltage well region doped with the first conductivity type are provided; the first high-voltage well region and the second high-voltage well region are both formed in a semiconductor substrate.

[0010] The gate structure covers the surface of a selected area of ​​the first high-voltage well region and extends above the surface of the second high-voltage well region. The surface of the first high-voltage well region covered by the gate structure is used to form a conductive channel.

[0011] A heavily doped source region of the first conductivity type is formed in a surface region of the first high-voltage well region outside the first side surface of the gate structure.

[0012] A first diffusion region heavily doped with a second conductivity type is also formed in a surface area of ​​the first high-voltage well region between the second side surface of the source region and the first side surface of the gate structure.

[0013] A body region lead-out region heavily doped with the second conductivity type is also formed in the surface area of ​​the first high-voltage well region outside the first side surface of the source region.

[0014] A drain region heavily doped with the first conductivity type is formed in the second high-voltage well region outside the second side surface of the gate structure.

[0015] The source region, the body region lead-out region and the gate structure are all connected to a source electrode composed of a front metal layer.

[0016] The drain region is connected to a drain electrode formed by a front metal layer.

[0017] The first diffusion region is a floating structure.

[0018] A parasitic transistor is formed by the source region, the first high-voltage well region including the first diffusion region, the second high-voltage well region and the drain region. The first high-voltage well region serves as a base region of the parasitic transistor. The first diffusion region is used to increase the width and concentration of the base region, thereby reducing the Beta coefficient of the parasitic transistor and thereby increasing the maintenance voltage of the LDMOS after snapback occurs.

[0019] A further improvement is that the LDMOS includes an N-type LDMOS, in which the first conductivity type is N-type, the second conductivity type is P-type, the source is connected to the ground, and the drain is connected to the electrostatic terminal.

[0020] A further improvement is that the LDMOS includes a P-type LDMOS, in which the first conductivity type is P-type, the second conductivity type is N-type, the source is connected to the electrostatic terminal, and the drain is connected to the ground.

[0021] A further improvement is that the semiconductor substrate comprises a silicon substrate.

[0022] A further improvement is that the semiconductor substrate is N-type doped or P-type doped.

[0023] A further improvement is that a first epitaxial layer is formed on the surface of the semiconductor substrate, and the first high-voltage well region and the second high-voltage well region are both formed in the first epitaxial layer.

[0024] A further improvement is that the first epitaxial layer is N-type doped or P-type doped.

[0025] A further improvement is that the second side surface of the first high-voltage well region is in contact with or not in contact with the first side surface of the second high-voltage well region.

[0026] A further improvement is that a buried layer is formed at the bottom of the first high-voltage well region and the second high-voltage well region, and the buried layer is N-type doped or P-type doped.

[0027] A further improvement is that a drift region field oxide is also formed in the second high-voltage well region, and the second side surface of the gate structure extends to the surface of the drift region field oxide.

[0028] A further improvement is that the gate structure is formed by stacking a gate dielectric layer and a polysilicon gate.

[0029] A further improvement is that a second field oxygen is formed between the body region lead-out region and the source region.

[0030] A further improvement is that the first side surface of the first diffusion region is in contact with or not in contact with the second side surface of the source region.

[0031] A further improvement is that the second side surface of the first diffusion region and the first side surface of the gate structure are self-aligned or spaced apart.

[0032] A further improvement is that a second injection region doped with a second conductive type is formed in the first high-voltage well region, the second injection region covers the first diffusion region, the doping concentration of the second injection region is greater than the doping concentration of the first high-voltage well region, the doping concentration of the first diffusion region is greater than the doping concentration of the second injection region, and the second injection region further increases the width and concentration of the base region.

[0033] A further improvement is that the second implantation region also extends into the bottom region of the gate structure.

[0034] A further improvement is that, in a top view, the gate structure, the first diffusion region, the source region, the body region lead-out region and the drain region are all in a strip-shaped structure.

[0035] In the present invention, in the LDMOS as an electrostatic protection device, a first diffusion region formed in the first high-voltage well region, i.e., the body region, is arranged between the source region and the gate structure. The doping type of the first diffusion region is the same as that of the first high-voltage well region. The first high-voltage well region serves as the base region in the parasitic triode formed by the source region, the first high-voltage well region, the second high-voltage well region, and the drain region of the LDMOS. The insertion of the first diffusion region not only increases the width of the base region, but also increases the second conductive type doping concentration of the base region. In the triode, the larger the width of the base region and the higher the doping concentration, the lower the Beta coefficient, i.e., the β coefficient. The Beta coefficient is an amplification coefficient formed by the ratio of the collector current to the base current. A reduction in the Beta coefficient increases the holding voltage of the LDMOS after a snapback occurs, thereby reducing the risk of a latch-up effect in high-voltage port applications.

[0036] The present invention can increase the sustaining voltage of LDMOS after snapback occurs by inserting a first diffusion region between a source region and a gate structure. The first diffusion region can be realized by changing the layout, and the area and concentration of the first diffusion region can be easily adjusted. By adjusting the area and concentration of the first diffusion region, it is easy to adjust the sustaining voltage of LDMOS after snapback occurs; for example, by increasing the area or concentration of the first diffusion region, the sustaining voltage of LDMOS after snapback occurs can be increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0038] Figure 1 It is the application circuit diagram of the electrostatic protection device;

[0039] Figure 2 It is a schematic diagram of the cross-sectional structure of an existing electrostatic protection device;

[0040] Figure 3 is a schematic cross-sectional structure diagram of an electrostatic protection device according to a first embodiment of the present invention;

[0041] Figure 4 is a layout diagram of an electrostatic protection device according to a first embodiment of the present invention;

[0042] Figure 5 FIG. 4 is a schematic cross-sectional structure diagram of an electrostatic protection device according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0043] like Figure 3 , which is a schematic cross-sectional structure diagram of an electrostatic protection device according to a first embodiment of the present invention; Figure 4 FIG. 1 is a layout diagram of an electrostatic protection device according to a first embodiment of the present invention; the electrostatic protection device according to the present invention is formed by LDMOS, and the LDMOS includes:

[0044] A first high-voltage well region 302 doped with the second conductivity type and a second high-voltage well region 303 doped with the first conductivity type are formed in a semiconductor substrate 301 .

[0045] In the first embodiment of the present invention, the semiconductor substrate 301 includes a silicon substrate.

[0046] The semiconductor substrate 301 is doped with a P type. In other embodiments, the semiconductor substrate 301 may be doped with an N type.

[0047] In some embodiments, a first epitaxial layer is formed on the surface of the semiconductor substrate 301 , and the first high-voltage well region 302 and the second high-voltage well region 303 are both formed in the first epitaxial layer.

[0048] The first epitaxial layer is N-type doped or P-type doped.

[0049] In some embodiments, a buried layer may be formed at the bottom of the first high-voltage well region 302 and the second high-voltage well region 303 , and the buried layer may be N-type doped or P-type doped.

[0050] The second side surface of the first high-voltage well region 302 contacts the first side surface of the second high-voltage well region 303. In other embodiments, the second side surface of the first high-voltage well region 302 and the first side surface of the second high-voltage well region 303 may not contact each other.

[0051] Depend on Figure 3 As shown, the body region is formed by the first high-voltage well region 302 , and the drift region is formed by the second high-voltage well region 303 .

[0052] The gate structure covers the surface of the selected area of ​​the first high-voltage well region 302 and extends above the surface of the second high-voltage well region 303. The surface of the first high-voltage well region 302 covered by the gate structure is used to form a conductive channel. A source region 306 heavily doped with the first conductivity type is formed in the surface area of ​​the first high-voltage well region 302 outside the first side surface of the gate structure.

[0053] In the first embodiment of the present invention, a drift region field oxide 310 a is further formed in the second high-voltage well region 303 , and the second side surface of the gate structure extends to the surface of the drift region field oxide 310 a .

[0054] The gate structure is formed by stacking a gate dielectric layer 304 and a polysilicon gate 305 .

[0055] A second field oxide 310 b is formed between the body lead-out region 308 and the source region 306 .

[0056] A first diffusion region 309 heavily doped with the second conductivity type is further formed in the surface area of ​​the first high-voltage well region 302 between the second side surface of the source region 306 and the first side surface of the gate structure.

[0057] In the first embodiment of the present invention, the first side surface of the first diffusion region 309 contacts the second side surface of the source region 306. In other embodiments, the first side surface of the first diffusion region 309 and the second side surface of the source region 306 may not contact each other.

[0058] In the first embodiment of the present invention, the second side of the first diffusion region 309 and the first side of the polysilicon gate 305 of the gate structure are self-aligned. In other embodiments, the second side of the first diffusion region 309 and the first side of the gate structure may be spaced apart.

[0059] A second conductive type heavily doped body region lead-out region 308 is further formed in a surface region of the first high-voltage well region 302 outside the first side surface of the source region 306 .

[0060] A drain region 307 heavily doped with the first conductivity type is formed in the second high-voltage well region 303 outside the second side surface of the gate structure. A field oxide 310 c is formed outside the second side of the drain region 307 .

[0061] The source region 306, the body region lead-out region 308 and the gate structure are all connected to the source electrode formed by the front metal layer. Figure 4 As shown, the source region 306, the body region lead-out region 308 and the top of the polysilicon gate 305 of the gate structure are all connected to the source through corresponding contact holes 311. The resistor R201 is connected between the polysilicon gate 305 and the source.

[0062] The drain region 307 is connected to the drain electrode formed by the front metal layer. The top of the drain region 307 is connected to the drain electrode through a corresponding contact hole 311.

[0063] The first diffusion region 309 is a floating structure.

[0064] In the first embodiment of the present invention, Figure 4 As shown, in a top view, the gate structure, the first diffusion region 309, the source region 306, the body region lead-out region 308 and the drain region 307 are all in a strip-shaped structure.

[0065] A parasitic transistor is formed by the source region 306, the first high-voltage well region 302 including the first diffusion region 309, the second high-voltage well region 303 and the drain region 307. The first high-voltage well region 302 serves as a base region of the parasitic transistor, and the first diffusion region 309 is used to increase the width and concentration of the base region, thereby reducing the Beta coefficient of the parasitic transistor and thereby increasing the maintenance voltage of the LDMOS after a snapback occurs.

[0066] In the first embodiment of the present invention, the LDMOS includes an N-type LDMOS, in which the first conductivity type is N-type, the second conductivity type is P-type, the source is connected to the ground, and the drain is connected to the electrostatic terminal.

[0067] Alternatively, the LDMOS may include a P-type LDMOS, in which the first conductivity type is P-type, the second conductivity type is N-type, the source is connected to an electrostatic terminal, and the drain is connected to a ground.

[0068] In the first embodiment of the present invention, in the LDMOS as an electrostatic protection device, a first diffusion region 309 formed in the first high-voltage well region 302, i.e., the body region, is provided between the source region 306 and the gate structure. The doping type of the first diffusion region 309 is the same as that of the first high-voltage well region 302. The first high-voltage well region 302 serves as a base region in a parasitic triode formed by the source region 306, the first high-voltage well region 302, the second high-voltage well region 303, and the drain region 307 of the LDMOS. The insertion of the first diffusion region 309 not only increases the width of the base region, but also increases the second conductive type doping concentration of the base region. In the triode, the larger the width of the base region and the higher the doping concentration, the lower the Beta coefficient, i.e., the β coefficient. The Beta coefficient is an amplification coefficient formed by the ratio of the collector current to the base current. A reduction in the Beta coefficient increases the holding voltage of the LDMOS after a snapback occurs, thereby reducing the risk of latch-up in high-voltage port applications.

[0069] The first embodiment of the present invention can increase the sustaining voltage of LDMOS after a snap back occurs by inserting a first diffusion region 309 between the source region 306 and the gate structure. The first diffusion region 309 can be realized by changing the layout, and it is easy to adjust the area and concentration of the first diffusion region 309. By adjusting the area and concentration of the first diffusion region 309, it is easy to adjust the sustaining voltage of LDMOS after a snap back occurs; for example, by increasing the area or concentration of the first diffusion region 309, the sustaining voltage of LDMOS after a snap back occurs can be increased.

[0070] like Figure 5 FIG. 1 is a schematic diagram of the cross-sectional structure of the electrostatic protection device of the second embodiment of the present invention; the difference between the electrostatic protection device of the second embodiment of the present invention and the electrostatic protection device of the first embodiment of the present invention is that the electrostatic protection device of the second embodiment of the present invention also includes the following features:

[0071] A second injection region 401 doped with a second conductive type is also formed in the first high-voltage well region 302. The second injection region 401 covers the first diffusion region 309. The doping concentration of the second injection region 401 is greater than the doping concentration of the first high-voltage well region 302. The doping concentration of the first diffusion region 309 is greater than the doping concentration of the second injection region 401. The second injection region 401 further increases the width and concentration of the base region.

[0072] The second implantation region 401 also extends into the bottom region of the gate structure.

[0073] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. An electrostatic protection device, characterized in that: The electrostatic protection device is formed by LDMOS, and the LDMOS includes: A first high-voltage well region doped with a second conductivity type and a second high-voltage well region doped with a first conductivity type; the first high-voltage well region and the second high-voltage well region are both formed in a semiconductor substrate; A gate structure covers a surface of a selected area of ​​the first high-voltage well region and extends above a surface of the second high-voltage well region, and the surface of the first high-voltage well region covered by the gate structure is used to form a conductive channel; A heavily doped source region of the first conductivity type is formed in a surface region of the first high-voltage well region outside the first side surface of the gate structure; A first diffusion region heavily doped with a second conductivity type is also formed in a surface area of ​​the first high-voltage well region between the second side surface of the source region and the first side surface of the gate structure; A second conductive type heavily doped body region lead-out region is also formed in the surface region of the first high-voltage well region outside the first side surface of the source region; A drain region heavily doped with a first conductivity type is formed in the second high-voltage well region outside the second side surface of the gate structure; The source region, the body region lead-out region and the gate structure are all connected to a source electrode composed of a front metal layer; The drain region is connected to a drain electrode composed of a front metal layer; The first diffusion region is a floating structure; A parasitic transistor is formed by the source region, the first high-voltage well region including the first diffusion region, the second high-voltage well region and the drain region. The first high-voltage well region serves as a base region of the parasitic transistor. The first diffusion region is used to increase the width and concentration of the base region, thereby reducing the Beta coefficient of the parasitic transistor and thereby increasing the maintenance voltage of the LDMOS after snapback occurs.

2. The electrostatic protection device according to claim 1, characterized in that: The LDMOS includes an N-type LDMOS, in which the first conductivity type is N-type, the second conductivity type is P-type, the source is connected to the ground, and the drain is connected to the electrostatic terminal.

3. The electrostatic protection device according to claim 1, characterized in that: The LDMOS includes a P-type LDMOS, in which the first conductivity type is P-type, the second conductivity type is N-type, the source is connected to the electrostatic terminal, and the drain is connected to the ground.

4. The electrostatic protection device according to claim 1, characterized in that: The semiconductor substrate includes a silicon substrate.

5. The electrostatic protection device according to claim 4, characterized in that: The semiconductor substrate is N-type doped or P-type doped.

6. The electrostatic protection device according to claim 4, characterized in that: A first epitaxial layer is also formed on the surface of the semiconductor substrate, and the first high-voltage well region and the second high-voltage well region are both formed in the first epitaxial layer.

7. The electrostatic protection device according to claim 6, characterized in that: The first epitaxial layer is N-type doped or P-type doped.

8. The electrostatic protection device according to claim 1, characterized in that: The second side surface of the first high-voltage well region is in contact with or not in contact with the first side surface of the second high-voltage well region.

9. The electrostatic protection device according to claim 1, characterized in that: A buried layer is formed at the bottom of the first high-voltage well region and the second high-voltage well region, and the buried layer is N-type doped or P-type doped.

10. The electrostatic protection device according to claim 1, characterized in that: A drift region field oxide is also formed in the second high-voltage well region, and the second side surface of the gate structure extends to a surface of the drift region field oxide.

11. The electrostatic protection device according to claim 10, characterized in that: The gate structure is formed by stacking a gate dielectric layer and a polysilicon gate.

12. The electrostatic protection device according to claim 1, characterized in that: A second field oxygen is formed between the body region lead-out region and the source region.

13. The electrostatic protection device according to claim 1, characterized in that: The first side surface of the first diffusion region is in contact with or not in contact with the second side surface of the source region.

14. The electrostatic protection device according to claim 13, characterized in that: The second side surface of the first diffusion region and the first side surface of the gate structure are self-aligned or spaced apart from each other.

15. The electrostatic protection device according to claim 13, characterized in that: A second injection region doped with a second conductive type is also formed in the first high-voltage well region. The second injection region covers the first diffusion region. The doping concentration of the second injection region is greater than the doping concentration of the first high-voltage well region. The doping concentration of the first diffusion region is greater than the doping concentration of the second injection region. The second injection region further increases the width and concentration of the base region.

16. The electrostatic protection device according to claim 15, characterized in that: The second implant region also extends into a bottom region of the gate structure.

17. The electrostatic protection device according to claim 1, characterized in that: In a top view, the gate structure, the first diffusion region, the source region, the body region lead-out region and the drain region are all in a strip-shaped structure.

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