Non-planar semiconductor device having a omega-shaped fin with a doped sub-fin region and method of manufacturing the same

Abstract

Describes a non-planar semiconductor device having ω-shaped fins and a method of manufacturing a non-planar semiconductor device having ω-shaped fins, the ω-shaped fins having doped sub-fin regions. For example, a semiconductor device includes a plurality of semiconductor fins disposed on a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion being narrower than the protruding portion. A solid-state dopant source layer is disposed on the semiconductor substrate, conformal with the sub-fin regions of each of the plurality of semiconductor fins but not conformal with the protruding portions. An isolation layer is disposed on the solid-state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed on the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.

Description

[0001] This application is a divisional application, and its original application is the international patent application PCT / US2014 / 044433 that entered the Chinese national stage on November 25, 2016, with an international filing date of June 26, 2014. The Chinese national application number of this original application is 201480079228.2, and the invention title is "Non-planar semiconductor device having omega-fins with doped sub-fin regions and method of manufacturing the same". Technical Field

[0002] Embodiments of the present invention pertain to the field of semiconductor devices and processing, and more particularly, to non-planar semiconductor devices and methods of manufacturing non-planar semiconductor devices having omega-fins with doped sub-fin regions. Background Art

[0003] In the past few decades, the scaling down of features in integrated circuits has been the driving force behind the growing semiconductor industry. Scaling down to ever-smaller features enables an increased density of functional units on the limited substrate area of a semiconductor chip. For example, shrinking the size of transistors allows for a greater number of memory or logic devices to be included on a chip, resulting in the manufacture of products with increased capacity. However, the drive for ever-increasing capacity is not without problems. The need to optimize the performance of each device has become increasingly important.

[0004] In the fabrication of integrated circuit devices, multi-gate transistors (e.g., tri-gate transistors) have become more prevalent as device dimensions continue to shrink. In conventional processes, tri-gate transistors are typically fabricated on a bulk silicon substrate or a silicon-on-insulator substrate. In some instances, a bulk silicon substrate is preferred due to its lower cost and compatibility with existing high-yield bulk silicon substrate infrastructure.

[0005] However, scaling down multi-gate transistors is not without consequences. As the dimensions of these basic building blocks of microelectronic circuits decrease, and as the absolute number of basic building blocks fabricated in a given area increases, the constraints on the semiconductor processes used to fabricate these building blocks have become very significant. Brief Description of the Drawings

[0006] Figure 1A is a cross-sectional view of a portion of a non-planar semiconductor device having a doped sub-fin region that tapers outwardly.

[0007] Figure 1B is a cross-sectional view of a portion of a non-planar semiconductor device having omega-fins with a doped sub-fin region in accordance with an embodiment of the present invention.

[0008] Figures 2A - 2I Illustrates cross-sectional views of respective operations in a method of manufacturing a non-planar semiconductor device having omega-shaped fins according to an embodiment of the present invention, the omega-shaped fins having doped sub-fin regions, wherein:

[0009] Figure 2A Illustrates a bulk semiconductor substrate having fins etched therein and a catalyst layer conformally formed therewith;

[0010] Figure 2B Illustrates after forming a mask on and over a plurality of fins Figure 2A the structure;

[0011] Figure 2C Illustrates after recessing the mask to form a recessed mask Figure 2B the structure;

[0012] Figure 2D Illustrates after removing the exposed portions of the catalyst layer Figure 2C the structure;

[0013] Figure 2E Illustrates the structure of FIG. 2D after removing the recessed mask to expose the patterned catalyst layer;

[0014] Figure 2F Illustrates after catalytic oxidation of the sub-fin regions Figure 2E the structure;

[0015] Figure 2G Illustrates the structure of FIG. 2F after removing the patterned catalyst layer and the formed oxide layer;

[0016] Figure 2H Illustrates after forming a solid-state dopant source layer and an optional overlying layer Figure 2G the structure;

[0017] Figure 2I Illustrates after patterning the solid-state dopant source layer and the optional overlying layer Figure 2H the structure.

[0018] Figure 3A Illustrates a cross-sectional view of a non-planar semiconductor device having omega-shaped fins according to an embodiment of the present invention, the omega-shaped fins having doped sub-fin regions.

[0019] Figure 3B Illustrates according to an embodiment of the present invention along Figure 3A a plan view of the semiconductor device taken along the a-a' axis.

[0020] Figure 4An exemplary computing device in accordance with one embodiment of the present invention is illustrated. Detailed Description

[0021] A non-planar semiconductor device having omega-shaped fins and a method of fabricating a non-planar semiconductor device having omega-shaped fins are described, the omega-shaped fins having doped sub-fin regions. In the following description, numerous specific details are set forth, such as particular integration and material conditions, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to those skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features such as integrated circuit design layouts are not described in detail so as not to unnecessarily obscure embodiments of the present invention. Further, it is to be understood that the various embodiments shown in the figures are illustrative representations and not necessarily drawn to scale.

[0022] One or more embodiments described herein are directed to a scheme for fabricating omega-shaped fins for enhanced sub-fin doping. Applications may include, but are not limited to, process technology nodes below 10 nm. In one or more embodiments, both solid-state sub-fin doping source technology and catalytic oxidation technology of the sub-fin region are used in semiconductor device fabrication.

[0023] Specifically, one or more embodiments described herein provide a scheme for fabricating an omega-shaped fin structure. For technology nodes below, for example, 10 nm, such an omega-shaped fin structure can facilitate enhanced sub-fin doping in closely spaced fins. Sub-fin doping can be achieved by depositing boron or phosphorus doped oxide (BSG / PSG) and subsequently depositing a SiN layer thereover. An annealing process is used to drive dopants from the BSG or PSG layer into the sub-fin. The degree of doping into the sub-fin is directly related to the thickness of the BSG or PSG layer. Additionally, a minimum thickness of SiN may be required to drive dopants into the sub-fin rather than having the dopants escape into the space between the fins. However, the combination of the required minimum BSG / PSG and SiN thicknesses can make it difficult to achieve sub-doping because the fin pitch is reduced. Although the fin pitch can be scaled, the BSG / PSG and SiN thicknesses may not scale proportionally, presenting a challenge. The embodiments described herein provide for the fabrication of sub-fins having a reduced width relative to the active (projecting) fin portion, thereby creating omega-shaped fins. In one such embodiment, even after reducing the fin pitch, the fabrication of omega-shaped fins provides additional space in the sub-fin region for depositing the required BSG / PSG or SiN layer thicknesses.

[0024] To provide a reference point for some of the concepts involved herein, Figure 1ACross-sectional view of a portion of a non-planar semiconductor device having a doped sub-fin region that tapers outwardly. Refer to Figure 1A , a bulk silicon substrate 100 having fins 102 etched therein is provided. The fins 102 are formed directly in the bulk substrate 100 and thus are formed continuously with the bulk substrate 100. Each fin 102 can be described as having a sub-fin region 102A and a protrusion 102B. The protrusion 102B is the portion on which the gate electrode is ultimately formed. As Figure 1A shown, each sub-fin region 102A tapers outwardly. A solid-state dopant source layer 120 and an optional capping layer 122 are confined to the sub-fin region 102A. The solid-state dopant source layer 120 can ultimately be used to dope the sub-fin region 102A. As described above, at least in part due to the outward taper of the sub-fin region 102A, the lower portions of the fins 102 and thus the solid-state dopant source layer 120 and the optional capping layer 122 are in close proximity to each other, making scaling of such features very difficult.

[0025] To provide further context, solutions that have been implemented to address scaling challenges involve one or more of the following: (a) increasing the dopant concentration in the solid-state dopant source layer (e.g., in BSG / PSG) or (b) increasing the density of the capping layer (e.g., SiN) to prevent dopant "leakage" into the space between the fins. Generally, the embodiments described herein achieve creating space in the sub-fin region to facilitate deposition of the required BSG / PSG and SiN films. In one such embodiment, a process for creating space in the sub-fin region is achieved by selective catalytic oxidation, as described in more detail below.

[0026] Thus, compared to Figure 1A Figure 1B is a cross-sectional view of a portion of a non-planar semiconductor device having omega-shaped fins with a doped sub-fin region, according to an embodiment of the present invention. Refer to Figure 1B , a bulk silicon substrate 150 having omega-shaped fins 152 etched therein is provided. The omega-shaped fins 152 are formed directly in the bulk substrate 150 and thus are formed continuously with the bulk substrate 150. Each omega-shaped fin 152 can be described as having a sub-fin region 152A and a protrusion 152B. The protrusion 152B is the portion on which the gate electrode is ultimately formed. As Figure 1BAs shown, each sub-fin region 152A is narrower than the corresponding protrusion 152B. The solid-state dopant source layer 120 and the optional overcoat layer 122 are confined to the sub-fin region 152A. The solid-state dopant source layer 120 can ultimately be used to dope the sub-fin region 152A. As described above, at least in part due to the omega-shaped fin geometry, the lower portion of the omega-shaped fin 152 and thus the solid-state dopant source layer 120 and the optional overcoat layer 122 are not relatively close to each other, making the scaling of such features feasible.

[0027] In a particular embodiment, the process flow for generating an omega-shaped fin structure includes using an oxidation catalyst layer deposited by atomic layer deposition (ALD) to provide a catalyst on all exposed surfaces of the fin. However, the catalyst may only be needed in the sub-fin regions of a plurality of semiconductor fins. Thus, a process is described below that protects the catalyst in the sub-fin regions while removing the catalyst from the active fin regions. In one embodiment, this is achieved by filling the spaces between the fins with a carbon hard mask (CHM) after catalyst deposition. The CHM is then recessed to a desired depth using, for example, dry etching techniques. Once the CHM is recessed, the exposed catalyst in the active fin regions is removed, for example, by a wet etching process. The CHM remaining in the spaces in the sub-fin regions can be removed by ashing techniques, leaving the exposed catalyst in the sub-fin regions. At this stage, low-pressure oxidation can be used to oxidize the silicon in the sub-fin regions. The presence of the catalyst in the sub-fin regions causes the oxidation to be approximately 10 - 15 times faster than in the active fin regions where the catalyst has been previously removed. After performing the oxidation, the catalyst and the oxide can be removed by wet etching to produce the omega-shaped fin structure.

[0028] In an exemplary process scenario, Figures 2A - 2I A cross-sectional view illustrating the various operations in a method of manufacturing a non-planar semiconductor device having omega-shaped fins in accordance with an embodiment of the present invention, the omega-shaped fins having doped sub-fin regions.

[0029] Referring to Figure 2A , a bulk semiconductor substrate 200 having fins 202 etched therein, such as a bulk single-crystalline silicon substrate, is provided.

[0030] In an embodiment, the fin is directly formed in the bulk substrate 200 and thus is formed continuously with the bulk substrate 200. There may also be fabrication artifacts remaining due to the fabrication of the fin 202. For example, although not shown, a hard mask layer (e.g., a silicon nitride hard mask layer) and a pad oxide layer (e.g., a silicon dioxide layer) may remain on top of the fin 202. In one embodiment, the bulk substrate 200 and thus the fin 202 are undoped or lightly doped at this stage. For example, in a particular embodiment, the bulk substrate 200 and thus the fin 202 have a concentration of boron dopant impurity atoms of less than about 1E17 atoms / cm 3 . In addition, each fin 202 can be described as having a sub-fin region 202A and a protrusion 202B. The protrusion 202B is the portion on which the gate electrode is ultimately formed. At this stage, due to the etching process used to form the fin 202, each sub-fin region 202A may be tapered outwardly, as Figure 2A shown.

[0031] Referring again to Figure 2A , the catalyst layer 204 is conformally formed with the substrate 200 / fin 202 structure. In an embodiment, the catalyst layer is an aluminum oxide (Al 2 O 3 ) layer. It should be appreciated that if present, the hard mask layer and / or the pad oxide layer may remain on top of the fin 202 at this stage. However, as shown, this hard mask layer and / or pad oxide layer used to form the fin has been removed prior to forming the catalyst layer 204, as Figure 2A shown.

[0032] Referring to Figure 2B , the mask 206 is formed on the Figure 2A structure.

[0033] In an embodiment, the mask 206 is formed to a height sufficient to completely cover the fin 202. The hard mask may be formed to have a substantially flat top surface or may be subjected to a planarization process such as chemical mechanical planarization (CMP). In one embodiment, the mask 206 is a carbon hard mask (CHM) material layer or includes a carbon hard mask (CHM) material layer.

[0034] Referring to Figure 2C , Figure 2B the mask 206 is recessed to a height below the top of the fin 202, forming a recessed mask 208.

[0035] In an embodiment, the recessed mask 208 is formed to a level substantially coplanar with the top of the sub-fin region 202A, exposing portions of the protrusion 202B and the catalyst layer 204, as Figure 2CAs shown. In an embodiment, the recess of the mask 206 is performed by an etching process to form a recessed mask 208, and the etching process is, for example, but not limited to, plasma, gas phase, ashing or wet etching process or a combination thereof. In one embodiment, the mask 206 is a carbon hard mask layer, and an oxygen-based ashing process is used to recess the mask 206.

[0036] Reference Figure 2D , the exposed portions of the catalyst layer 204 are removed to provide a patterned catalyst layer 210, and the patterned catalyst layer 210 is confined to the area protected by the recessed mask 208.

[0037] In one such embodiment, the patterned catalyst layer 210 is confined to the sub-fin region 202A, as Figure 2D shown. In an embodiment, a wet etching process is used to perform the removal of the exposed portions of the catalyst layer 204 to form a patterned catalyst layer 210. In one such embodiment, the catalyst layer is Al 2 O 3 layer or includes Al 2 O 3 layer, and the wet etching process is based on hydrofluoric acid (HF). In an embodiment, as Figure 2D shown, the wet etching process is selective to the recessed mask 208.

[0038] Reference Figure 2E , the recessed mask 208 is completely removed, exposing the patterned catalyst layer 210.

[0039] In an embodiment, the removal of the recessed mask 208 is performed by an etching process, and the etching process is, for example, but not limited to, plasma, gas phase, ashing or wet etching process or a combination thereof. In one embodiment, the recessed mask 208 is a carbon hard mask layer, and it is removed using an oxygen-based ashing process. In an embodiment, a process selective to the patterned catalyst layer 210 is used to perform the removal of the recessed mask 208, retaining the patterned catalyst layer 210, as shown in FIG. 2E.

[0040] Reference Figure 2F , the sub-fin region 202A of the plurality of fins 202 is oxidized using the patterned catalyst layer 210.

[0041] In an embodiment, the patterned catalyst layer 210 is exposed to a composition of hydrogen and oxygen (H 2 / O 2)to perform oxidation. During the oxidation process, in the region of the fin 202 having the patterned catalyst layer 210 thereon (i.e., the sub-fin region 202A), the patterned catalyst layer 210 accelerates the oxidation of the underlying / adjacent silicon, which is about 10 - 15 times faster than the oxidation of the other parts of the silicon fin (i.e., due to the presence of the patterned catalyst layer 210, the oxidation rate of the sub-fin region 202A is about 10 - 15 times faster than the oxidation rate of the protruding fin portion 202B). Thus, this selective catalytic oxidation enables the relatively rapid conversion of the sub-fin region 202A into an oxide layer 212 (e.g., silicon oxide or silicon dioxide) without significantly oxidizing the protruding portion 202B of the fin 202. Thus, in one embodiment, the remaining silicon of the fin 202 provides a omega-shaped fin 214 having a sub-fin region 214A that is narrower than the overlying protruding fin portion 214B, as Figure 2F shown. It should be appreciated that at least some oxidation may occur on the protruding portion 202B of the fin 202; however, the degree of oxidation can be negligible compared to the sub-fin region 202A.

[0042] Refer to Figure 2G , the patterned catalyst layer 210 and the oxide layer 212 are removed to expose the sub-fin region 214A and the protruding region 214B of the omega-shaped fin 214.

[0043] In one such embodiment, the catalyst layer is an Al 2 O 3 layer or includes an Al 2 O 3 layer, the oxide layer 212 is a SiO 2 layer or includes a SiO 2 layer, and the wet etching process is based on hydrofluoric acid (HF). In a particular embodiment, the patterned catalyst layer 210 and the oxide layer 212 are removed in a single wet etching operation. However, in other embodiments, the patterned catalyst layer 210 and the oxide layer 212 are removed in successive wet etching operations.

[0044] Refer to Figure 2H , the solid-state dopant source layer 216 is conformally formed with the Figure 2G substrate 200 / omega-shaped fin 214 structure.

[0045] In a first embodiment, the solid-state dopant source layer 216 is a p-type solid-state dopant source layer composed of a dielectric layer, which contains p-type dopants such as (but not limited to) p-type doped oxide, nitride, or carbide layers. In a specific such embodiment, the p-type solid-state dopant source layer is a borosilicate glass layer. The p-type solid-state dopant source layer can be formed by a process suitable for providing a conformal layer on the omega-shaped fin 214. For example, in one embodiment, the p-type solid-state dopant source layer is formed as a conformal layer over the entire structure of Figure 2G by chemical vapor deposition (CVD) process or other deposition processes (such as ALD, PECVD, PVD, HDP-assisted CVD, low-temperature CVD). In a particular embodiment, the p-type solid-state dopant source layer is a BSG layer, which has a boron concentration in the range of approximately 0.1 - 10 wt%.

[0046] In a second embodiment, the solid-state dopant source layer 216 is an n-type solid-state dopant source layer composed of a dielectric layer, which contains n-type dopants such as (but not limited to) n-type doped oxide, nitride, or carbide layers. In a specific such embodiment, the n-type solid-state dopant source layer is a phosphosilicate glass layer or an arsenosilicate glass layer. The n-type solid-state dopant source layer can be formed by a process suitable for providing a conformal layer on the omega-shaped fin 214. For example, in one embodiment, the n-type solid-state dopant source layer is formed as a conformal layer over the entire structure of Figure 2G by chemical vapor deposition (CVD) process or other deposition processes (such as ALD, PECVD, PVD, HDP-assisted CVD, low-temperature CVD). In a particular embodiment, the n-type solid-state dopant source layer is a PSG layer or an AsSG layer, which has a phosphorus or arsenic concentration in the range of approximately 0.1 - 10 wt%, respectively.

[0047] In an embodiment, as also shown in Figure 2H a capping layer 218 may optionally be formed on the solid-state dopant source layer 216. In one such embodiment, the capping layer 218 is formed as an in-situ formed capping layer to protect the solid-state dopant source layer 216 during subsequent exposure to environmental conditions. In a specific embodiment, the capping layer is a nitride layer, such as a silicon nitride layer.

[0048] Referring to Figure 2I , the solid-state dopant source layer 216 and the capping layer 218 (if present) are patterned to form a patterned solid-state dopant source layer 220 and a patterned capping layer 222.

[0049] In an embodiment, the solid-state dopant source layer 216 and the capping layer 218 are patterned by a plasma, vapor, or wet etching process. The patterning of the solid-state dopant source layer 216 and the capping layer 218 may be performed in the same or different processing operations. Although not shown, in an embodiment, the patterning includes first forming a dielectric fill layer and then recessing it, the dielectric fill layer being formed over the structure of FIG. 2H. The dielectric fill layer may be recessed to expose the protruding portions 214B of the omega-shaped fins 214 while recessing to a height substantially the same as the height of the sub-fin regions 214A. The solid-state dopant source layer 216 and the capping layer 218 are simultaneously recessed sequentially to a level substantially the same as the dielectric fill layer. Thus, in one embodiment, the resulting patterned solid-state dopant source layer 220 is confined to the sub-fin regions 214A of the plurality of omega-shaped fins 214, as Figure 2I shown.

[0050] In an embodiment, after forming the patterned solid-state dopant source layer 220 and an optional patterned capping layer 222, a drive-in anneal is performed to provide the doped sub-fin regions 214A of the omega fins 214. Specifically, upon heating, dopant atoms such as boron, phosphorus, or arsenic dopant atoms from the patterned solid-state dopant source layer 220 diffuse into the sub-fin regions 214A. The diffusion may also result in doping within the bulk substrate portion 200, where adjacent fins 214 share a common doped region within the bulk substrate 200. In this manner, the protruding portions 214B of the omega-shaped fins 214 substantially retain the doping profile of Figure 2A the fins 202 and the original bulk substrate 200. As a result, a doping profile interface may exist between the protruding portions 214B and the doped sub-fin regions (now doped 214A). In one such embodiment, the interface represents a doping concentration step or a rapid gradient change, where the doped sub-fin regions have a total dopant concentration of 2E18 atoms / cm 3 or greater, while the protruding portions 214B have a total dopant concentration significantly less than 2E18 atoms / cm 3 e.g., having a total dopant concentration of about 5E17 atoms / cm 3 or less. In an embodiment, the doped sub-fin regions are doped across the entire sub-fin region. In an embodiment, the drive-in operation is performed at a temperature in the range of about 800 - 1050 degrees Celsius.

[0051] Accordingly, one or more embodiments described herein include using a solid source doping layer (e.g., BSG, PSG, or AsSG) deposited on fins after fin etching. Then, after trench filling and polishing, the doping layer is recessed with the trench fill material to define the fin height (HSi) of the device. This operation removes the doping layer from the fin sidewalls above HSi. Thus, the doping layer only exists along the fin sidewalls in the sub-fin region, which ensures precise control of the doping arrangement. After drive-in annealing, the high doping is confined to the sub-fin region and rapidly transitions to low doping in the adjacent region above HSi of the fin, which forms the channel region of the transistor.

[0052] Generally, referring again to Figures 2A - 2I , in an embodiment, borosilicate glass (BSG) is implemented for NMOS fin doping, while phosphosilicate (PSG) or arsenosilicate glass (AsSG) layers are implemented for PMOS fin doping. It should be appreciated that in an embodiment, a process scheme involving both NMOS fin doping and PMOS fin doping for different respective fins on a common substrate may add some integration complexity, but is fully within the spirit and scope of the embodiments of the present invention.

[0053] More generally referring to Figure 1A , Figure 1B and Figures 2A - 2I , one or more embodiments described herein are directed to a process that selectively dopes the sub-fin region of a triple-gate or FinFET transistor fabricated on a bulk silicon wafer, for example, by the out-diffusion of a triple-gated doped glass sub-fin. For example, the above is a process of selectively doping the sub-fin region of a triple-gate or FinFET transistor to mitigate sub-fin leakage while maintaining low doping in the fins. The incorporation of solid-state doping sources (e.g., p-type and n-type doped oxides, nitrides, or carbides) into the transistor process flow (after recessing from the fin sidewalls) transfers well doping into the sub-fin region while keeping the fin body relatively undoped. Additionally, in an embodiment, one or more schemes described herein achieve self-alignment of the doping boundary between the bottom of the active portion of the bulk fin and the active portion and the remaining bulk portion (e.g., the portion under the gate control region).

[0054] For example, it may be desirable to use bulk silicon for the fins or triple gates. However, there are concerns that the region (sub-fin) under the active silicon fin portion of the device (e.g., the gate control region or HSi) is under reduced gate control or no gate control. Thus, if the source or drain region is at or below the HSi point, there may be a leakage path through the sub-fin region. According to an embodiment of the present invention, to address the above problem, sufficient doping is provided through sub-fin doping without transferring the same degree of doping to the HSi portion of the fin.

[0055] To provide further context, conventional solutions to the above problem involve using well implantation operations, where the sub-fin region is heavily doped (e.g., much greater than 2E18 / cm 3 ), which turns off sub-fin leakage but also results in significant doping in the fin. The addition of halo implants further increases the fin doping such that the back-end process fin is doped at a high level (e.g., greater than about 1E18 / cm 3 ). In contrast, one or more embodiments described herein provide low doping in the fin, which can be beneficial because higher current drive is achieved by improving carrier mobility, which would otherwise be reduced due to ionized impurity scattering in highly doped channel devices. Additionally, since the random variation of the threshold voltage (Vt) is proportional to the square root of the doping density, low-doped devices also have the advantage of reducing the random mismatch in Vt. This enables the product to operate at a lower voltage without functional failures. At the same time, the region immediately under the fin (i.e., the sub-fin) must be highly doped to prevent sub-fin source-drain leakage. Conventional implantation steps for transferring this doping to the sub-fin region also heavily dope the fin region, making it impossible to achieve both low-doped fins and suppression of sub-fin leakage simultaneously.

[0056] It should be appreciated that the structures resulting from the above exemplary processing schemes (e.g., the structures in Figure 2I ) can be used in the same or similar form for subsequent processing operations to complete device fabrication (e.g., PMOS and NMOS device fabrication). As an example of a completed device, Figure 3A and Figure 3B respectively illustrate a cross-sectional view of a non-planar semiconductor device having omega-shaped fins and a plan view (taken along the a-a' axis of the cross-sectional view) according to an embodiment of the present invention, the omega-shaped fins having a doped sub-fin region.

[0057] Refer to Figure 3A, the semiconductor structure or device 300 includes a non-planar active region (e.g., a fin structure including a protruding fin portion 304 and a sub-fin region 305) formed by a substrate 302 and formed within an isolation region 306. According to an embodiment of the present invention, the sub-fin region 305 is narrower than the corresponding protruding portion 304, and thus provides a fin with a ω-shaped fin geometry. Additionally, corresponding to the above embodiment, in an embodiment, a solid-state dopant source layer 390 and an optional capping layer 392 may be retained in the structure along the sidewalls of the sub-fin region 305.

[0058] In one embodiment, each of the plurality of semiconductor fins 304 / 305 has a ω-shaped fin geometry, as Figure 3A shown. In one embodiment, the protruding portion 304 of each of the plurality of semiconductor fins has a width of about 10 nanometers or less. In one embodiment, the solid-state dopant source layer 390 has a top surface that is substantially coplanar with the interface between the sub-fin portion 305 and the protruding portion 304 of each of the plurality of semiconductor fins, as Figure 3A shown. In one embodiment, the isolation layer 306 has a top surface that is substantially coplanar with the interface between the sub-fin portion 305 and the protruding portion 304 of each of the plurality of semiconductor fins, as Figure 3A shown. In one embodiment, the solid-state dopant source layer 390 is a borosilicate glass (BSG) layer. In one embodiment, the solid-state dopant source layer 390 is a phosphosilicate glass (PSG) layer or an arsenosilicate glass (AsSG) layer. In one embodiment, the capping layer 392 is composed of silicon nitride. In one embodiment, the capping layer 392 has a top surface that is substantially coplanar with the interface between the sub-fin portion 305 and the protruding portion 304 of each of the plurality of semiconductor fins, as Figure 3A shown.

[0059] Also as Figure 3A shown, in an embodiment, there is an interface 380 between the doping profile of the protruding fin portion 304 and the sub-fin region 305. The interface 380 may be a relatively abrupt transition region. One or more embodiments limit or substantially limit dopants from a doping process to the sub-fin region of the semiconductor device. As an example, the transition of the doping concentration may rapidly decrease from the sub-fin region to the protruding fin region. In one such embodiment, the transition is substantially immediate, where for each of the protruding portions in the protruding portion has a dopant concentration of less than about 5E17 atoms / cm 3 while for the corresponding sub-fin region has a dopant concentration of greater than about 2E18 atoms / cm 3The dopant concentration. Additionally, the substrate portion below the sub-fin region 305 may be doped to form a well region in a sense. In one embodiment, the lower portion of the substrate 302 is doped at least in part by diffusing downward from a solid-state dopant source (e.g., layer 390) into the underlying substrate.

[0060] Referring again to Figure 3A , the gate line 308 is disposed above the protruding portion 304 of the non-planar active region and above a portion of the isolation region 306. As shown, the gate line 308 includes a gate electrode 350 and a gate dielectric layer 352. In one embodiment, the gate line 308 may further include a dielectric overlay 354. Also visible from this perspective view are the gate contact 314 and the overlying gate contact via 316 as well as the overlying metal interconnect 360, all of which are disposed in the interlayer dielectric stack or layer 370. From Figure 3A the perspective view, it can also be seen that, in one embodiment, the gate contact 314 is disposed above the isolation region 306 but not above the non-planar active region.

[0061] Referring to Figure 3B , the gate line 308 is shown disposed above the protruding fin portion 304. The source region 304A and the drain region 304B of the protruding fin portion 304 can be seen from this perspective view. In one embodiment, the source region 304A and the drain region 304B are doped portions of the original material of the protruding fin portion 304. In another embodiment, the material of the protruding fin portion 304 is removed and replaced with another semiconductor material, for example, by epitaxial deposition. In either case, the source region 304A and the drain region 304B may extend below the height of the dielectric layer 306, i.e., into the sub-fin region 305. According to an embodiment of the present invention, the more heavily doped sub-fin region 305 (i.e., the doped portion of the fin below the interface 380) inhibits source-to-drain leakage through this portion of the bulk semiconductor fin.

[0062] In an embodiment, the semiconductor structure or device 300 is a non-planar device, such as but not limited to a finFET or a triple-gate device. In such an embodiment, the corresponding semiconductor channel region is constituted by or formed in a three-dimensional body. In one such embodiment, the gate electrode stack of the gate line 308 at least surrounds the top surface and a pair of sidewalls of the three-dimensional body, as Figure 3A shown.

[0063] The substrate 302 can be composed of a semiconductor material that can withstand the manufacturing process and through which charge can migrate. In an embodiment, the substrate 302 is a bulk substrate composed of crystalline silicon, silicon / germanium, or a germanium layer doped with charge carriers (e.g., but not limited to, phosphorus, arsenic, boron, or a combination thereof) to form an active region 304. In one embodiment, the concentration of silicon atoms in the bulk substrate 302 is greater than 97%. In another embodiment, the bulk substrate 302 is composed of an epitaxial layer grown on top of a different crystalline substrate, such as a silicon epitaxial layer grown on top of a boron-doped bulk silicon single crystal substrate. The bulk substrate 302 can alternatively be composed of III-V materials. In an embodiment, the bulk substrate 302 is composed of III-V materials, such as but not limited to gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, the bulk substrate 302 is composed of III-V materials, and the charge carrier dopant impurity atoms are the following atoms: such as but not limited to carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0064] The isolation region 306 can be composed of a material that is suitable for ultimately electrically isolating or facilitating the electrical isolation of portions of the permanent gate structure from the underlying bulk substrate, or isolating active regions formed within the underlying bulk substrate, such as isolated fin active regions. For example, in one embodiment, the isolation region 306 is composed of a dielectric material, such as but not limited to silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0065] The gate line 308 can be composed of a gate electrode stack including a gate dielectric layer 352 and a gate electrode layer 350. In an embodiment, the gate electrode in the gate electrode stack is composed of a metal gate, and the gate dielectric layer is composed of a high-k material. For example, in one embodiment, the gate dielectric layer is composed of the following materials: such as but not limited to hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. Additionally, a portion of the gate dielectric layer can include a native oxide layer formed from the top few layers of the substrate 302. In an embodiment, the gate dielectric layer is composed of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride.

[0066] In one embodiment, the gate electrode is formed of a metal layer, such as but not limited to, metal nitride, metal carbide, metal silicide, metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or a conductive metal oxide. In a specific embodiment, the gate electrode is composed of a non-work function-setting filler material formed over a metal work function-setting layer.

[0067] Although not shown, the spacer associated with the gate electrode stack may be composed of a material suitable for ultimately electrically isolating or facilitating the electrical isolation of the permanent gate structure from adjacent conductive contacts (e.g., self-aligned contacts). For example, in one embodiment, the spacer is composed of a dielectric material, such as but not limited to silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0068] The gate contact 314 and the overlying gate contact via 316 may be composed of a conductive material. In an embodiment, one or more of the contacts or vias are composed of a metal type. The metal type may be a pure metal such as tungsten, nickel, or cobalt, or may be an alloy, such as a metal-metal alloy or a metal-semiconductor alloy (e.g., a silicide material).

[0069] In an embodiment (although not shown), the structure 300 is provided including forming a contact pattern that is substantially perfectly aligned with an existing gate pattern without the use of a lithography step having a very strict registration budget. In one such embodiment, the solution enables the use of an inherently highly selective wet etch (e.g., compared to conventionally implemented dry etch or plasma etch) to generate the contact openings. In an embodiment, the contact pattern is formed by utilizing the existing gate pattern in combination with a contact plug lithography operation. In one such embodiment, the solution enables the elimination of the need for other critical lithography operations used to generate the contact pattern as in conventional solutions. In an embodiment, the trench contact grid is not patterned separately but is formed between polysilicon (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grating patterning but before the gate grating notching.

[0070] In addition, the gate stack structure 308 may be fabricated by an alternative gate process. In such a solution, dummy gate materials such as polysilicon or silicon nitride pillar materials may be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, contrary to what was accomplished in earlier processing. In an embodiment, the dummy gate is removed by a dry etch or a wet etch process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is replaced with a material including the use of SF 6is removed by a dry etching process. In another embodiment, the dummy gate is made of polysilicon or amorphous silicon and is removed by a wet etching process including using an NH 4 OH aqueous solution or tetramethylammonium hydroxide. In one embodiment, the dummy gate is made of silicon nitride and is removed by wet etching including an aqueous phosphoric acid solution.

[0071] In an embodiment, one or more of the aspects described herein substantially contemplate a dummy and replacement gate process in combination with a dummy and replacement contact process to arrive at structure 300. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow for high temperature annealing of at least a portion of the permanent gate stack. For example, in one such specific embodiment, for example, after forming the gate dielectric layer, annealing of at least a portion of the permanent gate structure is performed at a temperature greater than about 600 degrees Celsius. Annealing is performed before forming the permanent contact.

[0072] Referring again to Figure 3A , the arrangement of the semiconductor structure or device 300 places the gate contact above the isolation region. This arrangement can be regarded as an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure that contacts a portion of the gate electrode formed above the active region. Generally, before (e.g., in addition to) forming the gate contact structure (e.g., via) above the active portion of the gate and in the same layer as the trench contact via, one or more embodiments of the present invention include first using a gate-aligned trench contact process. Such a process can be implemented to form a trench contact structure for semiconductor structure fabrication (e.g., for integrated circuit fabrication). In an embodiment, the trench contact pattern is formed to be aligned with an existing gate pattern. In contrast, conventional approaches typically involve additional lithography processes where strict registration of the lithography contact pattern with the existing gate pattern is combined with selective contact etching. For example, a conventional process can include patterning a polycrystalline (gate) grid by separate patterning of contact features.

[0073] It should be appreciated that not all aspects of the above processes need to be implemented to fall within the spirit and scope of the embodiments of the present invention. For example, in one embodiment, a dummy gate need not be formed before fabricating a gate contact over the active portion of the gate stack. The gate stack may actually be the initially formed permanent gate stack. Additionally, the processes described herein can be used to fabricate one or more semiconductor devices. The semiconductor devices can be transistors or similar devices. For example, in an embodiment, the semiconductor device is a metal oxide semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. Additionally, in an embodiment, the semiconductor device has a three-dimensional architecture, such as a triple-gate device, a separately accessible double-gate device, or a FIN-FET. One or more embodiments can be particularly useful for fabricating semiconductor devices at a 10 nanometer (10 nm) or smaller (e.g., 7 nm) technology node.

[0074] Figure 4 Illustrated is a computing device 400 in accordance with one embodiment of the present invention. The computing device 400 houses a board 402. The board 402 may include a plurality of components, including but not limited to a processor 404 and at least one communication chip 406. The processor 404 is physically and electrically coupled to the board 402. In some embodiments, at least one communication chip 406 is also physically and electrically coupled to the board 402. In other embodiments, the communication chip 406 is part of the processor 404.

[0075] Depending on its application, the computing device 400 may include other components, which may or may not be physically and electrically coupled to the board 402. These other components include but are not limited to volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chip sets, antennas, displays, touchscreen displays, touchscreen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (e.g., hard disk drives, compact discs (CDs), digital versatile discs (DVDs), etc.).

[0076] The communication chip 406 implements wireless communication for data transfer to and from the computing device 400. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc. that can transfer data by using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not. The communication chip 406 can implement any wireless standard or protocol among a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocol designated as 3G, 4G, 5G, and more advanced. The computing device 400 can include multiple communication chips 406. For example, the first communication chip 406 can be dedicated to short-range wireless communication, such as Wi-Fi and Bluetooth, while the second communication chip 406 can be dedicated to long-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0077] The processor 404 of the computing device 400 includes an integrated circuit die encapsulated within the processor 404. In some implementations of embodiments of the present invention, the integrated circuit die of the processor includes one or more devices, such as MOS-FET transistors constructed according to embodiments of the present invention. The term "processor" can refer to any device or part of a device that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory.

[0078] The communication chip 406 also includes an integrated circuit die encapsulated within the communication chip 406. According to another embodiment of the present invention, the integrated circuit die of the communication chip includes one or more devices, such as MOS-FET transistors constructed according to embodiments of the present invention.

[0079] In other embodiments, another component housed within the computing device 400 can include an integrated circuit die that includes one or more devices, such as MOS-FET transistors constructed according to embodiments of the embodiments of the present invention.

[0080] In various embodiments, computing device 400 can be a laptop computer, a netbook computer, a notebook computer, a Ultrabook computer, a smart phone, a tablet computer, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In other embodiments, computing device 400 can be any other electronic device that processes data.

[0081] Thus, embodiments of the present invention include a non-planar semiconductor device having ω-shaped fin portions and a method of manufacturing a non-planar semiconductor device having ω-shaped fin portions, the ω-shaped fin portions having doped sub-fin regions.

[0082] In an embodiment, a semiconductor device includes a plurality of semiconductor fin portions disposed on a semiconductor substrate. Each semiconductor fin portion has a sub-fin portion below a protruding portion, and the sub-fin portion is narrower than the protruding portion. A solid-state dopant source layer disposed on the semiconductor substrate and conformal to the sub-fin regions of each of the plurality of semiconductor fin portions but not conformal to the protruding portions. An isolation layer disposed on the solid-state dopant source layer and between the sub-fin regions of the plurality of semiconductor fin portions. A gate stack disposed on the isolation layer and conformal to the protruding portions of each of the plurality of semiconductor fin portions, the gate stack including a gate dielectric layer and a gate electrode. Source regions and drain regions disposed in the protruding portions of each of the plurality of semiconductor fin portions, the source regions and the drain regions being located on either side of the gate stack.

[0083] In one embodiment, each of the plurality of semiconductor fin portions has an ω-shaped fin geometry.

[0084] In one embodiment, the protruding portion of each of the plurality of semiconductor fin portions has a width of about 10 nanometers or less.

[0085] In one embodiment, the top surface of the solid-state dopant source layer is substantially coplanar with the interface between the sub-fin portion and the protruding portion of each of the plurality of semiconductor fin portions.

[0086] In one embodiment, the top surface of the isolation layer is substantially coplanar with the interface between the sub-fin portion and the protruding portion of each of the plurality of semiconductor fin portions.

[0087] In one embodiment, the solid-state dopant source layer is a borosilicate glass (BSG) layer.

[0088] In one embodiment, the solid-state dopant source layer is a phosphosilicate glass (PSG) layer or an arsenosilicate glass (AsSG) layer.

[0089] In one embodiment, the semiconductor device further includes a capping layer disposed on and conformal to the solid-state dopant source layer. The isolation layer is disposed on the capping layer.

[0090] In one embodiment, the capping layer is composed of silicon nitride, and the top surface of the capping layer is substantially coplanar with the interface between the sub-fin portion and the protruding portion of each semiconductor fin among the plurality of semiconductor fins.

[0091] In one embodiment, the semiconductor device further includes a dopant concentration interface located between each protruding portion and the corresponding sub-fin portion of each semiconductor fin among the plurality of semiconductor fins.

[0092] In one embodiment, the dopant concentration interface is a mutation that is less than about 5E17 atoms / cm for each protruding portion of each semiconductor fin among the plurality of semiconductor fins 3 and greater than about 2E18 atoms / cm for the corresponding sub-fin portion. 3 of the mutation.

[0093] In one embodiment, the plurality of semiconductor fins disposed on the semiconductor substrate are a plurality of single-crystalline silicon fins continuous with a bulk single-crystalline silicon substrate.

[0094] In an embodiment, a semiconductor device includes a plurality of semiconductor fins disposed over a semiconductor substrate. Each of the plurality of semiconductor fins has a sub-fin portion below a protruding portion, and the sub-fin portion is narrower than the protruding portion. A dopant concentration interface is located between each protruding portion and a corresponding sub-fin portion of each of the plurality of semiconductor fins. An isolation layer is disposed between sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed over the isolation layer and conformal to the protruding portion of each of the plurality of semiconductor fins, and the gate stack includes a gate dielectric layer and a gate electrode. A source region and a drain region are disposed in the protruding portion of each of the plurality of semiconductor fins, and the source region and the drain region are located on either side of the gate stack.

[0095] In one embodiment, each of the plurality of semiconductor fins has a omega-shaped fin geometry.

[0096] In one embodiment, the protruding portion of each of the plurality of semiconductor fins has a width of about 10 nanometers or less.

[0097] In one embodiment, a top surface of the isolation layer is substantially coplanar with an interface between the sub-fin portion and the protruding portion of each of the plurality of semiconductor fins.

[0098] In one embodiment, the dopant concentration interface is a mutation that is less than about 5E17 atoms / cm 3 for each protruding portion of each of the plurality of semiconductor fins and greater than about 2E18 atoms / cm 3 for a corresponding sub-fin portion.

[0099] In one embodiment, the plurality of semiconductor fins disposed over the semiconductor substrate are a plurality of single-crystalline silicon fins continuous with a bulk single-crystalline silicon substrate.

[0100] In an embodiment, a method of manufacturing a semiconductor device includes forming a plurality of semiconductor fins over a semiconductor substrate. The method further includes forming a catalyst layer conformal to the plurality of semiconductor fins over the semiconductor substrate. The method further includes forming a mask over the catalyst layer. The method further includes recessing the mask and the catalyst layer to a level substantially below the top surface of the plurality of semiconductor fins, exposing a protruding portion of each of the plurality of semiconductor fins over a sub-fin region of each of the plurality of semiconductor fins. The method further includes using the catalyst layer to oxidize an outer portion of the sub-fin region of each of the plurality of semiconductor fins so as to catalytically oxidize the sub-fin region. The method further includes removing the oxide formed by the oxidation to provide a plurality of omega-shaped fins having a sub-fin region narrower than the corresponding protruding portion.

[0101] In one embodiment, the plurality of semiconductor fins are a plurality of silicon fins, and forming the catalyst layer includes forming an Al 2 O 3 layer conformal to the plurality of silicon fins.

[0102] In one embodiment, oxidizing the outer portion of the sub-fin region includes exposing the Al 2 O 3 layer to a composition of hydrogen and oxygen (H 2 / O 2 ).

[0103] In one embodiment, the method further includes, after providing the plurality of omega-shaped fins, forming a solid-state dopant source layer conformal to the plurality of omega-shaped fins over the semiconductor substrate. Then recessing the solid-state dopant source layer to be substantially coplanar with the sub-fin regions of the plurality of omega-shaped fins. Then driving dopants from the solid-state dopant source layer into the sub-fin regions of each of the plurality of omega-shaped fins.

[0104] In one embodiment, forming the solid-state dopant source layer includes forming a borosilicate glass (BSG) layer.

[0105] In one embodiment, forming the solid-state dopant source layer includes forming a phosphosilicate glass (PSG) layer or an arsenosilicate glass (AsSG) layer.

[0106] In one embodiment, the method further includes forming a gate stack conformal to the protruding portion of each of the plurality of omega-shaped fins. Then, on either side of the gate stack, source and drain regions are formed in the protruding portion of each of the plurality of omega-shaped fins.

Claims

1. A method of manufacturing a semiconductor device, the method comprises: forming a plurality of semiconductor fins over a semiconductor substrate; forming a catalyst layer conformal to the plurality of semiconductor fins over the semiconductor substrate; forming a mask over the catalyst layer; recessing the mask and the catalyst layer to the same level below a top surface of each of the plurality of semiconductor fins, the recessing exposing a protruding portion of each of the plurality of semiconductor fins that is over a sub-fin region of each of the plurality of semiconductor fins; using the catalyst layer to oxidize an outer portion of the sub-fin region of each of the plurality of semiconductor fins so as to catalytically oxidize the sub-fin region; and removing an oxide formed by the oxidation to provide a plurality of omega-shaped fins each having a thinned sub-fin region that is narrower than a corresponding protruding portion.

2. The method according to claim 1, wherein, The plurality of semiconductor fins are a plurality of silicon fins, and wherein forming the catalyst layer includes forming an Al 2 O 3 layer that is conformal to the plurality of silicon fins.

3. The method according to claim 2, wherein, Oxidizing the outer portion of the sub-fin region includes exposing the Al 2 O 3 layer to a composition of hydrogen and oxygen (H 2 / O 2 ).

4. The method according to claim 1, further comprises: after providing the plurality of omega-shaped fins, forming a solid-state dopant source layer conformal to the plurality of omega-shaped fins over the semiconductor substrate; recessing the solid-state dopant source layer to be coplanar with the thinned sub-fin region of each of the plurality of omega-shaped fins; and driving dopants from the solid-state dopant source layer into the thinned sub-fin region of each of the plurality of omega-shaped fins.

5. The method according to claim 4, wherein, forming the solid-state dopant source layer comprises forming a borosilicate glass (BSG) layer.

6. The method according to claim 4, wherein, forming the solid-state dopant source layer comprises forming a phosphosilicate glass (PSG) layer or an arsenosilicate glass (AsSG) layer.

7. The method according to claim 1, further comprises: forming a gate stack conformal to the protruding portion of each of the plurality of omega-shaped fins; and forming source and drain regions in the protruding portion of each of the plurality of omega-shaped fins on either side of the gate stack.

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