A Bootstrap Voltage Control System for GaN Power Transistors to Reduce dVS / dt Noise

Abstract

A bootstrap voltage control system for a GaN power transistor to reduce dVS / dt noise uses a bootstrap charging circuit to charge the bootstrap capacitor in time when the voltage of the bootstrap rail voltage VB - VS decreases, preventing under-voltage of VB - VS. When the Miller plateau phenomenon occurs during the driving of the GaN device, the control circuit reduces the efficiency of the bootstrap charging circuit to supplement the VB - VS voltage in time, extends the time of the plateau period, and reduces the noise of dVS / dt. The present invention solves the problems of under-voltage of the bootstrap rail voltage VB - VS that occurs over time due to the continuous conduction of the GaN upper power transistor Mn1 and the problem of excessive dV / dt noise caused by too short a Miller plateau period during the conduction of Mn1, improves the stability of the drive system, and has a simple circuit structure, low implementation difficulty, and high reliability.

Description

Technical Field

[0001] The present invention relates to a bootstrap technology in a DC / DC voltage conversion circuit, and particularly to a bootstrap voltage control system for a GaN (gallium nitride) power transistor that reduces dVS / dt noise, belonging to the technical field of electronic circuits and integrated circuits. Background Art

[0002] The bootstrap voltage control circuit can be widely applied to a DC / DC voltage conversion circuit. The DC / DC voltage conversion circuit adjusts the output voltage by alternately turning on the high-side GaN power transistor Mn1 and the low-side power transistor Mn2. The GaN power transistor requires a corresponding drive circuit to drive the switch. The drive circuit usually includes a high-side channel and a low-side channel. To improve the utilization efficiency of the power supply, a single power supply is generally used. The low-side channel is generally powered by a DC power supply VCC, while the circuit working in the high-voltage circuit area in the high-side channel needs to be powered by an externally connected bootstrap capacitor to generate a floating voltage VB. As Figure 1 shown, the traditional bootstrap circuit consists of a bootstrap capacitor Cboot1 and a bootstrap diode D3. When the low-side GaN power transistor lower transistor Mn2 is turned on and the high-side upper transistor Mn1 is turned off, the voltage of the high-side floating power supply VB decreases as the voltage of the high-side floating ground VS decreases. When the voltage at the VB point drops below the VCC voltage and the voltage difference between the two exceeds the forward voltage drop of the bootstrap diode D3, VCC charges the bootstrap capacitor Cboot1 through the bootstrap diode D3; when the upper transistor Mn1 is turned on and the lower transistor Mn2 is turned off, the voltage at the VB point will increase as the voltage at the VS point increases, and the VB voltage far exceeds the VCC voltage, and the bootstrap diode D3 is cut off, and the bootstrap capacitor Cboot1 supplies power to the high-side channel circuit.

[0003] Traditional bootstrap circuits have obvious drawbacks in applications: To ensure the stability of the high-side channel, the bootstrap capacitor Cboot1 is generally designed as an external large capacitor. If the bootstrap capacitor is to be integrated into the chip, it can only be on the order of pF. When the high side is turned on for a long time, as the charge on the capacitor Cboot1 slowly dissipates, the VB-VS voltage will gradually decrease until the high-side channel loses its basic function, and the integrated pF-level small capacitor exacerbates this drawback. When the VB-VS voltage drops to the critical voltage for the normal operation of the high-side channel, the voltage shift of the high side will lose its normal function, and the output signal HO will be incorrect, resulting in the inability of the high-side power transistor Mn1 to turn on normally and the output stage circuit to output an incorrect signal. In addition, when the high-side power transistor conducts, VS charges from 0 voltage to Vin, and VB will also rise with VS; rapidly rising VB within a short period of time will introduce dVS / dt noise in the voltage shift module, resulting in an incorrect output signal from the voltage shift module. The turn-on speed of GaN output power transistors is faster than that of silicon-based power transistors, and the dVS / dt noise is greater. Although various circuits for removing dVS / dt noise are added in conventional designs, the noise cannot be completely removed, and it increases the power consumption and delay of the overall circuit, which goes against the original intention of using GaN power devices. Summary of the Invention

[0004] The object of the present invention is to address the problems of undervoltage of the bootstrap rail voltage VB-VS and dVS / dt noise caused by the conduction of the high-side GaN power transistor in the above-mentioned existing technologies. The present invention proposes a GaN (gallium nitride) power transistor bootstrap voltage control circuit for reducing dVS / dt noise, which can not only ensure that the VB-VS voltage does not drop to the critical voltage for the normal operation of the high-side channel but also reduce the dVS / dt noise generated when the high-side GaN power transistor conducts.

[0005] To achieve the above object of the invention, the present invention adopts the following technical solutions: A GaN power transistor bootstrap voltage control system for reducing dVS / dt noise includes an input stage circuit (001) and an output stage circuit (002). The input stage circuit (001) includes a dead-time control circuit (008), a high-side channel (009), and a low-side channel (010); the output stage circuit (002) includes a drive stage circuit (011) containing a high-side drive circuit and a low-side drive circuit, a power stage circuit (012) containing a high-side GaN power transistor Mn1 and a low-side GaN power transistor Mn2, and a bootstrap capacitor C boot1and the bootstrap charging circuit (007) composed of the bootstrap diode D3; the high-side input signal HIN and the low-side input signal LIN are respectively connected to the two input terminals of the dead-time circuit (008), and the two output terminals of the dead-time circuit (008) are respectively connected to the input terminals of the high-side channel (009) and the low-side channel (010). The output of the high-side channel (009) is connected to the input terminal of the high-side driving circuit in the driving stage circuit (011). The output signal HO of the high-side driving circuit is connected to the gate of the high-side GaN power transistor Mn1 in the power stage circuit (011). The output of the low-side channel (010) is connected to the input terminal of the low-side driving circuit in the driving stage circuit (011). The output signal LO of the low-side driving circuit is connected to the gate of the low-side GaN power transistor Mn2 in the power stage circuit (012). The low-side channel (010) and the low-side driving circuit in the driving stage circuit (011) are powered by VCC. The high-side channel (009) and the high-side driving circuit in the driving stage circuit (011) are powered by the bootstrap rail voltage VB-VS generated by the bootstrap capacitor Cboot1 and the bootstrap diode D3 in the bootstrap charging circuit (007) from the VCC after voltage regulation of the power supply voltage Vin. The high-side reference ground is the floating voltage VS, and the low-side reference ground is GND;

[0006] It is characterized in that: a bootstrap voltage control circuit (003) including a dVS / dt detection circuit (004), a logic control and voltage gating circuit (005), a voltage-controlled oscillator (006) and a bootstrap charging control loop (070) is added. Among them, the bootstrap charging control loop (070) is jointly composed of the bootstrap charging circuit (007), diodes D1, D2 and capacitor Cboot2. The anode of diode D1 is connected to the floating ground VS. The cathode of diode D1, the anode of diode D2 and one end of capacitor Cboot2 are jointly connected to the VB1 terminal. The cathode of diode D2 is connected to the floating voltage VB, that is, the connection terminal of the cathode of the bootstrap diode D3 and the bootstrap capacitor Cboot1. The anode of the bootstrap diode D3 is connected to VCC. The other end of the bootstrap capacitor Cboot1 is connected to the floating ground VS, that is, the connection terminal of the source of the high-side GaN power transistor Mn1 and the drain of the low-side GaN power transistor Mn2;

[0007] The input terminal of the dVS / dt detection circuit (004) is connected to the floating ground VS. The level control signal Vfb output by the dVS / dt detection circuit (004), the voltage signal Vx linearly related to the magnitude of the dVS / dt noise, and the high-side input signal HIN are used as the input signals of the logic control and voltage gating circuit (005). The output signal Vctrl of the logic control and voltage gating circuit (005) is the input signal of the voltage-controlled oscillator (006). The output signal of the voltage-controlled oscillator (006) is an oscillation signal VB2 of 0 to VCC, which is connected to the other end of the capacitor Cboot2 in the bootstrap charging loop (070);

[0008] The dVS / dt detection circuit (004) includes a differentiating circuit, a current comparator, and a proportional operational amplifier; the differentiating circuit converts the voltage change slope of the input signal VS into a corresponding voltage signal, and this voltage signal generates a voltage signal Vx corresponding to the size of the dVS / dt noise linearly through the proportional operational amplifier; the current comparator is used to generate a switching signal for judging the size of the voltage change slope of VS, that is, a level control signal Vfb for judging whether the dVS / dt noise arrives;

[0009] In addition to the level control signal Vfb output by the dVS / dt detection circuit (004), the voltage signal Vx linearly related to the size of the dVS / dt noise, and the high-side input signal HIN, the input signals of the logic control and voltage gating circuit (005) also include two externally input bias voltage signals with different voltage values generated by the current-mode bandgap reference circuit, defined as the highest voltage Vmax and the lowest voltage Vmin; the logic control and voltage gating circuit (005) includes logic gates, transmission gates, and delay circuits, and is used to correspond to three states: the high-side GaN power transistor is conducting and the dVS / dt noise is detected, the high-side GaN power transistor is conducting but the dVS / dt noise is not detected, and the low-side GaN power transistor is conducting. The logic control and voltage gating circuit (005) only outputs one of the three states through the logic control of the input level control signal Vfb and the high-side input signal HIN: when the high-side GaN power transistor is conducting and the dVS / dt noise is detected, the signal Vctrl output by the logic control and voltage gating circuit (005) is the voltage signal Vx linearly related to the size of the dVS / dt noise; when the high-side GaN power transistor is conducting but the dVS / dt noise is not detected, the signal Vctrl output by the logic control and voltage gating circuit (005) is the highest voltage Vmax; when the low-side GaN power transistor is conducting, the signal Vctrl output by the logic control and voltage gating circuit (005) is the lowest voltage Vmin;

[0010] The frequency of the oscillation signal VB2 output by the voltage-controlled oscillator (006) is related to the input voltage. When the input voltage signal Vctrl is the lowest voltage Vmin, the output periodic signal frequency is only at the MHz level; when the input voltage signal Vctrl is the highest voltage Vmax, the output periodic signal frequency is at the hundreds of MHz level; when the input voltage signal Vctrl is the voltage signal Vx linearly related to the size of the dVS / dt noise, the output periodic frequency is between the previous two;

[0011] In the above structure, a dVS / dt detection circuit (004), logic control and voltage gating (005), and a voltage-controlled oscillator (006) are used to control the oscillation frequency of the oscillation signal VB2 output by the voltage-controlled oscillator (006), thereby indirectly controlling the rate of VB-VS voltage replenishment of the capacitor Cboot2 to the capacitor Cboot1. On the premise of ensuring that the VB-VS voltage meets the normal operating voltage of the high side, the voltage value of VB-VS during the Miller plateau is reduced, and the parasitic capacitance C between the gate and drain of the high-side GaN power transistor Mn1 caused by the Miller plateau device is reduced. GD The charging current is reduced, the residence time of the Miller plateau is extended, and the dVS / dt noise is reduced.

[0012] Further, the dVS / dt detection circuit (004) includes PMOS transistors P1 to P8, NMOS transistors N2 to N6, resistors R1, R2, and R3, capacitor C1, inverters X1 and X2, current source I, and operational amplifier OP1; one end of capacitor C1 is connected to the floating ground VS, and the other end of capacitor C1 is connected to the drain and gate of NMOS transistor N2, the gate of NMOS transistor N3, and the gate of NMOS transistor N4. The source of NMOS transistor N2 and the source of NMOS transistor N3 are grounded to GND. The drain of NMOS transistor N3 is connected to the drain and gate of PMOS transistor P1 and the gate of PMOS transistor P2. The source of PMOS transistor P1 and the source of PMOS transistor P2 are connected to VCC. The drain of PMOS transistor P2 is connected to one end of resistor R1 and outputs the voltage signal V2. The other end of resistor R1 is grounded to GND. The sources of PMOS transistor P2, PMOS transistor P3, PMOS transistor P4, PMOS transistor P5, PMOS transistor P6, and PMOS transistor P7 are all connected to VCC. The gate and drain of PMOS transistor P3 are interconnected and connected to the drain of NMOS transistor N4, the gate of PMOS transistor P4, and the gate of PMOS transistor P5. The source of NMOS transistor N4 is grounded to GND. The gates of PMOS transistor P6 and PMOS transistor P7 are interconnected and connected to the drain of PMOS transistor P6 and the input end of current source I. The output end of current source I is grounded to GND. The drains of PMOS transistor P7 and PMOS transistor P8 are interconnected and connected to the drain of NMOS transistor N5, the gate of NMOS transistor N5, and the gate of NMOS transistor N6. The sources of NMOS transistor N5 and NMOS transistor N6 are grounded to GND. The drain of NMOS transistor N6 is connected to the drain of PMOS transistor P5 and the input end of inverter X2. The output end of inverter X2 is connected to the input end of inverter X1 and the gate of PMOS transistor P8. The source of PMOS transistor P8 is connected to the drain of PMOS transistor P4. The output of inverter X1 serves as an output end of the dVS / dt detection circuit (004), outputting the level control signal Vfb. One end of resistor R2 is connected to the voltage signal V2. The other end of resistor R2 is connected to the negative end of operational amplifier OP1 and one end of resistor R3. The reference voltage Vref is connected to the positive end of operational amplifier OP1. The other end of resistor R3 is connected to the output end of operational amplifier OP1 and outputs the voltage signal Vx that is linearly related to the magnitude of the dVS / dt noise.

[0013] Further, the logic control and voltage gating circuit (005) includes a delay circuit delay, three inverters INV1, INV2, INV3, an OR gate OR1, a three-input AND gate AND1, and three transmission gates GT1, GT2, GT3; the high-side input signal HIN is connected to the input end of the delay circuit delay, the input end of the inverter INV1, and one input end of the three-input AND gate AND1. The level control signal Vfb output by the dVS / dt detection circuit (004) is connected to the input end of the inverter INV3 and the gate of the PMOS transistor in the transmission gate GT3. The voltage signal Vx output by the dVS / dt detection circuit (004) that is linearly related to the magnitude of the dVS / dt noise is connected to the input end of the transmission gate GT3. The output of the delay circuit delay is connected to the input end of the inverter INV2 and one input end of the OR gate OR1. The other input end of the OR gate OR1 is connected to the output of the inverter INV1. The output of the inverter INV2 is connected to the second input end of the three-input AND gate AND1. The output of the inverter INV3 is connected to the third input end of the three-input AND gate AND1. The output of the OR gate OR1 is connected to the gate of the PMOS transistor in the transmission gate GT1. The input end of the transmission gate GT1 is connected to the lowest voltage Vmin. The output of the three-input AND gate AND1 is connected to the gate of the PMOS transistor in the transmission gate GT2. The input end of the transmission gate GT2 is connected to the highest voltage Vmax. The gates of the NMOS transistors in the three transmission gates GT1, GT2, GT3 are commonly grounded to GND. The output ends of the three transmission gates GT1, GT2, GT3 are interconnected as the output end of the logic control and voltage gating circuit (005), and the output voltage signal Vctrl is output.

[0014] Further, the voltage-controlled oscillator (006) includes six PMOS transistors P11 to P16, six NMOS transistors N11 to N16, and five inverters X11 to X15; the gates of the NMOS transistors N11 to N16 are interconnected and connected to the output voltage signal Vctrl of the logic control and voltage gating circuit (005), the sources of the NMOS transistors N11 to N16 are interconnected and grounded to GND, the drain of the NMOS transistor N11 is connected to the drain of the PMOS transistor P11 and the gates of the PMOS transistors P11 to P16, the sources of the PMOS transistors P11 to P16 are interconnected and connected to VCC, the drain of the PMOS transistor P12 is connected to the power supply terminal of the inverter X11, the drain of the NMOS transistor N12 is connected to the ground terminal of the inverter X11, the drain of the PMOS transistor P13 is connected to the power supply terminal of the inverter X12, the drain of the NMOS transistor N13 is connected to the ground terminal of the inverter X12, the drain of the PMOS transistor P14 is connected to the power supply terminal of the inverter X13, the drain of the NMOS transistor N14 is connected to the ground terminal of the inverter X13, the drain of the PMOS transistor P15 is connected to the power supply terminal of the inverter X14, the drain of the NMOS transistor N15 is connected to the ground terminal of the inverter X14, the drain of the PMOS transistor P16 is connected to the power supply terminal of the inverter X15, the drain of the NMOS transistor N16 is connected to the ground terminal of the inverter X15, the output of the inverter X11 is the input of the inverter X12, the output of the inverter X12 is the input of the inverter X13, the output of the inverter X13 is the input of the inverter X14, the output of the inverter X14 is the input of the inverter X15, the output of the inverter X15 serves as the output terminal of the voltage-controlled oscillator (006), outputs an oscillation signal VB2 and is connected to the input terminal of the inverter X11.

[0015] The voltage-controlled oscillator (006) adopts a ring oscillator, and the five inverters X11, X12, X13, X14, and X15 have the same parameters, the six NMOS transistors N11, N12, N13, N14, N15, and N16 have the same parameters, and the six PMOS transistors P11, P12, P13, P14, P15, and P16 have the same parameters.

[0016] The capacitance values of the bootstrap capacitor Cboot1 and the capacitor Cboot2 are both at the pF level, and Cboot2 is slightly smaller than Cboot1, and they can be integrated into the chip.

[0017] The system under-voltage charging control process is as follows: When the low-side output signal LO is at a high level and the power transistor Mn2 is conducting, VS is at 0 potential, and VCC charges the capacitor Cboot1. VB is charged to VCC. At this time, the potential of VB2 is 0 to VCC. Affected by the clamping of VS, the voltage range of VB1 changes from 0 to VCC. The diode D2 makes VB1 and VB not interfere with each other, and VB is stably maintained at VCC. When the high-side output signal HO is at a high level and the power transistor Mn1 is conducting, the voltage range of VS is 0 to Vin. The voltage across the capacitor Cboot1 cannot change suddenly, and the change range of VB increases with VS to VS to VS+VCC. At this time, the voltage range of VB1 is VS to VS+VCC. When the power transistor Mn1 conducts for a long time, the charge of the capacitor Cboot1 cannot be replenished and will gradually be lost. The voltage of VB-VS will gradually decrease and even affect the normal operation of the high-side output power transistor. Therefore, when the voltage of VB-VS decreases, the capacitor Cboot2 replenishes the charge of the capacitor Cboot1 in time to ensure that the voltage of VB-VS is stably maintained at VCC.

[0018] The process of the system controlling the dVS / dt noise is as follows: When the GaN high-side output power transistor Mn1 conducts, it will encounter the Miller plateau. During the Miller plateau, the V DS voltage between the source and drain of the GaN device will drop rapidly, that is, the floating voltage VS will rise rapidly. The too-fast rising speed causes dVS / dt noise. Prolonging the duration of the plateau period can reduce the dVS / dt noise. The behavior of the capacitor Cboot2 replenishing the charge of the capacitor Cboot1 is achieved by the periodic signal output by the voltage-controlled oscillator (006) to raise VB1 to VS+VCC. Reducing the output frequency of the voltage-controlled oscillator (006), that is, reducing the amount of charge replenished by the capacitor Cboot2 to the capacitor Cboot1 per unit time, can control the value of the VB-VS voltage. When the high side conducts, when the dVS / dt detection (004) detects the dVS / dt noise, the noise signal will be converted into a voltage signal Vx linearly related to the magnitude of the dVS / dt noise and output to the logic control and voltage gating (005) to control the voltage-controlled oscillator (006) to output a frequency-periodic signal linearly related to Vx to control the bootstrap charging control loop (070) to reduce the charge replenishment amount, so that the charge replenishment amount is less than the charge loss amount on Cboot1. The voltage of VB-VS will decrease due to the charge loss on the capacitor Cboot1, and the high-side output signal HO will be lower than VCC, so that the gate-source voltage Vgs of the GaN device remains unchanged during the parasitic capacitance C of the GaN device GDThe charging rate decreases, thereby reducing the falling slope of the voltage difference Vds between the source and drain of the GaN device; if the dVS / dt noise is not detected, the voltage-controlled oscillator (006) is controlled to output the highest frequency, providing sufficient charge quantity for the capacitor Cboot1 to ensure that VB - VS is maintained at VCC; when the low side conducts, since VB1 and VB2 do not function, the voltage-controlled oscillator (006) is controlled to output the lowest frequency periodic signal to reduce the static power consumption.

[0019] Compared with the prior art, the advantages of the present invention are as follows:

[0020] (1) The present invention solves the problem of undervoltage of the bootstrap rail voltage VB - VS that occurs over time due to the continuous conduction of the GaN power upper transistor Mn1 and the problem of excessive dV / dt noise caused by too short a Miller plateau period during the conduction process of Mn1, improving the stability of the drive system.

[0021] (2) The present invention realizes the internal integration of the bootstrap capacitor, and the capacitor does not need to be made very large, saving chip area. At the same time, the number of external pins of the chip is less, and the chip reliability is higher.

[0022] (3) The present invention controls the capacitor Cboot2 to quickly replenish the charge of the bootstrap capacitor Cboot1 through the bootstrap charging control circuit (070), and there is no need to consider the problem of charge loss VB - VS undervoltage on the bootstrap capacitor when the high-side GaN power transistor is turned on for a long time.

[0023] (4) The present invention has a control effect on the undervoltage replenishment speed of VB - VS. When dV / dt noise comes, the replenishment speed can be slowed down, extending the platform time when the GaN power transistor is turned on and keeping V GS unchanged, reducing the dV / dt noise and improving the overall reliability of the drive chip.

[0024] (5) The structure of the present invention is simple. The internal components of the bootstrap voltage control circuit are all ordinary MOS transistors, resistors, capacitors, and diodes, and they are all low-voltage devices, with no special requirements for the process and low implementation difficulty. Description of the Drawings

[0025] Figure 1 is a traditional external bootstrap circuit;

[0026] Figure 2 is a circuit diagram of a specific implementation manner of the bootstrap control circuit proposed by the present invention;

[0027] Figure 3 is a schematic diagram of the Miller plateau when the GaN power transistor conducts;

[0028] Figure 4 is Figure 2Circuit schematic diagram for dV / dt noise detection (004);

[0029] Figure 5 For Figure 2 Circuit diagram for logic control & voltage gating (005) in

[0030] Figure 6 For Figure 2 Circuit diagram for voltage - controlled oscillator (006) in

[0031] Figure 7 Working waveform diagram of traditional external bootstrap circuit;

[0032] Figure 8 Working waveform diagram of the key - node voltage of the present invention;

[0033] Figure 9 For Figure 2 Specific working flowchart of the circuit;

[0034] Figure 10 Schematic diagram of the prior - art current - mode bandgap reference circuit for generating Vmax and Vmin. Specific embodiments

[0035] The principles and features of the present invention will be described below in conjunction with the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0036] As Figure 2 shown, in the prior art Figure 1On the basis of [the original circuit], the present invention additionally provides a bootstrap voltage control circuit (003) including a dVS / dt detection circuit (004), a logic control and voltage gating circuit (005), a voltage-controlled oscillator (006), and a bootstrap charging control loop (070). Among them, the bootstrap charging control loop (070) is jointly constituted by a bootstrap charging circuit (007), diodes D1, D2, and a capacitor Cboot2. The anode of diode D1 is connected to the floating ground VS. The cathode of diode D1, the anode of diode D2, and one end of capacitor Cboot2 are jointly connected to the VB1 terminal. The cathode of diode D2 is connected to the floating voltage VB, that is, the connection end of the cathode of the bootstrap diode D3 and the bootstrap capacitor Cboot1. The anode of the bootstrap diode D3 is connected to VCC. The other end of the bootstrap capacitor Cboot1 is connected to the floating ground VS, that is, the connection end of the source of the high-side GaN power transistor Mn1 and the drain of the low-side GaN power transistor Mn2. The input terminal of the dVS / dt detection circuit (004) is connected to the floating ground VS. The level control signal Vfb output by the dVS / dt detection circuit (004), the voltage signal Vx linearly related to the magnitude of the dVS / dt noise, and the high-side input signal HIN are used as the input signals of the logic control and voltage gating circuit (005). The output signal Vctrl of the logic control and voltage gating circuit (005) is the input signal of the voltage-controlled oscillator (006). The output signal of the voltage-controlled oscillator (006) is an oscillation signal VB2 of 0 to VCC, which is connected to the other end of the capacitor Cboot2 in the bootstrap charging loop (070).

[0037] The above circuit system can replenish the charge on Cboot1 at any time by using the voltage-controlled oscillator (006) without detecting whether VB - VS is under-voltage. When the high-side GaN power transistor is turned on, Cboot12 is used to replenish the charge of Cboot11, and D1 is used to clamp VS to VB1. When the low-side GaN power transistor is turned on, D3 is used to charge Cboot11 to VCC, and D2 is used for isolation protection to prevent VB1 from being overcharged to 2VCC.

[0038] The bootstrap charging control circuit (070) is used to charge the bootstrap capacitor Cboot1 in a timely manner when the voltage of the bootstrap rail voltage VB - VS decreases, preventing the under-voltage of VB - VS. When the Miller plateau phenomenon occurs during the driving of the GaN device, the control circuit reduces the efficiency of the bootstrap charging circuit to supplement the VB - VS voltage in a timely manner, extends the time of the plateau period, and reduces the noise of dVS / dt. After the system power is turned on, the capacitor Cboot2 is charged to VCC and is ready to charge the capacitor Cboot1 at any time. When VS is 0, VB is charged to VCC by D3; D2 is used to isolate the capacitors Cboot1 and Cboot2 to prevent the VB - VS from being charged to twice VCC when VS is 0, which may damage the devices in the high-side circuit. When VS is between 0 and Vin, D1 is used to clamp the voltage of VB1 so that the potential of VB1 remains near VS to VS + VCC. Once the voltage of VB is too low, D2 conducts forwardly, and the VB - VS voltage is supplemented. When the high-side input signal HIN flips to high, the logic control and voltage gating circuit (005) is activated. When HIN is transmitted to HO to drive the high-side GaN device Mn1, the dVS / dt detection circuit (004) transmits the detected noise signal to the logic control and voltage gating circuit (005), which outputs a voltage signal linearly related to the noise signal. If the dVS / dt signal is not detected, the highest output voltage Vmax is output; if the voltage gating module is not activated, the lowest output voltage Vmin is output. The output voltage of the logic control and voltage gating circuit (005) determines the oscillation frequency of the voltage-controlled oscillator (006). Cboot2 supplements charge to Cboot1 according to this frequency, thereby determining the efficiency of supplementing the VB - VS voltage through Cboot2.

[0039] If the high-side GaN output power device is not conducting, no dVS / dt noise will be generated, and the dVS / dt noise detection circuit (004) always outputs a fixed-level signal. When the dVS / dt noise comes, the dVS / dt detection circuit (004) outputs a level signal Vx linearly related to the noise. The logic control & voltage gating (005) is logically controlled by the level signals HIN and Vfb. When the low-side GaN power transistor conducts, the lowest voltage Vmin is output. When the high-side GaN power transistor conducts and the dVS / dt noise is detected, the voltage VC linearly related to the noise is output. When the high-side GaN power transistor conducts but the dVS / dt noise is not detected, the highest voltage Vmax is output. Only one of the three voltages is output in different states and is connected to the voltage-controlled oscillator (006).

[0040] The voltage-controlled oscillator (006) can output periodic signals ranging from the MHz level to the hundreds of MHz level, corresponding to the three output states of the above-mentioned logic control & voltage gating (005):

[0041] When the input voltage is Vmin, the output periodic signal frequency is only at the MHz level; when the input voltage is Vmax, the output periodic signal frequency is at the hundreds of MHz level; when the input voltage is Vx, the input periodic frequency is between the former two, and the frequency is linearly related to the input voltage value. The input of the bootstrap charging circuit (007) is connected to the output of the voltage-controlled oscillator (006), and the output is connected to the upper plate of the bootstrap capacitor Cboot1. Ignoring the conduction voltage drops of D1, D2, and D3, when the low-side GaN output power transistor conducts, the VS voltage is 0, the VB voltage is VCC, and when there is a charge loss on the bootstrap capacitor Cboot11, VCC will directly charge the capacitor Cboot1; at this time, the voltage range of VB1 is 0 to VCC. Since D2 plays an isolation and protection role, the voltage change of VB1 will not affect VB; when the high-side GaN output power transistor conducts, VS will rise to Vin, and VB will also rise to Vin + VCC. At this time, D3 is reverse cut-off to protect VCC; VB1 is clamped by VS, and the voltage change range is VS to VS + VCC. When the VB - VS voltage is under-voltage, D2 conducts forward, and the capacitor Cboot2 replenishes the charge of the capacitor Cboot1 to ensure that there is no under-voltage situation for VB - VS.

[0042] Figure 3It is a schematic diagram of the inevitable Miller plateau during the device conduction. The abscissa represents the voltage value of the high-side output HO, and the ordinate represents the voltage / current values of each parameter. During the time period t1, HO rises to the threshold voltage of the GaN device. The drain current IDS rises from 0 to the stable load current from the end of t1 to the start of t3, and the gate-source voltage Vgs rises to the Miller plateau voltage VGP as HO increases. During the time period t3, Vgs remains at the plateau voltage, and the drain-source voltage Vds begins to drop to the forward conduction voltage VF. After the time period t3, Vgs continues to rise to VCC. The reason for this phenomenon is that there are gate-source parasitic capacitance Cgs and gate-drain parasitic capacitance Cgd on the GaN device. The transient capacitance value of the parasitic capacitance is related to the product of the capacitance and the voltage. Before t3, Cgs is much larger than Cgd. Therefore, the rising slope of Cgs in this time period is mainly determined by Cgs, and Vgs rapidly rises as HO increases. When t3 starts, the change in Vgd causes the capacitance value of Cgd to increase, resulting in a rapid increase in the capacitance charging current. Most of the current of HO is used to charge Cgd, and almost no current flows to Cgs. Therefore, Vgs remains at the plateau voltage Vgp until the end of t3. When Vds drops to near 0 and no longer changes, Cgd no longer needs to be charged, and the current of HO all rushes to Cgs again, and Vgs rises as usual until it approaches VCC. It is worth noting in the change of this Miller plateau that the rapid drop of Vds during the time period t3 is exactly the time when VS rapidly rises, that is, the slope of the drop of Vds represents the value of dVS / dt noise. Appropriately extending t3 can reduce the dVS / dt noise and control it within a reasonable range.

[0043] Figure 4 It is a schematic diagram of an embodiment of the dVS / dt detection circuit (004), which includes a differential circuit, a current comparator, and a proportional operational amplifier. The differential circuit utilizes the characteristic of capacitor C1 to convert the change slope of VS into the magnitude of current, and then converts it into a voltage value through the MOS diode structure of N2. A voltage V2 linearly related to the change slope of VS is output through the two current mirror structures of N2, N3 and P1, P2, and a voltage Vx linearly related to the magnitude of the noise is output through the proportional operational amplifier composed of the operational amplifier, R2, and R3. The current mirror structures of N2, N4 and P3, P5 and the current mirror structures of P6, P7 and N5, N6 form a current comparator, which outputs a switching signal Vfb for judging the magnitude of the change slope of the VS voltage to judge whether the dVS / dt noise arrives. Among them, P8 and X1, X2 form a hysteresis effect.

[0044] Figure 5It is the schematic diagram of the logic control & voltage gating circuit embodiment (005). It includes a simple delay circuit, three NOT gates, one OR gate, one three-input AND gate, and three transmission gates. HIN and Vfb are respectively connected to the gates of the P transistors of transmission gates GT1, GT2, and GT3 according to the logical relationship formed by the logic gates in the figure. The gates of the N transistors of the three transmission gates are commonly grounded. The input of GT1 is connected to the external input signal Vmin, the input of GT2 is connected to the external input signal Vmax, the input of GT3 is connected to the external input signal Vx, and the outputs of GT1, GT2, and GT3 are all connected to the output terminal Vctrl. In this way, it can respectively correspond to the output signals in three states: the high side is not conducting, the high side is conducting but there is no dVS / dt noise, and the high side is conducting with dVS / dt noise. The three signals are logically controlled in different states, and only one of the signals is output.

[0045] Figure 6 It is the schematic diagram of the circuit embodiment of the voltage-controlled oscillator (006). The output frequency of the voltage-controlled oscillator is related to the input voltage. It includes six PMOS transistors P11 - P16, six NMOS transistors N11 - N16, and five inverters X11 - X15. The input signal Vctrl is connected to the gates of N11, N12, N13, N14, N15, and N16. The gate of N11 is connected to the drain, gate of P11, and the gates of P12, P13, P14, P15, and P16; the drain of P12 is connected to the power supply terminal of inverter X11, and the drain of N12 is connected to the ground terminal of inverter X11; the drain of P13 is connected to the power supply terminal of inverter X12, and the drain of N13 is connected to the ground terminal of inverter X12; the drain of P14 is connected to the power supply terminal of inverter X13, and the drain of N14 is connected to the ground terminal of inverter X13; the drain of P15 is connected to the power supply terminal of inverter X14, and the drain of N15 is connected to the ground terminal of inverter X14; the drain of P16 is connected to the power supply terminal of inverter X15, and the drain of N16 is connected to the ground terminal of inverter X15; the input terminal of X11 is connected to the output terminal of X15; the input terminal of X12 is connected to the output terminal of X11; the input terminal of X13 is connected to the output terminal of X12; the input terminal of X14 is connected to the output terminal of X13; the input terminal of X15 is connected to the output terminal of X14; the output terminal of X15 is VB2. N11 - N16 form a current mirror, and P11 - P16 form a current mirror. Since N11 and P11 are in the same branch, the current values copied by all current mirrors are the same; the magnitude of the Vctrl voltage determines the current of the current mirror, and the current charge and discharge speed determines the output frequency of the voltage-controlled oscillator (006).

[0046] To facilitate the design of the voltage-controlled oscillator using a ring oscillator, the five inverters X1, X2, X3, X4, and X5 have the same parameters, the six transistors N1, N2, N3, N4, N5, and N6 have the same parameters, and the six transistors P1, P2, P3, P4, P5, and P6 have the same parameters. The following given calculation formulas are applicable to any cascaded branch.

[0047] The oscillation frequency calculation formula is as follows:

[0048]

[0049] Where n is the number of cascaded inverters, and n is 5 in the design of the present invention; Idsat is the operating current of the inverter; Co is the output parasitic capacitance of the inverter; Vswing is the differential voltage of the output swing of the inverter, which is the supply voltage VCC in this circuit. The operating current of the inverter is determined by the sizes of N1, N2, N3, N4, N5, and N6, and the current calculation formula is μ is the mobility of the N1, N2, N3, N4, N5, N6 transistors with voltage-controlled input, Cox is the gate oxide capacitance value of the N1, N2, N3, N4, N5, N6 transistors, is the aspect ratio of the N1, N2, N3, N4, N5, N6 transistors, Vth is the threshold of the N1, N2, N3, N4, N5, N6 transistors, and Vctrl is the voltage-controlled input value of the voltage-controlled oscillator. The voltage correspondence is as follows: The voltage value of Vctrl corresponding to the oscillation frequency f = 50kHz of the voltage-controlled oscillator is Vmin; the voltage value of Vctrl corresponding to the oscillation frequency f = 500kHz of the voltage-controlled oscillator is Vmax.

[0050] Figure 7 is the working waveform diagram of the traditional bootstrap voltage control circuit. The diagram shows the voltage change of VB - VS under the traditional bootstrap voltage technology. When the high-side channel is working, VB rises with VS to exceed VCC, Figure 1 the diode D1 in is reverse cut-off, and VCC cannot replenish the charge of the bootstrap capacitor Cboot1. The voltage VB - VS across Cboot1 decreases as the high-side conduction time increases until the high-side channel is closed and the low-side channel is opened, and VB - VS returns to VCC again. Excessive high-side conduction time will cause VB - VS to drop to the undervoltage state. To address this problem, only the longest high-side conduction time can be controlled or the capacitance value of the bootstrap capacitor Cboot1 can be increased, which will limit the application scenarios of the circuit or increase the cost of the chip.

[0051] Figure 8 is the working waveform diagram of the key nodes of the bootstrap voltage control circuit of the present invention. During the T1 time period, the high-side GaN output power transistor is in the normal on state, the VS voltage is Vin, there is no dVS / dt noise, and Vfb is at a low potential. At this time, the logic control and voltage selection circuit outputs the highest voltage Vmax, controls the voltage-controlled oscillator to output the highest frequency periodic waveform, and VB1 replenishes the voltage of VB at the frequency of fMAX. VB is always maintained at VCC + VS; during the T1 - T2 time period, the low-side GaN output power transistor is in the normal on state, Vgs His at 0 potential, VS is grounded and there is no dVS / dt noise. At this time, the potential of VB is VCC, and the power supply VCC can charge Cboot1 through D3. The voltage-controlled oscillator temporarily does not need to perform the function of replenishing charge, so Vctrl is at the lowest potential Vmin, and the fB2 frequency decreases the power consumption; during the time period from T2 to T3, the high-side output HO is high, and the high-side GaN output power transistor starts to conduct, but the Vds of the GaN device has not changed yet, and the potential of VS remains at 0 and does not rise. Vfb, Vctrl, and fB2 maintain the state at the moment of T1 to T2; during the time period from T3 to T4, a Miller plateau appears in the high-side GaN device, Vgs remains unchanged, and the rapid decrease of Vds causes VS to rise. At this time, a signal related to the dVS / dt noise is output when the dVS / dt noise is detected at Vfb. The output of Vctrl starts to decrease, controlling the oscillator to decrease the output frequency fB2. After the voltage replenishment decreases, the VB - VS voltage starts to drop, and the charging current of the gate-drain parasitic capacitance Cgd of the GaN device decreases, and the Miller plateau time is elongated, so the dVS / dt noise is reduced; during the time period from T4 to T5, the decrease of Vds ends, Vgs rises normally, the high-side GaN output power transistor is normally turned on, the potential of VS rises to Vin, Vfb gradually decreases to 0, and Cboot1 lacks the power supply VCC to replenish charge, so the output of Vctrl is the highest voltage Vmax, and the oscillator outputs the highest frequency to replenish the VB - VS voltage to restore to the VCC voltage; the state of the time period from T5 to T6 continues that of the T1 time period, and the voltages of each node work normally. The difference from the traditional bootstrap voltage VB - VS is that except for a period of time from T3 to T4 when the high-side channel just conducts, VB - VS is almost stable at VCC throughout the whole process, that is, there is no situation of undervoltage of the bootstrap voltage VB - VS. The present invention can ensure that the high side can conduct for a long time, and there is no need to increase the capacitance value of the bootstrap capacitor, avoiding the trouble of increasing the layout area and increasing the cost.

[0052] Figure 9 is the method flow chart for the present invention to replenish charge for the bootstrap capacitor Cboot1 and reduce the dVS / dt noise. When the drive circuit works, it judges the working conditions of the high and low sides, so as to control the output frequency of the voltage-controlled oscillator; if the low-side GaN output power transistor of the drive circuit conducts, the voltage-controlled oscillator outputs the lowest frequency signal; if the high-side GaN output power transistor conducts, it judges whether there is dVS / dt noise coming. If there is no dVS / dt noise, it outputs the highest frequency signal; if there is dVS / dt noise coming, it outputs a frequency signal linearly related to the noise, controls the VB - VS voltage, and reduces the dVS / dt noise. Due to the existence of the Miller plateau, VS will quickly rise to Vin during the time period from T3 to T4, bringing dVS / dt noise and posing a hidden danger to the level-shifting circuit. This noise cannot be eliminated fundamentally and must be weakened through design.

[0053] Figure 10 This is the schematic diagram of a current-mode bandgap reference circuit used in the prior art to generate Vmax and Vmin. It includes an operational amplifier OP2, three P-type transistors P21, P22, P23, two PNP bipolar junction transistors BJT1, BJT2, with a device area ratio of 8:1, and five resistors R21, R22, R23, R24, R25. Due to the temperature characteristics of the PN junction of the transistor, we can obtain a current with a positive temperature coefficient a current with a negative temperature coefficient According to the mirror function of the current mirror, a current I with zero temperature coefficient can be obtained out = I 23 + V 22 , and then by adjusting the resistance values of resistors R24, R25, and R26, the desired reference voltages Vmax and Vmin can be output.

[0054]

[0055] Vmax and Vmin are generated by a current-mode bandgap reference circuit to produce a current independent of PVT. By adjusting the resistance value of the load resistor, two offset voltages with different voltage values are generated. The corresponding voltage value-taking method is as follows: The highest oscillation frequency of the voltage-controlled oscillator (006) is greater than or equal to 500 kHz, and the lowest oscillation frequency is less than or equal to 50 kHz. Through the linear relationship formula between the oscillation frequency of the voltage-controlled oscillator (006) and the voltage-controlled input voltage, the voltage value Vmax corresponding to the high oscillation frequency and the voltage value Vmin corresponding to the low oscillation frequency are deduced. The two input voltage values of Vmin and Vmax are determined by the logic control & voltage gating module (005) according to the circuit state to determine whether to output one of Vmin or Vmax to the voltage-controlled input port of the voltage-controlled oscillator (006).

[0056] The above are only the preferred examples of the present invention and are not limited to the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A bootstrap voltage control system for a GaN power transistor to reduce dVS / dt noise, comprising an input stage circuit (001) and an output stage circuit (002). The input stage circuit (001) includes a dead-time control circuit (008), a high-side channel (009), and a low-side channel (010); the output stage circuit (002) includes a drive stage circuit (011) containing a high-side drive circuit and a low-side drive circuit, a power stage circuit (012) containing a high-side GaN power transistor Mn1 and a low-side GaN power transistor Mn2, and a bootstrap charging circuit (007) composed of a bootstrap capacitor C boot1 and a bootstrap diode D3; a high-side input signal HIN and a low-side input signal LIN are respectively connected to two input terminals of the dead-time circuit (008). Two output terminals of the dead-time circuit (008) are respectively connected to input terminals of the high-side channel (009) and the low-side channel (010). The output of the high-side channel (009) is connected to the input terminal of the high-side drive circuit in the drive stage circuit (011). The output signal HO of the high-side drive circuit is connected to the gate of the high-side GaN power transistor Mn1 in the power stage circuit (011). The output of the low-side channel (010) is connected to the input terminal of the low-side drive circuit in the drive stage circuit (011). The output signal LO of the low-side drive circuit is connected to the gate of the low-side GaN power transistor Mn2 in the power stage circuit (012). The low-side channel (010) and the low-side drive circuit in the drive stage circuit (011) are powered by VCC. The high-side channel (009) and the high-side drive circuit in the drive stage circuit (011) are powered by a bootstrap rail voltage VB-VS generated by a bootstrap capacitor Cboot1 and a bootstrap diode D3 in the bootstrap charging circuit (007) from a regulated VCC of a power supply voltage Vin. The high-side reference ground is a floating voltage VS, and the low-side reference ground is GND; It is characterized in that: A bootstrap voltage control circuit (003) is added, which consists of a dVS / dt detection circuit (004), a logic control and voltage gating circuit (005), a voltage-controlled oscillator (006) and a bootstrap charging control loop (070). Among them, the bootstrap charging control loop (070) is jointly composed of a bootstrap charging circuit (007), diodes D1, D2 and a capacitor Cboot2. The anode of diode D1 is connected to the floating ground VS, and the cathode of diode D1, the anode of diode D2 and one end of capacitor Cboot2 are jointly connected to the VB1 terminal. The cathode of diode D2 is connected to the floating voltage VB, that is, the connection end of the cathode of the bootstrap diode D3 and the bootstrap capacitor Cboot1. The anode of the bootstrap diode D3 is connected to VCC, and the other end of the bootstrap capacitor Cboot1 is connected to the floating ground VS, that is, the connection end of the source of the high-side GaN power transistor Mn1 and the drain of the low-side GaN power transistor Mn2; The input terminal of the dVS / dt detection circuit (004) is connected to the floating ground VS. The level control signal Vfb output by the dVS / dt detection circuit (004), the voltage signal Vx linearly related to the magnitude of the dVS / dt noise, and the high-side input signal HIN are used as the input signals of the logic control and voltage gating circuit (005). The output signal Vctrl of the logic control and voltage gating circuit (005) is the input signal of the voltage-controlled oscillator (006). The output signal of the voltage-controlled oscillator (006) is an oscillation signal VB2 of 0 to VCC, which is connected to the other end of the capacitor Cboot2 in the bootstrap charging loop (070); The dVS / dt detection circuit (004) includes a differential circuit, a current comparator and a proportional operational amplifier; the differential circuit converts the voltage change slope of the input signal VS into a corresponding voltage signal, and this voltage signal generates a voltage signal Vx corresponding to the magnitude of the dVS / dt noise through the proportional operational amplifier; the current comparator is used to generate a switching signal for judging the magnitude of the VS voltage change slope, that is, a level control signal Vfb for judging whether the dVS / dt noise arrives; The input signals of the logic control and voltage gating circuit (005) include, in addition to the level control signal Vfb output by the dVS / dt detection circuit (004), the voltage signal Vx linearly related to the magnitude of the dVS / dt noise, and the high-side input signal HIN, two bias voltage signals with different voltage values generated by a current-mode bandgap reference circuit and input externally, defined as the highest voltage Vmax and the lowest voltage Vmin. The logic control and voltage gating circuit (005) includes logic gates, transmission gates, and delay circuits, and is used to correspond to three states: the high-side GaN power transistor is conducting and dVS / dt noise is detected, the high-side GaN power transistor is conducting but dVS / dt noise is not detected, and the low-side GaN power transistor is conducting. The logic control and voltage gating circuit (005) only outputs one of the three states through the logic control of the input level control signal Vfb and the high-side input signal HIN: when the high-side GaN power transistor is conducting and dVS / dt noise is detected, the signal Vctrl output by the logic control and voltage gating circuit (005) is the voltage signal Vx linearly related to the magnitude of the dVS / dt noise; when the high-side GaN power transistor is conducting but dVS / dt noise is not detected, the signal Vctrl output by the logic control and voltage gating circuit (005) is the highest voltage Vmax; when the low-side GaN power transistor is conducting, the signal Vctrl output by the logic control and voltage gating circuit (005) is the lowest voltage Vmin. The frequency of the oscillation signal VB2 output by the voltage-controlled oscillator (006) is related to the input voltage. When the input voltage signal Vctrl is the lowest voltage Vmin, the output period signal frequency is only at the MHz level; when the input voltage signal Vctrl is the highest voltage Vmax, the output period signal frequency is at the hundreds of MHz level; when the input voltage signal Vctrl is the voltage signal Vx linearly related to the magnitude of the dVS / dt noise, the output period frequency is between the former two. In the above structure, a dVS / dt detection circuit (004), logic control and voltage gating (005), and a voltage-controlled oscillator (006) are used to control the oscillation frequency of the oscillation signal VB2 output by the voltage-controlled oscillator (006), thereby indirectly controlling the rate of VB-VS voltage replenishment of the capacitor Cboot2 to the capacitor Cboot1. On the premise of ensuring that the VB-VS voltage meets the normal operating voltage of the high side, the voltage value of VB-VS during the Miller plateau is reduced, and the parasitic capacitance C between the gate and drain of the high-side GaN power transistor Mn1 of the Miller plateau device is reduced. GD The charging current is increased, the residence time of the Miller plateau is extended, and the dVS / dt noise is reduced.

2. The bootstrap voltage control system for a GaN power transistor to reduce dVS / dt noise according to claim 1, characterized in that: The dVS / dt detection circuit (004) includes PMOS transistors P1 to P8, NMOS transistors N2 to N6, resistors R1, R2, and R3, capacitor C1, inverters X1 and X2, current source I, and operational amplifier OP1; one end of capacitor C1 is connected to the floating ground VS, and the other end of capacitor C1 is connected to the drain and gate of NMOS transistor N2, the gate of NMOS transistor N3, and the gate of NMOS transistor N4. The source of NMOS transistor N2 and the source of NMOS transistor N3 are grounded to GND. The drain of NMOS transistor N3 is connected to the drain and gate of PMOS transistor P1 and the gate of PMOS transistor P2. The source of PMOS transistor P1 and the source of PMOS transistor P2 are connected to VCC. The drain of PMOS transistor P2 is connected to one end of resistor R1 and outputs the voltage signal V2. The other end of resistor R1 is grounded to GND. The sources of PMOS transistor P2, PMOS transistor P3, PMOS transistor P4, PMOS transistor P5, PMOS transistor P6, and PMOS transistor P7 are all connected to VCC. The gate and drain of PMOS transistor P3 are interconnected and connected to the drain of NMOS transistor N4, the gate of PMOS transistor P4, and the gate of PMOS transistor P5. The source of NMOS transistor N4 is grounded to GND. The gates of PMOS transistor P6 and PMOS transistor P7 are interconnected and connected to the drain of PMOS transistor P6 and the input end of current source I. The output end of current source I is grounded to GND. The drains of PMOS transistor P7 and PMOS transistor P8 are interconnected and connected to the drain of NMOS transistor N5, the gate of NMOS transistor N5, and the gate of NMOS transistor N6. The sources of NMOS transistor N5 and NMOS transistor N6 are grounded to GND. The drain of NMOS transistor N6 is connected to the drain of PMOS transistor P5 and the input end of inverter X2. The output end of inverter X2 is connected to the input end of inverter X1 and the gate of PMOS transistor P8. The source of PMOS transistor P8 is connected to the drain of PMOS transistor P4. The output of inverter X1 serves as an output end of the dVS / dt detection circuit (004), outputting the level control signal Vfb. One end of resistor R2 is connected to the voltage signal V2. The other end of resistor R2 is connected to the negative terminal of operational amplifier OP1 and one end of resistor R3. The reference voltage Vref is connected to the positive terminal of operational amplifier OP1. The other end of resistor R3 is connected to the output end of operational amplifier OP1 and outputs the voltage signal Vx that is linearly related to the magnitude of the dVS / dt noise.

3. The bootstrap voltage control system for a GaN power transistor to reduce dVS / dt noise according to claim 1, characterized in that: The logic control and voltage gating circuit (005) includes a delay circuit delay, three inverters INV1, INV2, INV3, an OR gate OR1, a three-input AND gate AND1, and three transmission gates GT1, GT2, GT3; the high-side input signal HIN is connected to the input terminal of the delay circuit delay, the input terminal of the inverter INV1, and one input terminal of the three-input AND gate AND1. The level control signal Vfb output by the dVS / dt detection circuit (004) is connected to the input terminal of the inverter INV3 and the gate of the PMOS transistor in the transmission gate GT3. The voltage signal Vx output by the dVS / dt detection circuit (004) that is linearly related to the magnitude of the dVS / dt noise is connected to the input terminal of the transmission gate GT3. The output of the delay circuit delay is connected to the input terminal of the inverter INV2 and one input terminal of the OR gate OR1. The other input terminal of the OR gate OR1 is connected to the output of the inverter INV1. The output terminal of the inverter INV2 is connected to the second input terminal of the three-input AND gate AND1. The output terminal of the inverter INV3 is connected to the third input terminal of the three-input AND gate AND1. The output of the OR gate OR1 is connected to the gate of the PMOS transistor in the transmission gate GT1. The input terminal of the transmission gate GT1 is connected to the lowest voltage Vmin. The output of the three-input AND gate AND1 is connected to the gate of the PMOS transistor in the transmission gate GT2. The input terminal of the transmission gate GT2 is connected to the highest voltage Vmax. The gates of the NMOS transistors in the three transmission gates GT1, GT2, GT3 are commonly grounded to GND. The output terminals of the three transmission gates GT1, GT2, GT3 are interconnected as the output terminal of the logic control and voltage gating circuit (005), and the output voltage signal Vctrl is output.

4. The bootstrap voltage control system for a GaN power transistor to reduce dVS / dt noise according to claim 1, characterized in that: The voltage-controlled oscillator (006) includes six PMOS transistors P11 to P16, six NMOS transistors N11 to N16, and five inverters X11 to X15. The gates of the NMOS transistors N11 to N16 are interconnected and connected to the output voltage signal Vctrl of the logic control and voltage gating circuit (005). The sources of the NMOS transistors N11 to N16 are interconnected and grounded to GND. The drain of the NMOS transistor N11 is connected to the drain of the PMOS transistor P11 and the gates of the PMOS transistors P11 to P16. The sources of the PMOS transistors P11 to P16 are interconnected and connected to VCC. The drain of the PMOS transistor P12 is connected to the power supply terminal of the inverter X11. The drain of the NMOS transistor N12 is connected to the ground terminal of the inverter X11. The drain of the PMOS transistor P13 is connected to the power supply terminal of the inverter X12. The drain of the NMOS transistor N13 is connected to the ground terminal of the inverter X12. The drain of the PMOS transistor P14 is connected to the power supply terminal of the inverter X13. The drain of the NMOS transistor N14 is connected to the ground terminal of the inverter X13. The drain of the PMOS transistor P15 is connected to the power supply terminal of the inverter X14. The drain of the NMOS transistor N15 is connected to the ground terminal of the inverter X14. The drain of the PMOS transistor P16 is connected to the power supply terminal of the inverter X15. The drain of the NMOS transistor N16 is connected to the ground terminal of the inverter X15. The output of the inverter X11 is the input of the inverter X12. The output of the inverter X12 is the input of the inverter X13. The output of the inverter X13 is the input of the inverter X14. The output of the inverter X14 is the input of the inverter X15. The output of the inverter X15 serves as the output terminal of the voltage-controlled oscillator (006), outputting an oscillation signal VB2 and connecting it to the input terminal of the inverter X11.

5. The GaN power transistor bootstrap voltage control system for reducing dVS / dt noise according to claim 4, wherein: The voltage-controlled oscillator (006) adopts a ring oscillator. The five inverters X11, X12, X13, X14, and X15 have the same parameters. The six NMOS transistors N11, N12, N13, N14, N15, and N16 have the same parameters. The six PMOS transistors P11, P12, P13, P14, P15, and P16 have the same parameters.

6. The GaN power transistor bootstrap voltage control system for reducing dVS / dt noise according to claim 1, wherein: The capacitance values of the bootstrap capacitor Cboot1 and the capacitor Cboot2 are both in the pF range, and Cboot2 < Cboot1.

7. The GaN power transistor bootstrap voltage control system for reducing dVS / dt noise according to any one of claims 1 to 6, wherein: The system under-voltage charging control process is as follows: When the low-side output signal LO is at a high level and the power transistor Mn2 is turned on, VS is at 0 potential, VCC charges the capacitor Cboot1, and VB is charged to VCC; at this time, the potential of VB2 is 0 to VCC, VB1 is affected by the clamping of VS, and the voltage change range is 0 to VCC. The diode D2 makes VB1 and VB not interfere with each other, and VB is stably maintained at VCC; when the high-side output signal HO is at a high level and the power transistor Mn1 is turned on, the voltage change range of VS is 0 to Vin. The voltage across the capacitor Cboot1 cannot change suddenly, and the change range of VB increases with VS to VS~VS + VCC; at this time, the voltage change range of VB1 is VS~VS + VCC; when the power transistor Mn1 is turned on for a long time, the charge of the capacitor Cboot1 cannot be replenished and will gradually be lost, and the voltage of VB - VS will gradually decrease and even affect the normal operation of the high-side output power transistor. Therefore, when the voltage of VB - VS decreases, the capacitor Cboot2 replenishes the charge of the capacitor Cboot1 in time to ensure that the voltage of VB - VS is stably maintained at VCC; The process of the system controlling dVS / dt noise is as follows: When the GaN high-side output power transistor Mn1 conducts, it encounters a Miller plateau. During the Miller plateau, the voltage between the source and drain of the GaN device will rapidly decrease, that is, the floating voltage VS will rapidly rise. The too-fast rising speed causes dVS / dt noise. Prolonging the duration of the plateau period can reduce dVS / dt noise. The behavior of the capacitor Cboot2 to replenish the charge of the capacitor Cboot1 is achieved by raising VB1 to VS + VCC through the periodic signal output by the voltage-controlled oscillator (006). Reducing the output frequency of the voltage-controlled oscillator (006), that is, reducing the amount of charge replenished by the capacitor Cboot2 to the capacitor Cboot1 per unit time, can control the VB - VS voltage value; when the high side conducts, when the dVS / dt detection (004) detects dVS / dt noise, the noise signal will be converted into a voltage signal Vx linearly related to the magnitude of the dVS / dt noise and output to the logic control and voltage gating (005), controlling the voltage-controlled oscillator (006) to output a frequency period signal linearly related to Vx to control the bootstrap charging control loop (070) to reduce the charge replenishment amount, so that the charge replenishment amount is less than the charge loss amount on Cboot1, and the VB - VS voltage will decrease due to the charge loss on the capacitor Cboot1, and the high-side output signal HO will be lower than VCC, so that the charging rate of the parasitic capacitor C of the GaN device decreases during the period when the gate-source voltage Vgs of the GaN device remains unchanged, thereby reducing the falling slope of the voltage difference Vds between the source and drain of the GaN device; if dVS / dt noise is not detected, the voltage-controlled oscillator (006) is controlled to output the highest frequency to provide sufficient charge for the capacitor Cboot1 to ensure that VB - VS is maintained at VCC; when the low side conducts, since VB1 and VB2 do not play a role, the voltage-controlled oscillator (006) is controlled to output the lowest frequency period signal to reduce the static power consumption. DS When the GaN high-side output power transistor Mn1 conducts, it encounters a Miller plateau. During the Miller plateau, the voltage between the source and drain of the GaN device will rapidly decrease, that is, the floating voltage VS will rapidly rise. The too-fast rising speed causes dVS / dt noise. Prolonging the duration of the plateau period can reduce dVS / dt noise. The behavior of the capacitor Cboot2 to replenish the charge of the capacitor Cboot1 is achieved by raising VB1 to VS + VCC through the periodic signal output by the voltage-controlled oscillator (006). Reducing the output frequency of the voltage-controlled oscillator (006), that is, reducing the amount of charge replenished by the capacitor Cboot2 to the capacitor Cboot1 per unit time, can control the VB - VS voltage value; when the high side conducts, when the dVS / dt detection (004) detects dVS / dt noise, the noise signal will be converted into a voltage signal Vx linearly related to the magnitude of the dVS / dt noise and output to the logic control and voltage gating (005), controlling the voltage-controlled oscillator (006) to output a frequency period signal linearly related to Vx to control the bootstrap charging control loop (070) to reduce the charge replenishment amount, so that the charge replenishment amount is less than the charge loss amount on Cboot1, and the VB - VS voltage will decrease due to the charge loss on the capacitor Cboot1, and the high-side output signal HO will be lower than VCC, so that the charging rate of the parasitic capacitor C of the GaN device decreases during the period when the gate-source voltage Vgs of the GaN device remains unchanged, thereby reducing the falling slope of the voltage difference Vds between the source and drain of the GaN device; if dVS / dt noise is not detected, the voltage-controlled oscillator (006) is controlled to output the highest frequency to provide sufficient charge for the capacitor Cboot1 to ensure that VB - VS is maintained at VCC; when the low side conducts, since VB1 and VB2 do not play a role, the voltage-controlled oscillator (006) is controlled to output the lowest frequency period signal to reduce the static power consumption. GD When the GaN high-side output power transistor Mn1 conducts, it encounters a Miller plateau. During the Miller plateau, the voltage between the source and drain of the GaN device will rapidly decrease, that is, the floating voltage VS will rapidly rise. The too-fast rising speed causes dVS / dt noise. Prolonging the duration of the plateau period can reduce dVS / dt noise. The behavior of the capacitor Cboot2 to replenish the charge of the capacitor Cboot1 is achieved by raising VB1 to VS + VCC through the periodic signal output by the voltage-controlled oscillator (006). Reducing the output frequency of the voltage-controlled oscillator (006), that is, reducing the amount of charge replenished by the capacitor Cboot2 to the capacitor Cboot1 per unit time, can control the VB - VS voltage value; when the high side conducts, when the dVS / dt detection (004) detects dVS / dt noise, the noise signal will be converted into a voltage signal Vx linearly related to the magnitude of the dVS / dt noise and output to the logic control and voltage gating (005), controlling the voltage-controlled oscillator (006) to output a frequency period signal linearly related to Vx to control the bootstrap charging control loop (070) to reduce the charge replenishment amount, so that the charge replenishment amount is less than the charge loss amount on Cboot1, and the VB - VS voltage will decrease due to the charge loss on the capacitor Cboot1, and the high-side output signal HO will be lower than VCC, so that the charging rate of the parasitic capacitor C of the GaN device decreases during the period when the gate-source voltage Vgs of the GaN device remains unchanged, thereby reducing the falling slope of the voltage difference Vds between the source and drain of the GaN device; if dVS / dt noise is not detected, the voltage-controlled oscillator (006) is controlled to output the highest frequency to provide sufficient charge for the capacitor Cboot1 to ensure that VB - VS is maintained at VCC; when the low side conducts, since VB1 and VB2 do not play a role, the voltage-controlled oscillator (006) is controlled to output the lowest frequency period signal to reduce the static power consumption.

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