A hybrid gate drive circuit

Abstract

A hybrid gate drive circuit, comprising a power supply circuit, a turn-on and turn-off circuit, a signal input circuit and a MOSFET device; the turn-on and turn-off circuit is connected with the MOSFET device, can receive a turn-on signal and a turn-off signal, turn on the MOSFET device in a voltage source driving mode according to the turn-on signal, and turn off the MOSFET device in a current source driving mode according to the turn-off signal; the signal input circuit is connected with the turn-on and turn-off circuit, and the power supply circuit supplies power to the MOSFET device, the turn-on and turn-off circuit and the signal input circuit. The turn-on and turn-off circuit of the present disclosure can receive a turn-on signal and a turn-off signal, turn on the MOSFET device in a voltage source driving mode according to the turn-on signal, and turn off the MOSFET device in a current source driving mode according to the turn-off signal, so that the MOSFET device can be used normally at a higher temperature, the turn-on and turn-off losses of the MOSFET are reduced, the switching loss is as low as possible, and the efficiency and reliability of the MOSFET can be improved.

Description

Technical Field

[0001] This disclosure belongs to the field of power electronics technology, and specifically relates to a hybrid gate drive circuit. Background Technology

[0002] Silicon carbide (SiC) power device driver integrated chips utilize silicon-based MOSFETs (metal-oxide-semiconductor field-effect transistors). These chips incorporate detection and protection circuits for unsafe operating conditions such as overvoltage, undervoltage, and overcurrent. Their switching frequencies can reach several hundred kHz, meeting the high-frequency operation requirements of SiC MOSFETs. However, these integrated chips cannot operate above 150°C. Above 150°C, the switching characteristics of the internal components are severely affected, failing to meet high-temperature performance requirements. Using integrated chips to drive SiC MOSFETs at high temperatures would limit their application in such environments due to driving limitations. Furthermore, there are currently no high-performance SiC-based integrated chips on the market. Chips designed for high-temperature environments primarily utilize silicon-on-insulator (SiI) technology, but these are extremely expensive, costing several times more than SiC power devices, significantly increasing the cost of the drive circuit. Therefore, improvements are needed to address the high-temperature driving conditions of SiC power devices. Summary of the Invention

[0003] In order to solve at least one of the above-mentioned technical problems, the present disclosure aims to provide a hybrid gate drive circuit that can avoid the adverse effects of high temperature of integrated chips, drive the turn-on process with voltage and the turn-off process with current, so that the switching loss decreases more and faster as the temperature rises, thereby improving the efficiency and reliability of MOSFET.

[0004] To achieve the objectives of this disclosure, the technical solution adopted is as follows:

[0005] A hybrid gate drive circuit, comprising:

[0006] MOSFET devices are used as actuators to turn external circuits on or off.

[0007] The turn-on and turn-off circuit connected to the MOSFET device is capable of receiving a turn-on signal and a turn-off signal, turning on the MOSFET device in a voltage source-driven manner according to the turn-on signal, and turning off the MOSFET device in a current source-driven manner according to the turn-off signal.

[0008] A signal input circuit connected to the on / off circuit is capable of sending the on signal or the off signal to the on / off circuit;

[0009] A power supply circuit is used to supply power to the MOSFET device, the turn-on / turn-off circuit, and the signal input circuit.

[0010] Optionally, the turn-on / turn-off circuit includes:

[0011] A turn-on circuit is provided, wherein the signal input circuit is connected to the MOSFET device through the turn-on circuit, and the turn-on circuit is capable of receiving the turn-on signal and turning on the MOSFET device in a voltage source-driven manner according to the turn-on signal;

[0012] A shutdown circuit is provided, wherein the signal input circuit is connected to the MOSFET device through the shutdown circuit, and the shutdown circuit is capable of receiving the shutdown signal and turning off the MOSFET device in a current-source driven manner according to the shutdown signal.

[0013] Optionally, the turn-on circuit includes a fourth transistor, a sixth transistor, and a twelfth resistor;

[0014] The base of the fourth transistor is connected to the output terminal of the signal input circuit, the emitter of the fourth transistor is connected to the base of the sixth transistor, the collectors of the fourth transistor and the sixth transistor are both connected to the power supply circuit, and the emitter of the sixth transistor is connected to the gate of the MOSFET device through the twelfth resistor.

[0015] Optionally, the shutdown circuit includes a fifth transistor and multiple parallel field-effect transistor circuits;

[0016] Each of the aforementioned field-effect transistor circuits includes a protection resistor and a field-effect transistor;

[0017] The base of the fifth transistor is connected to the output terminal of the signal input circuit, the collector of the fifth transistor is grounded, the emitter of the fifth transistor is connected to the source of the field-effect transistor through the protection resistor, the emitter of the fifth transistor is also connected to the gate of the field-effect transistor, and the drain of the field-effect transistor is connected to the gate of the MOSFET device.

[0018] Optionally, the power supply circuit includes a first resistor, a first diode, a second diode, a power supply VCC, a first power supply terminal, and a second power supply terminal;

[0019] The power supply VCC is connected to the turn-on / turn-off circuit and the signal input circuit respectively after passing through the first power supply terminal;

[0020] The power supply VCC is connected to the signal input circuit and the MOSFET device in sequence through the first resistor, the first diode, and the second power supply terminal.

[0021] The second power supply terminal is also grounded through the second diode.

[0022] Optionally, the signal input circuit includes:

[0023] The transmitting circuit can convert analog control signals into digital signals;

[0024] The receiving circuit is connected to the transmitting circuit and is capable of receiving the digital signal and restoring the digital signal to the control analog signal.

[0025] An amplifier circuit, connected to a receiving circuit, is used to convert the control analog signal restored by the receiving circuit into the turn-on signal or turn-off signal.

[0026] Optionally, the amplifier circuit includes an eleventh resistor and a third transistor;

[0027] The first power supply terminal of the power supply circuit is connected to one end of the eleventh resistor;

[0028] The collector of the third transistor is connected to the other end of the eleventh resistor and the turn-on / turn-off circuit. The base of the third transistor is electrically connected to the receiving circuit. The emitter of the third transistor is grounded.

[0029] Optionally, the transmitting circuit includes a PWM signal generator, a second resistor, a third resistor, and a first transformer;

[0030] One end of the PWM signal generator is grounded, and the other end of the PWM signal generator is connected to one end of the primary winding of the first transformer through the second resistor. The other end of the primary winding of the first transformer is grounded through the third resistor.

[0031] One end and the other end of the secondary winding of the first transformer are both connected to the receiving circuit.

[0032] Optionally, the receiving circuit includes a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a third diode, a fourth diode, a fifth diode, a first transistor, and a second transistor.

[0033] One output terminal of the signal input circuit is connected to one end of the fourth resistor and the positive terminal of the third diode, respectively; the other output terminal of the signal input circuit is connected to one end of the fifth resistor and the positive terminal of the fourth diode, respectively.

[0034] The base of the first transistor is connected to one end of the seventh resistor and the negative terminal of the third diode, respectively; the collector of the first transistor is connected to one end of the sixth resistor and one end of the eighth resistor, respectively.

[0035] The base of the second transistor is connected to the other end of the sixth resistor and the cathode of the fourth diode, respectively. The collector of the second transistor is connected to the other end of the seventh resistor, one end of the ninth resistor, and one end of the tenth resistor, respectively.

[0036] The emitter of the first transistor, the emitter of the second transistor, the other end of the fourth resistor, and the other end of the fifth resistor are all grounded;

[0037] The second power supply terminal is connected to the other end of the eighth resistor and the other end of the ninth resistor respectively through the fifth diode;

[0038] The other end of the tenth resistor is connected to the amplifier circuit.

[0039] Optionally, the receiving circuit further includes a first capacitor, a second capacitor, and a third capacitor;

[0040] The negative terminal of the fifth diode is grounded through the first capacitor, the second power supply terminal is grounded through the second capacitor, and the first power supply terminal is connected to the second power supply terminal through the third capacitor.

[0041] The advantage of this disclosure is that, under the drive of both voltage source and current source gate drive circuits, the turn-on loss of the MOSFET device decreases with increasing temperature, and under the same conditions, the turn-on loss of the MOSFET device driven by the voltage source gate drive circuit decreases faster with increasing temperature. Therefore, the turn-on loss is relatively low when the MOSFET device is turned on by voltage source drive.

[0042] Voltage source gate drive circuits drive MOSFET devices with a positive temperature coefficient of turn-off loss, while current source gate drive MOSFET devices have a negative temperature coefficient of turn-off loss; therefore, when turning off MOSFET devices by current source drive, the turn-off loss is relatively low.

[0043] The present disclosure discloses an on / off circuit capable of receiving an on signal and an off signal, turning on the MOSFET device in a voltage source-driven manner according to the on signal, and turning off the MOSFET device in a current source-driven manner according to the off signal.

[0044] This disclosure enables MOSFET devices to operate normally at higher temperatures, reduces MOSFET turn-on and turn-off losses, minimizes switching losses, and improves MOSFET efficiency and reliability. Attached Figure Description

[0045] The accompanying drawings illustrate exemplary embodiments of the present disclosure and, together with the description thereof, serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.

[0046] Figure 1 This is a circuit diagram of the hybrid gate drive circuit disclosed herein.

[0047] Figure 2 This is a schematic diagram of the voltage and current waveforms at different times during the turn-on process of the hybrid gate drive circuit disclosed herein.

[0048] Figure 3 The waveforms of the gate-source voltage during the turn-on process of the hybrid gate drive circuit disclosed herein and the drive circuit of the prior art are compared at 175°C.

[0049] Figure 4 The waveforms of the drain-source voltages of the hybrid gate drive circuit disclosed herein and the drive circuits of the prior art are compared at 175°C during the turn-on process.

[0050] Figure 5 The comparison shows the gate current waveforms during the turn-on process of the hybrid gate drive circuit disclosed herein and the drive circuit of the prior art at 175°C.

[0051] Figure 6 The waveforms of the drain current during the turn-on process of the hybrid gate drive circuit disclosed herein and the drive circuit of the prior art are compared at 175°C.

[0052] Figure 7 This is a schematic diagram of the voltage and current waveforms at different times during the turn-off process of the hybrid gate drive circuit disclosed herein.

[0053] Figure 8 The comparison shows the gate-source voltage waveforms of the hybrid gate drive circuit disclosed herein and the drive circuit of the prior art during the turn-off process at 175°C.

[0054] Figure 9 The comparison shows the drain-source voltage waveforms of the hybrid gate drive circuit disclosed herein and the drive circuit of the prior art during the turn-off process at 175°C.

[0055] Figure 10 The comparison shows the gate current waveforms of the hybrid gate drive circuit disclosed herein and the drive circuits of the prior art during the turn-off process at 175°C.

[0056] Figure 11 The comparison shows the drain current waveforms of the hybrid gate drive circuit disclosed herein and the drive circuits of the prior art during the turn-off process at 175°C. Detailed Implementation

[0057] The present disclosure will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present disclosure are shown in the accompanying drawings.

[0058] It should be noted that, where there is no conflict, the embodiments and features described in this disclosure can be combined with each other. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0059] Voltage source drive is a driving method that charges the gate charge of power devices using a regulated (or adjustable) voltage. Current source drive, on the other hand, charges the gate charge using an internal constant current source (or adjustable current).

[0060] Under both voltage and current source drive, the turn-on loss of MOSFET device 1 decreases with increasing temperature. Furthermore, under the same conditions, the turn-on loss of the voltage source-driven gate drive circuit for MOSFET device 1 decreases more rapidly with increasing temperature. Therefore, the turn-on loss is relatively low when MOSFET device 1 is driven by a voltage source. Under voltage source drive, the turn-off loss of MOSFET device 1 has a positive temperature coefficient, while the turn-off loss of the current source-driven MOSFET device 1 has a negative temperature coefficient. Therefore, the turn-off loss is relatively low when MOSFET device 1 is driven by a current source.

[0061] For the reasons described above, this disclosure provides an exemplary hybrid gate drive circuit, including a MOSFET device 1, a turn-on / turn-off circuit 2, a signal input circuit 3, and a power supply circuit 4; the signal input circuit 3 is connected to the turn-on / turn-off circuit 2, the turn-on / turn-off circuit 2 is connected to the MOSFET device 1, and the power supply circuit 4 is connected to the turn-on / turn-off circuit 2, the signal input circuit 3, and the power supply circuit 4, respectively; wherein...

[0062] Power supply circuit 4 supplies power to MOSFET device 1, turn-on / turn-off circuit 2, and signal input circuit 3. The power supply circuit can provide one or more different voltage levels to power other operating circuits.

[0063] The signal input circuit 3 can send an on signal or a off signal to the on / off circuit 2; the signal input circuit 3 can output a digital signal or an analog signal, and the input signal can be a carrier input signal, a photoelectric input signal, etc.; the on signal is used to turn on the MOSFET device 1, and the off signal is used to turn off the MOSFET device 1.

[0064] MOSFET device 1 serves as the actuator for turning on or off external circuits; MOSFET device is a metal-oxide-semiconductor field-effect transistor, which can be an N-type MOSFET device, a P-type MOSFET device, a SiC MOSFET, or a Si MOSFET, etc.; the model can be SCT30N120, SCT3030ALHR, SCT3017AL, SCT2120AF, SCT3017ALHR, SCT3022AL, etc.

[0065] The turn-on / turn-off circuit 2 can receive turn-on signals and turn-off signals. When a turn-on signal is received, the MOSFET device 1 is turned on by a voltage source drive according to the turn-on signal; when a turn-off signal is received, the MOSFET device 1 is turned off by a current source drive according to the turn-off signal.

[0066] In one embodiment, the power supply circuit 4 includes a first resistor R1, a first diode D1, a second diode D1, a power supply VCC, a first power supply terminal, and a second power supply terminal; multiple power supply terminals are used to output different voltages. The power supply VCC is connected to the on / off circuit 2 and the signal input circuit 3 after passing through the first power supply terminal; the power supply VCC is connected to the signal input circuit 3 and the MOSFET device 1 after passing through the first resistor, the first diode, and the second power supply terminal in sequence; the second power supply terminal is also grounded after passing through the second diode.

[0067] In this embodiment, the first diode D1 is a 20V Zener diode, and the second diode D2 is a 5V Zener diode. Both types of Zener diodes should have high temperature resistance and low forward voltage. The power supply circuit 4 uses a 25V power supply VCC, providing 20V and 5V voltages through a 20V Zener diode and a 5V Zener diode connected in series for the drive circuit. When turned on, the MOSFET device's gate is connected to +25V and its source is connected to +5V, thus generating a +20V turn-on gate drive voltage; when turned off, the MOSFET device's gate is connected to 0V and its source is connected to +5V, thus generating a -5V SMOSFET gate drive voltage.

[0068] In one embodiment, the signal input circuit 3 includes a transmitting circuit 31, a receiving circuit 32, and an amplifying circuit 33: the transmitting circuit 31 can convert the analog control signal into a digital signal; the receiving circuit 32 is connected to the transmitting circuit 31, and can receive the digital signal and restore the digital signal back to the analog control signal; the amplifying circuit 33 is connected to the receiving circuit 32, and is used to convert the analog control signal restored by the receiving circuit 32 into the on or off signal.

[0069] The transmitting circuit 31 in this disclosure specifically includes a PWM signal generator, a second resistor R2, a third resistor R3, and a first transformer T1. One end of the PWM signal generator is grounded, and the other end of the PWM signal generator is connected to one end of the primary winding of the first transformer T1 through the second resistor R2. The other end of the primary winding of the first transformer T1 is grounded through the third resistor R3. One end and the other end of the secondary winding of the first transformer T1 are both connected to the receiving circuit 32. The transmitting circuit 31, consisting of the primary winding of the first transformer T1 and a pair of resistors forming an RL differentiating circuit, can convert a 0 / 5V PWM square wave signal into a pulse signal. The transmitting circuit 31 can convert the PWM on / off signal into a pulse signal. The pulse signal has strong anti-interference capability when transmitted over long distances.

[0070] In this disclosure, the receiving end circuit 32 is mainly used to restore the pulse signal into an on or off signal; the receiving end circuit 32 specifically includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a tenth resistor R10. 10 Diodes D3, D4, D5, Q1, Q2;

[0071] The second power supply terminal is connected to the other end of the eighth resistor and the other end of the ninth resistor respectively through the fifth diode, serving as a power input.

[0072] One output terminal of the signal input circuit 3 is connected to one end of the fourth resistor R4 and the positive terminal of the third diode D3, respectively; the other output terminal of the signal input circuit 3 is connected to one end of the fifth resistor R5 and the positive terminal of the fourth diode D4, respectively; used to receive signals from the transmitting circuit 31.

[0073] In addition, the base of the first transistor Q1 is connected to one end of the seventh resistor R7 and the cathode of the third diode D3, respectively, and the collector of the first transistor Q1 is connected to one end of the sixth resistor R6 and one end of the eighth resistor R8, respectively.

[0074] The base of the second transistor Q2 is connected to the other end of the sixth resistor R6 and the cathode of the fourth diode D4, respectively. The collector of the second transistor Q2 is connected to the other end of the seventh resistor R7, one end of the ninth resistor R9, and the tenth resistor R... 10 One end is connected,

[0075] The emitter of the first transistor Q1, the emitter of the second transistor, the other end of the fourth resistor, and the other end of the fifth resistor are all grounded;

[0076] The other end of the tenth resistor is connected to the amplifier circuit 33 as the output terminal of the transmitter circuit 31.

[0077] The receiving circuit 32 receives pulses through two symmetrical resistors, R4 and R5. Then, the pulses are converted into PWM waves by the circuit structure consisting of transistors Q1 and Q2 and resistors. When the upper end of the secondary winding of the first transformer T1 is positive and the lower end is negative, transistor Q1 is turned on and transistor Q2 is turned off. The output of the secondary winding of the first transformer T1 is connected to the power supply voltage, thus providing a high-level output to the next stage. If the upper end of the secondary winding of the first transformer T1 is negative and the lower end is positive, transistor Q1 is turned off and transistor Q2 is turned on, connecting the output voltage to ground and providing a low-level output to the next stage. After the pulse ends, resistors R6, R7, R8, and R9 maintain the output state of the secondary winding of the first transformer T1, thus converting the pulse signal into a PWM wave.

[0078] In order to filter the power supply, the receiving circuit 32 also includes a first capacitor C1, a second capacitor C2 and a third capacitor C3; the negative terminal of the fifth diode D5 is grounded through the first capacitor C1, the second power supply terminal is grounded through the second capacitor C2, and the first power supply terminal is connected to the second power supply terminal through the third capacitor C3.

[0079] In this disclosure, the amplifier circuit 33 specifically includes an eleventh resistor R. 11 With the third transistor D3;

[0080] The first power supply terminal of the power supply circuit 4 is connected to the eleventh resistor R. 11 One end is connected;

[0081] The collector of the third transistor D3 and the eleventh resistor R 11 The other end is connected to the turn-on / turn-off circuit 2. The base of the third transistor D3 is electrically connected to the other end of the tenth resistor in the receiving circuit 32 to receive the turn-on and turn-off signals of the PWM wave. The emitter of the third transistor D3 is grounded.

[0082] The function of amplifier circuit 33 is to amplify the low-voltage PWM wave restored by receiver circuit 32 and convert its voltage to 0 / +25V to ground. When receiver circuit 32 outputs a high level to amplifier circuit, the third transistor Q3 is turned on, outputting a low level of 0V to ground to the next stage; when receiver circuit 32 outputs a low level to amplifier circuit, the third transistor Q3 is turned off, outputting a high level of 25V to ground to the next stage.

[0083] In another embodiment, the turn-on / turn-off circuit 2 includes a turn-on circuit 21 and a turn-off circuit 22: the signal input circuit 3 is connected to the MOSFET device 1 through the turn-on circuit 21, the turn-on circuit 21 is capable of receiving the turn-on signal and turning on the MOSFET device 1 in a voltage source driven manner according to the turn-on signal; the signal input circuit 3 is connected to the MOSFET device 1 through the turn-off circuit 22, the turn-off circuit 22 is capable of receiving the turn-off signal and turning off the MOSFET device 1 in a current source driven manner according to the turn-off signal.

[0084] In this disclosure, the turn-on circuit 21 specifically includes a fourth transistor Q4, a sixth transistor Q6, and a twelfth resistor R. 12 ;

[0085] The base of the fourth transistor Q4 is connected to the collector of the third transistor Q3 to receive the amplified signal. The emitter of the fourth transistor Q4 is connected to the base of the sixth transistor Q6. The collectors of both the fourth transistor Q4 and the sixth transistor Q6 are connected to the power supply circuit 4. The emitter of the sixth transistor Q6 is connected to the twelfth resistor R. 12 It is connected to the gate of the MOSFET device 1.

[0086] When the turn-on circuit 21 receives a high-level output from the amplifier circuit, the fourth transistor Q4 and the sixth transistor Q6 are turned on, the fifth transistor Q5 in the turn-off circuit 22 is turned off, the gate of the MOSFET device 1 becomes high, and the power supply circuit 4 is powered through the fourth transistor Q4, the sixth transistor Q6, and the twelfth resistor R. 12 Input capacitance C to MOSFET device 1 iss Charging gradually enables MOSFET device 1 to meet the turn-on conditions.

[0087] In this disclosure, the shutdown circuit 22 includes a fifth transistor Q5 and a plurality of parallel field-effect transistor circuits, each of the field-effect transistor circuits including a protection resistor and a field-effect transistor;

[0088] This disclosure uses a circuit with 6 field-effect transistors as an example. However, other numbers of field-effect transistor circuits can be used as needed without affecting the implementation of this disclosure. The protection resistor includes a protection circuit R. 13 To the protection circuit R 18 The field-effect transistors include field-effect transistors J1 to J6; the base of the fifth transistor Q5 is connected to the collector of the third transistor Q3 to receive the amplified signal; the collector of the fifth transistor Q5 is grounded; and the emitter of the fifth transistor Q5 is connected to the protection resistor (R). 13 -R 18The fifth transistor Q5 is connected to the source of each of the field-effect transistors (J1-J6) in a one-to-one correspondence. The emitter of the fifth transistor Q5 is also connected to the gate of each of the field-effect transistors (J1-J6). The drain of each of the field-effect transistors (J1-J6) is connected to the gate of the MOSFET device 1.

[0089] When the shutdown circuit receives a low-level output from the amplifier circuit, transistor Q5 turns on, while transistors Q4 and Q6 turn off. MOSFET 1 then goes low, and the input capacitor C of MOSFET 1... iss Discharge to ground through the JFET current source and the fifth transistor Q5.

[0090] The working principle of the hybrid gate drive circuit is analyzed below with reference to the embodiments of this disclosure. The turn-on and turn-off process of MOSFET device 1 can be divided into four stages, and the working principle of each stage is explained in detail below:

[0091] See Figures 2-6 As shown, the activation phase can be divided into four stages, from t0 to t4:

[0092] Phase 1 (t0~t1): At time t0, the driving voltage changes from -V EE Jump to +V CC The driving circuit charges the input capacitor of MOSFET device 1, and the gate-source voltage of MOSFET device 1 begins to rise. At time t1, the gate-source voltage of MOSFET device 1 rises to the threshold voltage V. th .

[0093] Phase 2 (t1~t2): At time t1, the gate-source voltage of MOSFET device 1 rises to the threshold voltage V. th The source of MOSFET device 1 begins to conduct, and the drain current i d The gate-source voltage begins to rise and continues to rise. At time t2, the drain current i d Increase to load current i L The gate-source voltage rises to the Miller plateau voltage V. miller .

[0094] Phase 3 (t2~t3): At time t2, the drain current of MOSFET device 1 reaches the load current i. L The gate-source voltage rises to the Miller plateau voltage V. miller Drain-source voltage V ds From the bus voltage V DC The voltage begins to decrease. At time t3, the drain-source voltage of MOSFET device 1 drops to the on-state voltage drop i. L* R ds(on) .

[0095] Phase 4 (t3~t4): At time t3, the drain-source voltage of MOSFET device 1 drops to the on-state voltage drop i. L* R ds(on) Subsequently, the gate-source voltage of MOSFET device 1 continued to increase. At time t4, the gate-source voltage of MOSFET device 1 continued to increase to the positive drive voltage +V. CC No losses occur during this stage.

[0096] See Figures 7-11 As shown, the turn-off process can be divided into four stages from t5 to t9:

[0097] Phase 5 (t5~t6): At time t5, the input capacitance of MOSFET device 1 begins to operate at a constant current i. goff As the device discharges, the gate-source voltage of MOSFET device 1 begins to decrease. At time t6, the gate-source voltage of MOSFET device 1 drops to the Miller plateau voltage.

[0098] Stage 6 (t6~t7): At time t6, the gate-source voltage of MOSFET device 1 drops to the Miller plateau voltage, and the drain-source voltage of MOSFET device 1 begins to rise. At time t7, the drain-source voltage rises to the bus voltage V. DC .

[0099] Phase 7 (t) 7～ t8): At time t7, the drain-source voltage rises to the bus voltage V. DC At time t8, the drain current of MOSFET device 1 begins to decrease. At time t8, the drain current of MOSFET device 1 drops to zero, and the gate-source voltage drops to the threshold voltage V. th .

[0100] Stage 8 (t8~t9): At time t8, the gate-source voltage of MOSFET device 1 drops to the threshold voltage V. th Subsequently, the gate-source voltage of MOSFET device 1 continued to decrease. At time t9, the gate-source voltage of MOSFET device 1 continued to decrease due to the negative drive voltage -V. EE No losses occur during this stage.

[0101] In summary, using voltage drive when MOSFET device 1 is turned on and current source drive when it is turned off improves the switching characteristics at high temperatures, reduces switching losses, and improves the reliability and efficiency of the system.

[0102] Furthermore, simulations were performed in LTspice software, adjusting parameters to ensure that the turn-on parameters and turn-off losses of the conventional and proposed drive circuits were identical at 25°C. Simulations were then conducted on both drive circuits at 175°C. When the conventional and proposed drive circuits had the same turn-on parameters and turn-off losses at 25°C, the turn-on loss of the proposed drive circuit at 175°C was 1839.62 μJ, the turn-off loss was 798.01 μJ, and the switching loss was 2637.63 μJ; the conventional drive circuit had a turn-on loss of 1878.24 μJ, a turn-off loss of 850.46 μJ, and a switching loss of 2728.7 μJ. Therefore, under the same 25°C driving conditions, at 175°C, the turn-on loss of the proposed drive circuit and the conventional drive circuit driving MOSFET device 1 decreased by 2.06%, the turn-off loss decreased by 6.16%, and the switching loss decreased by 3.34%.

[0103] Therefore, the high-temperature gate drive circuit of the MOSFET device 1 proposed in this disclosure enables the MOSFET device 1 to be used normally at higher temperatures, reduces the turn-on and turn-off losses of the MOSFET device 1, minimizes the switching losses as much as possible, and improves the efficiency and reliability of the MOSFET device 1.

[0104] In the description of this specification, the references to terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment / mode or example is included in at least one embodiment / mode or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments / modes or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.

[0105] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0106] Those skilled in the art should understand that the above embodiments are merely for illustrating the present disclosure and are not intended to limit the scope of the disclosure. Those skilled in the art can make other changes or modifications based on the above disclosure, and these changes or modifications still fall within the scope of the present disclosure.

Claims

1. A hybrid gate drive circuit, characterized in that, include: MOSFET devices are used as actuators to turn external circuits on or off. The turn-on and turn-off circuit connected to the MOSFET device is capable of receiving a turn-on signal and a turn-off signal, turning on the MOSFET device in a voltage source-driven manner according to the turn-on signal, and turning off the MOSFET device in a current source-driven manner according to the turn-off signal. A signal input circuit connected to the on / off circuit is capable of sending the on signal or the off signal to the on / off circuit; A power supply circuit is used to supply power to the MOSFET device, the on / off circuit, and the signal input circuit; The on / off circuit includes: A turn-on circuit is provided, wherein the signal input circuit is connected to the MOSFET device through the turn-on circuit, and the turn-on circuit is capable of receiving the turn-on signal and turning on the MOSFET device in a voltage source-driven manner according to the turn-on signal; A shutdown circuit is provided, wherein the signal input circuit is connected to the MOSFET device through the shutdown circuit, and the shutdown circuit is capable of receiving the shutdown signal and turning off the MOSFET device in a current source driven manner according to the shutdown signal; The turn-on circuit includes a fourth transistor, a sixth transistor, and a twelfth resistor; The base of the fourth transistor is connected to the output terminal of the signal input circuit, the emitter of the fourth transistor is connected to the base of the sixth transistor, the collectors of the fourth transistor and the sixth transistor are both connected to the power supply circuit, and the emitter of the sixth transistor is connected to the gate of the MOSFET device through the twelfth resistor.

2. The hybrid gate drive circuit as described in claim 1, characterized in that: The shutdown circuit includes a fifth transistor and multiple parallel field-effect transistor circuits; Each of the aforementioned field-effect transistor circuits includes a protection resistor and a field-effect transistor; The base of the fifth transistor is connected to the output terminal of the signal input circuit, the collector of the fifth transistor is grounded, the emitter of the fifth transistor is connected to the source of the field-effect transistor through the protection resistor, the emitter of the fifth transistor is also connected to the gate of the field-effect transistor, and the drain of the field-effect transistor is connected to the gate of the MOSFET device.

3. The hybrid gate drive circuit as described in claim 1, characterized in that: The power supply circuit includes a first resistor, a first diode, a second diode, a power supply VCC, a first power supply terminal, and a second power supply terminal. The power supply VCC is connected to the turn-on / turn-off circuit and the signal input circuit respectively after passing through the first power supply terminal; The power supply VCC is connected to the signal input circuit and the MOSFET device in sequence through the first resistor, the first diode, and the second power supply terminal. The second power supply terminal is also grounded through the second diode.

4. The hybrid gate drive circuit as described in claim 3, characterized in that: The signal input circuit includes: The transmitting circuit can convert analog control signals into digital signals; The receiving circuit is connected to the transmitting circuit and is capable of receiving the digital signal and restoring the digital signal to the control analog signal. An amplifier circuit, connected to a receiving circuit, is used to convert the control analog signal restored by the receiving circuit into the turn-on signal or turn-off signal.

5. The hybrid gate drive circuit as described in claim 4, characterized in that: The amplifier circuit includes an eleventh resistor and a third transistor; The first power supply terminal of the power supply circuit is connected to one end of the eleventh resistor; The collector of the third transistor is connected to the other end of the eleventh resistor and the turn-on / turn-off circuit. The base of the third transistor is electrically connected to the receiving circuit. The emitter of the third transistor is grounded.

6. The hybrid gate drive circuit as described in claim 4, characterized in that, The transmitting circuit includes a PWM signal generator, a second resistor, a third resistor, and a first transformer; One end of the PWM signal generator is grounded, and the other end of the PWM signal generator is connected to one end of the primary winding of the first transformer through the second resistor. The other end of the primary winding of the first transformer is grounded through the third resistor. One end and the other end of the secondary winding of the first transformer are both connected to the receiving circuit.

7. The hybrid gate drive circuit as described in claim 4, characterized in that: The receiving circuit includes a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a third diode, a fourth diode, a fifth diode, a first transistor, and a second transistor. One output terminal of the signal input circuit is connected to one end of the fourth resistor and the positive terminal of the third diode, respectively; the other output terminal of the signal input circuit is connected to one end of the fifth resistor and the positive terminal of the fourth diode, respectively. The base of the first transistor is connected to one end of the seventh resistor and the negative terminal of the third diode, respectively; the collector of the first transistor is connected to one end of the sixth resistor and one end of the eighth resistor, respectively. The base of the second transistor is connected to the other end of the sixth resistor and the cathode of the fourth diode, respectively. The collector of the second transistor is connected to the other end of the seventh resistor, one end of the ninth resistor, and one end of the tenth resistor, respectively. The emitter of the first transistor, the emitter of the second transistor, the other end of the fourth resistor, and the other end of the fifth resistor are all grounded; The second power supply terminal is connected to the other end of the eighth resistor and the other end of the ninth resistor respectively through the fifth diode; The other end of the tenth resistor is connected to the amplifier circuit.

8. The hybrid gate drive circuit as described in claim 7, characterized in that: The receiving circuit also includes a first capacitor, a second capacitor, and a third capacitor; The negative terminal of the fifth diode is grounded through the first capacitor, the second power supply terminal is grounded through the second capacitor, and the first power supply terminal is connected to the second power supply terminal through the third capacitor.

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