Digital beamforming device and synthetic aperture radar back-end digital processing system

Abstract

The present application provides a digital beamforming device and a synthetic aperture radar back-end digital processing system, the device comprising: an acquisition unit, a first processing unit and a second processing unit; the acquisition unit receives a first multi-path echo signal to generate a first data to be synthesized, and receives a second multi-path echo signal to generate a second data to be synthesized; the acquisition unit sends the first data to be synthesized to the first processing unit, and sends the second data to be synthesized to the second processing unit; the first processing unit synthesizes the first multi-path baseband data in the first data to be synthesized into the first combined baseband data; the second processing unit synthesizes the second multi-path baseband data in the second data to be synthesized into the second combined baseband data. By adopting the above-mentioned digital beamforming device and the synthetic aperture radar back-end digital processing system, the problems of difficult testing and verification, poor reliability and stability of data transmission in the existing digital beamforming device are solved.

Description

Technical Field

[0001] The present application relates to the technical field of digital signal processing, and in particular to a digital beamforming device and a synthetic aperture radar back-end digital processing system. Background Art

[0002] Digital Beam Forming (DBF) technology has been widely used in various technical fields. For example, it plays an important role in radar, sonar, communication, imaging, geophysical exploration and biomedicine. It can gather the multi-channel signals received by the array antenna in a specified direction and synthesize a digital beam for external devices to use the synthesized digital beam for imaging or communication processing.

[0003] After receiving multiple echo data, the existing digital beamforming device usually uses a field programmable gate array (FPGA) to complete the preprocessing, amplitude and phase correction and digital beamforming of each echo data. However, the use of the above digital beamforming device will cause the algorithm complexity of the single-chip FPGA to be high, and the testing and verification difficulties to be great. At the same time, due to the complex internal wiring of the single-chip FPGA, it is easy to cause the reliability and stability of data transmission to be poor. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide a digital beamforming device and a synthetic aperture radar back-end digital processing system, which can perform hierarchical processing on multi-channel echo data through multiple FPGAs, and each hierarchical processing process is completed in a different FPGA, thereby solving the problems of difficult testing and verification in existing digital beamforming devices and poor reliability and stability of data transmission.

[0005] In a first aspect, an embodiment of the present application provides a digital beamforming device, the digital beamforming device is carried on a radar installed on a mobile vehicle, and the digital beamforming device includes a collection unit, a first processing unit, and a second processing unit;

[0006] The acquisition unit is connected to the first processing unit and the second processing unit respectively;

[0007] The acquisition unit receives a first multi-channel echo signal to generate first data to be synthesized, and receives a second multi-channel echo signal to generate second data to be synthesized, wherein the first data to be synthesized includes first multi-channel baseband data, and the second data to be synthesized includes second multi-channel baseband data, and the first multi-channel echo signal and the second multi-channel echo signal are echo signals in different directions;

[0008] The acquisition unit sends the first data to be synthesized to the first processing unit, and sends the second data to be synthesized to the second processing unit;

[0009] The first processing unit receives the first data to be synthesized, and synthesizes the first multiple baseband data in the first data to be synthesized into first combined baseband data, so as to send the first combined baseband data to an external device;

[0010] The second processing unit receives the second data to be synthesized, and synthesizes the second multiple baseband data in the second data to be synthesized into second combined baseband data, so as to send the second combined baseband data to the external device.

[0011] Optionally, the acquisition unit includes a first acquisition sub-board, a first cache unit and an acquisition control chip, and the acquisition control chip is a field programmable logic gate array; the acquisition control chip of the acquisition unit generates first data to be synthesized through the following steps: receiving first multi-channel echo data sent by the first acquisition sub-board, and putting the first multi-channel echo data into the first cache unit for storage, the first multi-channel echo data is obtained after the first acquisition sub-board performs analog-to-digital conversion on the first multi-channel echo signal; determining whether the first multi-channel echo data stored in the first cache unit reaches a first set threshold; if it is determined that the stored first multi-channel echo data reaches the first set threshold, reading the first multi-channel echo data from the first cache unit; performing mixing and half-band filtering extraction processing on the read first multi-channel echo data to generate first multi-channel baseband data; framing the first multi-channel baseband data and the first auxiliary data to generate first data to be synthesized, the first auxiliary data is identification data of the first multi-channel baseband data.

[0012] Optionally, the acquisition unit also includes a second acquisition sub-board and a second cache unit; the acquisition control chip of the acquisition unit generates second data to be synthesized through the following steps: receiving second multi-channel echo data sent by the second acquisition sub-board, and storing the second multi-channel echo data in the second cache unit, where the second multi-channel echo data is obtained after the second acquisition sub-board performs analog-to-digital conversion on the second multi-channel echo signal; determining whether the second multi-channel echo data stored in the second cache unit reaches a second set threshold; if it is determined that the stored second multi-channel echo data reaches the second set threshold, reading the second multi-channel echo data from the second cache unit; performing mixing and half-band filtering extraction processing on the read second multi-channel echo data to generate second multi-channel baseband data; framing the second multi-channel baseband data and second auxiliary data to generate second data to be synthesized, where the second auxiliary data is identification data of the second multi-channel baseband data.

[0013] Optionally, the first processing unit includes a first processing chip and a third cache unit, and the first processing chip is a field programmable logic gate array; the first processing chip of the first processing unit synthesizes the first multi-channel baseband data into the first combined baseband data through the following steps: receiving the first data to be synthesized, and putting the received first data to be synthesized into the third cache unit for caching; determining whether the first data to be synthesized stored in the third cache unit reaches the first set threshold; if it is determined that the stored first data to be synthesized reaches the first set threshold, reading the first data to be synthesized from the third cache unit; parsing the read first data to be synthesized to obtain the first multi-channel baseband data; performing amplitude and phase correction, time domain weighted processing, and frequency domain weighted processing on the first multi-channel baseband data; and synthesizing the processed first multi-channel baseband data into the first combined baseband data.

[0014] Optionally, the second processing unit includes a second processing chip and a fourth cache unit, and the second processing chip is a field programmable logic gate array; the second processing unit synthesizes the second multi-channel baseband data into second combined baseband data through the following steps: receiving second data to be synthesized, and placing the received second data to be synthesized into a fourth cache unit for caching; determining whether the second data to be synthesized stored in the fourth cache unit reaches a second set threshold; if it is determined that the stored second data to be synthesized reaches the second set threshold, reading the second data to be synthesized from the fourth cache unit; parsing the read second data to be synthesized to obtain second multi-channel baseband data; performing amplitude and phase correction, time domain weighted processing, and frequency domain weighted processing on the second multi-channel baseband data; and synthesizing the processed second multi-channel baseband data into second combined baseband data.

[0015] Optionally, the third cache unit includes a first cache subunit and a second cache subunit; the first processing chip puts the received first data to be synthesized into the third cache unit for caching through the following steps: the first data to be synthesized with different pulse periods are respectively put into the first cache subunit and the second cache subunit for ping-pong caching.

[0016] Optionally, the fourth cache unit includes a third cache sub-unit and a fourth cache sub-unit; the second processing chip puts the received second data to be synthesized into the fourth cache unit for caching through the following steps: the second data to be synthesized with different pulse periods are respectively put into the third cache sub-unit and the fourth cache sub-unit for ping-pong caching.

[0017] In a second aspect, an embodiment of the present application further provides a synthetic aperture radar back-end digital processing system, the synthetic aperture radar back-end digital processing system includes a control module, a backplane connector and a digital beamforming device.

[0018] Optionally, the control module includes a main control computer; the main control computer is connected to a collection unit in the digital beamforming device via a backplane connector, and sends control instructions to the collection unit.

[0019] Optionally, the control module further includes a reference frequency unit; the reference frequency unit is respectively connected to the acquisition unit, the first processing unit and the second processing unit in the digital beamforming device through a backplane connector to provide a working clock for the acquisition unit, the first processing unit and the second processing unit.

[0020] The embodiments of the present application bring the following beneficial effects:

[0021] The digital beamforming device and synthetic aperture radar back-end digital processing system provided in the embodiments of the present application can perform hierarchical processing on multi-channel echo data through multiple FPGAs, and each hierarchical processing process is completed in a different FPGA. Compared with the digital beamforming device in the prior art, the problems of difficult testing and verification and poor reliability and stability of data transmission in the prior art are solved.

[0022] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 A schematic diagram of the structure of a digital beamforming device provided in an embodiment of the present application is shown;

[0025] Figure 2 A schematic diagram of the structure of a collection unit provided in an embodiment of the present application is shown;

[0026] Figure 3 A schematic diagram showing the working principle of the acquisition unit provided in an embodiment of the present application is shown;

[0027] Figure 4 A schematic diagram showing the structure of a first processing unit provided in an embodiment of the present application is shown;

[0028] Figure 5 A flow chart of a method for synthesizing first multi-channel baseband data and second multi-channel baseband data provided in an embodiment of the present application is shown;

[0029] Figure 6 A schematic diagram showing the structure of a second processing unit provided in an embodiment of the present application is shown;

[0030] Figure 7 A schematic diagram of the structure of a synthetic aperture radar back-end digital processing system provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0031] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application usually described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, each other embodiment obtained by those skilled in the art without making creative work belongs to the scope of protection of the present application.

[0032] It is worth noting that before the present application was proposed, digital beamforming technology has been widely used in various technical fields. For example, it plays an important role in radar, sonar, communication, imaging, geophysical exploration and biomedicine. It can gather the multi-channel signals received by the array antenna in a specified direction to form a digital beam for external equipment to use the digital beam for imaging or communication processing. After receiving multiple echo data, the existing digital beamforming device usually uses an FPGA to complete the preprocessing, amplitude and phase correction and digital beamforming of each echo data. However, the use of the above-mentioned digital beamforming device will cause the FPGA algorithm to be highly complex and difficult to test and verify. At the same time, due to the complex internal wiring of a single FPGA, it is easy to cause problems with the reliability and stability of data transmission.

[0033] Based on this, an embodiment of the present application provides a digital beamforming device to solve the problems of high difficulty in testing and verification and poor reliability and stability of data transmission in existing digital beamforming devices.

[0034] See also Figure 1 , Figure 1 This is a schematic diagram of the structure of a digital beamforming device provided in an embodiment of the present application. Figure 1 As shown, the digital beamforming device 10 provided in the embodiment of the present application is carried on a radar installed on a mobile vehicle. The digital beamforming device 10 includes: a collection unit 100, a first processing unit 200 and a second processing unit 300.

[0035] The acquisition unit 100 is connected to the first processing unit 200 and the second processing unit 300 respectively.

[0036] Here, the acquisition unit 100, the first processing unit 200 and the second processing unit 300 may all refer to field programmable gate arrays FPGA. The acquisition unit 100 is arranged at the front end of the digital beamforming device, and the first processing unit 200 and the second processing unit 300 are symmetrically arranged at the back end of the digital beamforming device.

[0037] The mobile vehicle may refer to a movable vehicle equipped with a radar. For example, the mobile vehicle may be a drone, a car, or a manned aircraft.

[0038] In the embodiment of the present application, the acquisition unit 100 in the digital beamforming device 10 is connected to the first processing unit 200 via the LVDS (Low-Voltage Differential Signaling, LVDS) bus and the SRIO (Serial RapidIO, SRIO) bus, and the acquisition unit 100 is connected to the second processing unit 300 via the LVDS bus and the SRIO bus. The acquisition unit 100 transmits auxiliary data to the first processing unit 200 and the second processing unit 300 via the LVDS bus, and the acquisition unit 100 transmits echo data to the first processing unit 200 and the second processing unit 300 via the SRIO bus. The first processing unit 200 and the second processing unit 300 are connected via the LVDS bus and the SRIO bus, and the first processing unit 200 and the second processing unit 300 can also perform data exchange of auxiliary data and echo data.

[0039] After receiving the echo signal, the radar antenna sends the received echo signal to the acquisition unit 100. The acquisition unit 100 receives the first multiple echo signals to generate the first data to be synthesized, and receives the second multiple echo signals to generate the second data to be synthesized.

[0040] The first multi-path echo signal may refer to a multi-path analog signal. As an example, the first multi-path echo signal may be a 4-path analog signal in a first direction returned after the radar illuminates the target area.

[0041] The second multi-path echo signal may refer to a multi-path analog signal. As an example, the second multi-path echo signal may be a 4-path analog signal in the second direction returned after the radar illuminates the target area.

[0042] The first data to be synthesized may refer to multiple first data to be synthesized, each first data to be synthesized corresponds to a pulse period, each first data to be synthesized includes first multi-channel baseband data, and each first data to be synthesized is data obtained by framing the first multi-channel baseband data and the first auxiliary data within a single pulse period.

[0043] The first multi-channel baseband data may refer to data obtained after preprocessing the first multi-channel echo data, and the first multi-channel echo data is data obtained after analog-to-digital conversion of the first multi-channel echo signals.

[0044] The first auxiliary data may refer to data corresponding to the first multi-path echo signal, and is used as identification data of the first multi-path echo signal. As an example, the first auxiliary data may be positioning information of a mobile vehicle corresponding to the first multi-path echo signal at different times, and control information sent by a main control computer connected to the digital beamforming device.

[0045] The second data to be synthesized may refer to multiple second data to be synthesized, each second data to be synthesized corresponds to a pulse period, each second data to be synthesized includes second multi-channel baseband data, and each second data to be synthesized is data obtained by framing the second multi-channel baseband data and the second auxiliary data within a single pulse period.

[0046] The second multi-channel baseband data may refer to data obtained after preprocessing the second multi-channel echo data, and the second multi-channel echo data is data obtained after analog-to-digital conversion of the second multi-channel echo signals.

[0047] The second auxiliary data may refer to data corresponding to the second multiple-path echo signal, and is used as identification data of the second multiple-path echo signal. As an example, the second auxiliary data may be positioning information of a mobile vehicle corresponding to the second multiple-path echo signal at different times, and control information sent by a main control computer connected to the digital beamforming device.

[0048] In the embodiment of the present application, the acquisition unit 100 receives a first multi-channel echo signal sent from a first analog receiver, and the acquisition unit 100 receives a second multi-channel echo signal sent from a second analog receiver. At the same time, the digital beamforming device 10 receives a synchronization signal and a sampling start signal from a main control computer, and controls the data beamforming process according to the received synchronization signal and sampling start signal. The digital beamforming device 10 also receives a reference clock and a sampling clock from a reference frequency unit, which are used to provide clock drive for the acquisition unit 100, the first processing unit 200, and the second processing unit 300. Among them, the first multi-channel echo signal and the second multi-channel echo signal are both 4-channel echo signals, and the acquisition unit 100 can complete the digital processing of a total of 8 analog signals of the first multi-channel echo signal and the second multi-channel echo signal.

[0049] In an optional embodiment, the acquisition unit includes a first acquisition sub-board, a first cache unit and an acquisition control chip, and the acquisition control chip is a field programmable logic gate array; the acquisition unit also includes a second acquisition sub-board and a second cache unit.

[0050] Figure 2 A schematic diagram of the structure of a collection unit provided in an embodiment of the present application is shown.

[0051] like Figure 2 As shown, the acquisition unit 100 includes an acquisition control chip 101, a first acquisition sub-board 102, a second acquisition sub-board 103, a first cache unit 104, and a second cache unit 105. Here, the acquisition unit 100 also includes a first program storage unit (not shown in the figure).

[0052] In an optional embodiment, the acquisition control chip of the acquisition unit generates the first data to be synthesized through the following steps: receiving the first multi-channel echo data sent by the first acquisition sub-board, and storing the first multi-channel echo data in the first cache unit, where the first multi-channel echo data is obtained after the first acquisition sub-board performs analog-to-digital conversion on the first multi-channel echo signal; determining whether the first multi-channel echo data stored in the first cache unit reaches a first set threshold; if it is determined that the stored first multi-channel echo data reaches the first set threshold, reading the first multi-channel echo data from the first cache unit; performing mixing and half-band filtering extraction processing on the read first multi-channel echo data to generate first multi-channel baseband data; framing the first multi-channel baseband data and the first auxiliary data to generate the first data to be synthesized, where the first auxiliary data is identification data of the first multi-channel baseband data.

[0053] Here, the first acquisition sub-board refers to a chip for collecting multi-channel analog signals. The first acquisition sub-board is used to collect first multi-channel echo signals. Exemplarily, the first acquisition sub-board can be an FMC sub-board (FPGA Mezzanine Card, FMC), and the FMC sub-board includes an HPC connector (High order path Connection, HPC).

[0054] The first cache unit may refer to a cache unit composed of a plurality of single-chip access memories. Exemplarily, each single-chip access memory may be a synchronous dynamic random access memory DDR3 (Double Data Rate SDRAM, DDR SDRAM).

[0055] The acquisition control chip may refer to a field programmable gate array FPGA. As an example, the acquisition control chip may be an XC7VX485T device of the Virtex7 series.

[0056] In an optional embodiment, the acquisition control chip of the acquisition unit generates second data to be synthesized through the following steps: receiving second multi-channel echo data sent by the second acquisition sub-board, and storing the second multi-channel echo data in the second cache unit, where the second multi-channel echo data is obtained after the second acquisition sub-board performs analog-to-digital conversion on the second multi-channel echo signal; determining whether the second multi-channel echo data stored in the second cache unit reaches a second set threshold; if it is determined that the stored second multi-channel echo data reaches the second set threshold, reading the second multi-channel echo data from the second cache unit; performing mixing and half-band filtering extraction processing on the read second multi-channel echo data to generate second multi-channel baseband data; framing the second multi-channel baseband data and second auxiliary data to generate second data to be synthesized, where the second auxiliary data is identification data of the second multi-channel baseband data.

[0057] Here, the second acquisition sub-board refers to a chip for collecting multi-channel analog signals. The second acquisition sub-board is used to collect second multi-channel echo signals. Exemplarily, the second acquisition sub-board can be an FMC sub-board (FPGA Mezzanine Card, FMC), and the FMC sub-board includes an HPC connector (High order path Connection, HPC).

[0058] The second cache unit may refer to a cache unit composed of a plurality of single-chip access memories. Exemplarily, each single-chip access memory may be a synchronous dynamic random access memory DDR3 (Double Data Rate SDRAM, DDR SDRAM).

[0059] Refer to the following Figure 3 The generation process of the first data to be synthesized and the second data to be synthesized in each pulse period is introduced.

[0060] Figure 3 A schematic diagram showing the working principle of the acquisition unit provided in an embodiment of the present application is shown.

[0061] like Figure 3 As shown, the auxiliary data parsing module receives auxiliary data through the LVDS bus and the RS-422 bus, parses the auxiliary data, and then sends the auxiliary data to the first combination module, which frames the received first multi-channel echo data and the first auxiliary data and puts them into the first cache unit for storage. Here, the first cache unit is 4 pieces of 2G-bit DDR3 SDRAM (128M (megabytes) × 16bit (bits)), and the working clock is 400MHz.

[0062] It should be noted that, when the acquisition control chip receives the first multi-channel echo signal, it also receives the first auxiliary data corresponding to the first multi-channel echo signal. Here, the acquisition control chip is connected to the internal bus interface of the backplane to obtain the first auxiliary data from the main control computer through the internal bus of the backplane.

[0063] Each first auxiliary data corresponds to a pulse cycle. Whenever the first multi-channel echo data and the first auxiliary data of a pulse cycle are received, the received first multi-channel echo data and the first auxiliary data are framed to obtain the first cache data, and the first cache data is placed in the first cache unit for storage. Each second auxiliary data corresponds to a pulse cycle, and the second auxiliary data and the first auxiliary data come from the main control computer and can be the same data. Whenever the second multi-channel echo data and the second auxiliary data of a pulse cycle are received, the received second multi-channel echo data and the second auxiliary data are framed to obtain the second cache data, and the second cache data is placed in the second cache unit for storage.

[0064] Among them, the first cache unit composed of 4 DDR3 chips is divided into two parts according to the storage address, and each part corresponds to the first cache data of one pulse cycle. For example, the first cache unit is divided into an A cache subunit and a B cache subunit. After receiving the first group of first cache data corresponding to the first pulse cycle, the first group of first cache data is placed in the A cache subunit for storage. After receiving the second group of first cache data corresponding to the second pulse cycle, the second group of first cache data is placed in the B cache subunit for storage. At the same time, when the acquisition control chip determines that the number of bytes of data stored in the A cache subunit reaches the first set threshold, the first group of first cache data is read from the A cache subunit, and then the third group of first cache data corresponding to the third pulse cycle is placed in the A cache subunit for storage. By analogy, the first cache data corresponding to each pulse cycle is accessed. It can be seen that the above-mentioned method of accessing the first cache data can access the first cache data corresponding to two pulse cycles at the same time, thereby improving the data access speed.

[0065] The acquisition control chip determines whether the first multi-channel echo data stored in the first cache unit reaches a first set threshold value. If it is determined that the stored first multi-channel echo data reaches the first set threshold value, the first multi-channel echo data of the first set threshold quantity is read from the first cache unit, and the read first multi-channel echo data is sent to the DDC controller for preprocessing.

[0066] Among them, the first set threshold is determined by the control instructions in the main control computer. For example: the control instructions include the number of sampling points when collecting data in each pulse period when collecting the first multi-channel echo signal. The amount of data collected can be determined based on the number of sampling points, and the first set threshold is determined based on the amount of data. Similarly, the control instructions also include the number of sampling points when collecting data in each pulse period when collecting the second multi-channel echo signal. The amount of data collected can be determined based on the number of sampling points, and the second set threshold is determined based on the amount of data.

[0067] Here, when the first multi-channel echo data is preprocessed, that is, when the down conversion (Digital Down Converter, DDC) processing is performed, the preprocessing of the first cache data can be implemented through the DDC controller to convert the first cache data from the intermediate frequency signal to the baseband data, and then the first multi-channel baseband data and the first auxiliary data are framed to generate the first data to be synthesized, and the first data to be synthesized is sent to the first processing unit through the GTX transceiver.

[0068] Among them, the mixing process is implemented by a filtering module, which is used to orthogonally demodulate the intermediate frequency signal into IQ baseband data. Half-band filtering extraction is implemented by a half-band filter, which is used to filter out the high-frequency components and high-frequency spurious signals after mixing to prevent spectrum aliasing. At the same time, after two samplings, the data is extracted at a ratio of 4:1 to reduce the amount of data. Among them, the first half-band filtering extraction is to filter out the high-frequency components and high-frequency spurious signals after mixing, prevent spectrum aliasing, and extract the data at a ratio of 2:1 to reduce the amount of data; the second half-band filtering extraction is also to extract the data at a ratio of 2:1, so that the total sampling ratio is 4:1. It should be pointed out that the DDC controller pre-processes each echo data in the first multi-channel echo data separately, and performs mixing, the first half-band filtering extraction and the second half-band filtering extraction on each echo data in turn.

[0069] At the same time, after preprocessing the first multi-channel echo data, automatic gain control (AGC) is also performed on it, that is, the amplitude of the first multi-channel echo data is adjusted to control the first multi-channel echo data within the optimal amplitude range and optimize the signal strength. A specific gain value can be obtained through AGC gain control, and then the gain value of the first multi-channel echo data is sent to an external device through the GPIO interface.

[0070] It should be noted that the processing process of the second multi-channel echo data in the acquisition unit is the same as the processing process of the first multi-channel echo data in the acquisition unit, which will not be repeated here.

[0071] The acquisition unit sends the first data to be synthesized to the first processing unit, and sends the second data to be synthesized to the second processing unit.

[0072] After preprocessing the first multi-channel echo data, the data is sent to the first processing unit through a GTX (Gigabit transceiver, GTX) transceiver, and after preprocessing the second multi-channel echo data, the data is sent to the second processing unit through another GTX transceiver.

[0073] In an optional embodiment, the first multi-path echo signal and the second multi-path echo signal are echo signals in different directions.

[0074] In the embodiment of the present application, the first multi-path echo signal received by the first analog receiver and the second multi-path echo signal received by the second analog receiver may be echo signals in different directions.

[0075] The first processing unit receives the first data to be synthesized, and synthesizes the first multiple baseband data in the first data to be synthesized into first combined baseband data, so as to send the first combined baseband data to an external device.

[0076] The first combined baseband data may refer to a digital beam obtained by combining the first multi-path echo data.

[0077] The external device may refer to an imaging device, which is used to display the position, size and speed information of the target detected by the radar according to the first combined baseband data.

[0078] In an optional embodiment, the first processing unit includes a first processing chip and a third cache unit, and the first processing chip is a field programmable logic gate array; the first processing chip of the first processing unit synthesizes the first multi-channel baseband data into the first combined baseband data through the following steps: receiving the first data to be synthesized, and placing the received first data to be synthesized into the third cache unit for caching; determining whether the first data to be synthesized stored in the third cache unit reaches a first set threshold; if it is determined that the stored first data to be synthesized reaches the first set threshold, reading the first data to be synthesized from the third cache unit; parsing the read first data to be synthesized to obtain the first multi-channel baseband data; performing amplitude and phase correction, time domain weighted processing, and frequency domain weighted processing on the first multi-channel baseband data; and synthesizing the processed first multi-channel baseband data into the first combined baseband data.

[0079] The first processing chip may refer to an FPGA, and the first processing chip is used to control the synthesis process of the first multi-channel baseband data.

[0080] In an optional embodiment, the third cache unit includes a first cache sub-unit and a second cache sub-unit; the first processing chip puts the received first data to be synthesized into the third cache unit for caching through the following steps: the first data to be synthesized with different pulse periods are respectively put into the first cache sub-unit and the second cache sub-unit for ping-pong caching.

[0081] Figure 4 A schematic diagram of the structure of the first processing unit provided in an embodiment of the present application is shown.

[0082] like Figure 4 As shown, the first processing unit 200 includes a first processing chip 210, a third cache unit 220, and a second program storage unit 230. The third cache unit 220 includes a first cache subunit 221 and a second cache subunit 222. The first processing chip 210 is connected to the second program storage unit 230. The first processing chip 210 obtains the control program from the second program storage unit 230 after power-on. As an example, the second program storage unit 230 can be a flash memory (FLASH). The first processing chip 210 is connected to the first cache subunit 221 and the second cache subunit 222. The first data to be synthesized under different pulse periods is put into the first cache subunit 221 and the second cache subunit 222 for ping-pong caching.

[0083] Taking the first data to be synthesized as an example, after receiving the first data to be synthesized, the received first data to be synthesized is placed in the third cache unit 220 for caching, that is, the received first data to be synthesized is placed in the first cache subunit 221 and the second cache subunit 222 for caching, the first cache subunit 221 is composed of multiple DDR3 caches, and the second cache subunit 222 is also composed of multiple DDR3 caches. The first data to be synthesized includes multiple groups of first data to be synthesized, and each group of data to be synthesized in the multiple groups of first data to be synthesized corresponds to a pulse cycle. When the first processing chip 210 receives the first group of first data to be synthesized, the first group of first data to be synthesized is placed in the first cache subunit 221 for caching, and when the first processing chip 210 receives the second group of first data to be synthesized, the second group of first data to be synthesized is placed in the second cache subunit 222 for caching, so as to realize the ping-pong cache of the first data to be synthesized corresponding to different pulse cycles. The first processing chip 210 determines whether the first data to be synthesized stored in the first cache subunit 221 reaches the first set threshold value. If it is determined that the stored first data to be synthesized reaches the first set threshold value, the first data to be synthesized is read from the first cache subunit 222, and the read first data to be synthesized is parsed to obtain the first multi-channel baseband data. Then, the first multi-channel baseband data is amplitude-phase corrected in the calibration front end and the calibration back end. After the amplitude-phase correction is performed on the first multi-channel baseband data, the first multi-channel baseband data is also subjected to time domain weighting, time delay filtering, frequency domain synthesis, and time-frequency transformation to obtain the first combined baseband data.

[0084] See below Figure 5 The data synthesis process of the first combined baseband data and the second combined baseband data is introduced.

[0085] Figure 5 A flow chart of a method for synthesizing first multi-channel baseband data and second multi-channel baseband data provided in an embodiment of the present application is shown.

[0086] like Figure 5 As shown, taking the data synthesis process of the first multi-channel baseband data as an example, the first multi-channel baseband data of a single pulse period sent by the acquisition unit is processed in the following steps:

[0087] Step S401: amplitude and phase correction.

[0088] In this step, for the first multiple-channel baseband data, the peak amplitude and phase of each channel of baseband data are calculated respectively, and the calculated peak amplitude and phase of each channel of baseband data are stored in a reference data storage module. Then, the peak amplitude and phase of the first channel of baseband data are used as the reference amplitude and reference phase, and the remaining three channels of baseband data are compared with the peak amplitude and phase of the first channel of baseband data respectively to complete the amplitude and phase consistency correction processing.

[0089] It should be noted that when the phase error between different roadbed band data is large, phase correction between different roadbed band data is required, otherwise the performance of the synthesized digital beam may be significantly reduced. Here, the first processing chip includes a calibration module, and the calibration module can be used to complete the error extraction and correction between different roadbed band data. When the SAR system works in the calibration mode, the first processing chip calculates the peak amplitude and phase of different roadbed band data through the calibration front end and stores them in the ROM (read-only memory). Then, when the SAR system works in the normal imaging mode, the amplitude and phase consistency correction is completed through the calibration back end. Among them, the SAR system is divided into two working modes when working, namely the normal imaging working mode and the system calibration mode. The calibration mode is a working mode of the SAR system. The calibration mode is used to calibrate the amplitude and phase characteristics of the system link. Generally, the system calibration is performed before the SAR system is imaged and after the SAR system is imaged (here, it can be called the first calibration and the tail calibration). When the system works in the calibration mode, the calibration data of 64 or 128 pulse repetition periods are stored in the digital waveform synthesis system as a reference.

[0090] In an embodiment of the present application, after the first processing chip receives the start signal sent by the first acquisition control chip, it starts the reference data storage module to store the amplitude and phase values ​​of each baseband data, performs FFT (4096 points) processing on each baseband data, performs complex multiplication on the baseband data after FFT processing and the reference data, performs IFFT (4096 points) processing on the data after the complex multiplication, calculates the amplitude and amplitude peak of the data after IFFT processing, obtains the amplitude and amplitude peak of each baseband data, uses the coordinate rotation digital algorithm Cordic (Coordinate Rotation Digital Computer, Cordic) to calculate the phase value of the amplitude peak, and stores the obtained amplitude peak and peak phase value in the reference data storage module.

[0091] The calibration backend module completes the correction processing of each baseband data separately. When implementing, the first processing chip only needs to complete the algorithm design of a single channel, and the remaining channels only need to reuse the completed algorithm. Here, the first processing chip includes multiple channels, each channel corresponds to processing one baseband data, and the first channel corresponds to processing the first baseband data. In order to realize the correction of each baseband data, the calibration backend module must first determine the correction amplitude of each baseband data. Since the reference phase and reference peak value of the first channel are itself, the first channel does not need to perform amplitude phase correction processing. The remaining three channels are compared with the amplitude peak value and phase stored in the first channel, and the comparison results are stored in the register. The register includes a peak storage table and a phase storage table. The peak storage table is used to store the amplitude peak value, and the phase storage table is used to store the phase. In this way, the correction amplitude of each baseband data is determined. Then, when the first baseband data arrives at the calibration backend module, the amplitude phase correction processing is performed on each baseband data.

[0092] Step S402: time domain weighting.

[0093] In this step, for the first multiple-channel baseband data after amplitude phase correction, the azimuth data corresponding to the first multiple-channel baseband data is determined according to the first auxiliary data corresponding to the first multiple-channel baseband data, and the instantaneous weight of each sampling point is determined based on the azimuth data corresponding to each sampling moment. Here, taking the mobile vehicle as a drone as an example, the instantaneous weight of each sampling point can be found from the instantaneous weight data table according to the flight altitude of the drone. For example: there are 1000 sampling points in a single pulse cycle, and the sampling moments of these 1000 sampling points can be determined in the first auxiliary data. Then, the flight altitude of the drone at each sampling moment is determined according to the sampling moment, and multiple instantaneous weights corresponding to the determined flight altitude are found in the instantaneous weight data table. For each channel of baseband data in the first baseband data, each instantaneous weight is multiplied by the baseband data at the corresponding sampling moment, and all the multiplication results are accumulated to obtain the weighted data of each channel of baseband data, completing the time domain weighted calculation.

[0094] Here, the instantaneous weight calculation formula of each baseband data at time t is:

[0095] ω n (t) = exp{-j2πd n Sin(α(t)) / λ}.

[0096] Where α(t) is the beam pointing, that is, the angle between the center of the receiving beam and the antenna normal, d n is the distance between the receiving antennas, λ is the wavelength of the SAR operating frequency, and j is the imaginary unit.

[0097] It can be understood that the instantaneous weight corresponding to different sampling points is a time-varying variable. Obtaining the instantaneous weight corresponding to each sampling point by table lookup can not only quickly obtain the instantaneous weight, but also save the resource usage of the first processing unit.

[0098] Step S403: delay filtering.

[0099] In this step, for the first multiple baseband data after time domain weighting processing, a 4096-point FFT operation is performed on each baseband data to convert it into a frequency domain signal, and then the frequency domain weighting coefficient of each channel is multiplied in the frequency domain. The processing method of frequency domain weighting is the same as that of time domain weighting, and is also obtained by table lookup based on the flight altitude.

[0100] Here, the delay of each echo data is different, and the delay filter module is used to eliminate the extension loss of each echo data. The calculation formula of the frequency domain weighting coefficient of each aperture is:

[0101]

[0102] Where j is the imaginary unit, f is the system operating frequency, d n is the distance between the receiving antennas, λ is the wavelength of the SAR operating frequency, k γ is the system frequency modulation slope, t0 is the round-trip time from the phase center of the transmitting antenna to the target, and α′(t0) is the rate of change of the beam pointing at time t0.

[0103] Step S404: frequency domain synthesis.

[0104] In this step, the first multiple-channel baseband data after delay filtering is synthesized into first combined baseband data through frequency domain accumulation operation on the first multiple-channel baseband data.

[0105] Step S405: time-frequency conversion.

[0106] In this step, the synthesized frequency domain data is processed by 4096-point IFFT and transformed into time domain data.

[0107] Here, the second processing unit receives the second data to be synthesized, and synthesizes the second multiple baseband data in the second data to be synthesized into second combined baseband data, so as to send the second combined baseband data to the external device.

[0108] The second combined baseband data may refer to a digital beam obtained by combining the second multi-path echo data.

[0109] In an optional embodiment, the second processing unit includes a second processing chip and a fourth cache unit, and the second processing chip is a field programmable logic gate array; the second processing unit synthesizes the second multi-channel baseband data into second combined baseband data through the following steps: receiving the second data to be synthesized, and placing the received second data to be synthesized into the fourth cache unit for caching; determining whether the second data to be synthesized stored in the fourth cache unit reaches the second set threshold; if it is determined that the stored second data to be synthesized reaches the second set threshold, reading the second data to be synthesized from the fourth cache unit; parsing the read second data to be synthesized to obtain the second multi-channel baseband data; performing amplitude and phase correction, time domain weighted processing, and frequency domain weighted processing on the second multi-channel baseband data; and synthesizing the processed second multi-channel baseband data into second combined baseband data.

[0110] In an optional embodiment, the fourth cache unit includes a third cache sub-unit and a fourth cache sub-unit; the second processing chip puts the received second data to be synthesized into the fourth cache unit for caching through the following steps: the second data to be synthesized with different pulse periods are respectively put into the third cache sub-unit and the fourth cache sub-unit for ping-pong caching.

[0111] Figure 6 A schematic diagram of the structure of the second processing unit provided in an embodiment of the present application is shown.

[0112] like Figure 6 As shown, the second processing unit 300 includes a second processing chip 310, a fourth cache unit 320, and a third program storage unit 330. The fourth cache unit 320 includes a third cache subunit 321 and a fourth cache subunit 322. The second processing chip 310 is connected to the third program storage unit 330. After power-on, the second processing chip 310 obtains the control program from the third program storage unit 330. As an example, the third program storage unit 330 can be a flash memory (FLASH). The second processing chip 310 is connected to the third cache subunit 321 and the fourth cache subunit 322, and the second data to be synthesized under different pulse periods is put into the third cache subunit 321 and the fourth cache subunit 322 for ping-pong caching.

[0113] It should be noted that the process of synthesizing data by the second processing unit is the same as that of the first processing unit, which will not be repeated here.

[0114] Compared with the virtual skill release method in the prior art, the present application can perform hierarchical processing on multi-channel echo data through multiple FPGAs, and each hierarchical processing process is completed in a different FPGA. Compared with the digital beamforming device in the prior art, the present application solves the problems of difficult testing and verification and poor reliability and stability of data transmission in the existing digital beamforming device.

[0115] Figure 7 This is an application scenario in which the digital beamforming device of the embodiment of the present application can be used. In this application scenario, the digital beamforming device 10 can be applied to a back-end digital processing system of a synthetic aperture radar.

[0116] See also Figure 7 , Figure 7 This is a schematic diagram of the structure of the synthetic aperture radar back-end digital processing system 1 provided in the embodiment of the present application. Figure 7 As shown, the synthetic aperture radar back-end digital processing system 1 includes a digital beamforming device 10 , a backplane connector 20 and a control module 30 .

[0117] Optionally, the control module 30 includes a main control computer, which is connected to a collection unit in the digital beamforming device via a backplane connector to send control instructions to the collection unit.

[0118] Optionally, the control module further includes a reference frequency unit, which is connected to the digital beamforming device via a backplane connector to provide a working clock for the acquisition unit, the first processing unit and the second processing unit.

[0119] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0120] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0121] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0122] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0123] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application can essentially be embodied in the form of a software product, or in other words, the part that contributes to the prior art or the part of the technical solution. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0124] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-mentioned embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-mentioned embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A digital beamforming device, characterized in that: The digital beam synthesis device is carried on a radar installed on a mobile vehicle, and the digital beam synthesis device includes a collection unit, a first processing unit and a second processing unit; The acquisition unit is connected to the first processing unit and the second processing unit respectively; The acquisition unit receives a first multi-path echo signal to generate first data to be synthesized, and receives a second multi-path echo signal to generate second data to be synthesized, wherein the first data to be synthesized includes first multi-path baseband data, and the second data to be synthesized includes second multi-path baseband data, and the first multi-path echo signal and the second multi-path echo signal are echo signals in different directions; The acquisition unit sends the first data to be synthesized to the first processing unit, and sends the second data to be synthesized to the second processing unit; The first processing unit receives the first data to be synthesized, and synthesizes the first multiple baseband data in the first data to be synthesized into first combined baseband data, so as to send the first combined baseband data to an external device; The second processing unit receives the second data to be synthesized, and synthesizes the second multiple-channel baseband data in the second data to be synthesized into second combined baseband data, so as to send the second combined baseband data to an external device; The acquisition unit includes a first acquisition sub-board, a first buffer unit and an acquisition control chip, and the acquisition control chip is a field programmable logic gate array; The acquisition control chip of the acquisition unit generates the first data to be synthesized by the following steps: receiving first multi-channel echo data sent by the first acquisition sub-board, and putting the first multi-channel echo data into the first cache unit for storage, wherein the first multi-channel echo data is obtained after the first acquisition sub-board performs analog-to-digital conversion on the first multi-channel echo signal; Determining whether the first multi-channel echo data stored in the first cache unit reaches a first set threshold; If it is determined that the stored first multi-channel echo data reaches the first set threshold, reading the first multi-channel echo data from the first cache unit; Performing frequency mixing and half-band filtering extraction processing on the read first multi-channel echo data to generate first multi-channel baseband data; framing the first multiple-channel baseband data and first auxiliary data to generate first data to be synthesized, wherein the first auxiliary data is identification data of the first multiple-channel baseband data; The first processing unit includes a first processing chip and a third cache unit, the first processing chip is a field programmable logic gate array, and the first processing chip of the first processing unit synthesizes the first multiple-channel baseband data into first combined baseband data through the following steps: receiving the first data to be synthesized, placing the received first data to be synthesized into the third cache unit for caching, and determining whether the first data to be synthesized stored in the third cache unit reaches the first set threshold; If it is determined that the stored first data to be synthesized reaches the first set threshold, the first data to be synthesized is read from the third cache unit, and the read first data to be synthesized is parsed to obtain first multi-channel baseband data; Performing amplitude and phase correction, time domain weighted processing, and frequency domain weighted processing on the first multi-channel baseband data, and synthesizing the processed first multi-channel baseband data into first combined baseband data; The second processing unit includes a second processing chip and a fourth cache unit, the second processing chip is a field programmable logic gate array, and the second processing unit synthesizes the second multi-channel baseband data into second combined baseband data through the following steps: receiving the second data to be synthesized, placing the received second data to be synthesized into the fourth cache unit for caching, and determining whether the second data to be synthesized stored in the fourth cache unit reaches a second set threshold; If it is determined that the stored second data to be synthesized reaches the second set threshold, the second data to be synthesized is read from the fourth cache unit, and the read second data to be synthesized is parsed to obtain second multi-channel baseband data; The second multi-channel baseband data is subjected to amplitude and phase correction, time domain weighted processing, and frequency domain weighted processing, and the processed second multi-channel baseband data is synthesized into second combined baseband data.

2. The device according to claim 1, characterized in that The acquisition unit also includes a second acquisition sub-board and a second cache unit; The acquisition control chip of the acquisition unit generates the second data to be synthesized by the following steps: receiving second multi-channel echo data sent by the second acquisition sub-board, and putting the second multi-channel echo data into the second cache unit for storage, wherein the second multi-channel echo data is obtained after the second acquisition sub-board performs analog-to-digital conversion on the second multi-channel echo signal; Determining whether the second multi-channel echo data stored in the second cache unit reaches a second set threshold; If it is determined that the stored second multi-channel echo data reaches the second set threshold, reading the second multi-channel echo data from the second buffer unit; Performing frequency mixing and half-band filtering extraction processing on the read second multi-channel echo data to generate second multi-channel baseband data; The second multiplexed baseband data and second auxiliary data are framed to generate second data to be synthesized, wherein the second auxiliary data is identification data of the second multiplexed baseband data.

3. The device according to claim 1, characterized in that The third cache unit includes a first cache sub-unit and a second cache sub-unit; The first processing chip puts the received first data to be synthesized into the third cache unit for caching through the following steps: The first to-be-synthesized data with different pulse periods are respectively put into the first cache subunit and the second cache subunit for ping-pong cache.

4. The device according to claim 1, characterized in that The fourth cache unit includes a third cache sub-unit and a fourth cache sub-unit; The second processing chip puts the received second data to be synthesized into the fourth cache unit for caching through the following steps: The second to-be-synthesized data with different pulse periods are respectively put into the third cache subunit and the fourth cache subunit for ping-pong cache.

5. A synthetic aperture radar back-end digital processing system, characterized in that: The synthetic aperture radar back-end digital processing system comprises a control module, a backplane connector and a digital beamforming device as claimed in any one of claims 1 to 4.

6. The system according to claim 5, characterized in that The control module includes a main control computer; The main control computer is connected to the acquisition unit in the digital beamforming device through a backplane connector, and sends the control instructions to the acquisition unit.

7. The system according to claim 5, characterized in that The control module also includes a reference frequency unit; The reference frequency unit is connected to the digital beamforming device via a backplane connector, and provides a working clock for the acquisition unit, the first processing unit and the second processing unit.

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