Acceleration of in-memory data queries

Abstract

The present disclosure includes apparatus and methods for accelerating data queries in memory. Several embodiments include a memory cell array and a processing circuit system configured to receive a query for specific data stored in the array from a host, execute the query, and send only the specific data to the host when executing the query.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor memory devices and methods, and more particularly to devices and methods for acceleration of data queries in memory. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic systems. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), etc. Non-volatile memory can provide persistent data by retaining stored data when power is not applied and can include NAND flash memory, NOR flash memory, and resistance variable memory (e.g., phase change random access memory (PCRAM)), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), etc.

[0003] An electronic system typically includes several processing resources (e.g., one or more processors) that can retrieve and execute instructions and store the results of the executed instructions to appropriate locations. For example, a processor may include several functional units, such as arithmetic logic unit (ALU) circuitry, floating point unit (FPU) circuitry, and / or combinatorial logic blocks, which can be used to execute instructions by performing operations on data (e.g., one or more operands). As used herein, operations can be, for example, Boolean operations such as AND, OR, NOT, NAND, NOR, and XOR, and / or other operations (e.g., inversion, shift, arithmetic, statistics, and many other possible operations). For example, a functional unit circuitry (FUC) can be used to perform arithmetic operations on operands via several logical operations, such as addition, subtraction, multiplication, and / or division.

[0004] Providing instructions to the FUC for execution may involve several components in the electronic system. Instructions may be generated, for example, by processing resources such as a controller and / or a host processor. Data (e.g., operands on which instructions are to be executed) may be stored in a memory array accessible to the FUC. Before the FUC begins executing instructions on the data, instructions and / or data may be retrieved from the memory array and sorted and / or buffered. In addition, since different types of operations may be performed by the FUC in one or more clock cycles, intermediate results of the operations and / or data may also be sorted and / or buffered. A sequence of operations completed in one or more clock cycles may be referred to as an operation cycle. The time consumed to complete an operation cycle is costly in terms of processing and computing performance and power consumption of a computing device and / or system.

[0005] In many examples, the processing resources (e.g., processors and / or associated FUCs) may be external to the memory array, and data may be accessed via a bus between the processing resources and the memory array to execute a set of instructions. Processing performance may be improved in a processor-in-memory (PIM) device, where the processor may be implemented inside and / or near the memory (e.g., directly on the same chip as the memory array), which may save time and power in processing. A PIM device may save time and / or power by reducing and / or eliminating external communications. Summary of the invention

[0006] Aspects of the present disclosure provide an apparatus comprising: a memory cell array; and a processing circuit system configured to: receive a query from a host for specific data stored in the array; execute the query; and send only the specific data to the host when executing the query.

[0007] Another aspect of the present disclosure provides a method of operating a processing circuit system, wherein the method includes receiving a query from a host for data stored in a memory cell array; identifying the data stored in the array that matches the query; and sending only the identified data that matches the query to the host.

[0008] Another aspect of the present disclosure provides a device comprising: a memory cell array; and a processing circuit system configured to: receive a query for data stored in the array from a host; identify the data stored in the array that matches the query by performing arithmetic operations on the data stored in the array; and send only the identified data that matches the query to the host.

[0009] Another aspect of the present disclosure provides a system comprising: a host; and a memory device coupled to the host; wherein: the host is configured to send a query to the memory device for specific data stored in the memory device; and the memory device is configured to: execute the query when receiving the query from the host; and send only the specific data to the host when executing the query. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram of an apparatus in the form of a computing system including a memory device according to several embodiments of the present disclosure.

[0011] Figure 2A is a table illustrating an example of data that may be stored in a database according to several embodiments of the present disclosure.

[0012] Figure 2B According to several embodiments of the present disclosure, Figure 2A The data in the table described in the example record can be stored in the database.

[0013] Figure 3 is a representation of a process for performing a data query according to several embodiments of the present disclosure.

[0014] Figure 4 is a schematic diagram of methods and registers according to several embodiments of the present disclosure.

[0015] Figure 5 is a schematic diagram of methods and registers according to several embodiments of the present disclosure.

[0016] Figure 6 is a schematic diagram of methods and registers according to several embodiments of the present disclosure.

[0017] Figure 7 is a block diagram of a portion of a memory device according to several embodiments of the present disclosure.

[0018] Figure 8 is a block diagram of a page buffer and a latch according to several embodiments of the present disclosure.

[0019] Fig. 9 is a block diagram of a portion of a memory system according to several embodiments of the present disclosure. DETAILED DESCRIPTION

[0020] The present disclosure includes apparatus and methods for accelerating data queries in memory. Several embodiments include a memory cell array and a processing circuit system configured to receive a query for specific data stored in the array from a host, execute the query, and send only the specific data to the host after executing the query.

[0021] A memory, such as NAND flash memory, may be used as a database in a computing system. In some previous approaches, coordination of queries (e.g., searches) for data stored in the memory (e.g., in a database) may be controlled by circuitry external to the memory. For example, in some previous approaches, when a user of a host computing device coupled to the memory issues a query for some specific data stored in the memory, the data stored in the memory (e.g., pages of data) is transferred from the memory to the host, and the host then processes the received data to identify any data contained therein that matches the query (e.g., satisfies the parameters of the query). For example, the host may perform an operation (e.g., an arithmetic operation) on the data to identify data from the memory that matches the query.

[0022] However, controlling data queries via circuitry external to the memory in this manner may be inefficient due to the amount of time (e.g., latency) associated with transferring (e.g., sending) all data from the memory to external circuitry (e.g., a host) for processing. This latency may be further exacerbated by bandwidth bottlenecks that may occur between the memory and the host.

[0023] In contrast, embodiments of the present disclosure may utilize control circuitry resident on (e.g., physically located on or tightly coupled to) a memory to process a data query issued by a host (e.g., to identify data stored in the memory that matches the query). For example, embodiments of the present disclosure may utilize processor-in-memory (PIM) capabilities to perform operations (e.g., arithmetic operations) required to identify data that matches the query, such that only data in the memory that matches the query is sent to the host (e.g., without having to send all data from the memory to the host for processing).

[0024] Therefore, compared with previous methods (e.g., methods in which the query is controlled via an external circuit system), embodiments of the present disclosure can accelerate (e.g., increase the speed of) data query. In addition, embodiments of the present disclosure can perform data query operations on multiple portions of data stored in the memory in parallel, which can further accelerate the query.

[0025] As used herein, the designator "N", particularly with respect to reference numbers in the drawings, indicates that the number of the particular feature so designated may be included in several embodiments of the present disclosure. Additionally, as used herein, "a", "an" or "several" things may refer to one or more of such things, and "plurality" things may refer to two or more such things. For example, a number of memory cells may refer to one or more memory cells, and a plurality of memory cells may refer to two or more memory cells.

[0026] The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number and the remaining digits identify the element or component in the figure. Similar elements or components between different figures may be identified by using similar numerals. For example, 408 in Figure 2B Reference may be made to component "08" and similar components may be found in Figure 3 It can be referred to as 508.

[0027] Figure 1 1 is a block diagram of an apparatus in the form of a computing system 100 including a memory device 120 according to several embodiments of the present disclosure. As used herein, the memory device 120, the memory array 130, the controller 140, the sensing circuit system 150, and / or the buffer 170 may also be individually considered as an "apparatus". In addition, the controller 140, the sensing circuit system 150, and the buffer 170 may include the processing circuit system of the memory device 120. That is, the "processing circuit system" as used herein may refer to and / or include the controller 140, the sensing circuit system 150, and / or the buffer 170.

[0028] exist Figure 1 In the example illustrated in , system 100 includes a host 110 coupled (e.g., connected) to a memory device 120 that includes a memory array 130. Host 110 may be a host system, such as a personal laptop computer, a desktop computer, a digital camera, a mobile (e.g., a smart) phone, a memory card reader, and / or an Internet of Things (IoT) enabled device, as well as various other types of hosts. Host 110 may include a system motherboard and / or a backplane, and may include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of control circuitry). System 100 may include separate integrated circuits, or both host 110 and memory device 120 may be on the same integrated circuit. For example, system 100 may be a server system and / or a high performance computing (HPC) system and / or a portion thereof. Although Figure 1 The examples shown in illustrate a system having a von Neumann architecture, but embodiments of the present disclosure may be implemented in a non-von Neumann architecture, which may not include one or more components typically associated with a von Neumann architecture (e.g., CPU, ALU, etc.).

[0029] For clarity, system 100 has been simplified to focus on features that are particularly relevant to the present disclosure. For example, memory array 130 may be a DRAM array, an SRAM array, an STT RAM array, a PCRAM array, a TRAM array, an RRAM array, a NAND flash array, and / or a NOR flash array. Array 130 may include memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as digit lines or data lines). Although Figure 1 A single array 130 is shown in the figure, but the embodiments are not so limited. For example, the memory device 120 may include several arrays 130.

[0030] In several embodiments, memory array 130 may include (e.g., be part of and / or function as) a database, such as an employee database in which data (e.g., information) about employees is stored. For example, memory array 130 may include a plurality of pages of memory cells storing the data of the database (e.g., the data of the database may be arranged in pages). Each respective page may store a plurality of data records of the database, wherein each respective record includes a plurality of data fields. The amount of data included in each respective field (e.g., the data structure of the record) may be defined by host 110 (e.g., by a user of the host). This document will further describe (e.g., in conjunction with Figure 2A to 2B ) an instance of this database and a representation of how data is stored in this database.

[0031] Memory device 120 includes address circuitry 142 to latch address signals provided by input / output (I / O) circuitry 144 over a combined data / address bus 156 (e.g., an external input / output bus connected to host 110), which may include an internal I / O bus. Address signals are received by address circuitry 142 and decoded by row decoder 146 and column decoder 152 to access memory array 130. Data may be sensed (e.g., read) from memory array 130 by sensing voltage and / or current changes on data lines using a number of sense amplifiers of sense circuitry 150 as described herein. Sense circuitry 150 (e.g., sense amplifiers of sense circuitry 150) may read and latch a page (e.g., row) of data from memory array 130. Buffers (e.g., page buffers) 170 may be coupled to sense circuitry 150 and may be used in combination with sense circuitry 150 to sense, store (e.g., cache and / or buffer), perform computational functions (e.g., operate on), and / or move data, as will be further described herein. I / O circuitry 144 may be used for bidirectional data communication with host 110 via I / O bus 156. Write circuitry 148 may be used to program (e.g., write) data to memory array 130.

[0032] The control circuitry (e.g., controller) 140 decodes signals provided by the control bus 154 from the host 110. These signals may include chip enable signals, write enable signals, and / or address latch signals, which are used to control operations performed on the memory array 130, including data read, data write, data storage, data move (e.g., copy, transfer, and / or transmit data values), and / or data erase operations. In various embodiments, the control circuitry 140 is responsible for executing instructions from the host 110 and accessing the memory array 130. The control circuitry 140 may be a state machine, a sequencer, or some other type of controller.

[0033] In several embodiments, the sensing circuitry 150 may include several latches that may be used to store temporary data. In several embodiments, the sensing circuitry 150 and the buffer 170 (e.g., latches included in the sensing circuitry 150) may be used to perform operations using data stored in the array 130 as input, such as operations associated with data queries received from the host 110, as will be further described herein, without performing sense line address accesses (e.g., transferring data via sense line address accesses) (e.g., without triggering column decode signals). Thus, various operations (e.g., operations associated with data queries received from the host 110, as will be further described herein) may be performed using and within the sensing circuitry 150 and the buffer 170, rather than (or in association with) being performed by processing resources external to the sensing circuitry 150 (e.g., by a processor associated with the host 110 and / or other processing circuitry, such as ALU circuitry, located on the device 120 (e.g., located on the control circuitry 140 or elsewhere)).

[0034] In various previous approaches, when a query is issued for some specific data stored in the memory array 130, the data will be read from the memory via the sensing circuitry and provided to the external ALU circuitry via the I / O lines (e.g., via local and / or global I / O lines) and / or an external data bus. The external ALU circuitry may include several registers and will perform operations (e.g., arithmetic operations) on the data to identify the data contained in the read data that matches the query. In contrast, in several embodiments of the present disclosure, the sensing circuitry 150 and the buffer 170 are configured to perform such operations on the data stored in the memory cells in the memory array 130 without transferring the data via (e.g., enabling) I / O lines (e.g., local I / O lines) coupled to the sensing circuitry and buffers, which may be formed on the same chip as the array and / or formed with spacing from the memory cells of the array. Enabling the I / O lines may include enabling (e.g., turning on, activating) a transistor having a gate coupled to a decoding signal (e.g., a column decoding signal) and a source / drain coupled to the I / O line. Embodiments are not so limited.For example, in several embodiments, the sensing circuitry and buffers may be used to perform operations without enabling the column decode lines of the array.

[0035] In various embodiments, methods and apparatus are provided that can be used as a PIM. As used herein, a "PIM" refers to a memory in which operations can be performed without moving the data to be operated on to an external location, such as a host processor, via an external bus (e.g., bus 156).

[0036] Thus, in several embodiments, circuitry external to array 130, sensing circuitry 150, and buffer 170 (e.g., registers and / or ALUs) may not be required to perform operations, such as arithmetic operations associated with data queries received from host 110, as will be further described herein, because sensing circuitry 150 and buffer 170 may be controlled to perform appropriate operations associated with such computational functions without using external processing resources. Thus, sensing circuitry 150 and buffer 170 may be used to supplement and / or replace, at least to some extent, external processing resources (or at least the bandwidth of such external processing resources) such as host 110. However, in several embodiments, sensing circuitry 150 and buffer 170 may be used to perform operations (e.g., execute instructions) in addition to operations performed by external processing resources (e.g., host 110). For example, host 110 and / or sensing circuitry 150 may be limited to performing only certain operations and / or a certain number of logical operations.

[0037] As an example, memory device 120 may receive a query from host 110 for some specific data stored in memory array 130. For example, the query may include a command to search for any data stored in array 130 that meets specific parameters, such as any data stored in a specific (e.g., specific) one of a number of data fields of each corresponding data record stored in array 130. The query may be issued by a user of host 110, which may send the query to memory device 120. This document will further describe (e.g., in conjunction with Figure 3 ) instances of this query.

[0038] When memory device 120 receives a query from host 110, sensing circuitry 150 and buffer 170 (which, for simplicity, may be collectively referred to herein as sensing circuitry 150) may perform (e.g., run) the query by searching (e.g., locating and retrieving) specific data in memory array 130. For example, sensing circuitry 150 may identify any data stored in array 130 that matches the query (e.g., satisfies the parameters of the query). Furthermore, the query may be performed on multiple pages of data stored in array 130. For example, sensing circuitry 150 may perform the query in parallel (e.g., concurrently) on each of the pages of data stored in array 130 to identify in parallel whether data stored in a particular one of the number of data fields in each respective data record stored in array 130 matches the query. For example, in some cases, one page of data may store more data records than other pages, which may be a source of a high degree of parallelism. Furthermore, in examples where the memory device 120 includes multiple memory arrays, the sense circuitry 150 may perform queries on each of the arrays in parallel (eg, may perform the same query on each of the arrays in parallel).

[0039] As an example, the sensing circuitry 150 may perform a query (e.g., identify data stored in the memory array 130 that matches the query) by performing an arithmetic operation (e.g., a function) on the data stored in the array 130. Performing an arithmetic operation on the data may include, for example, determining whether a quantity represented by the data is less than a particular quantity, or determining whether a quantity represented by the data is greater than a particular quantity, as well as other arithmetic operations.

[0040] As an example, the sensing circuitry 150 may identify data stored in the memory array 130 that matches the query by sensing (e.g., reading) the data stored in the array and storing the sensed data in the page buffer 170, creating (e.g., constructing) a mask for the sensed data in the page buffer 170 on which an arithmetic operation is to be performed, creating (e.g., constructing) an operand for the arithmetic operation, applying an operator of the arithmetic operation to the operand and the sensed data in the page buffer 170 for which the mask was created, and invalidating sensed data that is determined to be invalid (e.g., and therefore does not match the query) when applying the operator of the arithmetic operation, so that only the sensed data that matches the query is available on the page buffer 170. This disclosure will be further described (e.g., in conjunction with Figure 3 ) is used to identify instances of this process that match a query.

[0041] The sensing circuitry 150 may perform arithmetic operations on multiple portions of the data in the array 130 in parallel (e.g., on each respective data record). For example, combining the page buffer 170 with the operation of the sensing circuitry 150 and implementing a left / right shift operation for the page buffer 170 allows the memory device 120 to be used as a single instruction multiple data (SIMID) device. Thus, the sensing circuitry 150 may perform the same arithmetic operation on a large amount of data in parallel. This will be further described herein (e.g., in conjunction with Figures 4 to 6 ) are examples of such complex arithmetic functions that can be performed using left / right shift operations.

[0042] Controller 140 may have error correction code (ECC) capabilities. For example, controller 140 may perform an ECC operation on the sensed data stored in page buffer 170 (e.g., before performing an arithmetic operation on the sensed data), and sensing circuitry 150 may perform an arithmetic operation on the sensed data after performing the ECC operation (e.g., so that any errors in the sensed data are corrected before performing the arithmetic operation).

[0043] When the sensing circuit system 150 performs a query (e.g., identifies data stored in the memory array 130 that matches the query), the sensing circuit system 150 (e.g., the memory device 120) may send (e.g., output) only the identified data to the host 110. That is, only the specific (e.g., particular) data for which the query is issued is sent to the host, and data stored in the array 130 that does not match the query is not sent to the host 110. For example, only the sensed data in the buffer 170 that is determined to be valid when an operator of an arithmetic operation is applied thereto (e.g., only the sensed data in the buffer 170 that is not invalidated) is sent to the host 110.

[0044] In several embodiments, the sensing circuitry 150 may perform a query in parallel with a subsequent (e.g., next) sensing operation. For example, the memory device 120 may receive a command from the host 110 to sense (e.g., read) data stored in the memory array 130 (e.g., data stored in a particular page of the array), and the sensing circuitry 150 may perform the sensing command in parallel with performing the query.

[0045] Figure 2A is a table 201 illustrating an example of data that may be stored in a database according to several embodiments of the present disclosure. Figure 2B 208 is a representation of an example where the data of table 201 may be stored in a database according to several embodiments of the present disclosure. For example, the database may include the previously described Figure 1 The memory array 130 is described as being within and / or including the memory array 130 .

[0046] For example, the database may be an employee database in which data (e.g., information) about employees is stored. Figure 2A In the example illustrated in , the database may store data about three employees (e.g., John, Serena, and William). The data stored in the database may include, for example, a programming number assigned to each of the employees (e.g., 0 for John, 1 for Serena, and 2 for William), the age of each employee (e.g., John is 45 years old, Serena is 34 years old, and William is 65 years old), the seniority of each employee (e.g., years of working at the company) (e.g., 15 years for John, 7 years for Serena, and 30 years for William), the identity of each employee (e.g., name), and the department in which the employee is located (e.g., John is in the engineering department, Serena is in the finance department, and William is in the research and development department), such as Figure 2A However, embodiments of the present disclosure are not limited to a particular number of employees, a particular type of data that may be stored in a database, or a particular type of database.

[0047] Figure 2A The data about each corresponding employee described in table 201 in may be contained in different corresponding records that may be stored in the database. Figure 2B An example representation of this data record 208 is illustrated in FIG.

[0048] As in Figure 2B , data record 208 may include a number of data fields 209, 211, 216, 217, 218, 219, 221, 223, and 228. Each respective data field of record 208 may store data corresponding to (e.g., representing) data for one of the employees illustrated in table 201. For example, in Figure 2BIn the example illustrated in , data field 209 may store data corresponding to an assigned programming number for the employee, data field 211 may store data corresponding to the employee's age, data field 216 may store data corresponding to the employee's seniority, data fields 217, 218, 219, and 221 may store data corresponding to the employee's identity, and data fields 223 and 228 may store data corresponding to the employee's department.

[0049] exist Figure 2B In the example illustrated in , data field 209 (e.g., data corresponding to an assigned programming number for an employee) may include 1 byte of data, data field 211 (e.g., data corresponding to the employee's age) may include 1 byte of data, and data field 216 (e.g., data corresponding to the employee's seniority) may include 1 byte of data. In addition, data fields 217, 218, 219, and 221 (e.g., data corresponding to the employee's identity) may include 16 bytes of data together. For example, each respective data field 217, 218, 219, and 221 may include 4 bytes of data. In addition, data fields 223 and 228 (e.g., data corresponding to the employee's department) may include 4 bytes of data together. For example, each respective data field 223 and 228 may include 2 bytes of data.

[0050] The amount of data contained in each respective field (e.g., the data structure of record 208) may be defined, for example, by a command issued by the host (e.g., by a user of the host), such as previously described in conjunction with Figure 1 For example, in the example illustrated in FIG2B , the user of the host defines the data structure of record 208 as 1-1-1-4-2. However, embodiments of the present disclosure are not limited to a specific data structure of record 208.

[0051] As described previously herein (e.g., in conjunction with Figure 1 ), the data of the database may be arranged in pages, and each respective page may store multiple data records. In several embodiments, the boundary of each respective data record stored in a page may be a data field of the record that stores data corresponding to the assigned programming number of the employee of the record. For example, the boundary of data record 208 would be data field 209. However, data record boundaries are not necessarily aligned with byte positions of any particular (e.g., a particular) page in the database.

[0052] Figure 3 is a representation of a process for performing a data query (e.g., identifying data stored in a database that matches the query) according to several embodiments of the present disclosure. Figure 1The database may be an employee database in which data about employees is stored, such as that previously described in connection with Figure 2A The data described in the table 201 described above and the data about each corresponding employee may be contained in different corresponding records, such as previously combined records stored in the database. Figure 2B In addition, the data structure of the data record can be defined by a command issued by the user, as previously described in conjunction with Figure 2B Description, so that the internal controller of the memory device (for example, previously combined Figure 1 The controller 140 described herein is aware of the data structure.

[0053] The data query may be received from (eg, issued by) a host (eg, a user of the host), such as previously associated with Figure 1 The host 110 is described. Figure 3 In the example illustrated in , the user of the host computer wishes to issue a query for all employees with less than 20 years of seniority. Since it is the third data field (e.g., field 316) in the data record for each employee corresponding to the seniority of the employee, the query will include a command to search for data that satisfies the parameter less than 20 stored in the third data field of each corresponding record, e.g., "search(3,'<',20)".

[0054] In response to receiving the data query, the sensing circuit system 150 can sense (eg, read) each data record stored in the employee database and store the sensed data record in the buffer 170. Figure 3 At element 332 of , data records 308 - 0 , 308 - 1 , and 308 - 2 for employees John, Selina, and William, respectively, are each sensed from the database and stored in the buffer.

[0055] As in Figure 3, each respective data record 308-0, 308-1, 308-2 includes data fields 309, 311, 316, 317, 318, 319, 321, 353, and 328 in a manner similar to data record 208 (e.g., data record 308-0 includes fields 309-0, 311-0, 316-0, etc., data record 308-1 includes fields 309-1, 311-1, 316-1, etc., and data record 308-2 includes fields 309-2, 311-2, 316-2, etc.). For example, data field 309-0 of record 308-0 stores data corresponding to John's assigned programming number 0, data field 316-0 of record 308-0 stores data corresponding to John's 15 years of seniority in hexadecimal form (e.g., 000F), data field 309-1 of record 308-1 stores data corresponding to Selina's assigned programming number, data field 316-1 of record 308-1 stores data corresponding to Selina's 7 years of seniority in hexadecimal form (e.g., 0007), data field 309-2 of record 308-2 stores data corresponding to William's assigned programming number 2, and data field 316-2 of record 308-2 stores data corresponding to William's 30 years of seniority in hexadecimal form (e.g., 001E), as shown in FIG. Figure 3 In the description.

[0056] exist Figure 3 At element 333 of , a mask is created (e.g., constructed) for the data fields 316-0, 316-1, and 316-2 of records 308-0, 308-1, and 308-2, respectively, in the page buffer because it is the data stored in these fields that will be checked for this query. That is, the mask is created based on the data structure of the record that has been defined by the user. The mask can be created in hexadecimal form (e.g., FFFF), such as Figure 3 In the description.

[0057] exist Figure 3 At element 334 of , an operand (e.g., a second operand) is created (e.g., constructed) for an arithmetic operation that can be used to determine whether the data stored in fields 316-0, 316-1, and 316-2 matches the query, and the operand is placed on these data fields in the page buffer. Since the parameter to be satisfied for the query is whether the data stored in these fields is less than 20, the operand for the arithmetic operation for the query will be 20, which is in hexadecimal form (e.g., 0014), as shown in FIG. Figure 3 In the description.

[0058] exist Figure 3At element 335 of , the operator of the arithmetic operation is applied to the operands and the data stored in fields 316-0, 316-1, and 316-2 to determine whether the data stored in each of these respective fields is valid (e.g., matches the query). Since the parameter to be satisfied for the query is whether the data stored in these fields is less than 20, the operator of the arithmetic operation will be <, and applying the operator will include determining whether the data stored in each respective field 316-0, 316-1, and 316-2 is less than 20. Therefore, the data stored in fields 316-0 and 316-1 will be determined to be valid (e.g., true), and the data stored in field 316-2 will be determined to be invalid (e.g., false), as shown in FIG. Figure 3 In the description.

[0059] exist Figure 3 At element 336 of , any data fields that are determined to be invalid (e.g., and therefore do not match the query) will be invalidated. For example, by changing the first data field (e.g., field 309) of the employee's data record to -1, the invalid data fields can be invalidated. For example, data field 309-2 (e.g., William's assigned programming number) will be changed to -1, while data fields 309-0 and 309-1 (e.g., John and Selina's assigned programming numbers, respectively) will not be changed, as shown in FIG. Figure 3 After the invalid data fields have been discarded, only the valid data fields will remain on the page buffer and sent to the host as previously described herein (e.g., in conjunction with Figure 1 ).

[0060] Figures 4 to 6 is a diagram of methods and registers according to several embodiments of the present disclosure. Figures 4 to 6 The methods and registers described in the can be used to perform complex arithmetic operations (e.g., functions), such as summation and subtraction, using left / right shift operations, so that the same arithmetic operation can be performed in parallel on a large amount of data (e.g., multiple data records of the memory array 130). In addition, such complex operations (e.g., summation and subtraction) can be used to perform complex database queries described herein. For example, subtraction operations utilizing such shift operations can be used to apply greater than (>) and less than (<) operators for performing complex queries described herein.

[0061] refer to Figure 4, showing an example of a complex sum function. A pair of words A (in register 437) and B (in register 438) are to be added. A and B registers 439 and 441, which may be page buffer registers in one embodiment, are used as a sum register (A register) and a carry register (B register), respectively. The sum of the individual binary digits in word A and word B is written to the corresponding sum register 439 entry, and the carry binary digit, if any, is written to the carry register 441. For example, adding word A 011110 and word B 110101 results in a base sum 101011 and a carry result 010100. Once the base sum and carry result are stored in the sum register and carry register, respectively, the carry result is shifted left, as shown at 443, resulting in the carry register containing 0101000, with an additional 0 added to replace the shifted 0 from register entry 445. The sum (101011) is summed again with the shifted carry result (0101000), resulting in a sum of 000011 and a carry result of 0101000 (447). This can be achieved in one embodiment by loading the sum and the shifted carry result into registers 437 and 438 and performing the operation. In another embodiment, a second set of sum registers and carry registers can be used. It should be understood that no matter what registers are used, the operation is the same, and the embodiments of the present disclosure are suitable for use with four or more registers. The carry result is shifted left again, resulting in 01010000, and the sum 000011 is added to the shifted carry result 01010000 (449), resulting in a sum of 1010011 and a carry result of 0000000 (451). When the carry register is full of 0 entries, the sum of word A and word B is completed. That is, 011110+110101=1010011. This complex function can be performed using basic logic operations present in sensing circuitry 150, page buffer 170, and left / right shift operations.

[0062] refer to Figure 5 , shows an example of a complex subtraction function. Binary word B (in register 538) is subtracted bit by bit from word A (in register 537), the base subtraction result is stored in register 539, and any borrow results are stored in borrow register 541. That is, if a borrow is to be performed, the specific binary digit of the borrow register is written with a logic 1. Then, when the subtraction base result is in register 539 and the borrow result is in register 541, the borrow result is shifted to the left and the shifted borrow result is subtracted from the subtraction base result, resulting in another subtraction base result and borrow result. The process is repeated until the borrow result logic is all logic 0. An example of subtraction is shown in Figure 5547, where word B 011110 (in register 538) is to be subtracted from word A 110101 (in register 537). The subtraction result has a base subtraction result of 101011 stored in register 539, and a borrow result of 001010 stored in borrow register 541, with an extra 0 added to replace the shifted 0 from register entry 545. The borrow result in register 541 is shifted left as shown at 543, resulting in 010100, and the shifted borrow result is subtracted from the base subtraction result stored in register 539. This results in a base subtraction result of 111111 and a borrow result of 010100 (547). The borrow result is shifted, resulting in 101000, which is subtracted from 111111 (549) in 010111 resulting in 010111 as the base subtraction result with the 000000 borrow result stored in register 551. The subtraction is complete, i.e., 110101-011110=10111. Again, this complex function can be performed with basic logic operations present in sensing circuitry 150, page buffer 170, and left / right shift operations.

[0063] Additional complex arithmetic functions can be performed using the basic principles outlined above. For example, multiplication can be performed as a series of additions. In addition, multiplication and division can also be performed using multiple registers and the ability to shift register contents described herein. For example, in multiplication, the basic multiplication function can be broken down into multiple blocks that can be shifted and added like a standard long form multiplication. For example, Figure 6 As shown in FIG. 6 , to multiply word A 10111 (637) by word B 111 (638), the following process may be used. Word A and word B regions are loaded into registers 637 and 638, respectively. The least significant bit (LSB) of word B (1) is multiplied by word A. The result, product 1, 10111, is stored in third register 639. The second LSB of word B (1) is multiplied by word A. The result, product 2, 10111, is stored in fourth register 641, and the contents of register 641 are shifted left to produce 101110, with an additional 0 added to replace the shifted 1 from register entry 645 (643). The results stored in registers 639 and 641 are added (not shown, but as described above with respect to FIG. 6 ). Figure 4 1000101, which in one embodiment is stored in the fifth register or product 1 register 639 (647). The third LSB of word B (1) is multiplied by word A. The product, 10111, is stored in register (647), and the product is shifted left two positions to produce 1011100 (649). In one embodiment, using the above description of Figure 4The described method adds the described result to 1000101, producing 10100001, the result of multiplication (651). It should be understood that registers may be reused for intermediate sum and carry operations and that register design is within the scope of one of ordinary skill in the art.

[0064] It should also be appreciated that additional arithmetic functions may be performed using the sensing circuitry 150, registers, page buffer 170, and left / right shift operations, and that such functionality is within the scope of the present disclosure.

[0065] Arithmetic functions and logic operations as described above may be performed in the page buffers of the memory array 730, such as Figure 7 In the description. Figure 7 730 (eg, previously associated with Figure 1 The page buffer 770 (eg, previously described in conjunction with the memory array 130) of the sense (eg, bit) lines 772 of the memory array 130) is Figure 1 170 described above). Input buffer 774 is also coupled to memory array 730. Input buffer 774 may be used to temporarily store input feature vectors for comparison with data feature vectors stored in memory array 730. Memory array 730 may include a plurality of memory cell string series, such as NAND flash memory cells, and may be a memory device (e.g., previously described in conjunction with Figure 1 1. The memory device 120 described herein may be a portion of the memory device 120).

[0066] Figure 8 8 is a block diagram of a page buffer 870 and a latch 886 according to several embodiments of the present disclosure. For example, the page buffer 870 may be a previously combined Figure 7 Page buffer 770 is depicted. In an embodiment, page buffer 770 can be up to 7 bits of data in depth.

[0067] Control of the page buffer 870 may be accomplished by a controller 882 having dedicated firmware 884. The firmware 884 and controller 882, in conjunction with the above-described data shifting embodied in modified latches 886 (e.g., latches that allow data shifting as described above), allow for the arithmetic functions and logic operations of the present disclosure. The controller 882 may control the previously combined Figure 7 7. The memory array 730 is described as being accessed and may generate status information for an external controller (eg, an external processing resource).

[0068] Fig. 9 9 is a block diagram of a portion of a memory system 902 according to several embodiments of the present disclosure. Fig. 9, the memory system 902 may include a plurality of memory devices (eg, NAND memory devices) 920-1, 920-2, ..., 920-N, which may be similar to those previously described in connection with Figure 1 Memory devices 120 are described. For example, each respective NAND device 920-1, 920-2, ..., 920-N may include a plurality of NAND flash memory cell arrays arranged in rows coupled by access lines (e.g., word lines) and columns coupled by sense lines (e.g., bit lines). For example, each respective NAND device 920 may be a bare die, a single packaged chip, a multi-chip package including NAND, a managed NAND device, a memory card, a solid state drive, or some combination thereof.

[0069] like Fig. 9 , each respective memory device 920-1, 920-2, ..., 920-N may include a page buffer 970-1, 970-2, ..., 970-N, each of which may be similar to the previously described memory devices. Figure 1 , 7 8. For example, the page buffers 970-1, 970-2, ..., 970-N can perform the arithmetic functions and logical operations described above in conjunction with performing data queries according to the present disclosure. In addition, each respective memory device 920-1, 920-2, ..., 920-N can include an I / O circuit system 944-1, 944-2, ..., 944-N, such as Fig. 9 It is described in, which can be similar to the previous combination Figure 1 I / O circuitry 144 is described.

[0070] Each respective page buffer 970 may be formed on the same chip as the array of its respective NAND device 920. For example, page buffer 970-1 may be formed on the same chip as the array of NAND device 920-1, page buffer 970-2 may be formed on the same chip as the array of NAND device 920-2, and so on. Furthermore, although for simplicity and in order not to obscure the embodiments of the present disclosure, in Fig. 9 970 is shown for each respective NAND device 920, but each respective NAND device 920 may include several page buffers similar to page buffer 970. For example, each respective NAND device 920 may include a different respective page buffer for each respective memory array of the device (e.g., formed on the same chip therewith).

[0071] like Fig. 9, memory system 902 may include controller 983. Controller 983 may be an external controller (e.g., external to NAND device 920) that may control (e.g., control) NAND device 920. For example, controller 983 may be a controller on a host device, such as previously described in connection with Figure 1 A host 110 is described.

[0072] Although specific embodiments have been illustrated and described herein, it will be appreciated by those skilled in the art that arrangements calculated to achieve the same results may replace the specific embodiments shown. The present disclosure is intended to cover adaptations or variations of several embodiments of the present disclosure. It should be appreciated that the above description has been made in an illustrative and non-restrictive manner. After reviewing the above description, those skilled in the art will understand the combination of the above embodiments and other embodiments not explicitly described herein. The scope of several embodiments of the present disclosure includes other applications using the above structures and methods. Therefore, the scope of several embodiments of the present disclosure should be determined with reference to the attached claims and the full scope of equivalents to which such claims are entitled.

[0073] In the foregoing detailed description, some features are grouped in a single embodiment for the purpose of simplifying the present disclosure. This method of disclosure should not be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure must use more features than those explicitly recited in each claim. Rather, as the appended claims reflect, the subject matter of the invention exists in less than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, with each claim independently serving as a separate embodiment.

Claims

1. A device (120, 920), comprising: Memory cell array (130, 730); and Processing circuitry (140, 150, 170, 770, 870, 970) configured to: receiving a query from a host (110) for specific data stored in the array (130, 730); Execute the query by doing the following: sensing data stored in the array (130, 730); creating a mask for the sensed data on which the arithmetic operation is to be performed; creating operands for said arithmetic operation; applying an operator of the arithmetic operation to the operands and the sensed data for which the mask was created; and when applying the operator of the arithmetic operation, invalidating the sensed data determined to be invalid; and Only the specific data is sent to the host (110) when the query is performed.

2. The apparatus of claim 1, wherein the processing circuitry includes a page buffer (170, 770, 870, 970) configured to apply the operands of the arithmetic operation.

3. The apparatus of claim 1, wherein the array and the processing circuitry are formed on a same chip of the apparatus.

4. The apparatus according to claim 1, wherein: The query includes a command to search for the specific data; and The processing circuitry is configured to perform the query by searching the array for the particular data.

5. The apparatus according to any one of claims 1 to 4, wherein: The array includes a plurality of pages of memory cells; and The processing circuitry is configured to perform the query on each of the pages.

6. The apparatus of any one of claims 1 to 4, wherein the processing circuitry is configured to: receiving a command from the host to sense data stored in the array; and The command is executed to sense the data in parallel with executing the query.

7. A method of operating a processing circuit system (140, 150, 170, 770, 870, 970), comprising: receiving a query from a host (110) for data stored in a memory cell array (130, 730); performing an error correction code (ECC) operation on the data stored in the array (130, 730); identifying the data stored in the array (130, 730) that matches the query by performing an arithmetic operation on the data stored in the array (130, 730) after performing the ECC operation on the data; and Only the identified data matching the query is sent to the host (110).

8. The method of claim 7, wherein data stored in the array that does not match the query is not sent to the host.

9. The method according to any one of claims 7 to 8, wherein: The data stored in the array comprises a plurality of records (208, 308), wherein each respective record (208, 308) comprises a plurality of fields (209, 211, 216, 217, 218, 219, 221, 223, 228, 309, 311, 316, 317, 318, 319, 321, 353, 328); and Identifying the data stored in the array that matches the query includes identifying whether data in one of the several fields (209, 211, 216, 217, 218, 219, 221, 223, 228, 309, 311, 316, 317, 318, 319, 321, 353, 328) stored in each corresponding record (208, 308) matches the query.

10. An apparatus (120, 920), comprising: Memory cell array (130, 730); and Processing circuitry (140, 150, 170, 770, 870, 970) configured to: receiving a query from a host (110) for data stored in the array (130, 730); performing an error correction code (ECC) operation on the data stored in the array (130, 730); identifying the data stored in the array (130, 730) that matches the query by performing an arithmetic operation on the data stored in the array (130, 730) after performing the ECC operation on the data; and Only the identified data matching the query is sent to the host (110).

11. The apparatus of claim 10, wherein performing the arithmetic operation on the data stored in the array comprises performing the arithmetic operation on multiple portions of the data in parallel.

12. The apparatus of claim 10, wherein performing the arithmetic operation on the data stored in the array comprises determining whether a quantity represented by the data stored in the array is less than or greater than a particular quantity.

13. The apparatus of claim 10, wherein the processing circuitry is configured to identify the data stored in the array that matches the query by: sensing the data stored in the array; creating a mask for the sensed data on which the arithmetic operation is to be performed; creating operands for said arithmetic operation; applying an operator of the arithmetic operation to the operands and the sensed data for which the mask was created; and The sensed data determined to be invalid is discarded when applying the operator of the arithmetic operation.

14. The apparatus of any one of claims 10-13, wherein the processing circuitry is formed spaced apart from the memory cells of the array.

15. A system (100), comprising: Host (110); and a memory device (120, 920) coupled to the host (110); in: The host (110) is configured to send a query to the memory device (120, 920) for specific data stored in the memory device (120, 920); and The memory device (120, 920) is configured to: Upon receiving the query from the host (110), the query is performed by: sensing data stored in the memory device (120, 920); creating a mask for the sensed data on which the arithmetic operation is to be performed; creating operands for said arithmetic operation; applying an operator of the arithmetic operation to the operands and the sensed data for which the mask was created; and upon applying the operator of the arithmetic operation, invalidating the sensed data determined to be invalid; and Only the specific data is sent to the host (110) when the query is performed.

16. The system of claim 15, wherein: The memory device includes a plurality of records (208, 308) of data; and Each corresponding record (208, 308) includes a number of data fields (209, 211, 216, 217, 218, 219, 221, 223, 228, 309, 311, 316, 317, 318, 319, 321, 353, 328).

17. The system of claim 16, wherein the query for the specific data stored in the memory device comprises a query for data stored in a specific one of the number of data fields of each respective record.

18. The system of claim 16, wherein the host is configured to define an amount of data included in each respective data field of the plurality of records.

19. The system of any one of claims 15 to 18, wherein: The memory device includes a plurality of memory arrays (130, 730); and The memory device is configured to perform the query on each of the memory arrays (130, 730) in parallel.

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