Insulator flashover fault recognition method and device based on unet++ of cavity convolution, medium and equipment

Abstract

The application discloses an insulator flashover fault recognition method based on a cavity convolution Unet+++ and comprises the following steps: acquiring an insulator image to be recognized, obtaining a bright light image label graph and an insulator image label graph according to the insulator image, performing segmentation on the bright light image label graph based on the cavity convolution Unet+++, generating a bright light segmentation graph, extracting an insulator position according to the insulator label graph, corresponding the insulator position to a bright light position on the bright light segmentation graph, calculating a white pixel area proportion on the bright light position, and positioning an insulator flashover fault according to the white pixel area proportion. The application solves the problems of poor speed and precision in insulator flashover fault recognition in the prior art.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to an insulator flashover fault identification method, device, medium and equipment based on Unet+++ of void convolution. Background Art

[0002] In the existing power transmission and distribution sector, numerous overhead transmission lines are located in remote areas and traverse diverse climate zones. Insulators, a key component of these transmission lines, are essential insulation components. When exposed to various conditions, such as pollution, rain, snow, ice melt, and fog, these insulators experience varying degrees of degradation in insulation performance, increasing the probability of flashover failures. Therefore, studying the flashover characteristics of insulators and accurately identifying and locating their flashover locations is crucial.

[0003] Existing technologies for identifying insulator flashover faults include ultraviolet imaging, infrared imaging, electric field methods, machine learning-based threshold binarization methods, and deep learning-based methods. However, these methods all suffer from poor speed and accuracy when identifying insulator flashover faults. Summary of the Invention

[0004] The embodiments of the present invention provide a method, apparatus, medium and equipment for identifying insulator flashover faults based on Unet+++ of void convolution, so as to solve the problems of poor speed and accuracy in the prior art when identifying insulator flashover faults.

[0005] An insulator flashover fault identification method based on Unet+++ of void convolution, the method comprising:

[0006] Acquire an insulator image to be identified, and obtain a bright light image label map and an insulator image label map according to the insulator image;

[0007] The bright light image label map is segmented by Unet+++ based on the dilated convolution to generate a bright light segmentation map;

[0008] extracting the insulator position according to the insulator image label map;

[0009] Calculating the white pixel area ratio at the bright light position according to the correspondence between the insulator position and the bright light position on the bright light segmentation map;

[0010] The insulator flashover fault is located according to the white pixel area ratio.

[0011] Optionally, the acquiring of the insulator image to be identified and obtaining the bright light image label map and the insulator image label map according to the insulator image includes:

[0012] Acquiring an insulator image to be identified;

[0013] Marking a target area of ​​a bright light position in the insulator image to obtain a bright light image label map;

[0014] The insulator target area in the insulator image is labeled to obtain an insulator image label map.

[0015] Optionally, segmenting the bright light image label map using the Unet+++ based on dilated convolution to generate a bright light segmentation map includes:

[0016] In the encoding stage of the Unet+++ network, the bright light image label map is convolved several times in sequence to generate several encoding stage feature maps;

[0017] In the decoding stage of the Unet+++ network, the feature maps of the encoding stage are subjected to dilated convolution in a preset manner to generate a bright light segmentation map.

[0018] Optionally, the encoding stage includes a first encoding stage, a second encoding stage, a third encoding stage, a fourth encoding stage, and a fifth encoding stage;

[0019] In the encoding stage of the Unet+++ network, the bright light image label map is sequentially convolved several times to generate several encoding stage feature maps including:

[0020] In the first encoding stage, a convolution operation is performed on the bright light image label map according to a first convolution kernel to generate a first feature map of the encoding stage;

[0021] In the second encoding stage, a maximum pooling operation and a convolution operation according to a second convolution kernel are performed on the first feature map to generate a second feature map in the encoding stage;

[0022] In the third encoding stage, a maximum pooling operation and a convolution operation according to a third convolution kernel are performed on the second feature map to generate a third feature map in the encoding stage;

[0023] In the fourth encoding stage, a maximum pooling operation and a convolution operation according to a fourth convolution kernel are performed on the third feature map to generate a fourth feature map in the encoding stage;

[0024] In the fifth encoding stage, a maximum pooling operation and a convolution operation are performed on the fourth feature map according to the fifth convolution kernel to generate a fifth feature map in the encoding stage.

[0025] Optionally, the decoding stage includes a first decoding stage, a second decoding stage, a third decoding stage, and a fourth decoding stage;

[0026] In the decoding stage of the Unet+++ network, performing dilated convolution on the plurality of encoding stage feature maps in a preset manner to generate a bright light segmentation map includes:

[0027] In the fourth decoding stage, the first feature map is downsampled 8 times, the first convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the first feature map, and then batch normalization and Relu activation function operations are performed to obtain the first feature map after tensor processing; the second feature map is downsampled 4 times, the second convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the second feature map, and then batch normalization and Relu activation function operations are performed to obtain the second feature map after tensor processing; the third feature map is downsampled 2 times, the third convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the third feature map, and then batch normalization and Relu activation function operations are performed to obtain a tensor. the processed third feature map; for the fourth feature map, updating the fourth convolution kernel to a convolution kernel with a dilation rate of 2, using the updated convolution kernel to perform a convolution operation on the fourth feature map, and then performing batch normalization and Relu activation function operations to obtain the fourth feature map after tensor processing; performing 2x bilinear interpolation upsampling on the fifth feature map, updating the fourth convolution kernel to a convolution kernel with a dilation rate of 2, using the updated convolution kernel to perform a convolution operation on the fifth feature map, and then performing batch normalization and Relu activation function operations to obtain the fifth feature map after tensor processing; performing tensor dimension splicing on the first feature map, the second feature map, the third feature map, the fourth feature map and the fifth feature map after tensor processing, and then performing convolution operations, batch normalization and Relu activation function operations to generate a fourth decoding stage feature map;

[0028] In the third decoding stage, the first feature map is downsampled by 4 times, the first convolution kernel is updated to a convolution kernel with a dilation rate of 2, the first feature map is convolved with the updated convolution kernel, and then batch normalization and Relu activation function operations are performed to obtain the first feature map after tensor processing; the second feature map is downsampled by 2 times, the second convolution kernel is updated to a convolution kernel with a dilation rate of 2, the second feature map is convolved with the updated convolution kernel, and then batch normalization and Relu activation function operations are performed to obtain the second feature map after tensor processing; for the third feature map, the third convolution kernel is updated to a convolution kernel with a dilation rate of 2, the third feature map is convolved with the updated convolution kernel, and then batch normalization and Relu activation function operations are performed to obtain the third feature map after tensor processing; the fourth decoding The fourth decoding stage feature map is upsampled by 2 times bilinear interpolation, the fourth convolution kernel is updated to a convolution kernel with a dilation rate of 2, and the updated convolution kernel is used to perform a convolution operation on the fourth decoding stage feature map, and then batch normalization and Relu activation function operations are performed to obtain the fourth decoding stage feature map after tensor processing; the fifth feature map is upsampled by 4 times bilinear interpolation, the fifth convolution kernel is updated to a convolution kernel with a dilation rate of 2, and the fifth feature map is convolved with the updated convolution kernel, and then batch normalization and Relu activation function operations are performed to obtain the fifth feature map after tensor processing; the first feature map, the second feature map, the third feature map, the fourth decoding stage feature map and the fifth feature map after tensor processing are spliced ​​in tensor dimension, and then convolution operation, batch normalization and Relu activation function operation are performed to generate the third decoding stage feature map;

[0029] In the second decoding stage, the first feature map is downsampled by 2 times, the first convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the first feature map, and then batch normalization processing and Relu activation function operation are performed to obtain the first feature map after tensor processing; for the second feature map, the second convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the second feature map, and then batch normalization processing and Relu activation function operation are performed to obtain the second feature map after tensor processing; the third decoding stage feature map is upsampled by 2 times bilinear interpolation, the third convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the third decoding stage feature map, and then batch normalization processing and Relu activation function operation are performed to obtain the third decoding stage feature map after tensor processing; The fourth decoding stage feature map is upsampled by 4 times bilinear interpolation, the fourth convolution kernel is updated to a convolution kernel with a dilation rate of 2, and the updated convolution kernel is used to perform a convolution operation on the fourth decoding stage feature map, and then batch normalization and Relu activation function operations are performed to obtain the fourth decoding stage feature map after tensor processing; the fifth feature map is upsampled by 8 times bilinear interpolation, the fifth convolution kernel is updated to a convolution kernel with a dilation rate of 2, and the updated convolution kernel is used to perform a convolution operation on the fifth feature map, and then batch normalization and Relu activation function operations are performed to obtain the fifth feature map after tensor processing; the first feature map, the second feature map, the third decoding stage feature map, the fourth decoding stage feature map and the fifth feature map after tensor processing are tensor dimension spliced, and then convolution operation, batch normalization and Relu activation function operation are performed to generate the second decoding stage feature map;

[0030] In the first decoding stage, for the first feature map, the first convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the first feature map, and then batch normalization processing and Relu activation function operation are performed to obtain the first feature map after tensor processing; the second decoding stage feature map is upsampled by 2 times bilinear interpolation, the second convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the second decoding stage feature map, and then batch normalization processing and Relu activation function operation are performed to obtain the second decoding stage feature map after tensor processing; the third decoding stage feature map is upsampled by 4 times bilinear interpolation, the third convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the third decoding stage feature map, and then batch normalization processing and Relu activation function operation are performed to obtain the third decoding stage feature map after tensor processing. segment feature map; perform 8 times bilinear interpolation upsampling on the fourth decoding stage feature map, update the fourth convolution kernel to a convolution kernel with a dilation rate of 2, use the updated convolution kernel to perform a convolution operation on the fourth decoding stage feature map, and then perform batch normalization and Relu activation function operation to obtain the fourth decoding stage feature map after tensor processing; perform 16 times bilinear interpolation upsampling on the fifth feature map, update the fifth convolution kernel to a convolution kernel with a dilation rate of 2, use the updated convolution kernel to perform a convolution operation on the fifth feature map, and then perform batch normalization and Relu activation function operation to obtain the fifth feature map after tensor processing; perform tensor dimension splicing on the first feature map, the second decoding stage feature map, the third decoding stage feature map, the fourth decoding stage feature map and the fifth feature map after tensor processing, and then perform convolution operation, batch normalization and Relu activation function operation to generate the first decoding stage feature map;

[0031] A convolution operation is performed on the feature map of the first decoding stage to generate a bright light segmentation map.

[0032] Optionally, the calculating the white pixel area ratio at the bright light position according to the correspondence between the insulator position and the bright light position on the bright light segmentation map includes:

[0033] Binarization is performed on the bright light segmentation image, and pixels with grayscale values ​​within a first threshold range are set to white, otherwise pixels are set to black;

[0034] The bright light position on the bright light segmentation map corresponding to the insulator position is obtained, and the area ratio of the white pixels at the bright light position to the bright light position is calculated.

[0035] Optionally, locating the insulator flashover fault according to the white pixel area ratio includes:

[0036] Comparing the white pixel area ratio with a preset ratio threshold;

[0037] If the white pixel area ratio is greater than or equal to the preset ratio threshold, a flashover fault occurs in the insulator corresponding to the bright light position;

[0038] If the white pixel area ratio is smaller than the preset ratio threshold, no flashover fault occurs to the insulator at the bright light position.

[0039] An insulator flashover fault identification device based on Unet+++ of void convolution, the device comprising:

[0040] an acquisition module, configured to acquire an insulator image to be identified, and obtain a bright light image label map and an insulator image label map according to the insulator image;

[0041] A segmentation module, configured to segment the bright light image label map based on Unet+++ with dilated convolution to generate a bright light segmentation map;

[0042] an extraction module, configured to extract the insulator position according to the insulator image label map;

[0043] A calculation module, configured to calculate the area ratio of white pixels at the bright light position according to the correspondence between the insulator position and the bright light position on the bright light segmentation map;

[0044] A fault identification module is used to locate the insulator flashover fault according to the white pixel area ratio.

[0045] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the insulator flashover fault identification method based on Unet+++ of void convolution.

[0046] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the insulator flashover fault identification method based on Unet+++ of the void convolution is implemented.

[0047] The embodiment of the present invention obtains an insulator image to be identified, obtains a bright light image label map and an insulator image label map based on the insulator image; segments the bright light image label map based on Unet+++ with void convolution to generate a bright light segmentation map; extracts the insulator position based on the insulator image label map; calculates the white pixel area ratio at the bright light position based on the correspondence between the insulator position and the bright light position on the bright light segmentation map; and locates the insulator flashover fault based on the white pixel area ratio, thereby effectively improving the speed and accuracy of insulator flashover fault identification. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0049] Figure 1 This is a flow chart of an insulator flashover fault identification method based on Unet+++ of void convolution provided by one embodiment of the present invention;

[0050] Figure 2 This is a flowchart for implementing step S102 in the insulator flashover fault identification method based on Unet+++ of void convolution provided by one embodiment of the present invention;

[0051] Figure 3 This is a flowchart for implementing step S104 in the insulator flashover fault identification method based on Unet+++ of void convolution provided by one embodiment of the present invention;

[0052] Figure 4 This is a flowchart for implementing step S105 in the insulator flashover fault identification method based on Unet+++ of void convolution provided by one embodiment of the present invention;

[0053] Figure 5 1 is a schematic structural diagram of an insulator flashover fault identification device based on Unet+++ of void convolution provided by an embodiment of the present invention;

[0054] Figure 6 FIG. 1 is a schematic diagram of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0055] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0056] The embodiment of the present invention realizes the segmentation of flashover faults in the insulator image to be identified through an image segmentation network, and realizes the positioning of the insulator flashover faults through big data processing, thereby effectively improving the speed and accuracy of insulator flashover fault identification.

[0057] The following is a detailed description of the insulator flashover fault identification method based on Unet+++ provided by this embodiment. Figure 1 As shown, the insulator flashover fault identification method based on Unet+++ of void convolution includes:

[0058] In step S101 , an insulator image to be identified is acquired, and a bright light image label map and an insulator image label map are obtained according to the insulator image.

[0059] Optionally, as a preferred embodiment of the present invention, step S101 includes:

[0060] In step S1011 , an image of an insulator to be identified is obtained.

[0061] Here, the embodiment of the present invention collects monitoring site video and intercepts the video as one frame every 10 seconds to obtain the insulator image to be identified.

[0062] In step S1012, the target area of ​​the bright light position in the insulator image is marked to obtain a bright light image label map.

[0063] In step S1013 , the insulator target area in the insulator image is labeled to obtain an insulator image label map.

[0064] Here, the embodiment of the present invention performs two annotations: one is to annotate the bright light position target area in the insulator image to generate a bright light image label map; the other is to annotate the insulator target area in the insulator image to generate an insulator image label map.

[0065] In step S102, the bright light image label map is segmented based on the Unet+++ of the dilated convolution to generate a bright light segmentation map.

[0066] Here, the Unet+++ network is a deep learning network with an encoding-decoding structure, including an encoding stage and a decoding stage, and is widely used in image segmentation. Figure 2 As shown, step S102 includes:

[0067] In step S1021, in the encoding stage of the Unet+++ network, the bright light image label map is sequentially convolved several times to generate several encoding stage feature maps.

[0068] In step S1022, in the decoding stage of the Unet+++ network, a dilated convolution is performed on the feature maps in the encoding stage according to a preset method to generate a bright light segmentation map.

[0069] The embodiment of the present invention adopts the image segmentation network Unet+++ in the identification of insulator network faults, which can segment and identify insulator flashover faults in the image; and in the decoding stage of the image segmentation network Unet+++, the convolution layer is changed to a void convolution, and the feature map in the encoding stage is subjected to void convolution, which can effectively improve the speed and accuracy of insulator flashover fault identification.

[0070] Optionally, as a preferred example of the present invention, the encoding stage includes a first encoding stage, a second encoding stage, a third encoding stage, a fourth encoding stage, and a fifth encoding stage;

[0071] In the encoding stage of the Unet+++ network, the bright light image label map is sequentially convolved several times to generate several encoding stage feature maps including:

[0072] In the first encoding stage, a convolution operation is performed on the bright light image label map according to a first convolution kernel to generate a first feature map of the encoding stage;

[0073] In the second encoding stage, a maximum pooling operation and a convolution operation according to a second convolution kernel are performed on the first feature map to generate a second feature map in the encoding stage;

[0074] In the third encoding stage, a maximum pooling operation and a convolution operation according to a third convolution kernel are performed on the second feature map to generate a third feature map in the encoding stage;

[0075] In the fourth encoding stage, a maximum pooling operation and a convolution operation according to a fourth convolution kernel are performed on the third feature map to generate a fourth feature map in the encoding stage;

[0076] In the fifth encoding stage, a maximum pooling operation and a convolution operation are performed on the fourth feature map according to the fifth convolution kernel to generate a fifth feature map in the encoding stage.

[0077] Here, the embodiment of the present invention divides the encoding stage into five sub-stages, and the corresponding outputs are the first feature map h1, the second feature map h2, the third feature map h3, the fourth feature map h4, and the fifth feature map h5. First, the bright light image label map is input into the Unet+++ network, and a normal convolution operation is performed to generate the first feature map h1 of the encoding stage. The first feature map h1 is used as input, and maximum pooling and convolution operations are performed to generate the second feature map h2 of the encoding stage. The first feature map h2 is used as input, and maximum pooling and convolution operations are performed to generate the third feature map h3 of the encoding stage. The third feature map h3 is used as input, and maximum pooling and convolution operations are performed to generate the fourth feature map h4 of the encoding stage. The fourth feature map h4 is used as input, and maximum pooling and convolution operations are performed to generate the fifth feature map hd5 of the encoding stage. The embodiment of the present invention uses the encoding stage to sort out the relationships between image pixels.

[0078] Optionally, as a preferred example of the present invention, the decoding stage includes a first decoding stage, a second decoding stage, a third decoding stage, and a fourth decoding stage;

[0079] In the decoding stage of the Unet+++ network, performing dilated convolution on the plurality of encoding stage feature maps in a preset manner to generate a bright light segmentation map includes:

[0080] In the fourth decoding stage, the first feature map is downsampled 8 times, the first convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the first feature map, and then batch normalization and Relu activation function operations are performed to obtain the first feature map after tensor processing; the second feature map is downsampled 4 times, the second convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the second feature map, and then batch normalization and Relu activation function operations are performed to obtain the second feature map after tensor processing; the third feature map is downsampled 2 times, the third convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the third feature map, and then batch normalization and Relu activation function operations are performed to obtain a tensor. the processed third feature map; for the fourth feature map, updating the fourth convolution kernel to a convolution kernel with a dilation rate of 2, using the updated convolution kernel to perform a convolution operation on the fourth feature map, and then performing batch normalization and Relu activation function operations to obtain the fourth feature map after tensor processing; performing 2x bilinear interpolation upsampling on the fifth feature map, updating the fourth convolution kernel to a convolution kernel with a dilation rate of 2, using the updated convolution kernel to perform a convolution operation on the fifth feature map, and then performing batch normalization and Relu activation function operations to obtain the fifth feature map after tensor processing; performing tensor dimension splicing on the first feature map, the second feature map, the third feature map, the fourth feature map and the fifth feature map after tensor processing, and then performing convolution operations, batch normalization and Relu activation function operations to generate a fourth decoding stage feature map;

[0081] In the third decoding stage, the first feature map is downsampled by 4 times, the first convolution kernel is updated to a convolution kernel with a dilation rate of 2, the first feature map is convolved with the updated convolution kernel, and then batch normalization and Relu activation function operations are performed to obtain the first feature map after tensor processing; the second feature map is downsampled by 2 times, the second convolution kernel is updated to a convolution kernel with a dilation rate of 2, the second feature map is convolved with the updated convolution kernel, and then batch normalization and Relu activation function operations are performed to obtain the second feature map after tensor processing; for the third feature map, the third convolution kernel is updated to a convolution kernel with a dilation rate of 2, the third feature map is convolved with the updated convolution kernel, and then batch normalization and Relu activation function operations are performed to obtain the third feature map after tensor processing; the fourth decoding The fourth decoding stage feature map is upsampled by 2 times bilinear interpolation, the fourth convolution kernel is updated to a convolution kernel with a dilation rate of 2, and the updated convolution kernel is used to perform a convolution operation on the fourth decoding stage feature map, and then batch normalization and Relu activation function operations are performed to obtain the fourth decoding stage feature map after tensor processing; the fifth feature map is upsampled by 4 times bilinear interpolation, the fifth convolution kernel is updated to a convolution kernel with a dilation rate of 2, and the fifth feature map is convolved with the updated convolution kernel, and then batch normalization and Relu activation function operations are performed to obtain the fifth feature map after tensor processing; the first feature map, the second feature map, the third feature map, the fourth decoding stage feature map and the fifth feature map after tensor processing are spliced ​​in tensor dimension, and then convolution operation, batch normalization and Relu activation function operation are performed to generate the third decoding stage feature map;

[0082] In the second decoding stage, the first feature map is downsampled by 2 times, the first convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the first feature map, and then batch normalization processing and Relu activation function operation are performed to obtain the first feature map after tensor processing; for the second feature map, the second convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the second feature map, and then batch normalization processing and Relu activation function operation are performed to obtain the second feature map after tensor processing; the third decoding stage feature map is upsampled by 2 times bilinear interpolation, the third convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the third decoding stage feature map, and then batch normalization processing and Relu activation function operation are performed to obtain the third decoding stage feature map after tensor processing; The fourth decoding stage feature map is upsampled by 4 times bilinear interpolation, the fourth convolution kernel is updated to a convolution kernel with a dilation rate of 2, and the updated convolution kernel is used to perform a convolution operation on the fourth decoding stage feature map, and then batch normalization and Relu activation function operations are performed to obtain the fourth decoding stage feature map after tensor processing; the fifth feature map is upsampled by 8 times bilinear interpolation, the fifth convolution kernel is updated to a convolution kernel with a dilation rate of 2, and the updated convolution kernel is used to perform a convolution operation on the fifth feature map, and then batch normalization and Relu activation function operations are performed to obtain the fifth feature map after tensor processing; the first feature map, the second feature map, the third decoding stage feature map, the fourth decoding stage feature map and the fifth feature map after tensor processing are tensor dimension spliced, and then convolution operation, batch normalization and Relu activation function operation are performed to generate the second decoding stage feature map;

[0083] In the first decoding stage, for the first feature map, the first convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the first feature map, and then batch normalization processing and Relu activation function operation are performed to obtain the first feature map after tensor processing; the second decoding stage feature map is upsampled by 2 times bilinear interpolation, the second convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the second decoding stage feature map, and then batch normalization processing and Relu activation function operation are performed to obtain the second decoding stage feature map after tensor processing; the third decoding stage feature map is upsampled by 4 times bilinear interpolation, the third convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the third decoding stage feature map, and then batch normalization processing and Relu activation function operation are performed to obtain the third decoding stage feature map after tensor processing. segment feature map; perform 8 times bilinear interpolation upsampling on the fourth decoding stage feature map, update the fourth convolution kernel to a convolution kernel with a dilation rate of 2, use the updated convolution kernel to perform a convolution operation on the fourth decoding stage feature map, and then perform batch normalization and Relu activation function operation to obtain the fourth decoding stage feature map after tensor processing; perform 16 times bilinear interpolation upsampling on the fifth feature map, update the fifth convolution kernel to a convolution kernel with a dilation rate of 2, use the updated convolution kernel to perform a convolution operation on the fifth feature map, and then perform batch normalization and Relu activation function operation to obtain the fifth feature map after tensor processing; perform tensor dimension splicing on the first feature map, the second decoding stage feature map, the third decoding stage feature map, the fourth decoding stage feature map and the fifth feature map after tensor processing, and then perform convolution operation, batch normalization and Relu activation function operation to generate the first decoding stage feature map;

[0084] A convolution operation is performed on the feature map of the first decoding stage to generate a bright light segmentation map.

[0085] In the hierarchical stage of the decoding phase, the embodiment of the present invention changes the convolution layer of the second layer into a hole convolution, and effectively improves the speed and accuracy of insulator flashover fault identification by performing hole convolution on the feature map input to the hierarchical stage.

[0086] In step S103, the insulator position is extracted according to the insulator image label map.

[0087] Here, the embodiment of the present invention extracts four points of each insulator position, which are respectively denoted as x min 、y min 、x max 、y max .

[0088] In step S104 , the area ratio of white pixels at the bright light position is calculated based on the correspondence between the insulator position and the bright light position on the bright light segmentation map.

[0089] Alternatively, as a preferred embodiment of the present invention, Figure 3 As shown, step S104 includes:

[0090] In step S1041, the bright light segmentation map is binarized, and pixels with grayscale values ​​within a first threshold range are set to white, otherwise set to black.

[0091] Here, the first threshold range is (130, 255). After extracting each insulator position, the embodiment of the present invention performs binarization on the bright light segmentation map to obtain the grayscale values ​​of the pixels. Pixels with grayscale values ​​falling within the range of (130, 255) are then set to white, and the remaining pixels are set to black.

[0092] In step S1042, the bright light position on the bright light segmentation map corresponding to the insulator position is obtained, and the area ratio of the white pixels at the bright light position to the bright light position is calculated.

[0093] Then, according to the four points x of the insulator position extracted min 、y min 、x max 、y max Corresponding to the bright light position on the bright light segmentation map, the total number of pixels and the number of white pixels at the bright light position are obtained, and the area ratio of the white pixels at the bright light position to the bright light position is obtained based on the ratio between the number of white pixels and the total number of pixels.

[0094] In step S105 , the insulator flashover fault is located according to the white pixel area ratio.

[0095] Here, the embodiment of the present invention pre-sets a ratio threshold, and determines the location of the insulator flashover fault by matching the white pixel area ratio with the ratio threshold. Figure 4 As shown, the step S105 further includes:

[0096] In step S1051 , the white pixel area ratio is compared with a preset ratio threshold.

[0097] In step S1052, if the white pixel area ratio is greater than or equal to the preset ratio threshold, a flashover fault occurs in the insulator corresponding to the bright light position.

[0098] In step S1053, if the white pixel area ratio is less than the preset ratio threshold, no flashover fault occurs in the insulator at the bright light position.

[0099] Optionally, as a preferred embodiment of the present invention, the preset ratio threshold is preferably 80%. If the white pixel area ratio is greater than or equal to 80%, a flashover fault occurs in the insulator corresponding to the bright light position; if the white pixel area ratio is less than 80%, no flashover fault occurs in the insulator at the bright light position.

[0100] In summary, the embodiment of the present invention realizes the recognition of flashover faults in the insulator image to be identified through the image segmentation network, and changes the convolution layer of the second layer in the grading stage into a void convolution through big data processing. By performing void convolution on the input feature map, the speed and accuracy of insulator flashover fault identification are effectively improved.

[0101] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0102] In one embodiment, the present invention further provides an insulator flashover fault identification device based on void convolution Unet+++, which corresponds one-to-one to the insulator flashover fault identification method based on void convolution Unet+++ in the above embodiment. Figure 5 As shown, the insulator flashover fault identification device based on Unet+++ of void convolution includes an acquisition module 51, a segmentation module 52, an extraction module 53, a calculation module 54, and a fault identification module 55. The functional modules are described in detail as follows:

[0103] An acquisition module 51 is configured to acquire an insulator image to be identified, and obtain a bright light image label image and an insulator image label image based on the insulator image;

[0104] A segmentation module 52 is configured to segment the bright light image label map based on a Unet+++ with dilated convolution to generate a bright light segmentation map;

[0105] An extraction module 53 is configured to extract the insulator position according to the insulator image label map;

[0106] A calculation module 54 is configured to calculate the area ratio of white pixels at the bright light position according to the correspondence between the insulator position and the bright light position on the bright light segmentation map;

[0107] The fault identification module 55 is configured to locate the insulator flashover fault according to the white pixel area ratio.

[0108] Optionally, the acquisition module 51 includes:

[0109] An acquisition unit, configured to acquire an image of an insulator to be identified;

[0110] a first labeling unit, configured to label a target area of ​​a bright light position in the insulator image to obtain a bright light image label map;

[0111] The second labeling unit is configured to label the insulator target area in the insulator image to obtain an insulator image label map.

[0112] Optionally, the segmentation module 52 includes:

[0113] An encoding unit, configured to perform multiple convolutions on the bright light image label map in sequence during the encoding phase of the Unet+++ network to generate multiple encoding phase feature maps;

[0114] The decoding unit is used to perform dilated convolution on the feature maps of the encoding stage in a preset manner in the decoding stage of the Unet+++ network to generate a bright light segmentation map.

[0115] Optionally, the encoding stage includes a first encoding stage, a second encoding stage, a third encoding stage, a fourth encoding stage, and a fifth encoding stage;

[0116] The encoding unit is used for:

[0117] In the first encoding stage, a convolution operation is performed on the bright light image label map according to a first convolution kernel to generate a first feature map of the encoding stage;

[0118] In the second encoding stage, a maximum pooling operation and a convolution operation according to a second convolution kernel are performed on the first feature map to generate a second feature map in the encoding stage;

[0119] In the third encoding stage, a maximum pooling operation and a convolution operation according to a third convolution kernel are performed on the second feature map to generate a third feature map in the encoding stage;

[0120] In the fourth encoding stage, a maximum pooling operation and a convolution operation according to a fourth convolution kernel are performed on the third feature map to generate a fourth feature map in the encoding stage;

[0121] In the fifth encoding stage, a maximum pooling operation and a convolution operation are performed on the fourth feature map according to the fifth convolution kernel to generate a fifth feature map in the encoding stage.

[0122] Optionally, the decoding stage includes a first decoding stage, a second decoding stage, a third decoding stage, and a fourth decoding stage;

[0123] The decoding unit is used for:

[0124] In the fourth decoding stage, the first feature map is downsampled 8 times, the first convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the first feature map, and then batch normalization and Relu activation function operations are performed to obtain the first feature map after tensor processing; the second feature map is downsampled 4 times, the second convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the second feature map, and then batch normalization and Relu activation function operations are performed to obtain the second feature map after tensor processing; the third feature map is downsampled 2 times, the third convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the third feature map, and then batch normalization and Relu activation function operations are performed to obtain a tensor. the processed third feature map; for the fourth feature map, updating the fourth convolution kernel to a convolution kernel with a dilation rate of 2, using the updated convolution kernel to perform a convolution operation on the fourth feature map, and then performing batch normalization and Relu activation function operations to obtain the fourth feature map after tensor processing; performing 2x bilinear interpolation upsampling on the fifth feature map, updating the fourth convolution kernel to a convolution kernel with a dilation rate of 2, using the updated convolution kernel to perform a convolution operation on the fifth feature map, and then performing batch normalization and Relu activation function operations to obtain the fifth feature map after tensor processing; performing tensor dimension splicing on the first feature map, the second feature map, the third feature map, the fourth feature map and the fifth feature map after tensor processing, and then performing convolution operations, batch normalization and Relu activation function operations to generate a fourth decoding stage feature map;

[0125] In the third decoding stage, the first feature map is downsampled by 4 times, the first convolution kernel is updated to a convolution kernel with a dilation rate of 2, the first feature map is convolved with the updated convolution kernel, and then batch normalization and Relu activation function operations are performed to obtain the first feature map after tensor processing; the second feature map is downsampled by 2 times, the second convolution kernel is updated to a convolution kernel with a dilation rate of 2, the second feature map is convolved with the updated convolution kernel, and then batch normalization and Relu activation function operations are performed to obtain the second feature map after tensor processing; for the third feature map, the third convolution kernel is updated to a convolution kernel with a dilation rate of 2, the third feature map is convolved with the updated convolution kernel, and then batch normalization and Relu activation function operations are performed to obtain the third feature map after tensor processing; the fourth decoding The fourth decoding stage feature map is upsampled by 2 times bilinear interpolation, the fourth convolution kernel is updated to a convolution kernel with a dilation rate of 2, and the updated convolution kernel is used to perform a convolution operation on the fourth decoding stage feature map, and then batch normalization and Relu activation function operations are performed to obtain the fourth decoding stage feature map after tensor processing; the fifth feature map is upsampled by 4 times bilinear interpolation, the fifth convolution kernel is updated to a convolution kernel with a dilation rate of 2, and the fifth feature map is convolved with the updated convolution kernel, and then batch normalization and Relu activation function operations are performed to obtain the fifth feature map after tensor processing; the first feature map, the second feature map, the third feature map, the fourth decoding stage feature map and the fifth feature map after tensor processing are spliced ​​in tensor dimension, and then convolution operation, batch normalization and Relu activation function operation are performed to generate the third decoding stage feature map;

[0126] In the second decoding stage, the first feature map is downsampled by 2 times, the first convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the first feature map, and then batch normalization processing and Relu activation function operation are performed to obtain the first feature map after tensor processing; for the second feature map, the second convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the second feature map, and then batch normalization processing and Relu activation function operation are performed to obtain the second feature map after tensor processing; the third decoding stage feature map is upsampled by 2 times bilinear interpolation, the third convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the third decoding stage feature map, and then batch normalization processing and Relu activation function operation are performed to obtain the third decoding stage feature map after tensor processing; The fourth decoding stage feature map is upsampled by 4 times bilinear interpolation, the fourth convolution kernel is updated to a convolution kernel with a dilation rate of 2, and the updated convolution kernel is used to perform a convolution operation on the fourth decoding stage feature map, and then batch normalization and Relu activation function operations are performed to obtain the fourth decoding stage feature map after tensor processing; the fifth feature map is upsampled by 8 times bilinear interpolation, the fifth convolution kernel is updated to a convolution kernel with a dilation rate of 2, and the updated convolution kernel is used to perform a convolution operation on the fifth feature map, and then batch normalization and Relu activation function operations are performed to obtain the fifth feature map after tensor processing; the first feature map, the second feature map, the third decoding stage feature map, the fourth decoding stage feature map and the fifth feature map after tensor processing are tensor dimension spliced, and then convolution operation, batch normalization and Relu activation function operation are performed to generate the second decoding stage feature map;

[0127] In the first decoding stage, for the first feature map, the first convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the first feature map, and then batch normalization processing and Relu activation function operation are performed to obtain the first feature map after tensor processing; the second decoding stage feature map is upsampled by 2 times bilinear interpolation, the second convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the second decoding stage feature map, and then batch normalization processing and Relu activation function operation are performed to obtain the second decoding stage feature map after tensor processing; the third decoding stage feature map is upsampled by 4 times bilinear interpolation, the third convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the third decoding stage feature map, and then batch normalization processing and Relu activation function operation are performed to obtain the third decoding stage feature map after tensor processing. stage feature map; performing 8 times bilinear interpolation upsampling on the fourth decoding stage feature map, updating the fourth convolution kernel to a convolution kernel with a dilation rate of 2, using the updated convolution kernel to perform a convolution operation on the fourth decoding stage feature map, and then performing batch normalization and Relu activation function operations to obtain the fourth decoding feature map after tensor processing; performing 16 times bilinear interpolation upsampling on the fifth feature map, updating the fifth convolution kernel to a convolution kernel with a dilation rate of 2, using the updated convolution kernel to perform a convolution operation on the fifth feature map, and then performing batch normalization and Relu activation function operations to obtain the fifth feature map after tensor processing; performing tensor dimension splicing on the first feature map, the second decoding stage feature map, the third decoding stage feature map, the fourth decoding stage feature map and the fifth feature map after tensor processing, and then performing convolution operations, batch normalization and Relu activation function operations to generate the first decoding stage feature map;

[0128] A convolution operation is performed on the feature map of the first decoding stage to generate a bright light segmentation map.

[0129] Optionally, the calculation module includes:

[0130] a setting unit, configured to perform a binarization process on the bright light segmentation image, setting pixels whose grayscale values ​​are within a first threshold range of (130, 255) to white, and otherwise to black;

[0131] The calculation unit is used to obtain the bright light position on the bright light segmentation map corresponding to the insulator position, and calculate the area ratio of the white pixels at the bright light position to the bright light position.

[0132] Optionally, the fault identification module includes:

[0133] a comparing unit, configured to compare the white pixel area ratio with a preset ratio threshold;

[0134] A fault identification unit is used to determine that if the white pixel area ratio is greater than or equal to the preset ratio threshold, a flashover fault occurs in the insulator corresponding to the bright light position; if the white pixel area ratio is less than the preset ratio threshold, no flashover fault occurs in the insulator at the bright light position.

[0135] Regarding the specific limitations of the insulator flashover fault identification device based on Unet+++ of void convolution, please refer to the limitations of the insulator flashover fault identification method based on Unet+++ of void convolution above, which will not be repeated here. Each module in the above-mentioned insulator flashover fault identification device based on Unet+++ of void convolution can be implemented in whole or in part by software, hardware, or a combination thereof. Each of the above-mentioned modules can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory in software form, so that the processor can call and execute the corresponding operations of each of the above modules.

[0136] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Figure 6 As shown. The computer device includes a processor, a memory, a network interface, and a database connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, an insulator flashover fault identification method based on Unet+++ of void convolution is implemented.

[0137] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the following steps are performed:

[0138] Acquire an insulator image to be identified, and obtain a bright light image label map and an insulator image label map according to the insulator image;

[0139] The bright light image label map is segmented by Unet+++ based on the dilated convolution to generate a bright light segmentation map;

[0140] Extracting the insulator position according to the insulator label map;

[0141] Calculating the white pixel area ratio at the bright light position according to the correspondence between the insulator position and the bright light position on the bright light segmentation map;

[0142] The insulator flashover fault is located according to the white pixel area ratio.

[0143] Those skilled in the art will appreciate that all or part of the processes in the above-described embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the above-described embodiments. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct RAM bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM).

[0144] Those skilled in the art will clearly understand that for the sake of convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0145] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A method for identifying insulator flashover faults based on Unet+++ with void convolution, characterized in that: include: Acquire an insulator image to be identified, and obtain a bright light image label map and an insulator image label map according to the insulator image; The bright light image label map is segmented by Unet+++ based on the dilated convolution to generate a bright light segmentation map; extracting the insulator position according to the insulator image label map; Binarization is performed on the bright light segmentation map, pixels with grayscale values ​​in the range of (130, 255) are set to white, and pixels otherwise are set to black; based on the correspondence between the insulator position and the bright light position on the bright light segmentation map, the area ratio of white pixels at the bright light position to the area ratio of the bright light position is calculated; The insulator flashover fault is located according to the white pixel area ratio.

2. The insulator flashover fault identification method based on Unet+++ of void convolution according to claim 1, characterized in that: The step of acquiring an insulator image to be identified and obtaining a bright light image label map and an insulator image label map according to the insulator image includes: Acquiring an insulator image to be identified; Marking a target area of ​​a bright light position in the insulator image to obtain a bright light image label map; The insulator target area in the insulator image is labeled to obtain an insulator image label map.

3. The insulator flashover fault identification method based on Unet+++ of void convolution according to claim 1 or 2, characterized in that: The Unet+++ based on dilated convolution segments the bright light image label map to generate a bright light segmentation map, which includes: In the encoding stage of the Unet+++ network, the bright light image label map is convolved several times in sequence to generate several encoding stage feature maps; In the decoding stage of the Unet+++ network, the feature maps of the encoding stage are subjected to dilated convolution in a preset manner to generate a bright light segmentation map.

4. The insulator flashover fault identification method based on Unet+++ of void convolution according to claim 3, characterized in that: The encoding stage includes a first encoding stage, a second encoding stage, a third encoding stage, a fourth encoding stage, and a fifth encoding stage; In the encoding stage of the Unet+++ network, the bright light image label map is sequentially convolved several times to generate several encoding stage feature maps including: In the first encoding stage, a convolution operation is performed on the bright light image label map according to a first convolution kernel to generate a first feature map of the encoding stage; In the second encoding stage, a maximum pooling operation and a convolution operation according to a second convolution kernel are performed on the first feature map to generate a second feature map in the encoding stage; In the third encoding stage, a maximum pooling operation and a convolution operation according to a third convolution kernel are performed on the second feature map to generate a third feature map in the encoding stage; In the fourth encoding stage, a maximum pooling operation and a convolution operation according to a fourth convolution kernel are performed on the third feature map to generate a fourth feature map in the encoding stage; In the fifth encoding stage, a maximum pooling operation and a convolution operation are performed on the fourth feature map according to the fifth convolution kernel to generate a fifth feature map in the encoding stage.

5. The insulator flashover fault identification method based on Unet+++ of void convolution according to claim 4, characterized in that: The decoding stage includes a first decoding stage, a second decoding stage, a third decoding stage, and a fourth decoding stage; In the decoding stage of the Unet+++ network, performing dilated convolution on the plurality of encoding stage feature maps in a preset manner to generate a bright light segmentation map includes: In the fourth decoding stage, the first feature map is downsampled 8 times, the first convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the first feature map, and then batch normalization and Relu activation function operations are performed to obtain the first feature map after tensor processing; the second feature map is downsampled 4 times, the second convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the second feature map, and then batch normalization and Relu activation function operations are performed to obtain the second feature map after tensor processing; the third feature map is downsampled 2 times, the third convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the third feature map, and then batch normalization and Relu activation function operations are performed to obtain a tensor. the processed third feature map; for the fourth feature map, updating the fourth convolution kernel to a convolution kernel with a dilation rate of 2, using the updated convolution kernel to perform a convolution operation on the fourth feature map, and then performing batch normalization and Relu activation function operations to obtain the fourth feature map after tensor processing; performing 2x bilinear interpolation upsampling on the fifth feature map, updating the fourth convolution kernel to a convolution kernel with a dilation rate of 2, using the updated convolution kernel to perform a convolution operation on the fifth feature map, and then performing batch normalization and Relu activation function operations to obtain the fifth feature map after tensor processing; performing tensor dimension splicing on the first feature map, the second feature map, the third feature map, the fourth feature map and the fifth feature map after tensor processing, and then performing convolution operations, batch normalization and Relu activation function operations to generate a fourth decoding stage feature map; In the third decoding stage, the first feature map is downsampled by 4 times, the first convolution kernel is updated to a convolution kernel with a dilation rate of 2, the first feature map is convolved with the updated convolution kernel, and then batch normalization and Relu activation function operations are performed to obtain the first feature map after tensor processing; the second feature map is downsampled by 2 times, the second convolution kernel is updated to a convolution kernel with a dilation rate of 2, the second feature map is convolved with the updated convolution kernel, and then batch normalization and Relu activation function operations are performed to obtain the second feature map after tensor processing; for the third feature map, the third convolution kernel is updated to a convolution kernel with a dilation rate of 2, the third feature map is convolved with the updated convolution kernel, and then batch normalization and Relu activation function operations are performed to obtain the third feature map after tensor processing; the fourth decoding The fourth decoding stage feature map is upsampled by 2 times bilinear interpolation, the fourth convolution kernel is updated to a convolution kernel with a dilation rate of 2, and the updated convolution kernel is used to perform a convolution operation on the fourth decoding stage feature map, and then batch normalization and Relu activation function operations are performed to obtain the fourth decoding stage feature map after tensor processing; the fifth feature map is upsampled by 4 times bilinear interpolation, the fifth convolution kernel is updated to a convolution kernel with a dilation rate of 2, and the fifth feature map is convolved with the updated convolution kernel, and then batch normalization and Relu activation function operations are performed to obtain the fifth feature map after tensor processing; the first feature map, the second feature map, the third feature map, the fourth decoding stage feature map and the fifth feature map after tensor processing are spliced ​​in tensor dimension, and then convolution operation, batch normalization and Relu activation function operation are performed to generate the third decoding stage feature map; In the second decoding stage, the first feature map is downsampled by 2 times, the first convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the first feature map, and then batch normalization processing and Relu activation function operation are performed to obtain the first feature map after tensor processing; for the second feature map, the second convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the second feature map, and then batch normalization processing and Relu activation function operation are performed to obtain the second feature map after tensor processing; the third decoding stage feature map is upsampled by 2 times bilinear interpolation, the third convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the third decoding stage feature map, and then batch normalization processing and Relu activation function operation are performed to obtain the third decoding stage feature map after tensor processing; The fourth decoding stage feature map is upsampled by 4 times bilinear interpolation, the fourth convolution kernel is updated to a convolution kernel with a dilation rate of 2, and the updated convolution kernel is used to perform a convolution operation on the fourth decoding stage feature map, and then batch normalization and Relu activation function operations are performed to obtain the fourth decoding stage feature map after tensor processing; the fifth feature map is upsampled by 8 times bilinear interpolation, the fifth convolution kernel is updated to a convolution kernel with a dilation rate of 2, and the updated convolution kernel is used to perform a convolution operation on the fifth feature map, and then batch normalization and Relu activation function operations are performed to obtain the fifth feature map after tensor processing; the first feature map, the second feature map, the third decoding stage feature map, the fourth decoding stage feature map and the fifth feature map after tensor processing are tensor dimension spliced, and then convolution operation, batch normalization and Relu activation function operation are performed to generate the second decoding stage feature map; In the first decoding stage, for the first feature map, the first convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the first feature map, and then batch normalization processing and Relu activation function operation are performed to obtain the first feature map after tensor processing; the second decoding stage feature map is upsampled by 2 times bilinear interpolation, the second convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the second decoding stage feature map, and then batch normalization processing and Relu activation function operation are performed to obtain the second decoding stage feature map after tensor processing; the third decoding stage feature map is upsampled by 4 times bilinear interpolation, the third convolution kernel is updated to a convolution kernel with a dilation rate of 2, the updated convolution kernel is used to perform a convolution operation on the third decoding stage feature map, and then batch normalization processing and Relu activation function operation are performed to obtain the third decoding stage feature map after tensor processing. segment feature map; perform 8 times bilinear interpolation upsampling on the fourth decoding stage feature map, update the fourth convolution kernel to a convolution kernel with a dilation rate of 2, use the updated convolution kernel to perform a convolution operation on the fourth decoding stage feature map, and then perform batch normalization and Relu activation function operation to obtain the fourth decoding stage feature map after tensor processing; perform 16 times bilinear interpolation upsampling on the fifth feature map, update the fifth convolution kernel to a convolution kernel with a dilation rate of 2, use the updated convolution kernel to perform a convolution operation on the fifth feature map, and then perform batch normalization and Relu activation function operation to obtain the fifth feature map after tensor processing; perform tensor dimension splicing on the first feature map, the second decoding stage feature map, the third decoding stage feature map, the fourth decoding stage feature map and the fifth feature map after tensor processing, and then perform convolution operation, batch normalization and Relu activation function operation to generate the first decoding stage feature map; A convolution operation is performed on the feature map of the first decoding stage to generate a bright light segmentation map.

6. The insulator flashover fault identification method based on Unet+++ of void convolution according to claim 1, characterized in that: The locating of the insulator flashover fault according to the white pixel area ratio includes: Comparing the white pixel area ratio with a preset ratio threshold; If the white pixel area ratio is greater than or equal to the preset ratio threshold, a flashover fault occurs in the insulator corresponding to the bright light position; If the white pixel area ratio is smaller than the preset ratio threshold, no flashover fault occurs to the insulator at the bright light position.

7. An insulator flashover fault identification device based on Unet+++ of void convolution, characterized in that: The device comprises: an acquisition module, configured to acquire an insulator image to be identified, and obtain a bright light image label map and an insulator image label map according to the insulator image; A segmentation module, configured to segment the bright light image label map based on Unet+++ with dilated convolution to generate a bright light segmentation map; an extraction module, configured to extract the insulator position according to the insulator image label map; a calculation module, configured to perform a binarization process on the bright light segmentation map, setting pixels with grayscale values ​​in the range of (130, 255) to white, and otherwise to black; and calculating the area ratio of white pixels at the bright light position to the area ratio of the bright light position based on the correspondence between the insulator position and the bright light position on the bright light segmentation map; A fault identification module is used to locate the insulator flashover fault according to the white pixel area ratio.

8. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the insulator flashover fault identification method based on Unet+++ of void convolution is implemented as claimed in any one of claims 1 to 6.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the insulator flashover fault identification method based on Unet+++ of void convolution is implemented as described in any one of claims 1 to 6.

Images