Control circuit of a memory device

Abstract

The present disclosure relates to control circuitry for memory devices. A device includes a memory array, bit line pairs, word lines, a modulation circuit, and a control signal generator. The memory array has a plurality of bit cells arranged in rows and columns. Each bit line pair is connected to bit cells of a respective column. Each word line is connected to bit cells of a respective row. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a trace of wiring, a trace length of the trace being positively correlated with a depth distance of the word line. The control signal generator is configured to generate a control signal that switches to a first voltage level for a first duration of time with reference to the trace length for controlling the modulation circuit. Methods of controlling the above device are also disclosed.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a control circuit of a memory device. BACKGROUND

[0002] Electronic devices and electronic-based systems require some form of high-speed memory device to store and retrieve information. Random access memory (RAM) is a commonly used memory in integrated circuits. Embedded RAM is particularly popular in high-speed communication, image processing, and system-on-chip (SOC) applications. RAM contains an array of individual bit cells. A user can perform read and write operations on the bit cells of the RAM.

[0003] RAM is typically organized in a system into addressable blocks, each block containing a predetermined number of bit cells. Each bit cell in the RAM represents an information bit. The bit cells are organized into rows and columns. Each row of bit cells forms a word line. Each bit cell in a row is coupled to the same word line for activating the bit cells in the row. Each bit cell in a column of memory is also individually coupled to a pair of bit lines. These bit lines are further coupled to local input / output (LIO) lines. These local input / output lines are used to read data from or write data to the activated memory array. Thus, a bit cell is accessed by activating the appropriate word line and a pair of bit lines. SUMMARY

[0004] According to one embodiment of the present disclosure, a memory device is provided, comprising: a memory array having a plurality of bit cells arranged in rows and columns; a plurality of bit line pairs, each bit line pair connected to bit cells of a respective column; a plurality of word lines, each word line connected to bit cells of a respective row; a modulation circuit coupled with at least one bit line pair; and a control signal generator coupled with the modulation circuit, wherein the control signal generator comprises a tracking wire having a tracking length positively correlated to a depth distance of the word line, the control signal generator configured to generate a control signal switching to a first voltage level for a first duration of time with reference to the tracking length for controlling the modulation circuit.

[0005] According to another embodiment of the disclosure, a memory device is provided, comprising: a memory array having a plurality of bit cells arranged in rows and columns, wherein the memory array comprises a first sub-array of bit cells and a second sub-array of bit cells; a first pair of bit lines coupled to bit cells in the first sub-array on a column of the memory array; a second pair of bit lines coupled to bit cells in the second sub-array on a column of the memory array; a plurality of word lines extending along a plurality of rows of the memory array; a first modulation circuit coupled with the first pair of bit lines; a second modulation circuit coupled with the second pair of bit lines; and a control signal generator coupled with the first modulation circuit and the second modulation circuit, wherein the control signal generator comprises a first tracking wire having a first tracking length positively correlated to a half-depth distance of the word lines, the control signal generator is configured to generate a first control signal that switches to a first voltage level for a first duration of time with reference to the first tracking length for controlling the first modulation circuit, and wherein the control signal generator comprises a second tracking wire having a second tracking length positively correlated to a full-depth distance of the word lines, the control signal generator is configured to generate a second control signal that switches to the first voltage level for a second duration of time with reference to the second tracking length for controlling the second modulation circuit.

[0006] According to yet another embodiment of the disclosure, a method for a memory device is provided, comprising: delaying a clock signal as a first delayed clock signal with a first tracking wire having a first tracking length positively correlated to a first depth distance of word lines; and generating a first control signal with reference to the clock signal and the first delayed clock signal. BRIEF DESCRIPTION OF DRAWINGS

[0007] Various aspects of the disclosure can be best understood from the following detailed description when read with the accompanying drawings in which: NOTE, according to industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 is a schematic diagram illustrating a memory device according to various embodiments of the disclosure.

[0009] Figure 2 is a schematic diagram illustrating an internal structure of a modulation circuit and a control signal generator in Figure 1 according to various embodiments of the disclosure.

[0010] Figure 3 is a schematic diagram illustrating a method for a memory device according to various embodiments of the disclosure. Figure 1 and Figure 2The signal waveform of the relevant signal generated in the memory device.

[0011] Figure 4 This illustrates various embodiments according to the present disclosure. Figure 1 A schematic diagram of the internal structure of the modulation circuit and control signal generator.

[0012] Figure 5 This illustrates various embodiments according to the present disclosure. Figure 1 A schematic diagram of the internal structure of the modulation circuit and control signal generator.

[0013] Figure 6 This is a schematic diagram illustrating a memory device according to various embodiments of the present disclosure.

[0014] Figure 7 This illustrates various embodiments according to the present disclosure. Figure 6 A schematic diagram of the internal structure of the modulation circuit and control signal generator.

[0015] Figure 8 This illustrates various embodiments according to the present disclosure. Figure 6 and Figure 7 The signal waveform of the relevant signal generated in the memory device. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] The terms used in this specification generally have their ordinary meaning in the art and in the specific context in which each term is used. The use of examples in this specification (including examples of any terms discussed herein) is merely illustrative and in no way limits the scope and meaning of this disclosure or any exemplary terminology. Similarly, this disclosure is not limited to the various embodiments given in this specification.

[0018] It will be understood that, although the terms“first,”“second,” etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the example. As used herein, the term“and / or” includes any and all combinations of one or more of the associated list items.

[0019] As used herein, the terms“comprises,”“comprising,”“includes,”“including,”“has,”“having,”“contains,”“containing,”“involves,”“involving,” and the like can be used interchangeably with the term“consisting of.”

[0020] Throughout this specification, use of the term“one embodiment,”“an embodiment,” or“some embodiments” means that a particular feature, structure, implementation, or characteristic described in connection with (one or more) embodiment is included in at least one embodiment of the disclosure. The appearance of the phrases“in one embodiment” or“in an embodiment” or“in some embodiments” in various places in the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, implementations, or characteristics can be combined in any suitable manner in one or more embodiments.

[0021] Figure 1 is a schematic diagram illustrating a memory device 100 in accordance with various embodiments of the present disclosure. In Figure 1 In the illustratively shown embodiment, the memory device 100 includes a memory array 120 that includes a number of bitcells BC arranged on a plurality of rows and columns. As shown in the memory array 120, the bitcells BC on the same column are connected to one bitline pair. For example, the bitcells BC on the left side first column are connected to one bitline pair that includes one bitline BL1 and one complementary bitline BLB1, and the bitcells BC on the right side nth column are connected to another bitline pair that includes another bitline BLn and another complementary bitline BLBn. In some embodiments, n is a positive integer. For example, n can be 8, 16, 32, or other suitable number. For brevity, only two columns of the memory array 120 are shown in Figure 1 The embodiments of the present disclosure are not limited to the particular number of columns in the memory array 120.

[0022] As Figure 1Illustratively shown, in some embodiments, the bit cells BC on the same row are connected to the same word line. For example, the bit cells BC on the 1st row (starting from the bottom side of the memory array 120) are connected to the word line WL1; the bit cells BC on the kth row are connected to the word line WLk; the bit cells BC on the k+1th row are connected to the word line WLk+1; the bit cells BC on the k+2th row are connected to the word line WLk+2; and, the bit cells BC on the 2kth row are connected to the word line WL2k. In some embodiments, k is a positive integer. For example, in a memory array 120 having 2048 rows of bit cells BC, k equals 1024, and there are 2048 word lines distributed from the bottom side to the top side of the memory array 120.

[0023] As Figure 1 Illustratively shown, in some embodiments, the memory device 100 includes a local input / output circuit 140, a main control circuit 160, and a word line decoder 180. The main control circuit 160 is coupled with the local input / output (LIO) circuit 140 and the word line decoder 180.

[0024] In some embodiments, the main control circuit 160 includes a control signal generator 162, and the control signal generator 162 is configured to generate some control signals to control / activate / deactivate functions in the local input / output circuit 140 and the word line decoder 180. As Figure 1 Illustratively shown, in some embodiments, the control signal generator 162 is configured to generate a control signal BLEQB for pre-charge and equalization to the local input / output circuit 140, generate another control signal YSEL for column selection to the local input / output circuit 140, and generate yet another control signal DEC to the word line decoder 180. In some other embodiments, the control signal generator 162 is capable of generating other control signals for controlling other functions. Embodiments of the present disclosure are not limited to these control signals.

[0025] In some embodiments, the local input / output circuit 140 includes a modulation circuit 142a-142b, a selection circuit 144, and a read / write circuit 146. During a write operation, the read / write circuit 146 is configured to generate a write signal and a complementary write signal onto a bit line pair including a bit line BL and a complementary bit line BLB in the local input / output circuit 140, and the selection circuit 144 is configured to couple the bit line pair (i.e., the bit line BL and the complementary bit line BLB) to one of the bit line pairs in the memory array 120 according to the selection signal YSEL, so as to write data into the bit cells BC on the target column.

[0026] For example, when the target column is the 1st column, the selection circuit 144 is configured to couple the bit line BL and the complementary bit line BLB in the local input / output circuit 140 with the bit line BL1 and the complementary bit line BLB1 in the memory array 120; when the target column is the n* column, the selection circuit 144 is configured to couple the bit line BL and the complementary bit line BLB in the local input / output circuit 140 with the bit line BLn and the complementary bit line BLBn in the memory array 120.

[0027] In some embodiments, during a read operation to read data from the target column, the selection circuit 144 is configured to couple the bit line pair (i.e., the bit line BL and the complementary bit line BLB in the local input / output circuit 140) to one of the bit line pairs corresponding to the target column in the memory array 120 according to the selection signal YSEL, the read / write circuit 146 is configured to sense a voltage level from the bit line pair, and thereby read data from the bit cell BC on the target column.

[0028] As Figure 1 Illustratively shown, the modulation circuits 142a and 142b are coupled with bit line pairs on columns of the memory array 120. For example, one modulation circuit 142a is coupled with the bit line BL1 and the complementary bit line BLB1 on the 1st column, and another modulation circuit 142b is coupled with the bit line BLn and the complementary bit line BLBn on the n* column. For the sake of brevity, only two modulation circuits 142a and 142b on two columns of the memory array 120 are shown for the purpose of illustration, Figure 1 However, embodiments of the present disclosure are not limited to a particular number of modulation circuits.

[0029] In some embodiments, the modulation circuit 142a is configured to modulate voltage levels on the bit line BL1 and the complementary bit line BLB1 when the memory device 100 is not accessing (e.g., writing or reading) the bit cell BC. For example, during a write operation or a read operation, one of the bit line BL1 and the complementary bit line BLB1 will be charged to a higher level, e.g., a high reference voltage level VDD, while the other of the bit line BL1 and the complementary bit line BLB1 will be discharged to a lower level, e.g., a low reference voltage level VSS or a ground level.

[0030] In some embodiments, outside of a write operation or a read operation, the modulation circuit 142a is triggered by the control signal BLEQB and is configured to couple the bit line BL1 and the complementary bit line BLB1 together, thereby equalizing the voltage levels on the bit line BL1 and the complementary bit line BLB1. In some embodiments, outside of a write operation or a read operation, the modulation circuit 142a is configured to pre-charge the voltage levels on the bit line BL1 and the complementary bit line BLB1 to a fixed level, such as a high reference voltage level VDD. In this case, the bit line BL1 and the complementary bit line BLB1 are configured to be at a fixed level instead of a floating level, and the data stored in the bit cell BC can be protected and from being affected by an unintended floating level on the bit line BL1 and the complementary bit line BLB1.

[0031] On the other hand, during a write operation or a read operation, the modulation circuit 142a is disabled by the control signal BLEQB, such that the voltage levels of the bit line BL1 and the complementary bit line BLB1 are released and not controlled by the modulation circuit 142a. In this case, the bit line BL1 and the complementary bit line BLB1 can be used in the write operation or the read operation of the read / write circuit 146.

[0032] Similarly, outside of a write operation or a read operation, the modulation circuit 142b is configured to equalize the voltage levels on the bit line BLn and the complementary bit line BLBn, and / or is configured to pre-charge the voltage levels on the bit line BLn and the complementary bit line BLBn to a fixed level.

[0033] As Figure 1 As illustratively shown, the word line decoder 180 is coupled with the word lines WL1-WL2k. In some embodiments, the word line decoder 180 is configured to generate a word line signal to select a target row to be written or read in a write operation or a read operation. In response to the 1st row being selected, the word line decoder 180 is configured to generate a word line signal to the word line WL1 to activate the bit cells BC connected with the word line WL1. In this case, the memory device 100 is able to perform a write operation or a read operation on the bit cells BC of the 1st row. In response to the 2nd row being selected, the word line decoder 180 is configured to generate a word line signal to the word line WL2 to activate the bit cells BC connected with the word line WL2. In response to the upper side row being selected, the word line decoder 180 is configured to generate a word line signal to the word line WL2k to activate the bit cells BC connected with the word line WL2k. For a memory device 100 with a large data capacity, the memory device 100 can have 512 rows, 1024 rows, or even more rows. In this case, the depth distance DPf between the first word line WL1 and the last word line WL2k among the word lines WL1-WL2k is relatively long.

[0034] In some embodiments, the word line decoder 180 is controlled by a control signal DEC generated by the control signal generator 162. In some embodiments, the word line decoder 180 includes a number of decoder units 182, and each decoder unit 182 is configured to provide one word line signal to one of the word lines WL1-WL2k. The control signal DEC is used to control the addressing and gating functions of the decoder units 182 in the word line decoder 180. In some embodiments, the memory array 120 can include a number of rows of bit cells BC. When the control signal DEC is sent from the side of the control signal generator 162 to the decoder units 182 in the word line decoder 180, the control signal DEC arrives at different decoder units 182 at different points in time. For example, for the decoder units 182 at the bottom side close to the control signal generator 162, the control signal DEC arrives early. On the other hand, for the decoder units 182 at the top side far away from the control signal generator 162, the control signal DEC arrives later. In other words, the control signal DEC will arrive at different decoder units 182 at different points in time. Due to the different arrival timing of the control signal DEC as described above, the word line signals generated by the decoder units 182 in the word line decoder 180 to the word lines WL1-WL2k have pulses with different timing.

[0035] When the deep distance DPf is longer, the time difference between the pulses on the word line signals on the word line WL1 and the word line WL2k will be larger. If the control signal generator 162 generates the control signal BLEQB without considering the time difference on the word line signals on the word line WL1 and the word line WL2k, the control signal BLEQB can not activate the modulation circuits 142a and 142b at the correct timing, and this can cause some problems, such as read / write margin degradation, transient crowbar current increase, bit cell stability degradation, etc. Further details will be discussed in the following paragraphs.

[0036] In some embodiments, the control signal generator 162 is configured to generate the control signal BLEQB with reference to the deep distance DPf between the first word line WL1 and the last word line WL2k in the word lines WL1-WL2k, so as to avoid the above-mentioned problems.

[0037] Further reference is made to Figure 2 and Figure 3 . Figure 2 is a schematic diagram showing the internal structure of a modulation circuit and a control signal generator in Figure 1 according to various embodiments of the present disclosure. Figure 3 is a signal waveform showing a related signal generated in the memory device 100 in Figure 1 and Figure 2 according to various embodiments of the present disclosure. Regarding Figure 1For ease of understanding, Figure 2 and Figure 3 Similar elements in the embodiments shown in Figure 2 The structure related to the 1st column of the memory array 120 is shown. The structure related to other columns is similar and can be understood by the embodiments shown in Figure 2 The control signal generator 162-1 illustratively shown in Figure 2 is one embodiment of the control signal generator 162 shown in Figure 1

[0038] As shown in Figure 2 Illustratively shown, the modulation circuit 142a includes transistors T1, T2 and T3. The gates of the transistors T1, T2 and T3 are controlled by the control signal BLEQB. Two terminals of the transistor T1 are connected with the bit line BL1 and the complementary bit line BLB1.

[0039] When the control signal BLEQB is at a low voltage level (e.g., 0V, GND level or VSS level), the transistor T1 is turned on to couple the bit line BL1 and the complementary bit line BLB1 (in the bit line pair on the 1st column) to each other together, so that the voltage levels on the bit line BL1 and the complementary bit line BLB1 are equalized. When the control signal BLEQB is at a low voltage level (e.g., 0V), the transistor T2 is turned on to connect the bit line BL1 to the high reference voltage level VDD, so that the voltage level on the bit line BL1 is fixed to the high reference voltage level VDD. When the control signal BLEQB is at a low voltage level (e.g., 0V), the transistor T3 is turned on to connect the complementary bit line BLB1 to the high reference voltage level VDD, so that the voltage level on the complementary bit line BLB1 is fixed to the high reference voltage level VDD. In this case, the bit line BL1 and the complementary bit line BLB1 are configured to be at fixed levels instead of floating levels, and the data stored in the bit cell BC can be protected and avoid being affected by unexpected floating levels on the bit line BL1 and the complementary bit line BLB1.

[0040] In some embodiments, in addition to the write operation or the read operation, the modulation circuit 142a is further configured to pre-charge the voltage levels on the bit line BL1 and the complementary bit line BLB1 to fixed levels, e.g., the high reference voltage level VDD. In this case, the bit line BL1 and the complementary bit line BLB1 are configured to be at fixed levels instead of floating levels, and the data stored in the bit cell BC can be protected and avoid being affected by unexpected floating levels on the bit line BL1 and the complementary bit line BLB1.

[0041] ​When the control signal BLEQB is at a high voltage level (e.g., 3V, 5V, or VDD level), all of the transistors T1, T2, and T3 in the modulation circuit 142a are turned off, such that the modulation circuit 142a is disabled, and the voltage levels on the bit line BL1 and the complementary bit line BLB1 are released from the modulation circuit 142a and controlled by the read / write circuit 146. Figure 1 The read / write circuit 146 controls.

[0042] As Figure 2 and Figure 3 illustratively shown, during the time duration DWL1, the word line signal to the word line WL1 is switched to a high voltage level, and the bit cell BC connected to the word line WL1 should be ready for read / write, such that the rising edge of the control signal BLEQB needs to arrive at the same time (or before) the rising edge of the word line signal on the word line WL1. If the rising edge of the control signal BLEQB arrives after the rising edge of the word line signal on the word line WL1, the modulation circuit 142a can not release the bit line BL1 and the complementary bit line BLB1 in time, such that the read / write margin to the bit cell BC will be reduced.

[0043] As Figure 1 , Figure 2 and Figure 3 illustratively shown, during the time duration DWL2k, the word line signal to the word line WL2k is switched to a high voltage level, and the bit cell BC connected to the word line WL2k should be ready for read / write, such that the falling edge of the control signal BLEQB needs to arrive at the same time (or after) the falling edge of the word line signal on the word line WL2k. If the falling edge of the control signal BLEQB arrives before the falling edge of the word line signal on the word line WL2k, the modulation circuit 142a can raise both the voltage levels on the bit line BL1 and the complementary bit line BLB1 to a high voltage level while the word line WL2k is still active for accessing the bit cell BC, such that the data bit stored in the bit cell BC connected to the word line WL2k can be corrupted due to the wrong configuration of the voltage levels on the bit line BL1 and the complementary bit line BLB1 (e.g., both the voltage levels on the bit line BL1 and the complementary bit line BLB1 are charged to a high level by the modulation circuit 142b). Similarly, if the falling edge of the control signal BLEQB arrives before the falling edge of the word line signal on the word line WL2k, other modulation circuits (e.g., the modulation circuit 142b) can raise both the voltage levels on its corresponding bit line (e.g., the bit line BLn) and its corresponding complementary bit line (e.g., the complementary bit line BLBn) to a high voltage level while the word line WL2k is still active for accessing the bit cells BC on the corresponding row.

[0044] In addition, as Figure 1As shown, bit lines BL1-BLn and complementary bit lines BLB1-BLBn are arranged across word lines WL1-WL2k, and the signals between these signal lines are coupled. At the falling edge of the control signal BLEQB, the control signal BLEQB activates modulation circuits 142a-142b, causing the voltage levels on bit lines BL1-BLn and complementary bit lines BLB1-BLBn to be raised to a high voltage level by their respective modulation circuits 142a-142b. Due to the coupling effect, the word line signals on word lines WL1-WL2k are raised to a higher level according to the increased voltage levels on bit lines BL1-BLn and complementary bit lines BLB1-BLBn. Specifically, if the falling edge of the control signal BLEQB arrives before the falling edge of the word line signal on word line WL2k, the word line signal on word line WL2k will be further raised (e.g., exceeding the VDD level), and may cause instability in the bit cell BC connected to word line WL2k.

[0045] In other words, the duration D1 for the control signal BLEQB to switch to a high voltage level needs to include the rising edge of the word line signal on word line WL1 and the falling edge of the word line signal on word line WL2k. In some embodiments, the control signal generator 162-1 can generate the control signal BLEQB with reference to the depth distance DPf at the correct timing.

[0046] like Figure 2 As shown, in some embodiments, the control signal generator 162-1 includes a tracking wiring TR, two inverters INV1 and INV2, and two logic gates NAND1 and NAND2. In some embodiments, the control signal generator 162-1 receives an input control signal PRE and an input clock signal CKP.

[0047] The tracking length of the trace routing TR is positively correlated with the depth distance of the word lines WL1-WL2k. For example... Figure 2 As shown, in some embodiments, the trace routing TR includes a first trace segment S1 and a second trace segment S2. The first trace segment S1 extends from the bottom edge of word lines WL1-WL2k towards the midpoint of word lines WL1-WL2k (e.g., at a horizontal position between word lines WLk and WLk+1). The second trace segment S2 extends from the midpoint of word lines WL1-WL2k towards the bottom edge of word lines WL1-WL2k. In this case, the sum of the lengths of the first trace segment S1 and the second trace segment S2 is similar to or approximately equal to the depth distance DPf.

[0048] The logic gate NAND2 and the inverter INV2 are configured to generate a control signal DEC to the word line decoder 180 based on the input control signal PRE and the input clock signal CKP. In this case, the generation of the control signal DEC has two gate delays relative to the input clock signal CKP (caused by the logic gate NAND2 and the inverter INV2).

[0049] Inverter INV1 is configured to convert the input clock signal CKP into an inverted clock signal CKPB. Logic gate NAND1 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of logic gate NAND1 is configured to receive the inverted clock signal CKPB. The second input terminal of logic gate NAND1 is configured to receive the inverted delayed clock signal CKPBd (i.e., the inverted clock signal CKPBd delayed by the trace wiring TR).

[0050] The output terminal of logic gate NAND1 is configured to generate the control signal BLEQB. Logic gate NAND1 is configured to execute a NAND Boolean function between its two input terminals and generate the control signal BLEQB. The relationship between the inputs and outputs of logic gate NAND1 is shown in Table 1.

[0051]

[0052] Table 1

[0053] like Figure 3 As shown in Table 1, the rising edge of the control signal BLEQB is triggered by the falling edge of the inverted clock signal CKPB. Figure 2 In the embodiment shown, the rising edge of the control signal BLEQB arrives with two gate delays relative to the input clock signal CKP (caused by the inverter INV1 and the logic gate NAND1).

[0054] Note that the control signal DEC is generated with two gate delays relative to the input clock signal CKP, and the control signal DEC is sent to the word line decoder 180 (for triggering). Figure 1 The decoder unit 182 shown generates word line signals on word lines WL1-WL2k. In this case, the rising edge of the word line signal on word line WL1 arrives with (or later than) two gate delays relative to the input clock signal CKP. As described above, the rising edge of the control signal BLEQB arrives with two gate delays relative to the input clock signal CKP. Therefore, the rising edge of the control signal BLEQB can enclose the rising edge of the word line signal on word line WL1.

[0055] In some embodiments, since the clock signal CKPBd is delayed by the tracking wire TR corresponding to the depth distance DPf, the timing of the clock signal CKPBd will be similar to the timing of the control signal DEC reaching the decoder unit connected to the top side word line WL2k. As shown in Figure 3 , the timing of the rising edge of the inverted delayed clock signal CKPBd is similar to the word line signal on the word line WL2k. As shown in Figure 3 and Table 1, the falling edge of the control signal BLEQB is triggered by the rising edge of the inverted delayed clock signal CKPBd. As shown in Figure 3 , the falling edge of the control signal BLEQB is determined by the rising edge of the inverted delayed clock signal CKPBd, and when the falling edge of the word line signal on the word line WL2k arrives, the falling edge of the control signal BLEQB arrives with similar timing.

[0056] In other words, the duration Dl of the control signal BLEQB switching to the high voltage level is extended according to the inverted delayed clock signal CKPBd delayed by the tracking wire TR. By means of the tracking wire TR to track the delay with respect to the depth distance DPf, the falling edge of the control signal BLEQB is able to enclose the falling edge of the word line signal on the word line WL2k. Since the falling edge of the control signal BLEQB is able to enclose the falling edge of the word line signal on the word line WL2k, it is possible to avoid the modulation circuit 142a being activated prematurely before the access path to the bit cell BC is turned off by the word line signals on the word lines WL1-WL2k. Thus, this can avoid the data bit stored in the bit cell being corrupted since the modulation circuit 142a is activated (to charge the corresponding bit line BL1 and complementary bit line BLB1) after the word lines WL1-WL2k are pulled low to turn off the pass gates of the bit cell, thereby improving the stability of the data bit stored in the bit cell.

[0057] It is to be noted that Figure 2 the control signal generator 162-1 illustratively shown in Figure 1 is one exemplary embodiment of the control signal generator 162 shown in Figure 4 . However, the present disclosure is not limited thereto. Further reference is made to Figure 4 , which shows the internal structure of the modulation circuit and the control signal generator in Figure 1 according to various embodiments of the present disclosure. Figure 4 the control signal generator 162-2 illustratively shown in Figure 1 is another embodiment of the control signal generator 162 shown in Figure 2 . Compared to the control signal generator 162-1 illustratively shown in Figure 4 , the control signal generator 162-2 in Figure 2As shown, the control signal BLEQB is generated by a logic gate NAND 1 from the clock signal CKPBd and the inverted delayed clock signal CKPBd. On the other hand, as shown in FIG. 2B, the control signal BLEQB is generated by a logic gate NOR 1 and an inverter INV 3 from the input clock signal CKP and the delayed clock signal CKPd. Figure 4 As shown, the control signal BLEQB is generated by a logic gate NOR 1 and an inverter INV 3 from the input clock signal CKP and the delayed clock signal CKPd.

[0058] As shown in FIG. 2A, in some embodiments, the control signal generator 162-1 includes a track wire TR, a logic gate NAND 2, and an inverter INV 2. In some embodiments, the control signal generator 162-1 receives an input control signal PRE and an input clock signal CKP. Figure 4

[0059] The track wire TR has a track length that is positively correlated to the depth distance DPf of the word lines WL1-WL2k.

[0060] The logic gate NAND 2 and the inverter INV 2 are configured to generate a control signal DEC to the word line decoder 180 from the input control signal PRE and the input clock signal CKP. In this case, the control signal DEC has two gate delays (caused by the logic gate NAND 2 and the inverter INV 2) relative to the input clock signal CKP.

[0061] The logic gate NOR 1 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the logic gate NOR 1 is configured to receive the input clock signal CKP. The second input terminal of the logic gate NOR 1 is configured to receive the delayed clock signal CKPd (i.e., the input clock signal CKP after being delayed by the track wire TR).

[0062] The output terminal of the logic gate NOR 1 is connected to the inverter INV 3. The inverter INV 3 is configured to invert the output signal from the logic gate NOR 1 and accordingly generate the control signal BLEQB. The logic gate NOR 1 is configured to perform a NOR Boolean function between the two input terminals and generate an output signal that is further inverted by the inverter INV 3 to the control signal BLEQB. The relationship between the inputs and outputs of the logic gate NOR 1 and the inverter INV 3 is shown in Table 2.

[0063]

[0064] Table 2

[0065] Based on Boolean logic:

[0066] BLEQB generated by the output of the inverter INV 3 in FIG. 2A Figure 4 BLEQB generated by the output of the inverter INV 3 in FIG. 2B

[0067] = NOT[​Figure 4 Output of the NOR1 logic gate

[0068] = NOT [NOT [CKP U CKPd]]

[0069] = CKP U CKPd

[0070] = NOT [CKP B AND CKP Bd]

[0071] = Figure 2 Output of the NAND1 logic gate

[0072] In other words, Figure 4 the logic gate NOR1 and the inverter INV3 in the Figure 2 the logic gate NAND1 discussed in the embodiment of

[0073] In a similar manner, the rising edge of the control signal BLEQB generated by the logic gate NOR1 and the inverter INV3 in the Figure 4 is triggered by the rising edge of the input clock signal CKP. By means of the trace wiring TR, the delay with respect to the depth distance DPf is tracked, and the falling edge of the control signal BLEQB generated by the logic gate NOR1 and the inverter INV3 in the Figure 4 is triggered by the falling edge of the delayed clock signal CKPd, which is equal to the input clock signal CKP delayed by the trace wiring TR. In this case, the control signal BLEQB is able to enclose both the rising edge of the word line signal on the word line WL1 and the falling edge of the word line signal on the word line WL2k.

[0074] Further reference is made to Figure 5 , Figure 5 shows the internal structure of the modulation circuit and the control signal generator in the Figure 1 according to various embodiments of the present disclosure. Figure 5 The control signal generator 162-3 illustratively shown in the Figure 1 is another embodiment of the control signal generator 162 shown in Figure 2 comparing to the control signal generator 162-1 illustratively shown in the Figure 4 and the control signal generator 162-2 illustratively shown in the Figure 5 the control signal generator 162-3 in the utilizes a different combination of logic gates and inverters to generate the control signal BLEQB. As shown in Figure 2 the control signal BLEQB is generated by the logic gate NAND1 from the clock signal CKPBd and the inverted delayed clock signal CKPBd. As shown in Figure 5As shown, the control signal BLEQB is generated by logic gate NOR1 and inverter INV3 based on the input clock signal CKP and the delayed clock signal CKPd. Figure 4 Compared to the control signal generator 162-2 shown, Figure 5 The control signal generator 162-3 includes an additional inverter for converting the clock signal.

[0075] like Figure 5 As shown, in some embodiments, the control signal generator 162-3 includes a tracking route TR, logic gates NAND2 and NOR1, and inverters INV1-INV4. In some embodiments, the control signal generator 162-3 receives an input control signal PRE and an inverted input clock signal CKPB. The tracking length of the tracking route TR is positively correlated with the depth distance DPf of the word lines WL1-WL2k.

[0076] Figure 5 The control signal generator 162-3 shown is... Figure 4 The control signal generator 162-2 shown is similar, except that... Figure 5 The control signal generator 162-3 shown also includes two additional inverters, INV1 and INV4. Inverter INV1 is configured to invert the inverted input clock signal CKPB into an input clock signal CKP, which is sent to logic gate NOR1. Inverter INV3 is configured to invert the output of logic gate NOR1 to generate the control signal BLEQB. Inverter INV4 is configured to invert the inverted input clock signal CKPB into an input clock signal CKP, which is sent to logic gate NAND2.

[0077] like Figure 5 As shown, logic gate NOR1 receives the input clock signal CKP and the delayed input clock signal CKPd, and the output of logic gate NOR1 is further inverted by inverter INV3 to become the control signal BLEQB. Based on Boolean logic, Figure 5 In the illustrated embodiment, the control signal BLEQB generated by inverter INV3 is equal to Figure 4 The output of inverter INV3 in the illustrated embodiment is also equal to... Figure 2 The output of logic gate NAND1 in the illustrated embodiment.

[0078] In a similar manner, by Figure 5 The rising edge of the control signal BLEQB generated by the inverter INV3 and logic gate NOR1 is triggered by the rising edge of the input clock signal CKP. The delay with respect to the depth distance DPf is tracked using the trace wiring TR. Figure 5The falling edge of the control signal BLEQB generated by the inverter INV3 and logic gate NOR1 is triggered by the falling edge of the delayed clock signal CKPd, which is equal to the input clock signal CKP delayed by the tracked wiring TR. In this case, by Figure 5 The control signal BLEQB generated by the inverter INV3 and logic gate NOR1 can surround the rising edge of the word line signal on word line WL1 and the falling edge of the word line signal on word line WL2k.

[0079] Further reference Figure 6 . Figure 6 This is a schematic diagram illustrating another memory device 200 according to various embodiments of the present disclosure. Figure 1 Compared to the memory device 100 shown, which includes bit cells BC arranged in an array but not divided into subarrays, Figure 6 The memory device 200 includes bit cells BC arranged in different subarrays and flying bit lines for transmitting signals on one of the subarrays. Figure 6 In the illustrated embodiment, memory device 200 includes memory array 220, which includes a plurality of bit cells BC arranged in multiple rows and columns. Figure 6 As shown in the embodiment, the memory array 220 includes two subarrays 222, another subarray 224, and stripe cells 226 located between the two subarrays 222 and 224.

[0080] like Figure 6 As illustrated, bit cells BC located adjacent to the bottom side of memory array 220 are grouped into subarray 222, and bit cells BC located adjacent to the top side of memory array 220 are grouped into subarray 224. Figure 6 As illustrated, in some embodiments, bit cells BC on the same row are connected to the same word line. For example, bit cells BC on the first row (starting from the bottom side of memory array 220) are connected to word line WL1; bit cells BC on the second row are connected to word line WL2; and bit cells BC on the kth row are connected to word line WLk. The bit cells BC connected to word lines WL1-WLk are grouped into subarray 222.

[0081] On the other hand, bit cell BC in row (k+1) is connected to word line WLk+1; bit cell BC in row (k+2) is connected to word line WLk+2; and bit cell BC in row (2k) is connected to word line WL2k. Bit cells BC connected to word lines WLk+1-WL2k are grouped into subarray 224.

[0082] In some embodiments, k is a positive integer. For example, in a memory array 120 having 2048 rows of bitcells BC, k equals 1024, and 2048 wordlines are distributed from a bottom side to a top side of the memory array 120. In this example, bitcells BC on rows 1 through 1024 are in subarray 222, and bitcells BC on rows 1025 through 2048 are in subarray 224.

[0083] Bitcells BC in subarray 222 on the same column are connected to one bitline pair. For example, bitcells BC in subarray 222 on the left side first column are connected to one bitline pair that includes one bitline BLId and one complementary bitline BLBId, and bitcells BC in subarray 222 on the right side nth column are connected to another bitline pair that includes another bitline BLnd and another complementary bitline BLBnd. As shown, bitline BLId and one complementary bitline BLBId extend from a bottom side edge of memory array 220 along the first column of subarray 222 and terminate between subarray 222 and subarray 224. In some embodiments, n is a positive integer. For example, n can be approximately 8, 16, 32, or other suitable number. For brevity, only two columns of memory array 220 are shown in Figure 6 Figure 6 for illustrative purposes, only two columns of memory array 220 are shown. However, embodiments of the present disclosure are not limited to a particular number of columns in memory array 220.

[0084] Bitcells BC in subarray 224 on the same column are connected to one bitline pair. For example, bitcells BC in subarray 224 on the left side first column are connected to one bitline pair that includes one bitline BLlu and one complementary bitline BLBlu, and bitcells BC in subarray 222 on the right side nth column are connected to another bitline pair that includes another bitline BLnu and another complementary bitline BLBnu. As shown, bitline BLlu and one complementary bitline BLBlu extend from a stripe cell 226 of memory array 220 along the first column of subarray 224 to a top side edge of memory array 220. In some embodiments, stripe cell 226 is located at a gap space between subarrays 222 and 224. In some embodiments, a fly bitline BLlf and a complementary fly bitline BLBlf are connected to bitline BLlu and one complementary bitline BLBlu at stripe cell 226. Figure 6

[0085] As Figure 6 Illustratively shown, in some embodiments, memory device 200 includes local input / output circuitry 240, a main control circuit 260, and a wordline decoder 280. Main control circuit 260 is coupled with local input / output (LIO) circuitry 240 and wordline decoder 280. Figure 6 ​​Some functions and behaviors of the local input / output circuit 240, the main control circuit 260, and the word line decoder 280 of the embodiment in FIG. 2B are similar to those of the local input / output circuit 140, the main control circuit 160, and the word line decoder 180 of the embodiment in FIG. 2A, and can refer to the above-mentioned embodiments discussed in Figure 1 and Figure 2 the embodiment in FIG. 2B. Figure 1 and Figure 2 the embodiment in FIG. 2B.

[0086] In some embodiments, the main control circuit 260 includes a control signal generator 262, and the control signal generator 262 is configured to generate some control signals to control / activate / disable functions in the local input / output circuit 240 and the word line decoder 280. As Figure 6 Illustratively shown, in some embodiments, the control signal generator 262 is configured to generate a control signal BLEQBd (corresponding to the subarray 222) to the local input / output circuit 240, generate another control signal BLEQBu (corresponding to the subarray 224) to the local input / output circuit 240, generate yet another control signal YSEL to the local input / output circuit 240, and generate a control signal DEC to the word line decoder 280. In some other embodiments, the control signal generator 262 is capable of generating other control signals for controlling other functions. Embodiments of the present application are not limited to these control signals.

[0087] In some embodiments, the local input / output circuit 240 includes a modulation circuit 242a-242b (corresponding to the subarray 222), a modulation circuit 243a-243b (corresponding to the subarray 224), a selection circuit 244, and a read / write circuit 246.

[0088] During a write operation to the subarray 222, the read / write circuit 246 is configured to generate a write signal and a complementary write signal to a bit line pair including the bit line BLd and the complementary bit line BLBd in the local input / output circuit 240, and the selection circuit 244 is configured to couple the bit line pair (i.e., the bit line BLd and the complementary bit line BLBd) to one of the bit line pairs in the subarray 222 of the memory array 220 according to the selection signal YSEL, so as to write data into the bit cell BC on a target column in the subarray 222.

[0089] For example, when the target column of the write operation is the 1stcolumn in the subarray 222, the selection circuit 244 is configured to couple the bit line BLd and the complementary bit line BLBd in the local input / output circuit 240 to the bit line BL1d and the complementary bit line BLB1d on the 1stcolumn in the subarray 222 of the memory array 220, so as to write data into the bit cell BC on the 1stcolumn in the subarray 222.

[0090] During a write operation to sub-array 224, read / write circuit 246 is configured to generate a write signal and a complementary write signal onto a bit line pair including bit line BLu and complementary bit line BLBu in local input / output circuit 240. As shown, memory array 220 also includes some flying bit line pairs that are configured to connect the bit line pair in upper sub-array 224 with selection circuit 244 and read / write circuit 246 located below the bottom side of memory array 220. Figure 6

[0091] For example, when the target column of a write operation is column 1 in sub-array 224, selection circuit 244 is configured to couple bit line BLu and complementary bit line BLBu in local input / output circuit 240 to bit line BLlu and complementary bit line BLB1u on column 1 in sub-array 224 of memory array 220 via flying bit line BL1f and complementary flying bit line BLB1f in order to write data into bit cells BC on column 1 in sub-array 224.

[0092] There are many rows in a memory array such that the resistance-capacitance loaded on a bit line pair connected to bit cells on an entire column is relatively large. By dividing memory array 220 into two sub-arrays 222 and 224, the resistance-capacitance loaded on one bit line pair (e.g., BL1d and BLB1d; BL1u and BLB1u) can be reduced. As shown in embodiments, Figure 6 As shown in embodiments, each bit line pair in a memory array is connected to about half of the bit cells on the same column such that the resistance-capacitance loaded on each bit line pair can be reduced by about 50% (compared to being connected to all bit cells on the same column).

[0093] It is noted that there are three bit line pairs corresponding to column 1 of memory array 220. The three bit line pairs include a first bit line pair (e.g., bit line BL1d and complementary bit line BLB1d) connecting bit cells BC in sub-array 222 to selection circuit 244 and read / write circuit 246, a second bit line pair (e.g., bit line BL1u and complementary bit line BLB1u) connecting bit cells BC in sub-array 224, and a third bit line pair (e.g., flying bit line BL1f and complementary flying bit line BLB1f) connecting from the second bit line pair to selection circuit 244 and read / write circuit 246. Similarly, there are another three bit line pairs corresponding to column n of memory array 220.

[0094] As shown, memory array 220 also includes some flying bit line pairs that are configured to connect the bit line pair in upper sub-array 224 with selection circuit 244 and read / write circuit 246 located below the bottom side of memory array 220. Figure 6 ​As illustratively shown, the modulation circuit 242a is coupled to the bit line BLId and the complementary bit line BLBId (i.e., the first bit line pair) connected to the bit cells BC in the first column of the subarray 222. The modulation circuit 242a is configured to modulate the voltage levels on the bit line BLId and the complementary bit line BLBId in the subarray 222 according to the control signal BLEQBd.

[0095] The modulation circuit 243a is coupled to the bit line BL1u and the complementary bit line BLB1u (i.e., the second bit line pair) in the subarray 224 through the flying bit line BL1f and the complementary bit line BLB1f (i.e., the third bit line pair). The modulation circuit 243a is configured to modulate the voltage levels on the bit line BL1u and the complementary bit line BLB1u in the subarray 224 according to the control signal BLEQBu.

[0096] Outside of a write operation or a read operation, in some embodiments, the modulation circuit 242a is triggered by the control signal BLEQBd and configured to couple the bit line BLId and the complementary bit line BLBId to each other, thereby equalizing the voltage levels on the bit line BLId and the complementary bit line BLBId. In some embodiments, outside of a write operation or a read operation, the modulation circuit 242a is further configured to pre-charge the voltage levels on the bit line BLId and the complementary bit line BLBId to a fixed level, such as a high reference voltage level VDD.

[0097] Outside of a write operation or a read operation, in some embodiments, the modulation circuit 243a is triggered by the control signal BLEQBu and configured to couple the bit line BL1u and the complementary bit line BLB1u to each other, thereby equalizing the voltage levels on the bit line BL1u and the complementary bit line BLB1u. In some embodiments, outside of a write operation or a read operation, the modulation circuit 243a is further configured to pre-charge the voltage levels on the bit line BL1u and the complementary bit line BLB1u to a fixed level, such as a high reference voltage level VDD. The functions and behaviors of the modulation circuits 242a and 243a can be referred to the modulation circuit 142a in the embodiments discussed in Figure 2

[0098] Similarly, the modulation circuit 242b is configured to modulate the voltage levels on the bit line BLnd and the complementary bit line BLBnd in the subarray 222 according to the control signal BLEQBd, and the modulation circuit 243b is configured to modulate the voltage levels on the bit line BLnu and the complementary bit line BLBnu in the subarray 224 according to the control signal BLEQBu.

[0099] ​In some embodiments, the word line decoder 280 is controlled by a control signal DEC generated by the control signal generator 262. In some embodiments, the word line decoder 280 includes a number of decoder units 282, and each decoder unit 282 is configured to provide one word line signal to one of the word lines WL1-WL2k. The control signal DEC is used to control the addressing and gating functions of the decoder units 282 in the word line decoder 280. When the control signal DEC is sent from the side of the control signal generator 262 to the decoder units 282 in the word line decoder 280, the control signal DEC reaches different decoder units 282 at different time points. Due to the different arrival timing of the control signal DEC as described above, the word line signals generated by the decoder units 282 in the word line decoder 280 to the word lines WL1-WL2k have pulses with different timing.

[0100] In some embodiments, the control signal generator 262 is configured to generate the control signal BLEQBd with reference to the full depth distance DPf between the word line WL1 and the word line WL2k, and also generate the control signal BLEQBu with reference to the half depth distance DPh between the word line WL1 and the word line WLk.

[0101] Further reference is made to Figure 7 and Figure 8 . Figure 7 is a schematic diagram showing the internal structure of the modulation circuit and the control signal generator in Figure 6 according to various embodiments of the present disclosure. Figure 8 is a signal waveform showing the relevant signals generated in the memory device 200 in Figure 6 and Figure 7 according to various embodiments of the present disclosure. With respect to the embodiments of Figure 6 for ease of understanding, Figure 7 and Figure 8 similar elements in Figure 7 are designated with the same reference numerals. Note that for brevity, Figure 7 shows the structure related to the 1st column of the subarray 222 and the subarray 224. The structure related to other columns is similar and can be understood by the embodiments shown in Figure 7 Figure 6 The control signal generator 262-1 shown in is one embodiment of the control signal generator 262 shown in

[0102] . Figure 7Illustratively, the modulation circuit 242a includes three transistors. The gates of the transistors in the modulation circuit 242a are controlled by the control signal BLEQBd. The transistors in the modulation circuit 242a are coupled to the bit line BLId and the complementary bit line BLBId in the subarray 222. When the control signal BLEQBd is at a low voltage level (e.g., 0V, GND level, or VSS level), the modulation circuit 242a is configured to couple the bit line BLId and the complementary bit line BLBId (in the bit line pair on the 1stcolumn in the subarray 222) together, thereby equalizing the voltage levels on the bit line BLId and the complementary bit line BLBId. When the control signal BLEQBd is at a low voltage level (e.g., 0V), the modulation circuit 242a is further configured to connect the bit line BLId and the complementary bit line BLBId to the high reference voltage level VDD, thereby fixing the voltage levels on the bit line BLId and the complementary bit line BLBId to the high reference voltage level VDD. The behavior and details about the modulation circuit 242a are similar to those described in the above embodiments in connection with the modulation circuit 142a. Figure 2 The modulation circuit 242a.

[0103] In some embodiments, in addition to the write operation or the read operation, the modulation circuit 242a is configured to pre-charge the voltage levels on the bit line BLId and the complementary bit line BLBId to a fixed level, e.g., the high reference voltage level VDD. In this case, the bit line BLId and the complementary bit line BLBId are configured to a fixed level instead of a floating level, and the data stored in the bit cell BC can be protected and avoid being affected by an unintended floating level on the bit line BLId and the complementary bit line BLBId.

[0104] Similarly, the modulation circuit 243a includes another three transistors. The gates of the transistors in the modulation circuit 243a are controlled by the control signal BLEQBu. When the control signal BLEQBu is at a low voltage level (e.g., 0V, GND level, or VSS level), the modulation circuit 243a is configured to couple the bit line BL1u (via the flying bit line BL1f) and the complementary bit line BLB1u (via the complementary flying bit line BLB1f) together, thereby equalizing the voltage levels on the bit line BL1u and the complementary bit line BLB1u. When the control signal BLEQBu is at a low voltage level (e.g., 0V), the modulation circuit 243a is further configured to connect the bit line BL1u (via the flying bit line BL1f) and the complementary bit line BLB1u (via the complementary flying bit line BLB1f) to the high reference voltage level VDD, thereby fixing the voltage levels on the bit line BL1u and the complementary bit line BLB1u to the high reference voltage level VDD.

[0105] Similarly, outside of write or read operations, modulation circuit 243a is configured to precharge the voltage levels on bit line BL1u and complementary bit line BLB1u to a fixed level, such as a high reference voltage level VDD. In this case, modulation circuit 243a is able to prevent data stored in the corresponding bit cell BC from being affected by unexpected floating levels on bit line BL1u and complementary bit line BLB1u.

[0106] When the control signal BLEQBd is at a high voltage level (e.g., VDD level), the modulation circuit 242a is deactivated, and the voltage levels on bit line BL1d and complementary bit line BLB1d are released from the modulation circuit 242a and controlled by... Figure 6 The read / write circuit 246 shown is controlled by this circuit.

[0107] like Figure 7 and Figure 8 As illustrated, during the duration DWL1, the word line signal to word line WL1 is switched to a high voltage level, and the bit cell BC connected to word line WL1 should be ready for read / write, such that the rising edge of the control signal BLEQBd needs to arrive simultaneously with (or before) the rising edge of the word line signal on word line WL1. If the rising edge of the control signal BLEQBd arrives after the rising edge of the word line signal on word line WL1, the modulation circuit 242a may not release bit line BL1d and complementary bit line BLB1d in time, causing the read / write margin for bit cell BC to be degraded.

[0108] like Figure 7 and Figure 8 As illustrated, during the duration DWL2k, the word line signal to word line WL2k is switched to a high voltage level, and the bit cell BC connected to word line WL2k should be ready for read / write, such that the falling edge of the control signal BLEQBd needs to arrive simultaneously with (or after) the falling edge of the word line signal on word line WLk. If the falling edge of the control signal BLEQBd arrives before the falling edge of the word line signal on word line WLk, the modulation circuit 242a can raise the voltage levels on both bit line BL1d and complementary bit line BLB1d to a high voltage level while word line WLk is still active for access to bit cell BC, so that the data bits stored in bit cell BC may be corrupted due to the misconfiguration of the voltage levels on bit line BL1d and complementary bit line BLB1d.

[0109] In other words, the duration D1 for which the control signal BLEQBd switches to a high voltage level needs to include the rising edge of the word line signal on word line WL1 and the falling edge of the word line signal on word line WLk. In some embodiments, the control signal generator 262-1 can generate the control signal BLEQBd with reference to the half-depth distance DPh in the correct timing.

[0110] For similar reasons, the duration D2 for the control signal BLEQBu to switch to a high voltage level needs to include the rising edge of the word line signal on word line WLk+1 and the falling edge of the word line signal on word line WL2k. In some embodiments, the control signal generator 262-1 can generate the control signal BLEQBu with reference to the half-depth distance DPh and the full-depth distance DPf at the correct timing.

[0111] like Figure 7 As shown, in some embodiments, the control signal generator 262-1 includes two tracking lines TR1 and TR2, three logic gates NOR1, NOR2 and NAND2, and six inverters INV1a, INV1b, INV2, INV3a, INV3b and INV4. In some embodiments, the control signal generator 262-1 includes two sets of logic gates NOR1 and NOR2 coupled to the two sets of tracking lines TR1 and TR2.

[0112] In some embodiments, the control signal generator 262-1 receives an input control signal PRE and an inverted input clock signal CKPB. In some embodiments, the logic gate NOR1 and the inverter INV3a are configured to generate a control signal BLEQBd based on the input clock signal CKP and a first delayed clock signal CKPd1, which is then sent to the modulation circuit 242a corresponding to the subarray 222. Figure 7 The behavior and function of logic gate NOR1 and inverter INV3a in the control signal generator 262-1 shown are similar to those of... Figure 5 The logic gate NOR1 and inverter INV3 in the control signal generator 162-1 shown are similar. The relationship between the input of logic gate NOR1 and the output of inverter INV3a is shown in Table 3.

[0113]

[0114] Table 3

[0115] In some embodiments, logic gate NOR2 and inverter INV3b are configured to generate a control signal BLEQBu based on a first delayed clock signal CKP and a second delayed clock signal CKPd2, which is then sent to a modulation circuit 243a corresponding to subarray 224. Figure 7 The behavior and function of the logic gate NOR2 and inverter INV3b in the control signal generator 262-1 shown are similar to those of... Figure 5 The logic gate NOR1 and inverter INV3 in the control signal generator 162-1 shown are similar. The relationship between the input of logic gate NOR2 and the output of inverter INV3b is shown in Table 4.

[0116]

[0117]

[0118] Table 4

[0119] As shown in the embodiments of Figure 7 and Figure 8 , the first delayed clock signal CKPd1 is generated by delaying the input clock signal CKP with the use of the trace wiring TR1. The trace wiring TR1 has a trace length that is positively correlated to the half-depth distance DPh of the word lines WL1-WL2k of the entire memory array 220. In other words, the half-depth distance DPh is approximately the full-depth distance of the word lines WL1-WLk of the sub-array 222. As shown in Figure 7 , in some embodiments, the trace wiring TR1 includes a first trace segment S1 and a second trace segment S2. The first trace segment S1 extends from the bottom side edge of the word lines WL1-WL2k to the quarter position of the word lines WL1-WL2k. For example, when there are a total of 2048 word lines (k = 1024) in the entire memory array 220, the first trace segment S1 extends from the word line WL1 to the 512th word line (not shown in the figure). The second trace segment S2 extends from the quarter position of the word lines WL1-WL2k to the bottom side edge of the word lines WL1-WL2k. In this case, the sum of the lengths of the first trace segment S1 and the second trace segment S2 is similar to or approximately equal to the half-depth distance DPh. The half-depth distance DPh can be considered as the full-depth distance of the word lines WL1-WLk of the sub-array 222.

[0120] The rising edge of the control signal BLEQBd generated by the inverter INV3a and the logic gate NOR1 in Figure 7 and Figure 8 is triggered by the rising edge of the input clock signal CKP. The delay with respect to the half-depth distance DPh is traced by means of the trace wiring TR. The falling edge of the control signal BLEQBd generated by the inverter INV3a and the logic gate NOR1 in Figure 7 is triggered by the falling edge of the first delayed clock signal CKPd1, which is equal to the input clock signal CKP delayed by the trace wiring TR1. In this case, as shown in Figure 8 , the duration D1 during which the control signal BLEQBd switches to the high voltage level can contain the rising edge of the word line signal on the word line WL1 and the falling edge of the word line signal on the word line WLk.

[0121] As shown in the embodiments of Figure 7 and Figure 8As shown in the embodiment, the second delayed clock signal CKPd2 is generated by delaying the input clock signal CKP using the tracking wiring TR2. The tracking length of the tracking wiring TR2 is positively correlated with the full depth distance DPh of the word lines WL1-WL2k of the entire memory array 220. Figure 7 As shown, in some embodiments, the tracking wiring TR2 includes a third tracking segment S3 and a fourth tracking segment S4. The third tracking segment S3 extends from the bottom edge of word lines WL1-WL2k to halfway down word lines WL1-WL2k. For example, when there are a total of 2048 word lines (k = 1024) in the entire memory array 220, the first tracking segment S3 extends from the first word line WL1 to the 1024th word line WLk. The fourth tracking segment S4 extends from halfway down word lines WL1-WL2k to the bottom edge of word lines WL1-WL2k. In this case, the sum of the lengths of the third tracking segment S3 and the fourth tracking segment S4 is similar to or approximately equal to the full depth distance DPf.

[0122] Depend on Figure 7 and Figure 8 The rising edge of the control signal BLEQBu generated by the inverter INV3b and logic gate NOR2 is triggered by the rising edge of the first delayed clock signal CKPd1. The delay with respect to the half-depth distance DPf is tracked using the trace wiring TR2. Figure 7 The falling edge of the control signal BLEQBu generated by the inverter INV3b and logic gate NOR2 is triggered by the falling edge of the second delayed clock signal CKPd2, which is equal to the input clock signal CKP delayed by the tracked wiring TR2. In this case, as... Figure 8 As shown, the duration D2 for the control signal BLEQBu to switch to a high voltage level can include the rising edge of the word line signal on word line WLk+1 and the falling edge of the word line signal on word line WL2k.

[0123] In the embodiments discussed above, the control signal BLEQBd generated by the control signal generator 262-1 is determined based on the depth distance of subarray 222, such that the control signal BLEQBd switches to a high voltage level before (or simultaneously with) word line WL1 being set to a high voltage level, and the control signal BLEQBd remains at a high voltage level for a sufficiently long time until word line WLk is set to a low voltage level. On the other hand, the control signal BLEQBu generated by the control signal generator 262-1 is determined based on the depth distance of subarray 224, such that the control signal BLEQBu switches to a high voltage level before (or simultaneously with) word line WLk+1 being set to a high voltage level, and the control signal BLEQBu remains at a high voltage level for a sufficiently long time until word line WL2k is set to a low voltage level.

[0124] Please note,Figure 7 The control signal generator 262-1 illustratively shown is an implementation of Figure 6 The control signal generator 262-1 illustratively shown is an implementation of Figure 5 The control signal generator 262-1 illustratively shown is an implementation of Figure 6 The control signal generator 262-1 illustratively shown is an implementation of Figure 2 The control signal generator 262-1 illustratively shown is an implementation of Figure 4 The control signal generator 262-1 illustratively shown is an implementation of

[0125] In some embodiments, a device includes a memory array, a plurality of bit line pairs, a plurality of word lines, a modulation circuit, and a control signal generator. The memory array has a plurality of bit cells arranged in rows and columns. Each bit line pair is connected to bit cells of a respective column. Each word line is connected to bit cells of a respective row. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a tracking line having a tracking length that positively correlates with a depth distance of the word lines. The control signal generator is configured to generate a control signal that switches to a first voltage level for a first duration of time with reference to the tracking length to control the modulation circuit.

[0126] In some embodiments, in response to the control signal being at a second voltage level different from the first voltage level, the modulation circuit is configured to connect a bit line and a complementary bit line of the at least one bit line pair to each other to equalize voltage levels on the bit line and the complementary bit line.

[0127] In some embodiments, in response to the control signal being at the first voltage level, the modulation circuit is configured to pre-charge the bit line and the complementary bit line of the at least one bit line pair to a reference voltage level.

[0128] In some embodiments, the device further includes a read / write circuit coupled to the at least one bit line pair. In response to the control signal switching to the first voltage level, the modulation circuit is disabled, and the read / write circuit is configured to access bit cells connected with the at least one bit line pair.

[0129] In some embodiments, the trace wiring includes a first trace segment and a second trace segment. The first trace segment extends from a side edge of the word line to a half location of the word line. The second trace segment extends from the half location of the word line to the side edge of the word line. A sum of lengths of the first trace segment and the second trace segment positively correlates with a depth distance of the word line.

[0130] In some embodiments, the control signal generator includes a logic gate. The logic gate has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the logic gate is configured to receive the clock signal. The second input terminal of the logic gate is configured to receive the clock signal delayed through the trace wiring. The output terminal is configured to produce the control signal.

[0131] In some embodiments, a device includes a memory array, a first bit line pair, a second bit line pair, a plurality of word lines, a first modulation circuit, a second modulation circuit, and a control signal generator. The memory array has a plurality of bit cells arranged in rows and columns. The memory array includes a first subarray of bit cells and a second subarray of bit cells. The first bit line pair is coupled to bit cells in the first subarray on a column of the memory array. The second bit line pair is coupled to bit cells in the second subarray on the column of the memory array. The plurality of word lines extends along a plurality of rows of the memory array. The first modulation circuit is coupled with the first bit line pair. The second modulation circuit is coupled with the second bit line pair. The control signal generator is coupled with the first modulation circuit and the second modulation circuit. The control signal generator includes a first trace wiring having a first trace length positively correlated with a half-depth distance of the word lines. The control signal generator is configured to produce a first control signal that switches to a first voltage level for a first duration of time with reference to the first trace length for controlling the first modulation circuit. The control signal generator includes a second trace wiring having a second trace length positively correlated with a full-depth distance of the word lines, and the control signal generator is configured to produce a second control signal that switches to the first voltage level for a second duration of time with reference to the second trace length for controlling the second modulation circuit.

[0132] In some embodiments, the first bit line pair is configured to extend along the column of the memory array from a first side edge of the memory array and terminate between the first subarray and the second subarray. The first bit line pair is coupled to bit cells of the first subarray in the column.

[0133] In some embodiments, the second bit line pair is configured to extend along the column of the memory array from the stripe cell between the first subarray and the second subarray to a second side edge of the memory array, and the second bit line pair is coupled to bit cells of the second subarray in the column.

[0134] In some embodiments, the device further includes a third bit line pair coupled between the second modulation circuit and the second bit line pair. The third bit line pair extends along a column of the memory array and is parallel to the first bit line pair.

[0135] In some embodiments, in response to the first control signal being at a second voltage level different from the first voltage level, the first modulation circuit is configured to connect the bit line and the complementary bit line in the first bit line pair to each other and pre-charge the bit line and the complementary bit line in the first bit line pair to a reference voltage level.

[0136] In some embodiments, in response to the second control signal being at a second voltage level different from the first voltage level, the second modulation circuit is configured to connect the bit line and the complementary bit line in the second bit line pair to each other and pre-charge the bit line and the complementary bit line in the second bit line pair to a reference voltage level.

[0137] In some embodiments, the device further includes a read / write circuit coupled to the first bit line pair and the second bit line pair. In response to the first control signal and the second control signal switching to the first voltage level, the first modulation circuit and the second modulation circuit are disabled, the read / write circuit is configured to access a bit cell connected to the first bit line pair or the second bit line pair.

[0138] In some embodiments, the first trace wiring includes a first trace segment and a second trace segment. The first trace segment extends from a side edge of the word line to a quarter position of the word line. The second trace segment extends from the quarter position of the word line to the side edge of the word line. The sum of the lengths of the first trace segment and the second trace segment positively correlates to a half-depth distance of the word line.

[0139] In some embodiments, the second trace wiring includes a third trace segment and a fourth trace segment. The third trace segment extends from a side edge of the word line to a center of the word line. The fourth trace segment extends from a half position of the word line to the side edge of the word line. The sum of the lengths of the third trace segment and the fourth trace segment positively correlates to a full-depth distance of the word line.

[0140] In some embodiments, the control signal generator includes a first logic gate having a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first logic gate is configured to receive a clock signal. The second input terminal of the first logic gate is configured to receive the clock signal delayed through the first trace wiring, and the output terminal is configured to generate the first control signal.

[0141] In some embodiments, the control signal generator includes a second logic gate having a first input terminal, a second input terminal, and an output terminal. The first input terminal of the second logic gate is configured to receive the clock signal delayed through the first trace. The second input terminal of the second logic gate is configured to receive the clock signal delayed through the second trace. The output terminal of the second logic gate is configured to generate the second control signal.

[0142] In some embodiments, the first subarray is arranged relatively proximate to a side edge of the memory array, and the second subarray is arranged relatively distal to the side edge.

[0143] In some embodiments, a method includes the following operations. A clock signal is delayed into a first delayed clock signal with a first trace. The first trace has a first trace length positively correlated to a first depth distance of a word line. A first control signal is generated with reference to the clock signal and the first delayed clock signal.

[0144] In some embodiments, the method further includes the following operations. The clock signal is delayed into a second delayed clock signal with a second trace. The second trace has a second trace length positively correlated to a second depth distance of a word line. A second control signal is generated with reference to the first delayed clock signal and the second delayed clock signal.

[0145] The foregoing summary has outlined rather broadly the features of several embodiments so as to provide those skilled in the art with a better understanding of aspects of the disclosure. The skilled artisan should appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein without departing from the spirit and scope of the disclosure. Those skilled in the art should appreciate that they can readily use the conceptual aspects of the disclosure to

[0146] Example 1 is a memory device comprising: a memory array having a plurality of bit cells arranged in rows and columns; a plurality of bit line pairs, each bit line pair connected to bit cells of a respective column; a plurality of word lines, each word line connected to bit cells of a respective row; a modulation circuit coupled with at least one bit line pair; and a control signal generator coupled with the modulation circuit, wherein the control signal generator includes a trace having a trace length positively correlated to a depth distance of the word line, the control signal generator configured to generate a control signal that switches to a first voltage level for a first duration of time with reference to the trace length for controlling the modulation circuit.

[0147] Example 2 is the device of Example 1, wherein, in response to the control signal being at a second voltage level different from the first voltage level, the modulation circuit is configured to connect a bit line and a complementary bit line in the at least one bit line pair to each other to equalize voltage levels on the bit line and the complementary bit line.

[0148] Example 3 is the device of Example 1, wherein, in response to the control signal being at the first voltage level, the modulation circuit is configured to pre-charge the bit line and the complementary bit line in the at least one bit line pair to a reference voltage level.

[0149] Example 4 is the device of Example 1, further comprising a read / write circuit coupled to the at least one bit line pair, wherein, in response to the control signal switching to the first voltage level, the modulation circuit is disabled and the read / write circuit is configured to access bit cells connected to the at least one bit line pair.

[0150] Example 5 is the device of Example 1, wherein the trace wiring includes a first trace segment extending from a side edge of the word line to a half location of the word line, and a second trace segment extending from the half location of the word line to the side edge of the word line, a sum of lengths of the first trace segment and the second trace segment positively correlates with a distance from the depth of the word line.

[0151] Example 6 is the device of Example 1, wherein the control signal generator includes a logic gate having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the logic gate is configured to receive a clock signal, the second input terminal of the logic gate is configured to receive the clock signal delayed through the trace wiring, and the output terminal is configured to generate the control signal.

[0152] Example 7 is a memory device comprising: a memory array having a plurality of bit cells arranged in rows and columns, wherein the memory array includes a first subarray of bit cells and a second subarray of bit cells; a first bit line pair coupled to bit cells in the first subarray on a column of the memory array; a second bit line pair coupled to bit cells in the second subarray on a column of the memory array; a plurality of word lines extending along a plurality of rows of the memory array; a first modulation circuit coupled with the first bit line pair; a second modulation circuit coupled with the second bit line pair; and a control signal generator coupled with the first modulation circuit and the second modulation circuit, wherein the control signal generator includes a first tracking wire having a first tracking length positively correlated to a half-depth distance of the word lines, the control signal generator configured to generate a first control signal that switches to a first voltage level for a first duration of time referenced to the first tracking length for controlling the first modulation circuit, and wherein the control signal generator includes a second tracking wire having a second tracking length positively correlated to a full-depth distance of the word lines, the control signal generator configured to generate a second control signal that switches to the first voltage level for a second duration of time referenced to the second tracking length for controlling the second modulation circuit.

[0153] Example 8 is the device of Example 7, wherein the first bit line pair is configured to extend along the column of the memory array from a first side edge of the memory array and terminate between the first subarray and the second subarray, the first bit line pair coupled to bit cells of the first subarray in the column.

[0154] Example 9 is the device of Example 8, wherein the second bit line pair is configured to extend along the column of the memory array from a stripe cell between the first subarray and the second subarray to a second side edge of the memory array, the second bit line pair coupled to bit cells of the second subarray in the column.

[0155] Example 10 is the device of Example 9, further comprising: a third bit line pair coupled between the second modulation circuit and the second bit line pair, wherein the third bit line pair extends along the column of the memory array and is parallel to the first bit line pair.

[0156] Example 11 is the device of Example 7, wherein, in response to the first control signal being at a second voltage level different from the first voltage level, the first modulation circuit is configured to mutually connect bit lines and complementary bit lines in the first bit line pair and pre-charge the bit lines and complementary bit lines in the first bit line pair to a reference voltage level.

[0157] Example 12 is the device of Example 7, wherein, in response to the second control signal being at a second voltage level different from the first voltage level, the second modulation circuit is configured to connect a bit line and a complementary bit line in the second pair of bit lines to each other and pre-charge the bit line and the complementary bit line in the second pair of bit lines to a reference voltage level.

[0158] Example 13 is the device of Example 7, further comprising a read / write circuit coupled to the first pair of bit lines and the second pair of bit lines, wherein, in response to the first control signal and the second control signal switching to the first voltage level, the first modulation circuit and the second modulation circuit are disabled, and the read / write circuit is configured to access a bit cell connected to the first pair of bit lines or the second pair of bit lines.

[0159] Example 14 is the device of Example 7, wherein the first trace includes a first trace segment extending from a side edge of the word line to a quarter location of the word line, and a second trace segment extending from the quarter location of the word line to the side edge of the word line, a sum of lengths of the first trace segment and the second trace segment positively correlates to a half-depth distance of the word line.

[0160] Example 15 is the device of Example 7, wherein the second trace includes a third trace segment extending from a side edge of the word line to a center of the word line, and a fourth trace segment extending from a half location of the word line to the side edge of the word line, a sum of lengths of the third trace segment and the fourth trace segment positively correlates to a full-depth distance of the word line.

[0161] Example 16 is the device of Example 7, wherein the control signal generator includes a first logic gate having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the first logic gate is configured to receive a clock signal, the second input terminal of the first logic gate is configured to receive the clock signal delayed through the first trace, and the output terminal is configured to generate the first control signal.

[0162] Example 17 is the device of Example 16, wherein the control signal generator includes a second logic gate having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the second logic gate is configured to receive the clock signal delayed through the first trace, the second input terminal of the second logic gate is configured to receive the clock signal delayed through the second trace, and the output terminal of the second logic gate is configured to generate the second control signal.

[0163] Example 18 is the device of Example 16, wherein the first subarray is disposed relatively proximate to a side edge of the memory array and the second subarray is disposed relatively distal to the side edge.

[0164] Example 19 is a method for a memory device, comprising: delaying a clock signal into a first delayed clock signal with a first tracking wire having a first tracking length positively correlated to a first depth distance of a word line; and generating a first control signal with reference to the clock signal and the first delayed clock signal.

[0165] Example 20 is the method of Example 19, further comprising: delaying the clock signal into a second delayed clock signal with a second tracking wire having a second tracking length positively correlated to a second depth distance of a word line; and generating a second control signal with reference to the first delayed clock signal and the second delayed clock signal.

Claims

1. A memory device, comprising: a memory array having a plurality of bit cells arranged in rows and columns; a plurality of bit line pairs, each bit line pair connected to bit cells of a respective column; a plurality of word lines, each word line connected to bit cells of a respective row; a modulation circuit coupled with at least one bit line pair; and a control signal generator coupled with the modulation circuit, wherein the control signal generator includes a trace wire having a trace length positively correlated to a depth distance of the word line, the control signal generator configured to generate a control signal that switches to a first voltage level for a first duration of time with reference to the trace length for controlling the modulation circuit. in response to the control signal being at a second voltage level different from the first voltage level, the modulation circuit configured to mutually connect a bit line and a complementary bit line in the at least one bit line pair to equalize voltage levels on the bit line and the complementary bit line.

2. The device of claim 1, wherein, in response to the control signal being at the first voltage level, the modulation circuit configured to pre-charge the bit line and the complementary bit line in the at least one bit line pair to a reference voltage level.

3. The device of claim 1, wherein, 4. The device of claim 1, further comprising: a read / write circuit coupled to the at least one bit line pair, wherein, in response to the control signal switching to the first voltage level, the modulation circuit is disabled and the read / write circuit is configured to access bit cells connected with the at least one bit line pair. the trace wire includes:

5. The device of claim 1, wherein, a first trace segment extending from a side edge of the word line to a half location of the word line; and a second trace segment extending from the half location of the word line to the side edge of the word line, a sum of lengths of the first trace segment and the second trace segment positively correlated to the depth distance of the word line. the control signal generator includes:

6. The device of claim 1, wherein, a logic gate having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the logic gate configured to receive a clock signal, the second input terminal of the logic gate configured to receive the clock signal delayed through the trace wire, and the output terminal configured to generate the control signal.

7. A memory device, comprising: a memory array having a plurality of bit cells arranged in rows and columns, wherein the memory array includes a first subarray of bit cells and a second subarray of bit cells; a first bit line pair coupled to bit cells in the first subarray on a column of the memory array; a second bit line pair coupled to bit cells in the second subarray on the column of the memory array; a plurality of word lines extending along a plurality of rows of the memory array; a first modulation circuit coupled with the first bit line pair; a second modulation circuit coupled with the second bit line pair; and a control signal generator coupled with the first modulation circuit and the second modulation circuit, ​ wherein the control signal generator includes a first tracking line having a first tracking length positively correlated to a half-depth distance of the word line, the control signal generator configured to generate a first control signal that switches to a first voltage level for a first duration with reference to the first tracking length for controlling a first modulation circuit, and wherein the control signal generator includes a second tracking line having a second tracking length positively correlated to a full-depth distance of the word line, the control signal generator configured to generate a second control signal that switches to the first voltage level for a second duration with reference to the second tracking length for controlling a second modulation circuit.

8. The device of claim 7, wherein, The first bit line pair is configured to extend along columns of the memory array from a first side edge of the memory array and terminate between the first subarray and the second subarray, the first bit line pair coupled to bit cells of the first subarray in the columns.

9. The device of claim 8, wherein, The second bit line pair is configured to extend along columns of the memory array from the stripe cell between the first subarray and the second subarray to a second side edge of the memory array, the second bit line pair coupled to bit cells of the second subarray in the columns.

10. The device of claim 9, further comprising: a third bit line pair coupled between the second modulation circuit and the second bit line pair, wherein the third bit line pair extends along columns of the memory array and is parallel to the first bit line pair.

11. The device of claim 7, wherein, In response to the first control signal being at a second voltage level different from the first voltage level, the first modulation circuit is configured to interconnect bit lines and complementary bit lines in the first bit line pair and pre-charge the bit lines and complementary bit lines in the first bit line pair to a reference voltage level.

12. The device of claim 7, wherein, In response to the second control signal being at a second voltage level different from the first voltage level, the second modulation circuit is configured to interconnect bit lines and complementary bit lines in the second bit line pair and pre-charge the bit lines and complementary bit lines in the second bit line pair to a reference voltage level.

13. The device of claim 7, further comprising: a read / write circuit coupled to the first bit line pair and the second bit line pair, wherein in response to the first control signal and the second control signal switching to the first voltage level, the first modulation circuit and the second modulation circuit are disabled, the read / write circuit configured to access bit cells connected to the first bit line pair or the second bit line pair.

14. The device of claim 7, wherein, The first tracking line includes: a first tracking segment extending from a side edge of the word line to a quarter position of the word line; and a second tracking segment extending from the quarter position of the word line to the side edge of the word line, a sum of lengths of the first tracking segment and the second tracking segment positively correlated to the half-depth distance of the word line.

15. The device of claim 7, wherein, The second tracking line includes: a third tracking segment extending from a side edge of the word line to a center of the word line; and a fourth tracking segment extending from the center of the word line to the side edge of the word line, a sum of lengths of the third tracking segment and the fourth tracking segment positively correlated to the full-depth distance of the word line. a fourth tracking segment extending from a half location of the word line toward a side edge of the word line, a sum of lengths of the third tracking segment and the fourth tracking segment being positively correlated with a full depth of the word line.

16. The device of claim 7, wherein, The control signal generator includes: a first logic gate having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the first logic gate configured to receive a clock signal, the second input terminal of the first logic gate configured to receive the clock signal delayed through the first tracking wiring, and the output terminal configured to produce the first control signal.

17. The device of claim 16, wherein, The control signal generator includes: a second logic gate having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the second logic gate configured to receive the clock signal delayed through the first tracking wiring, the second input terminal of the second logic gate configured to receive the clock signal delayed through the second tracking wiring, and the output terminal of the second logic gate configured to produce the second control signal.

18. The device of claim 16, wherein, The first subarray is arranged relatively close to a side edge of the memory array, and the second subarray is arranged relatively far from the side edge.

19. A method for a memory device, comprising: delaying a clock signal as a first delayed clock signal with a first tracking wiring having a first tracking length positively correlated with a first depth distance of a word line; and generating a first control signal with reference to the clock signal and the first delayed clock signal.

20. The method of claim 19, further comprising: delaying a clock signal as a second delayed clock signal with a second tracking wiring having a second tracking length positively correlated with a second depth distance of a word line; and generating a second control signal with reference to the first delayed clock signal and the second delayed clock signal.

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