Pattern generation for multi-channel memory arrays

Abstract

This application relates to pattern generation for multi-channel memory arrays. An apparatus can include a memory array and circuitry for testing the memory array. The memory array can include a first set of memory cells coupled with a first channel and a second set of memory cells coupled with a second channel. The circuitry can be coupled with the memory array and can include a pattern generator and an output response analyzer. The pattern generator can be configured to selectively output a single pattern when operating in a single pattern mode or to selectively output multiple patterns when operating in a multiple pattern mode. The output response analyzer is configured to determine whether the memory array includes one or more errors based at least in part on the pattern output by the pattern generator.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 029,718, filed September 23, 2020, entitled “Pattern Generation for Multi-Channel Memory Araby”, which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to pattern generation for multi-channel memory arrays. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, often identified by logic 1 or logic 0. In some instances, a single memory cell can support more than two states and can store any of those states. To access the stored information, a component can read or sense at least one of the stored states in the memory device. To store information, a component can write states into the memory device or program states.

[0005] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, and chalcogenide memory technology. Memory cells can be volatile or non-volatile. For example, non-volatile FeRAM can maintain its stored logic state for a long time even without external power. Volatile DRAM devices, on the other hand, may lose their stored state when disconnected from external power. Summary of the Invention

[0006] Describe an apparatus. The apparatus may include: a memory array including a first set of memory cells and a second set of memory cells, the first set of memory cells being coupled to a first channel and the second set of memory cells being coupled to a second channel; circuitry coupled to the memory array and including: a pattern generator configured to selectively output a single pattern when operating in a single-pattern mode or selectively output multiple patterns when operating in a multi-pattern mode; and an output response analyzer configured to determine, at least in part, whether the memory array contains one or more errors based on the patterns output by the pattern generator.

[0007] Describe a method. The method may include: identifying whether a pattern generator of circuitry coupled to a memory array operates in a single-pattern mode or a multi-pattern mode; dividing a dataset used to test the memory array into a first portion and a second portion, at least in part based on identifying that the pattern generator operates in a multi-pattern mode; transmitting the first portion of the dataset to a first channel of the memory array and the second portion of the dataset to a second channel of the memory array, at least in part based on the division of the dataset; and determining whether the memory array contains one or more errors, at least in part based on transmitting the first portion to the first channel and the second portion to the second channel.

[0008] A non-transitory computer-readable medium is described, storing code including instructions. When executed by a processor of an electronic device, the instructions cause the electronic device to: identify whether a pattern generator of a circuit coupled to a memory array operates in a single-pattern mode or a multi-pattern mode; divide a dataset used to test the memory array into a first portion and a second portion, at least in part based on the identification that the pattern generator operates in a multi-pattern mode; transmit the first portion of the dataset to a first channel of the memory array and the second portion of the dataset to a second channel of the memory array, at least in part based on the division of the dataset; and determine whether the memory array contains one or more errors, at least in part based on the transmission of the first portion to the first channel and the transmission of the second portion to the second channel. Attached Figure Description

[0009] Figure 1 This document describes an example of a system that supports pattern generation for a multi-channel memory array, based on the examples disclosed herein.

[0010] Figure 2 This document describes an example of a memory die that supports the patterning of a multi-channel memory array based on the examples disclosed herein.

[0011] Figure 3 This document describes an example of a system that supports pattern generation for a multi-channel memory array, based on the examples disclosed herein.

[0012] Figure 4This document describes an example of a circuit system that supports pattern generation for a multi-channel memory array, based on the examples disclosed herein.

[0013] Figure 5 This document describes an example of a circuit system that supports pattern generation for a multi-channel memory array, based on the examples disclosed herein.

[0014] Figure 6 This document describes an example of a circuit system that supports pattern generation for a multi-channel memory array, based on the examples disclosed herein.

[0015] Figure 7 A block diagram of a memory device generated from a pattern of a multi-channel memory array based on the examples disclosed herein is shown.

[0016] Figure 8 The flowchart illustrates one or more methods for generating patterns for multi-channel memory arrays based on the examples disclosed herein. Detailed Implementation

[0017] Some memory devices include self-test circuitry systems, such as Memory Built-in Self-Test (MBIST) circuitry, which enable the memory device to perform self-test procedures to identify or repair defects in the memory device. Such self-test circuitry systems may include, for example, a pattern generator configured to generate test vectors and memory addressing sequences for testing the memory array. The self-test circuitry system may be configured to proceed step-by-step through a sequence of instructions: writing test vector values ​​to the memory array, reading values ​​back from the memory array, and determining whether the memory array is faulty (e.g., whether it contains one or more errors) based on whether the value read from the memory array corresponds to the value written to the memory array.

[0018] Some pattern generators are configured to generate a single test pattern. In this case, the self-test circuitry system can execute a single instruction sequence (e.g., a predetermined sequence) using a single set of test vectors and memory addresses generated by the pattern generator. However, in some cases, it may be necessary to use multiple test patterns (e.g., by executing multiple different sets of instructions, or by generating multiple sets of test vectors or memory addresses) to test the memory device to increase the likelihood of detecting memory faults. Furthermore, some memory devices contain a relatively large number of input / output channels, and may require the use of different test patterns on different channels to improve the detection of certain defects or conditions that highlight different flaws. For example, while one channel is executing a first instruction sequence, another channel may be executing another command sequence or performing a refresh operation, thus potentially allowing the self-test circuitry system to detect faults occurring while operations are performed in parallel. Therefore, some self-test circuits may include two (or more) pattern generators to support the generation of multiple different test patterns. In some cases, each pattern generator may include its own circuitry for generating test vectors and memory addresses. This approach unnecessarily increases the area required to implement the self-test circuitry system to support multiple pattern generation.

[0019] As described herein, a memory device may include a pattern generator configured to operate as a single-pattern generator or a multi-pattern generator. That is, the pattern generator may output a single pattern when operating in single-pattern mode and two (or more) patterns when operating in multi-pattern mode. For example, the pattern generator may include a single instruction sequence that can be divided into a first pattern and a second pattern based on a split point or reversal point associated with one of the instructions.

[0020] The self-test circuitry system may include output control that controls which pattern is provided to which channel of the memory device. For example, when the pattern generator operates in single-pattern mode, the output control may deliver a (single) pattern to some or all of the channels of the memory device. When the pattern generator operates in multi-pattern mode, the output control may deliver different patterns to different channels, for example, by delivering a first pattern to a set of first channels (e.g., even-numbered channels) and a second pattern to a set of second channels (e.g., odd-numbered channels). This approach provides multi-pattern generation and channel interleaving capabilities without unduly increasing the area available for the pattern generator and simplifies the output control circuitry system compared to using multiple separate pattern generators for multi-pattern generation.

[0021] Initially in reference Figure 1 and 2 The features of this disclosure are described in the context of the system described. (See references...) Figures 3 to 6The features of this disclosure are described in the context of the systems and circuits described herein. (This is achieved through reference to...) Figures 7 to 8 The device diagrams and flowcharts generated from the described pattern of the multi-channel memory array further illustrate and describe these and other features of this disclosure, and are further described with reference to the device diagrams and flowcharts.

[0022] Figure 1 This document describes an example of a system 100 that supports pattern generation for a multi-channel memory array, based on the examples disclosed herein. System 100 may include a host device 105, a memory device 110, and multiple channels 115 coupling the host device 105 to the memory device 110. System 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0023] System 100 may include portions of an electronic device, such as a computing device, mobile computing device, wireless device, graphics processing device, vehicle, or other system. For example, system 100 may describe a computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, or the like. Memory device 110 may be a component of the system operable to store data from one or more other components of system 100.

[0024] At least a portion of system 100 may be an instance of host device 105. Furthermore, host device 105 may be an instance of a processor or other circuitry within a device that uses memory to perform processes within, for example, a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, system-on-a-chip (SoC), or some other fixed or portable electronic device, and other examples. In some instances, host device 105 may refer to hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 120. In some instances, external memory controller 120 may be referred to as a host or host device 105.

[0025] Memory device 110 may be a separate device or component operable to provide physical memory address / space available for use or reference by system 100. In some instances, memory device 110 may be configured to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: modulation schemes for modulating signals, various pin configurations for transmitting signals, various form factors of the physical packages of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0026] Memory device 110 is operable to store data for components of host device 105. In some instances, memory device 110 may act as a slave device to host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of the following: write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0027] The host device 105 may include an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or one or more other components such as one or more peripheral components or one or more input / output controllers. The components of the host device 105 may be coupled to each other via bus 135.

[0028] Processor 125 is operable to provide control or other functionality to at least a portion of system 100 or at least a portion of host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such instances, processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or SoC, and other instances. In some instances, external memory controller 120 may be implemented by or be part of processor 125.

[0029] BIOS component 130 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more read-only memory (ROM), flash memory, or other non-volatile memory.

[0030] Memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more groups, one or more pattern blocks, one or more segments), wherein each memory cell is operable to store at least one data bit. Memory device 110 comprising two or more memory dies may be referred to as a multi-die memory or multi-die package, or a multi-chip memory or multi-chip package.

[0031] Memory die 160 may be an example of a two-dimensional (2D) memory cell array or an example of a three-dimensional (3D) memory cell array. A 2D memory die 160 may contain a single memory array 170. A 3D memory die 160 may contain two or more memory arrays 170, which may be stacked one on top of the other or positioned adjacent to each other (e.g., relative to a substrate). In some instances, the memory arrays 170 in a 3D memory die 160 may be referred to as a stack, hierarchy, layer, or die. A 3D memory die 160 may contain any number of stacked memory arrays 170 (e.g., two highs, three highs, four highs, five highs, six highs, seven highs, eight highs). In some 3D memory dies 160, different stacks may share at least one common access line, such that some stacks may share one or more word lines, digital lines, or board lines.

[0032] The device memory controller 155 may include circuitry, logic, or components operable to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions enabling the memory device 110 to perform various operations and operable to receive, transmit, or execute commands, data, or control information associated with components of the memory device 110. The device memory controller 155 is operable to communicate with one or more of an external memory controller 120, one or more memory dies 160, or a processor 125. In some instances, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with a local memory controller 165 of the memory die 160.

[0033] A local memory controller 165 (e.g., local to memory die 160) may include circuitry, logic, or components operable to control the operation of memory die 160. In some instances, the local memory controller 165 is operable to communicate with a device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, memory device 110 may not include a device memory controller 155 and a local memory controller 165, or an external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 is operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or processor 125, or combinations thereof. Examples of components that may be included in device memory controller 155 or local memory controller 165 or both may include a receiver for receiving signals (e.g., from external memory controller 120), a transmitter for transmitting signals (e.g., to external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuitry or controllers operable to support the operation of the described device memory controller 155 or local memory controller 165 or both.

[0034] External memory controller 120 is operable to enable the communication of one or more of the information, data, or commands between components of system 100 or host device 105 (e.g., processor 125) and memory device 110. External memory controller 120 can translate or interpret the communications exchanged between components of host device 105 and memory device 110. In some instances, external memory controller 120, or other components of system 100 or host device 105, or the functionality described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or combinations thereof, implemented by processor 125, system 100, or other components of host device 105. Although external memory controller 120 is depicted as external to memory device 110, in some instances, external memory controller 120, or the functionality described herein, may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0035] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 are operable to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. Signal paths may be examples of conductive paths operable to carry signals. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins are operable to act as part of a channel.

[0036] Channel 115 (and associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, signaling may be conveyed via channel 115 using single data rate (SDR) signaling or dual data rate (DDR) signaling. In SDR signaling, one modulation symbol of the signal (e.g., signal level) may be registered for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, both modulation symbols of the signal (e.g., signal levels) may be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0037] In some cases, system 100 may include a self-test circuitry system 175 and a test collar 180. The self-test circuitry system 175 may be configured to perform a self-test procedure on memory device 110 to detect defects, faults, or errors within memory device 110. The test collar 180 may be configured to enable memory device 110 to communicate with the self-test circuitry system 175 during test mode and with host device 105 during normal mode. The test collar 180 may be coupled to channel 115.

[0038] The self-test circuit system 175 can be configured to operate in a single-pattern mode or a multi-pattern mode. The self-test circuit system 175 may include a pattern generator configured to operate as a single-pattern generator or a multi-pattern generator. That is, the pattern generator can output a single pattern when operating in single-pattern mode, and can output two (or more) patterns when operating in multi-pattern mode. For example, the pattern generator may include a single instruction sequence that can be divided into a first pattern and a second pattern based on a split point or reversal point associated with one of the instructions.

[0039] The self-test circuitry 175 may include output control that controls which pattern is provided to which channel of the memory device 110. For example, when the pattern generator operates in single-pattern mode, the output control may deliver a (single) pattern to some or all of the channels of the memory device 110. When the pattern generator operates in multi-pattern mode, the output control may deliver different patterns to different channels, for example, by delivering a first pattern to a set of first channels (e.g., even-numbered channels) and a second pattern to a set of second channels (e.g., odd-numbered channels). This approach provides multi-pattern generation and channel interleaving capabilities without unduly increasing the die area used by the pattern generator and simplifies the output control circuitry compared to using multiple separate pattern generators for multi-pattern generation.

[0040] Figure 2 This document describes an example of a system 200 that supports pattern generation for a multi-channel memory array, based on the examples disclosed herein. System 200 may be an example of high-bandwidth memory (HBM) technology (e.g., HBM, HBM2, HBM3, HBM3x, etc.). System 200 may include a host device 205 coupled to a memory device 210 using a high-density interposer 215 (e.g., a silicon interposer or a glass interposer). The high-density interposer 215 may be positioned on a package substrate 225. In some cases, the package substrate 225 may include a power plane or a ground plane, or both. Host device 205 may be a reference. Figure 1 An example of the described host device 105. Memory device 210 may be referenced. Figure 1 An example of the described memory device 110. The memory device 210 may include one or more memory dies 220. Each memory die 220 may be a reference. Figure 1 An example of the memory die 160 described. In some cases, the memory die 220 may be referred to as a memory array, a memory cell array, or a memory cell stack.

[0041] The high-density interposer 215 may include multiple channels coupling the memory device 210 to the host device 205. These channels may have resistance, and the resistance may affect the amount of power used to transmit data at a given data rate or frequency.

[0042] Memory device 210 may include a plurality of memory dies 220 stacked on top of each other. Each memory die 220 may be a reference. Figure 7 and 8 An example of the described memory device 705. In some cases, channel 240 may include a plurality of TSVs extending between memory dies 220. Each memory die 220 may include a plurality of pins coupling memory cells to channel 240.

[0043] Memory device 210 may include a logic die 230 (or interface layer) positioned between a stack and an interposer layer 215 of memory die 220. The logic die 230 (e.g., an HBM interface, interface, or interface layer) may be coupled to memory die 220 and host device 205. The logic die 230 may include a self-test circuitry system 235. The self-test circuitry system 235 may be configured to perform a self-test procedure on memory device 210 to detect defects, faults, or errors within memory device 210. The self-test circuitry system 235 may be configured to operate in a single-pattern mode or a multi-pattern mode. The self-test circuitry system 235 may include a pattern generator configured to operate as a single-pattern generator or a multi-pattern generator. That is, the pattern generator may output a single pattern when operating in single-pattern mode and two (or more) patterns when operating in multi-pattern mode. The self-test circuitry system 235 may include output controls for various channels 240 that control which pattern is provided to memory device 210. In some cases, logic die 230 may be a die that is different from the die of a memory array containing memory cells.

[0044] Figure 3 This document describes an example of a system 300 that supports pattern generation for multi-channel memory arrays, based on the examples disclosed herein. System 300 may be used as a reference. Figure 1 and 2 Examples of the described system 100 or 200. System 300 includes a self-test circuitry system 305 and a memory device 310. The memory device 310 may be an example of memory device 110 or memory device 210, and may include multiple channels 315 (e.g., channels 315-a, 315-b, 315-c, 315-d) or may be coupled to multiple channels 315 for communicating information with, for example, the self-test circuitry system 305, a host device, or another device. The self-test circuitry system 305 may be a reference. Figure 1 and 2 Examples of the described circuit systems 175 and 235. In some instances, the self-test circuit system 305 may include a sequencer coupled to the controller 325 and the pattern generator 330, and is configured to receive one or more commands from the controller and generate one or more signals to initiate the pattern generator.

[0045] The self-test circuit system 305 can be configured to perform a self-test procedure on the memory device 310 to detect defects, faults, or errors within the memory device 310. For example, the self-test circuit system 305 can be configured to perform one or more verification algorithms to check for errors in the memory device 310, such as the March algorithm, the chessboard algorithm, or another algorithm or a combination thereof. The verification algorithm can be executed, for example by the self-test circuit system 305, to write values ​​to various memory cells in the memory device 310, read values ​​from memory cells, and determine whether the value read from the memory cell matches the value written to the memory cell. Such verification algorithms can be used to detect various faults in one or more memory arrays of the memory device 310, such as fixation faults (where the state of a memory cell is "fixed" at a specific value), transition faults (where a memory cell fails to transition from 0 to 1, or vice versa), and coupling faults (where writing a value to a memory cell affects the values ​​of neighboring memory cells).

[0046] In some instances, system 300 may include a test collar 320 for switching memory device 310 between communicating with self-test circuitry system 305 and communicating with a host device as part of a standard operating mode of memory device 310. For example, the test collar 320 may couple memory device 310 to one or more operating components 345 (e.g., a host device) during normal operation and may couple memory device 310 to self-test circuitry system 305 during a self-test procedure. In some instances, the test collar 320 may be configured to receive signals from an external controller (e.g., from a host device) and may couple memory device 310 to self-test circuitry system 305 or to another device based on said signals. The test collar 320 may be a reference. Figure 1 An example of the test collar 180 described.

[0047] The self-test circuit system 305 can be configured to perform one or more tests on the memory device 310. The self-test circuit system 305 may include a controller 325, a pattern generator 330, an output controller 335, and a response analyzer 340.

[0048] In some instances, controller 325 may be configured to initiate a self-test procedure by providing signals to pattern generator 330. Pattern generator 330 may generate and output one or more patterns in response to receiving signals from controller 325 for use in a verification algorithm for memory device 310. Such patterns may include memory access instructions, test vectors (e.g., a set of logical states to be written to memory device 310), memory address sequences, or combinations thereof for performing the verification algorithm. In some instances, pattern generator 330 may include an address generator for generating memory addresses. In some instances, pattern generator 330 may include counter-based circuitry or a linear feedback shift register for generating test vectors.

[0049] In some cases, the self-test circuit system 305 can use test vectors and memory addresses generated by the pattern generator 330 to execute a sequence of memory access instructions on the memory device 310. In some cases, the pattern generator 330 can be configured to operate in single-pattern mode (where the pattern generator 330 generates a single pattern) or multi-pattern mode (where the pattern generator 330 generates multiple patterns). Using a single pattern generator 330 to generate multiple patterns reduces the area available for the pattern generator and improves the error detection / correction capability of the self-test circuit system 305.

[0050] Output control 335 may include circuitry or logic for routing patterns output by pattern generator 330 to channels 315 of memory device 310. For example, if pattern generator 330 operates in multi-pattern mode and outputs two patterns, output control 335 may transmit the first pattern to a first channel (or set of first channels) of memory device 310, and may transmit the second pattern to a second channel (or set of second channels) of memory device 310. In some instances, output control 335 may support channel interleaving, allowing different patterns to be routed to alternating channels. In some instances, output control 335 may be configured to receive signals from controller 325 and route patterns received from pattern generator 330 based on the signals received from controller 325. In some cases, output control 335 and test loop 320 may be configured to route signals to selected channels. For example, test collar 320 may be configured to couple memory device 310 to self-test circuitry 305 or to another operating component 345 (e.g., host device), and output control 335 may be configured to route different patterns to different channels. In some cases, the circuitry performing the functions of output control 335 and test collar 320 may be implemented by output control 335, test collar 320, or a combination thereof.

[0051] Response analyzer 340 may be coupled to pattern generator 330 and memory device 310. Response analyzer 340 may receive data output from memory device 310 during a self-test procedure (e.g., in response to a read command) and compare the value received from memory device 310 with the expected value indicated by pattern generator 330. Response analyzer 340 may determine whether memory device 310 contains one or more errors based on one or more patterns output by pattern generator. In some cases, response analyzer may determine whether memory array contains one or more errors based on comparison. Response analyzer 340 may output an indication of whether memory device 310 contains one or more errors. In some cases, response analyzer 340 may be referred to as an output response analyzer. In some cases, response analyzer 340 may include one or more comparators or other supporting circuitry. In some cases, the output of response analyzer 340 may enable repair of the memory array based on the presence of one or more errors. For example, redundant lines built into the memory array may be used to replace faulty conductive lines. The response analyzer 340 or the host device can cause this repair to occur based on the output of the response analyzer 340.

[0052] refer to Figures 4 to 6 Additional details are provided regarding the operation and characteristics of the self-test circuit system 305.

[0053] Figure 4 This document describes an example of a circuit system 400 that supports pattern generation for a multi-channel memory array, based on the examples disclosed herein. The circuit system 400 may be an example of a portion of a self-test circuit system 305, a memory device 310, and a test collar 320.

[0054] Circuit system 400 may include a pattern generator 405 coupled to output control 410. Pattern generator 405 may be configured to output one or more patterns to output control 410 during a self-test procedure of the memory device. For example, pattern generator 405 may output a pattern that may include a sequence of instructions 420 for performing a self-test procedure of the memory device (e.g., for executing a Markov algorithm or another verification algorithm). For example, instructions 420 may include instructions 420-a, 420-b, and 420-c. Such instructions 420 may include memory access instructions for writing logic states to a memory array (e.g., memory array 170), reading logic states from a memory array, or performing other operations related to the memory array.

[0055] In some instances, pattern generator 405 may generate one or more test vectors (e.g., logical state sequences, such as 0 and 1) and memory addresses that can be used to perform a self-test procedure. Pattern generator 405 may output one or more patterns containing such test vectors, memory addresses, or both.

[0056] In some instances, pattern generator 405 may output a pattern corresponding to the sequence of instructions 420 executed in ascending order, for example, based on the value of an incrementing counter. For example, instruction 420-a may be associated with counter value 425-a(1), instruction 420-b may be associated with counter value 425-b(L), and instruction 420-c may be associated with counter value 425-c(N).

[0057] In some instances, one or more instructions 420 (or corresponding counter values) may be associated with a storage element 430 (e.g., a register) that may contain split point values. The split point value may be, for example, a value of 0 or 1 stored in storage element 430, and may indicate whether the sequence of instructions 420 should be divided (split) into two shorter instruction sequences to produce two output patterns. Thus, in some instances, the split point value may provide an indication (e.g., based on one or more split points) that the pattern generator 405 is operating in a single-pattern mode where the pattern generator can output a single pattern or in a multi-pattern mode where the pattern generator can output two or more patterns. In some cases, storage element 430 stores a value indicating which test mode (e.g., single-pattern or multi-pattern mode) the self-test circuit system uses for testing, and the split point may be identified based on the mode. In some cases, storage element 430 may store a value indicating the test mode and may store an indicator of the split point's location within the instruction sequence of pattern generator 405. When splitting the pattern, the first number of instructions in the first part of the dataset and the second number of instructions in the second part of the dataset can be identified based on the split points.

[0058] In the example of circuit system 400, instruction 420-b is depicted as associated with storage element 430. In this example, a split point value "0" stored in storage element 430 indicates that no split should occur under instruction 420-b. In this case, pattern generator 405 can output a single pattern to output control 410 via path 445 based on a stepwise sequential progression from instruction 420-a to instruction 420-c (e.g., via logic path 435, which may indicate the direction of instruction execution). For example, pattern generator 405 can increment a counter from 1 to N stepwise via instruction 420, where counter value 1 is associated with the first instruction in the instruction sequence and counter value N is associated with the last instruction in the instruction sequence.

[0059] In some instances, if the split point value "1" is stored in storage element 430, it can indicate that a split should be performed under instruction 420-b to divide the pattern (e.g., the instruction sequence from 420-a to 420-c, possibly along with corresponding test vector values ​​and memory addresses) into a first pattern containing instructions 420-a to 420-b and a second pattern containing instructions following instructions 420-b to 420-c. In this case, pattern generator 405 can output the first pattern (corresponding to instructions 420-a to 420-b) to output control 410 via path 440, and can output the second pattern (e.g., corresponding to instructions following instructions 420-b to 420-c) to output control 410 via path 445. In some instances, pattern generator 405 can output the first and second patterns sequentially or in parallel. For example, if the instruction patterns are stored in a storage device, different instructions from the stored set are output in parallel. In this instance, instructions (or datasets) can be retrieved from memory as part of operation in single-pattern or multi-pattern mode. Alternatively, instructions or datasets retrieved from memory can be divided into first and second parts in multi-pattern mode to generate different patterns for use on different channels. In other instances, if instructions are generated sequentially via a circuit system, a first pattern can be generated first, followed by a second pattern. In this instance, the first pattern can be stored, and the first and second patterns can be implemented in parallel, even if they are not generated in parallel.

[0060] Output control 410 may include selector 450, which may include a first input coupled to path 440 and a second input coupled to path 445. Selector 450 may be coupled to a set of channels (e.g., even-indexed channels or odd-indexed channels) and may be configured to select patterns to be applied to those channels. Selector 450 may be configured to select a first pattern (e.g., from path 445) or a second pattern (e.g., from path 440) based on a control signal received via path 455 at a third input of selector 450. The control signal may be provided by a controller of a self-test circuitry system, such as controller 325. Selector 450 may include an output coupled to path 465 for outputting the selected pattern via path 465. In some instances, selector 450 may output a first pattern (e.g., from path 445) when pattern generator 405 operates in single-pattern mode and may output a second pattern (e.g., from path 440) when pattern generator 405 operates in multi-pattern mode. In some instances, selector 450 may be unavailable when the pattern generator operates in single-pattern mode, in which case selector 450 may not output a pattern. In some instances, selector 450 may be or may contain a multiplexer or other types of switching circuitry.

[0061] Output control 410 may include output logic 460, which may include logic circuitry configured to route one or more patterns (e.g., patterns output by pattern generator 405) to channel 415 of the memory device. Output logic 460 may be coupled to pattern generator 405 via path 445 and to selector 450 via path 465. Output logic 460 may receive a first pattern via path 455 and may receive (the same) first pattern, a second pattern, or no pattern via path 465, depending on whether selector 450 is configured to select the first or second pattern and whether selector 450 is unavailable. In some cases, the signal on path 455 may be based on the value of memory element 430.

[0062] In some instances, when pattern generator 405 operates in single-pattern mode, output logic 460 can output the same single pattern to some or all of channels 470. In some instances, when pattern generator 405 operates in multi-pattern mode, output logic 460 can output a first pattern to some channels 470 and output a second pattern to other channels 470. For example, pattern generator 405 can output a first pattern to odd-numbered channels (e.g., including channel 470-a) and output a second pattern to even-numbered channels (e.g., including channel 470-b). In this way, pattern generator 405 and output control 410 can support multi-pattern channel interleaving for self-test procedures.

[0063] In some instances, output logic 460 may include hardwired circuitry to route patterns received via paths 465 and 445 to a specific channel 470. In some instances, output logic 460 may include circuitry configurable to route patterns to channel 470 based on one or more control signals received from a controller, as referenced. Figure 6 The discussion.

[0064] although Figure 4 The pattern generator 405 is depicted with a single split point, but in other instances, the pattern generator 405 may contain multiple split points associated with multiple different instructions and may be able to generate three or more patterns based on the split points. In this case, each pattern may be output by the pattern generator 405 on a different path similar to path 440, received by output control 410, and routed to one or more channels 470.

[0065] Figure 5This document describes an example of a circuit system 500 that supports pattern generation for a multi-channel memory array, based on the examples disclosed herein. Circuit system 500 may be an example of a portion of a self-test circuit system 305, a memory device 310, and a test collar 320. Circuit system 500 may be similar to circuit system 400 and may include some of the same elements as circuit system 400 (which may retain, for example...). Figure 4 (The same reference numerals are shown), but it supports a reverse-based self-test process, where instructions can be executed in reverse sequence (e.g., using a decrement instruction counter instead of an increment instruction counter).

[0066] The circuit system 500 may include a pattern generator 505 coupled to the output control 410. The pattern generator 505 may be similar to the pattern generator 405, but may use reverse points to generate and output multiple patterns instead of using split points.

[0067] In some instances, one or more instructions 420 (or corresponding counter values) may be associated with a storage element 530 (e.g., a register) that may contain a reverse point value. The reverse point value may be, for example, a value of 0 or 1 stored in storage element 530, and may indicate whether the instruction sequence 420 should be divided into two shorter instruction sequences to produce two output patterns. Therefore, in some instances, the reverse point value may provide an indication (e.g., based on the reverse point) of whether the pattern generator 505 operates in a single-pattern mode where the pattern generator can output a single pattern or in a multi-pattern mode where the pattern generator can output two patterns.

[0068] In some instances, when the reverse point value is set to "0", pattern generator 505 can behave similarly to pattern generator 405 and can output a single pattern corresponding to instructions 1 to N via path 445. That is, the pattern generator can sequentially pass through instructions 1 to N, for example, using an incrementing counter.

[0069] Conversely, when the reverse point value is set to "1", pattern generator 505 can generate and output two patterns: a first pattern corresponding to instructions L to 1 executed in descending order (e.g., via a decrement counter, which could be an instance of the second direction of the incrementing instruction), and a second pattern corresponding to instructions L+1 to N executed in ascending order (e.g., via an increment counter, which could be an instance of the first direction of the incrementing instruction). Pattern generator 505 can output the first pattern to output control 410 via path 540, and can output the second pattern via path 445.

[0070] In some cases, storage element 430 stores a value indicating which test mode (e.g., single-pattern or multi-pattern) the self-test circuit system uses for testing, and the breakpoint can be identified based on the mode. In some cases, storage element 430 may also store the breakpoint used in multi-pattern mode (see reference). Figure 4 (as described) or the reverse point (refer to) Figure 5 The indicator (described). In some cases, the storage element 430 may also store the indicator of the position of the split or reverse point in the instruction sequence of the pattern generator 405.

[0071] although Figure 5 Pattern generator 505 is depicted with a single reverse point, but in other instances, pattern generator 505 may include multiple reverse points associated with different locations within an instruction, multiple split points associated with one or more reverse points and one or more split points within an instruction, or combinations thereof. In this case, each pattern may be output by pattern generator 505 on different paths similar to path 540, received by output control 410, and routed to one or more channels 470.

[0072] Other operations of circuit system 500 may be similar to those described in reference circuit system 400. In some instances, the pattern generator may support both split points and reverse points to implement multi-pattern generation.

[0073] Figure 6 This document describes an example of a circuit system 600 that supports pattern generation for a multi-channel memory array, based on the examples disclosed herein. Circuit system 600 may be used as a reference. Figure 4 and 5 The described example circuit system is 400 or 500.

[0074] Circuit system 600 may include a pattern generator 605 coupled to output control 610. Pattern generator 605 may be a reference. Figure 4 and 5 Examples of pattern generators 405 and 505 are described. Output control 610 may be an example of output control 410 or a replacement for output control 410. Pattern generator 605 may output a first pattern to output control 610 via path 645, and may output a second pattern to output control 610 via path 640. The pattern output by pattern generator 605 may be similar to the referenced pattern. Figure 4 and 5 The described pattern and features.

[0075] Output control 610 may include multiple selectors 650, which may be instances of selector 450. Similar to the operation of selector 450, each selector 650 may be configured to receive one or both of a first pattern and a second pattern, and select whether to output the first pattern or the second pattern to channel 470 via control signal 655 based on control signal 655. In some instances, each channel 470 may be coupled to a corresponding selector 650, such that output control 610 may be able to route either of the two patterns to either of the channels 470 using the corresponding selector 650. That is, output control 610 can provide additional flexibility in channel interleaving relative to a predetermined pattern-to-channel routing of output control, for example, the output control may be configured to always route one pattern to an odd-numbered channel and the other pattern to an even-numbered channel. In output control 610, each channel may be selected among different patterns output by pattern generator 605. (See reference...) Figure 4 and 5 Compared to the described output controls 410 and 510, output control 610 provides additional granularity of control.

[0076] Figure 7 A block diagram 700 illustrates a memory device 705 generated according to a pattern of a multi-channel memory array as disclosed herein. The memory device 705 may be as described in the references... Figures 1 to 6 Examples of aspects of the described memory device. Memory device 705 may include a mode component 710, a partitioning component 715, a driver 720, an error control component 725, a retrieval component 730, a test loop 735, and a repair component 740. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0077] Pattern component 710 can identify whether a pattern generator coupled to a memory array operates in single-pattern or multi-pattern mode. In some instances, pattern component 710 can identify an indicator associated with a dataset, wherein identifying whether the pattern generator operates in single-pattern or multi-pattern mode is based on identifying the indicator. In some instances, pattern component 710 can generate a signal configured to cause a selector to transmit a first portion of the dataset to a second channel or a second portion of the dataset to a second channel based on identifying whether the pattern generator operates in single-pattern or multi-pattern mode, wherein transmitting the first and second portions is based on generating the signal. In some instances, pattern component 710 can identify that the pattern generator operates in single-pattern mode.

[0078] The partitioning component 715 can partition a dataset used to test the memory array into a first portion and a second portion based on identifying that the pattern generator operates in a multi-pattern mode. In some instances, the partitioning component 715 can identify a first number of instructions in the first portion of the dataset and a second number of instructions in the second portion of the dataset based on indicators, wherein partitioning the dataset is based on identifying the first number of instructions and the second number of instructions. In some instances, the partitioning component 715 can identify a first direction of incrementing instructions in the first portion of the dataset and a second direction of incrementing instructions in the second portion of the dataset based on indicators, wherein transferring the first portion and the second portion is based on identifying the first direction and the second direction.

[0079] The driver 720 can transmit a first portion of the dataset to a first channel of the memory array and a second portion of the dataset to a second channel of the memory array based on partitioning the dataset. In some instances, the driver 720 can transmit a second dataset to both the first and second channels of the memory array based on recognizing that the pattern generator is operating in a single-pattern mode.

[0080] Error control component 725 can determine whether the memory array contains one or more errors based on transmitting a first portion to a first channel and a second portion to a second channel. In some instances, error control component 725 can determine whether the memory array contains one or more errors based on transmitting a second dataset to both the first and second channels.

[0081] The retrieval component 730 can retrieve a dataset from memory, wherein the identification of whether the pattern generator operates in single-pattern mode or multi-pattern mode is based on retrieving the dataset from memory.

[0082] The test collar 735 couples the circuitry to the memory array, where identifying whether the pattern generator operates in single-pattern or multi-pattern mode is based on coupling the circuitry to the memory array.

[0083] Repair component 740 can repair the memory array based on determining that the memory array contains one or more errors.

[0084] Figure 8 The flowchart illustrates one or more methods 800 generated from patterns supporting multi-channel memory arrays according to examples disclosed herein. Operation of method 800 may be implemented by a memory device or its components as described herein. For example, operation of method 800 may be performed as described in the references... Figure 7 The described memory device performs the functions described. In some instances, the memory device may execute an instruction set to control the functional elements of the memory device to perform the functions described. Alternatively, the memory device may use dedicated hardware to perform aspects of the functions described.

[0085] At 805, the memory device can identify whether the pattern generator of the circuit coupled to the memory array operates in single-pattern or multi-pattern mode. Operation of 805 can be performed according to the methods described herein. In some instances, it can be achieved by, as referenced... Figure 7 The described mode component performs 805 operations.

[0086] At 810, the memory device can divide the dataset used to test the memory array into a first part and a second part based on identifying that the pattern generator operates in a multi-pattern mode. Operation of 810 can be performed according to the method described herein. In some instances, it can be done as described in the reference... Figure 7 The described aspect of the partitioning component performing 810 operations.

[0087] At point 815, the memory device can transmit a first portion of the dataset to a first channel of the memory array and a second portion of the dataset to a second channel of the memory array based on partitioning the dataset. Operation of point 815 can be performed according to the method described herein. In some instances, aspects of the operation of point 815 can be as described in references... Figure 7 The described driver is used.

[0088] At 820, the memory device can determine whether the memory array contains one or more errors based on transmitting a first portion to a first channel and a second portion to a second channel. Operation of 820 can be performed according to the methods described herein. In some instances, aspects of the operation of 820 can be derived from, as referenced... Figure 7 The described error control component is used.

[0089] In some instances, the device as described herein may perform one or more methods, such as method 800. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following operations: identifying whether a pattern generator coupled to a memory array operates in a single-pattern mode or a multi-pattern mode; dividing a dataset used to test the memory array into a first portion and a second portion based on identifying that the pattern generator operates in a multi-pattern mode; transmitting the first portion of the dataset to a first channel of the memory array and the second portion of the dataset to a second channel of the memory array based on the division of the dataset; and determining whether the memory array contains one or more errors based on transmitting the first portion to the first channel and the second portion to the second channel.

[0090] Some instances of the method 800 and device described herein may further include operations, features, components, or instructions for performing the following: identifying an indicator associated with a dataset, wherein the identification of whether the pattern generator can operate in a single-pattern mode or a multi-pattern mode may be based on the identification indicator.

[0091] Some instances of the method 800 and device described herein may further include operations, features, components, or instructions for performing the following: identifying a first number of instructions in a first part of a dataset and a second number of instructions in a second part of a dataset based on indicators, wherein the division of the dataset may be based on identifying the first number of instructions and the second number of instructions.

[0092] Some instances of the method 800 and device described herein may further include operations, features, components, or instructions for performing the following: a first direction of an instruction to identify a first portion of an incrementing dataset based on an indicator and a second direction of an instruction to increment a second portion of the dataset, wherein transmission of the first and second portions may be based on the identification of the first and second directions.

[0093] Some instances of the method 800 and device described herein may further include operations, features, components, or instructions for performing the following: generating a signal configured such that a selector transmits a first portion of a dataset to a second channel and a second portion of the dataset to the second channel based on whether the pattern generator can operate in a single-pattern mode or the multi-pattern mode, wherein the transmission of the first and second portions may be based on the generation of the signal.

[0094] Some instances of the method 800 and device described herein may further include operations, features, components, or instructions for performing the following: retrieving a dataset from memory, wherein identifying whether the pattern generator can be in a single pattern mode or a multi-pattern mode operation can be based on retrieving the dataset from memory.

[0095] Some instances of the method 800 and apparatus described herein may further include operations, features, components, or instructions for performing the following: identifying that the pattern generator can operate in a single pattern mode; transmitting a second dataset to a first and a second channel of the memory array based on identifying that the pattern generator can operate in a single pattern mode; and determining whether the memory array contains one or more errors based on transmitting the second dataset to the first and a second channel.

[0096] Some examples of the methods 800 and devices described herein may further include operations, features, components, or instructions for performing the following: coupling circuitry to a memory array using a test collar, wherein identifying whether a pattern generator can operate in a single-pattern or multi-pattern mode can be based on coupling the circuitry to the memory array.

[0097] Some instances of the methods 800 and devices described herein may further include operations, features, components, or instructions for repairing a memory array based on determining that the memory array contains one or more errors.

[0098] It should be noted that the methods described herein describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods may be combined.

[0099] Describe an apparatus. The apparatus may include: a memory array comprising a first set of memory cells and a second set of memory cells, the first set of memory cells being coupled to a first channel and the second set of memory cells being coupled to a second channel; and circuitry coupled to the memory array and comprising: a pattern generator configured to selectively output a single pattern when operating in a single-pattern mode or selectively output a set of patterns when operating in a multi-pattern mode; and an output response analyzer configured to determine whether the memory array contains one or more errors based on the patterns output by the pattern generator.

[0100] In some instances, the circuit may further include operations, features, components, or instructions for output control configured to transmit a first pattern from a pattern set to a first channel and a second pattern from a pattern set to a second channel when the pattern generator is operating in a multi-pattern mode, and to transmit a single pattern to both the first and second channels when the pattern generator is operating in a single-pattern mode.

[0101] In some instances, output control may include operations, features, components, or instructions for a selector coupled to a second channel of the memory array and configured to selectively output a first pattern from the pattern generator to the second channel or a second pattern from the pattern generator to the second channel based on whether the pattern generator can operate in single-pattern or multi-pattern mode.

[0102] In some instances, the circuit may further include a controller configured to cause the circuit to perform a test procedure. In some instances, the controller may further be configured to cause the pattern generator to operate in a single-pattern mode or a multi-pattern mode.

[0103] In some instances, the circuit may further include a sequencer configured to receive one or more commands from the controller and generate one or more signals to initiate the pattern generator.

[0104] Some instances of the device may include a test loop configured to selectively couple the memory array to circuitry or to a host device.

[0105] Some instances of the device may include a high-bandwidth memory interface coupled to the memory array and the host device.

[0106] In some instances, the circuit may be located on a first die, which is different from the second die containing the memory array.

[0107] The information and signals described herein can be represented using any of a variety of techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate signals as single signals; however, those skilled in the art will understand that the signals may represent signal buses, where the buses may have various bit widths.

[0108] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" refer to the relationship between components that enables the flow of signals between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that can enable the flow of signals between them at any given time. At any given time, the conductive path between components that are electronically communicating (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, may be used to interrupt the flow of signals between connected components for a period of time.

[0109] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship, in which a signal is currently unable to travel between the components via a conductive path, and in which a signal can travel between the components via the conductive path. When a component, such as a controller, couples other components together, the component initially allows a change in the flow of signals between the other components via conductive paths that were previously not permitted.

[0110] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. If there is an open circuit between components, then those components are isolated from each other. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0111] The devices containing memory arrays discussed herein can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by using doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0112] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority of charge carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of charge carriers are holes), then the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, makes the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0113] The descriptions herein, illustrated with reference to the accompanying drawings, depict exemplary configurations and do not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0114] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components that have the same first reference numeral but are independent of the second reference numeral.

[0115] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0116] The various illustrative blocks and modules described herein can be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0117] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions may also be physically located in various locations, including distributions such that portions of the functions are implemented in different physical locations. Furthermore, as used herein (included in the claims), "or" as used in a list of items (e.g., a list of items beginning with phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of, for example, at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0118] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any medium that facilitates the transfer of a computer program from one location to another. Non-transitory storage media can be any available medium accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code elements in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, wireless, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, wireless, and microwave are included in the definition of media. As used in this article, disks and optical discs include CDs, laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs. Disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0119] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: A memory array comprising a first set of memory cells and a second set of memory cells, wherein the first set of memory cells is coupled to a first channel and the second set of memory cells is coupled to a second channel; as well as A circuit coupled to the memory array and comprising: A pattern generator configured to selectively output a single pattern in response to operation in a single-pattern mode of a test procedure, and to selectively output multiple patterns in response to operation in a multi-pattern mode of the test procedure. Output control, configured to, in response to the pattern generator operating in the multi-pattern mode of the test procedure, transmit a first pattern of the plurality of patterns to the first channel and a second pattern of the plurality of patterns to the second channel in parallel, and, when the pattern generator operates in the single-pattern mode of the test procedure, transmit a single pattern to both the first and second channels; and An output response analyzer is configured to determine, at least in part, whether the memory array contains one or more errors based on the pattern output by the pattern generator.

2. The device of claim 1, wherein the output control includes a selector coupled to the second channel of the memory array and configured to selectively output the first pattern from the pattern generator to the second channel or selectively output the second pattern from the pattern generator to the second channel, at least in part, based on whether the pattern generator is operating in the single-pattern mode or the multi-pattern mode.

3. The device of claim 1, wherein the circuitry further comprises a controller configured to cause the circuitry to perform the test procedure.

4. The device of claim 3, wherein the controller is further configured to cause the pattern generator to operate in the single-pattern mode or the multi-pattern mode.

5. The device according to claim 3, wherein the circuit further comprises: A sequencer configured to receive one or more commands from the controller and generate one or more signals to start the pattern generator.

6. The device according to claim 1, further comprising: A test ring configured to selectively couple the memory array to the circuitry or to a host device.

7. The device according to claim 1, further comprising: A high-bandwidth memory interface coupled to the memory array and the host device.

8. The device of claim 1, wherein the circuitry is located on a first die, which is different from the second die of the memory array comprising memory cells.

9. A method comprising: Identify whether the pattern generator of the circuit coupled to the memory array operates in single-pattern mode or multi-pattern mode. The dataset used to test the memory array is divided into a first part and a second part, at least in part, based on the identification that the pattern generator is operating in the multi-pattern mode; At least in part, based on the partitioning of the dataset, the first portion of the dataset is transmitted in parallel to the first channel of the memory array, and the second portion of the dataset is transmitted to the second channel of the memory array; as well as Whether the memory array contains one or more errors is determined at least in part based on transmitting the first portion of the dataset to the first channel and transmitting the second portion of the dataset to the second channel.

10. The method of claim 9, further comprising: Identifying indicators associated with the dataset, wherein identifying whether the pattern generator operates in the single-pattern mode or the multi-pattern mode is at least in part based on identifying the indicators.

11. The method of claim 10, further comprising: A first number of instructions in the first part of the dataset and a second number of instructions in the second part of the dataset are identified at least in part based on the indicator, wherein the division of the dataset is based at least in part on identifying the first number of instructions and the second number of instructions.

12. The method of claim 10, further comprising: A first direction for an instruction to increment the first portion of the dataset and a second direction for an instruction to increment the second portion of the dataset are identified at least in part based on the indicator, wherein the transmission of the first portion of the dataset and the second portion of the dataset is at least in part based on the identification of the first direction and the second direction.

13. The method of claim 9, further comprising: A signal is generated, the signal being configured such that a selector transmits either the first portion of the dataset to the second channel or the second portion of the dataset to the second channel based at least in part on identifying whether the pattern generator is operating in the single-pattern mode or the multi-pattern mode, wherein the transmission of the first portion and the second portion of the dataset is at least in part based on the generation of the signal.

14. The method of claim 9, further comprising: Retrieving the dataset from memory, wherein identifying whether the pattern generator operates in the single-pattern mode or the multi-pattern mode is at least in part based on retrieving the dataset from the memory.

15. The method of claim 9, further comprising: The pattern generator is identified as operating in the single pattern mode; The second dataset is transmitted to the first and second channels of the memory array, at least in part, based on the identification that the pattern generator is operating in the single pattern mode. as well as Whether the memory array contains the one or more errors is determined at least in part based on transmitting the second dataset to the first channel and the second channel.

16. The method of claim 9, further comprising: The circuit is coupled to the memory array using a test collar, wherein identifying whether the pattern generator operates in the single-pattern mode or the multi-pattern mode is based at least in part on coupling the circuit to the memory array.

17. The method of claim 9, further comprising: The memory array is repaired at least in part based on the determination that the memory array contains one or more of the errors.

18. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to perform the following operations: Identify whether the pattern generator of the circuit coupled to the memory array operates in single-pattern mode or multi-pattern mode. The dataset used to test the memory array is divided into a first part and a second part, at least in part, based on the identification that the pattern generator is operating in the multi-pattern mode; The first portion of the dataset is transmitted in parallel to a first channel of the memory array and the second portion of the dataset is transmitted to a second channel of the memory array, at least in part based on the partitioning of the dataset. as well as Whether the memory array contains one or more errors is determined at least in part based on transmitting the first portion of the dataset to the first channel and transmitting the second portion of the dataset to the second channel.

19. The non-transitory computer-readable medium of claim 18, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to perform the following operations: Identifying indicators associated with the dataset, wherein identifying whether the pattern generator operates in the single-pattern mode or the multi-pattern mode is at least in part based on identifying the indicators.

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