Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the forming method comprising: providing a substrate, a channel structure, a power rail line, a gate structure, a source-drain doped region and an interlayer dielectric layer; forming a conductive via through the interlayer dielectric layer on the part of the power rail line, including a bottom via and a top via on the bottom via; forming a bottom plug in the bottom via and in contact with the power rail line; forming a filling dielectric layer on the bottom plug and filling the top via; etching the interlayer dielectric layer and the filling dielectric layer to form an interconnection groove through the interlayer dielectric layer on top of the source-drain doped region and expose the top via; filling the top via and the interconnection groove to form a top plug in the top via and in contact with the bottom plug and a source-drain interconnection layer in the interconnection groove and in contact with the source-drain doped region, the top plug and the bottom plug forming a conductive plug. The embodiment of the present application is conducive to increasing the process window of forming Via-BPR.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] Logic chips are composed of standard cells. The size of a standard cell depends on the metal pitch, standard cell height, polysilicon pitch, and whether it is single diffused barrier (SDB) or double diffused barrier (DDB). For many years, chip miniaturization has been driven by metal pitch (MP) and polysilicon pitch (PP) scaling, but MP scaling faces challenges from lithography limitations and increasing resistance. Furthermore, polysilicon pitch scaling has slowed due to device limitations. The introduction of Design Process Co-optimization (DTCO) has made compressing the standard cell height the primary scaling option. As cell height gradually decreases, the number of fins per device per cell also decreases, leading to a reduction in drive current.

[0003] The widths of the power rails (Vdd and Vss) in a standard cell are typically weighted into the MP value. Power rails provide power to different components of the chip and are generally supplied by metal layers in the Back End of Line (BEOL) process. However, power rails occupy a significant amount of space.

[0004] To meet the ever-growing demands of logic chip miniaturization, and to optimize power supply capabilities when metal pitch is extremely tight, one approach is to move the power rails down into the Si substrate to form buried power rails (BPR). In a buried power rail structure, the power rails are embedded in the substrate, extending deep into the shallow trench isolation (STI) module, thereby freeing up interconnect wiring resources. Furthermore, they provide lower resistive local current distribution for techniques that increase BEOL resistance during pitch reduction. In addition, buried power rails help reduce the effects of wiring congestion and resistance degradation on the grid-like distribution of VDD, VSS, word lines, and bit lines, improving write margin and read speed.

[0005] In devices with embedded power rail structures, conductive plugs are typically used to connect the embedded power rails to the outside. However, developing conductive plugs (Via-BPR) for electrical connection of embedded power rails currently presents significant challenges. Summary of the Invention

[0006] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby increasing the process window for forming conductive plugs (Via-BPR) for electrically connecting buried power rails.

[0007] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate including a device region and a power track region; wherein discrete channel structures are formed on the substrate of the device region, power track lines are formed in the substrate of the power track region, the extension direction of the power track lines being parallel to the extension direction of the channel structures; a gate structure spanning the channel structures is formed on the substrate; source and drain doped regions are formed in the channel structures on both sides of the gate structure; and an interlayer dielectric layer covering the source and drain doped regions is formed on the substrate and power track lines on the side of the gate structure; and forming conductive vias penetrating the interlayer dielectric layer located on a portion of the power track lines, including a bottom via exposing the power track lines and a top via located on the bottom via. A bottom plug is formed in the bottom via, contacting the power track line, the top surface of the bottom plug being lower than the top surface of the interlayer dielectric layer; a filling dielectric layer is formed on the bottom plug to fill the top via; the interlayer dielectric layer and the filling dielectric layer are etched to form an interconnect trench in the interlayer dielectric layer penetrating the top of the source / drain doped region and to expose the top via, the interconnect trench communicating with the top via along the extension direction of the gate structure; the top via and the interconnect trench are filled to form a top plug located in the top via and in contact with the bottom plug, and a source / drain interconnect layer located in the interconnect trench and in contact with the source / drain doped region, the top plug and the bottom plug constituting a conductive plug.

[0008] Accordingly, embodiments of the present invention also provide a semiconductor structure, comprising: a substrate including a device region and a power rail region; a channel structure disposed on the substrate of the device region; a power rail line located in the substrate of the power rail region, the extension direction of the power rail line being parallel to the extension direction of the channel structure; a gate structure located on the substrate and spanning the channel structure; source / drain doped regions located in the channel structures on both sides of the gate structure; an interlayer dielectric layer located on the substrate on the side of the gate structure and covering the source / drain doped regions; a conductive plug penetrating the interlayer dielectric layer above the power rail line and contacting the power rail line, the conductive plug including a bottom plug and a top plug located on the bottom plug, the top surface of the bottom plug being lower than the top surface of the interlayer dielectric layer; and a source / drain interconnect layer penetrating the interlayer dielectric layer above the source / drain doped regions and contacting the source / drain doped regions, the source / drain interconnect layer contacting the top plug along the extension direction of the gate structure, and the source / drain interconnect layer and the top plug being an integral structure.

[0009] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0010] In the semiconductor structure formation method provided by this invention, conductive vias are first formed, including bottom vias and top vias located on the bottom vias. Then, a bottom plug is formed in the bottom via, with the top surface of the bottom plug lower than the top surface of the interlayer dielectric layer. A filling dielectric layer filling the top via is formed on the bottom plug, thereby providing a flat surface for the photolithography and etching processes of forming interconnect trenches. This helps reduce the process difficulty of forming interconnect trenches and increases the process window for forming interconnect trenches. Furthermore, by forming a bottom plug in the bottom via, with the top surface of the bottom plug lower than the top surface of the interlayer dielectric layer, a filling dielectric layer is formed on the bottom plug. The top surface of the interlayer dielectric layer is etched, thereby enabling the formation of a filling dielectric layer in the top via. In the step of forming the interconnect trench, not only the interlayer dielectric layer located on top of the source / drain doped region is etched, but the filling dielectric layer located on the bottom plug is also etched simultaneously. This helps to reduce etching differences in interconnect trench formation and reduce damage to the source / drain doped region, thereby increasing the process window for interconnect trench formation, improving the uniformity of critical dimensions and cross-sectional morphology of the interconnect trench, further increasing the process window for forming conductive plugs and source / drain interconnect layers, and improving the formation quality of conductive plugs and source / drain interconnect layers, thus enhancing the performance of the semiconductor structure. Attached Figure Description

[0011] Figures 1 to 5 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0012] Figures 6 to 7 This is a schematic diagram of the structure corresponding to each step in another method of forming a semiconductor structure;

[0013] Figures 8 to 24 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0014] As is known from the background art, forming conductive plugs (Via-BPR) for connecting embedded power rails currently presents significant challenges. This paper analyzes the reasons for these challenges in forming conductive plugs (Via-BPR) using a semiconductor structure formation method. Figures 1 to 5 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0015] refer to Figure 1 and Figure 2 , Figure 1 This is a top view. Figure 2 yes Figure 1A cross-sectional view along direction aa shows a substrate (not shown) including a device region 10a and a power track region 10b. A discrete channel structure 1 is formed on the substrate of the device region 10a. A power track line 2 is formed in the substrate of the power track region 10b. The extension direction of the power track line 2 is parallel to the extension direction of the channel structure 1. An isolation layer 3 covering the power track line 2 is formed on the substrate exposed by the channel structure 1. The top surface of the isolation layer 3 is lower than the top surface of the channel structure 1. A gate structure 4 spanning the channel structure 1 is formed on the isolation layer 3. Source and drain doped regions 5 are formed in the channel structure 1 on both sides of the gate structure 4. An interlayer dielectric layer 6 covering the source and drain doped regions 5 is formed on the isolation layer 3 on the side of the gate structure 4.

[0016] refer to Figure 3 An initial top via 7 is formed that penetrates the interlayer dielectric layer 6 above the partial power track line 2 and an interconnect trench 8 that penetrates the source / drain doped region 5. The interconnect trench 8 and the initial top via 7 are connected along the extension direction of the gate structure 4.

[0017] refer to Figure 4 The isolation layer 3 below the initial top via 7 is etched to form a top via 9 that exposes the power track line 2. The step of etching the isolation layer 3 below the initial top via 7 includes: forming a fill layer (not shown) that fills the initial top via 7 and the interconnect trench 8, the fill layer also covering the interlayer dielectric layer 6 and the gate structure 4; etching the fill layer in the initial top via 7 and the isolation layer 3 below the initial top via 7 to form the top via 9; and removing the fill layer.

[0018] refer to Figure 5 Conductive material is filled into the interconnect trench 8 and the top through hole 9 to form a source-drain interconnect layer 81 located in the interconnect trench 8 and a conductive plug 91 located in the top through hole 9.

[0019] In the above method, due to the different densities of interconnect trenches 8 and initial top vias 7 in the dense and sparse areas, the number of interconnect trenches 8 and initial top vias 7 in the sparse areas is less than that in the dense areas. During the filling layer formation step, the filling rate in the sparse areas is greater than that in the dense areas. Therefore, the top surface of the filling layer in the sparse areas is higher than that in the dense areas, resulting in significant differences in the uniformity of the top surface height of the filling layers in different density areas. In the etching steps of the filling layer in the initial top vias 7 and the isolation layer 3 below the initial top vias 7, the required etching thickness of the filling layer in different density areas differs, leading to different etching times and amounts of the isolation layer 3 in different density areas. This, in turn, results in poor consistency in the opening size and cross-sectional morphology of the top vias 9 in different density areas, consequently causing flushing.

[0020] Another method is to form conductive plugs. Figures 6 to 7 This is a schematic diagram of the steps in another method for forming a semiconductor structure. The similarities between this method and the aforementioned method will not be repeated here. The differences between this method and the aforementioned method are as follows:

[0021] refer to Figure 6 After providing a substrate (not shown), a channel structure (not shown), a power track line 11, an isolation layer 12, a gate structure 13, source / drain doped regions 14, and an interlayer dielectric layer 15, a top via 16 is formed that penetrates the top of the power track line 11 and the isolation layer 12.

[0022] refer to Figure 7 Interconnect trenches 17 are formed that penetrate the top of the interlayer dielectric layer 15 of the source / drain doped region 14.

[0023] However, in the above method, in the step of forming the interconnect trench 17 of the interlayer dielectric layer 15 that penetrates the top of the source / drain doped region 14, the top via 16 is exposed to the etching process environment, which easily causes double etching on the sidewalls and bottom of the top via 16. This makes it difficult to control the opening size and depth of the top via 16, resulting in poor cross-sectional morphology and opening size consistency of the top via 16. It also easily causes mis-etching of the power rail line 11 at the bottom of the top via 16, making it quite difficult to form a conductive plug (Via-BPR) for electrical connection of the buried power rail.

[0024] To address the aforementioned technical problems, the semiconductor structure formation method provided in this embodiment of the invention first forms conductive vias, then forms bottom plugs in the bottom vias, with the top surface of the bottom plug being lower than the top surface of the interlayer dielectric layer. A filling dielectric layer filling the top via is formed on the bottom plug, thereby providing a flat surface for the photolithography and etching processes of forming interconnect trenches. This helps reduce the process difficulty of forming interconnect trenches and increases the process window for forming interconnect trenches. Moreover, by making the top surface of the bottom plug lower than the top surface of the interlayer dielectric layer, a filling dielectric layer can be formed in the top via. In the step of forming the interconnect trench, not only the interlayer dielectric layer located on top of the source / drain doped region is etched, but the filling dielectric layer located on the bottom plug can also be etched simultaneously. This helps reduce etching differences in forming interconnect trenches and reduce damage to the source / drain doped regions, thereby increasing the process window for forming interconnect trenches, improving the uniformity of critical dimensions and cross-sectional morphology of interconnect trenches, further increasing the process window for forming conductive plugs and source / drain interconnect layers, and improving the formation quality of conductive plugs and source / drain interconnect layers, thus enhancing the performance of the semiconductor structure.

[0025] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Figures 8 to 24 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0026] refer to Figures 8 to 10 , Figure 8 This is a top view. Figure 9 for Figure 8 Cross-sectional view along the AA direction. Figure 10 for Figure 8 In the cross-sectional view at the BB position, a substrate 100 is provided, including a device region I and a power track region II. Discrete channel structures 110 are formed on the substrate 100 of the device region I. Power track lines 120 are formed in the substrate 100 of the power track region II. The extension direction of the power track lines 120 is parallel to the extension direction of the channel structures 110. A gate structure 140 is formed on the substrate 100 that spans the channel structures 110. Source and drain doped regions 150 are formed in the channel structures 110 on both sides of the gate structure 140. An interlayer dielectric layer 160 covering the source and drain doped regions 150 is formed on the substrate 100 on the side of the gate structure 140.

[0027] Substrate 100 is used to provide a process platform for subsequent processes. As an example, substrate 100 is a silicon substrate. Substrate 100 of device region I is used to form transistors, such as one or both of PMOS and NMOS transistors.

[0028] When the device is in operation, the channel structure 110 is used to provide a conductive channel for the transistor. In this embodiment, there are multiple channel structures 110, which are arranged in parallel and spaced apart.

[0029] As an example, the channel structure 110 is a fin. Accordingly, a fin field-effect transistor (FinFET) is formed on the substrate 100 of the device region I. In this embodiment, the material of the fin is the same as that of the substrate 100, which is silicon. In other embodiments, the channel structure is spaced apart from the substrate, and the channel structure includes one or more spaced-apart channel layers, with a gate structure covering a portion of the top of the channel structure and surrounding the channel layers. Accordingly, a gate-all-around (GAA) transistor or a forksheet transistor can be formed on the substrate of the device region.

[0030] Power rail region II is used to form power rail lines 120. Power rail lines 120 are used to provide power to different components of the chip. In this embodiment, power rail lines 120 are located in the substrate 100 of power rail region II. Power rail lines 120 are buried power rails (BPR), which helps to free up wiring resources for back-end interconnects and reduces the height of standard cells to meet the needs of continuous logic chip miniaturization. In addition, the buried power rails use pitch miniaturization to increase back-end (BEOL) resistance, which also helps to provide a lower resistance local current distribution.

[0031] The power rail line 120 has a long strip structure, and the extension direction of the power rail line 120 is (e.g., Figure 8 The power track 120 (as shown in the x-direction) is parallel to the extension direction of the channel structure 110, and there is a gap between the power track 120 and the channel structure 110. The material of the power track 120 is a conductive material. In this embodiment, the material of the power track 120 is a metallic material, including one or more of Co, W, Ni, and Ru. The low resistivity of the material of the power track 120 is beneficial for improving RC delay and increasing the processing speed of the chip.

[0032] In this embodiment, an insulating layer 125 is also formed between the sidewall of the power track line 120 and the substrate 100. The insulating layer 125 is used to achieve insulation between the power track line 120 and the device region I substrate 100. Therefore, the material of the insulating layer 125 is an insulating material, such as silicon oxide, silicon oxynitride, or silicon nitride.

[0033] An isolation layer 130 covering the power track line 120 is formed on the substrate 100 exposed by the channel structure 110. The top surface of the isolation layer 130 is lower than the top surface of the channel structure 110. The isolation layer 130 is used to isolate adjacent channel structures 110, and also to isolate the substrate 100 from the gate structure 140. In this embodiment, the channel structure 110 is a fin, and the portion of the fin exposed in the isolation layer 130 is used as an active fin, which provides a conductive channel for device operation.

[0034] In this embodiment, the isolation layer 130 is a shallow trench isolation structure (STI), and the material of the isolation layer 130 is an insulating material, such as one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0035] The gate structure 140 serves as the device gate, controlling the opening and closing of the conductive channel during device operation. In this embodiment, the gate structure 140 is a metal gate structure. In this embodiment, the gate structure 140 is located on the isolation layer 130. The extension direction of the gate structure 140 (e.g., Figure 8 (As shown in the y-direction) Perpendicular to the extension direction of the channel structure 110 and the power track line 120.

[0036] In this embodiment, a gate cap layer 145 is also formed on the top of the gate structure 140. In the subsequent step of forming the through interconnect trench, the gate cap layer 145 is used to protect the top of the gate structure 140 to reduce the probability of damage to the gate structure 140 and short circuit between the gate structure 140 and the source-drain interconnect layer.

[0037] The gate cap layer 145 is made of a material that has etching selectivity with the interlayer dielectric layer 160, thereby ensuring that the gate cap layer 145 can protect the gate structure 110. The material of the gate cap layer 145 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the gate cap layer 145 is silicon nitride.

[0038] In this embodiment, sidewalls 170 are also formed on the sidewalls of the gate structure 140 and the gate cap layer 145.

[0039] Sidewall 170 defines the location of the source / drain doped region 150. Sidewall 170 also protects the sidewall of the gate structure 140, which is subsequently formed into the source / drain interconnect layer. Sidewall 170 is located between the source / drain interconnect layer and the gate structure 140, and also isolates the source / drain interconnect layer and the gate structure 140. In this embodiment, the sidewall 170 is made of a low-k dielectric material or an ultra-low-k dielectric material, which helps to reduce the effective capacitance between the source / drain interconnect layer and the gate structure 140. In this embodiment, for ease of illustration and explanation, only... Figure 9The diagram shows the side wall at 170.

[0040] The source / drain doped regions 150 are used to provide a carrier source during device operation. When forming an NMOS device, the source / drain doped regions 150 are doped with N-type ions; when forming a PMOS device, the source / drain doped regions 150 are doped with P-type ions. In this embodiment, the source / drain doped regions 150 are located in the channel structures 110 on both sides of the gate structure 140 and the sidewall 170. In this embodiment, along the extension direction of the gate structure 140, the source / drain doped regions 150 located in the plurality of channel structures 110 are in contact with each other (e.g., ...). Figure 8 and Figure 10 (As shown).

[0041] Interlayer dielectric layer 160 is used to isolate adjacent devices. The material of interlayer dielectric layer 160 is an insulating material. In this embodiment, the material of interlayer dielectric layer 160 is silicon oxide. In this embodiment, interlayer dielectric layer 160 covers the sidewall of sidewall 170 and is located on the isolation layer 130 on the side of gate structure 140.

[0042] refer to Figures 11 to 13 , Figure 11 This is a top view. Figure 12 for Figure 11 Cross-sectional view along the AA direction. Figure 13 for Figure 11 In the cross-sectional view at the BB position, a conductive via 180 is formed through the interlayer dielectric layer 160 located on a portion of the power track 120, including a bottom via 81 exposing the power track 120 and a top via 82 located on the bottom via 81.

[0043] The conductive via 180 provides space for the subsequent formation of a conductive plug. Specifically, the bottom via 81 provides space for the formation of a bottom plug, and the top via 82 provides space for the subsequent formation of a filling dielectric layer. In this embodiment, the conductive via 180 penetrates the interlayer dielectric layer 160 and the insulating layer 130 at the top of a portion of the power track line 120.

[0044] In this embodiment, a conductive via 180 is first formed. The steps of forming the conductive via 180 include photolithography and etching processes. Therefore, in the step of forming the conductive via 180, the photolithography and etching processes are performed on the flat top surface, which helps to increase the process window for forming the conductive via 180, reduce the difficulty of the photolithography and etching processes, and correspondingly improve the controllability of the cross-section of the conductive via 180.

[0045] In this embodiment, along the extension direction of the gate structure 140, the conductive via 180 is located in the interlayer dielectric layer 160 and the isolation layer 130 at the end of the source / drain doped region 150, so that after the interconnect trench is subsequently formed through the interlayer dielectric layer 160 at the top of the source / drain doped region 150, the interconnect trench can be connected to the top via 82 along the extension direction of the gate structure 140.

[0046] In this embodiment, the step of forming the conductive via 180 includes: forming a planarization layer (not shown), an anti-reflection layer (not shown), and a pattern layer (not shown) stacked sequentially from bottom to top on the interlayer dielectric layer 160 and the gate cap layer 145, wherein a pattern opening (not shown) is formed in the pattern layer above a portion of the power track line 120; etching the interlayer dielectric layer 160 and the isolation layer 130 sequentially along the pattern opening to form a conductive via 180 exposing the power track line 120; and removing the planarization layer, the anti-reflection layer, and the pattern layer.

[0047] The planarization layer provides a flat surface for forming the pattern layer, thereby improving the pattern accuracy. In this embodiment, the planarization layer is made of spin-on carbon (SOC). The anti-reflective layer reduces reflection during exposure, thereby improving the transfer accuracy of the pattern. In this embodiment, the anti-reflective layer is made of BARC (bottom anti-reflective coating). The pattern layer serves as a mask for etching the interlayer dielectric layer 160 and the isolation layer 130.

[0048] In this embodiment, the material of the pattern layer is photoresist, and the process for forming the pattern layer is photolithography. In this embodiment, both the planarization layer and the anti-reflection layer are formed on a flat surface. The high consistency of the thickness of the planarization layer and the anti-reflection layer provides a flat surface for forming the pattern layer, thereby improving the accuracy of pattern transfer during the photolithography process, and further improving the pattern accuracy and morphological quality of the pattern opening.

[0049] In this embodiment, an anisotropic dry etching process is used along the pattern opening to sequentially etch the interlayer dielectric layer 160 and the isolation layer 130, which helps to improve the control of the etching profile and the accuracy of pattern transfer. One or both of the ashing process and the wet resist removal process are used to remove the planarization layer, the anti-reflection layer and the pattern layer.

[0050] refer to Figure 14 and Figure 15 , Figure 14 Based on Figure 12 sectional view, Figure 15 Based on Figure 13The cross-sectional view shows a bottom plug 210 formed in the bottom through hole 81, which is in contact with the power track line 120. The top surface of the bottom plug 210 is lower than the top surface of the interlayer dielectric layer 160.

[0051] By forming a bottom plug 210 in the bottom via 81, with the top surface of the bottom plug 210 being lower than the top surface of the interlayer dielectric layer 160, the top via 82 can be exposed, reserving space for the subsequent formation of a filling dielectric layer to fill the top via 82. This provides a flat surface for the subsequent photolithography and etching processes for forming interconnect trenches, which helps to reduce the process difficulty of forming interconnect trenches and increase the process window for forming interconnect trenches. Furthermore, by forming a bottom plug 210 in the bottom via 81, with the top surface of the bottom plug 210 being lower than the top surface of the interlayer dielectric layer 160, a filling dielectric layer can be subsequently formed in the top via 82. Accordingly, in the subsequent step of forming interconnect trenches, not only the interlayer dielectric layer 160 on top of the source / drain doped regions 150 can be etched, but the filling dielectric layer can also be etched simultaneously. This helps to reduce etching differences during interconnect trench formation and reduce damage to the source / drain doped regions 150. Consequently, the process window for forming interconnect trenches is increased, the uniformity of critical dimensions and cross-sectional morphology of interconnect trenches is improved, and the process window for forming conductive plugs and source / drain interconnect layers is increased. This also improves the formation quality of conductive plugs and source / drain interconnect layers, thereby enhancing the performance of the semiconductor structure.

[0052] The bottom plug 210, together with the subsequent top plug, forms a conductive plug, which enables electrical connection between the power rail 120 and external circuitry or other interconnect structures. The bottom plug 210 is made of a conductive material. In this embodiment, the bottom plug 210 is made of a metallic material, including one or more of Co, W, Ni, and Ru. The low resistivity of the bottom plug 210 material is beneficial for improving RC delay and increasing the chip's processing speed.

[0053] The distance between the top surface of the bottom plug 210 and the top surface of the source / drain doped region 150 should not be too large; otherwise, the effect of reducing etching differences during interconnect formation and reducing damage to the source / drain doped region 150 will be insignificant during subsequent interconnect formation. Therefore, in this embodiment, the distance between the top surface of the bottom plug 210 and the top surface of the source / drain doped region 150 is less than or equal to 100 Å during the formation of the bottom plug 210.

[0054] As an example, the top surface of the bottom plug 210 is flush with the top surface of the source / drain doped region 150. Therefore, the good height consistency between the bottom plug 210 and the top surface of the source / drain doped region 150 is beneficial to making the reduction of subsequent etching differences in interconnect formation and etching damage to the source / drain doped region 150 more significant.

[0055] In this embodiment, the step of forming the bottom plug 210 includes: using a selective deposition process to form the bottom plug 210 in the bottom via 81. By using a selective deposition process, the bottom plug 210 can be selectively deposited on the surface of a highly conductive film layer (e.g., a metal layer), while it is difficult to deposit on the surface of a film layer with weak conductivity (e.g., a weakly conductive layer or a dielectric layer). That is, the bottom plug 210 can be selectively formed on the top surface of the power track line 120, while it is difficult to form on the surface of the interlayer dielectric layer 160 or the gate cap layer 145. This allows the bottom plug 210 to be precisely formed on the top surface of the power track line 120, which correspondingly improves the alignment accuracy between the bottom plug 210 and the power track line 120. Moreover, no etching process is required during the formation of the bottom plug 210, simplifying the process steps.

[0056] In this embodiment, the selective deposition process is selective chemical vapor deposition (CVD). CVD offers good selective deposition performance and high process stability.

[0057] In other embodiments, the selective deposition process can also be selective electroless metal deposition (SEMD). Using the SEMD process, conductive materials can be selectively deposited on the surface of a highly conductive layer, exhibiting high deposition selectivity.

[0058] In other embodiments, the step of forming the bottom plug may further include: forming an initial plug filling the conductive via; etching back a portion of the initial plug thickness, with the remaining initial plug in the bottom via serving as the bottom plug. The process for forming the initial plug includes one or more of chemical vapor deposition, physical vapor deposition, and electrochemical plating. The process for etching back a portion of the initial plug thickness includes dry etching.

[0059] refer to Figures 16 to 18 , Figure 16 This is a top view. Figure 17 for Figure 16 Cross-sectional view along the AA direction. Figure 18 for Figure 16 In the cross-sectional view at the BB position, a filling medium layer 190 is formed on the bottom plug 210 to fill the top through hole 82.

[0060] By forming a filling dielectric layer 190 that fills the top via 82, a flat surface can be provided for the subsequent photolithography and etching processes for forming interconnect trenches. This helps to reduce the difficulty of forming interconnect trenches and increase the process window for forming interconnect trenches. Correspondingly, in the subsequent steps of forming interconnect trenches, not only is the interlayer dielectric layer 160 on top of the source / drain doped region 150 etched, but the filling dielectric layer can also be etched at the same time. This helps to reduce etching differences during interconnect trench formation and reduce damage to the source / drain doped region 150. Consequently, the process window for forming interconnect trenches is increased, and the uniformity of the critical dimensions and cross-sectional morphology of interconnect trenches is improved.

[0061] The fill dielectric layer 190 occupies space for the subsequent formation of the top plug. The fill dielectric layer 190 is made of a dielectric material, making the etching properties of the fill dielectric layer 190 and the interlayer dielectric layer 160 similar. This helps reduce etching differences during the subsequent formation of interconnect trenches. Furthermore, since the fill dielectric layer 190 is made of a dielectric material and the bottom plug 210 is made of a metallic material, there is a high etching selectivity between the fill dielectric layer 190 and the bottom plug 210. During the subsequent etching of the interlayer dielectric layer 160 on top of the source / drain doped region 150 and the fill dielectric layer 190 on the bottom plug 210, the etching process can easily stop at the bottom plug 210, which not only reduces the difficulty of the etching process but also helps reduce etching damage to the source / drain doped region 150. Specifically, the material of the fill dielectric layer 190 includes one or more of silicon oxide, silicon oxynitride, silicon nitride, amorphous silicon, silicon carbide, silicon oxycarbonate, and silicon carbonitride. As an example, the material of the filling dielectric layer 190 is the same as that of the interlayer dielectric layer 160, which helps to further improve process compatibility.

[0062] In other embodiments, the material filling the dielectric layer may also be one or more of spin-on carbon (SOC), amorphous carbon, organic dielectric layer (ODL), bottom anti-reflective coating (BARC), silicon anti-reflective coating (Si-ARC), deep UV light absorbing oxide (DUO), dielectric anti-reflective coating (DARC), and advanced patterning film (APF).

[0063] In this embodiment, the step of forming the filling dielectric layer 190 includes: forming a dielectric material layer (not shown) that fills the top via 82, the dielectric material layer also being located on the interlayer dielectric layer 160; using a planarization process, removing the dielectric material layer above the top surface of the interlayer dielectric layer 160, the remaining dielectric material layer located in the top via 82 being used as the filling dielectric layer 190.

[0064] In this embodiment, the process for forming the dielectric material layer includes one or both of atomic layer deposition and flow chemical vapor deposition. The process for forming the dielectric material layer is one with strong gap-filling capability, thereby improving the filling capability and filling quality of the filling dielectric layer 190 in the top via 82.

[0065] In this embodiment, the planarization process includes chemical mechanical planarization (CMP). CMP is a type of global planarization process that helps reduce the difficulty of the planarization process and improves the top surface height consistency between the filling dielectric layer 190 and the interlayer dielectric layer 160. This provides a highly flat surface for subsequent photolithography and etching processes to form interconnect trenches, and consequently improves the accuracy of pattern transfer.

[0066] refer to Figures 19 to 21 , Figure 19 This is a top view. Figure 20 for Figure 19 Sectional view along the AA direction, Figure 21 for Figure 19 In the cross-sectional view at the BB position, the interlayer dielectric layer 160 and the filling dielectric layer 190 are etched to form an interconnect trench 200 through the top of the interlayer dielectric layer 160 of the source and drain doped regions 150 and expose the top via 82. The interconnect trench 200 is connected to the top via 82 along the extension direction of the gate structure 140.

[0067] In this embodiment, since a bottom plug 210 is formed in the bottom via 81 and a filling dielectric layer 190 is formed in the top via 82, the height difference between the bottom plug 210 and the top surface of the source / drain doped region 150 is small. Therefore, not only can the interlayer dielectric layer 160 located on top of the source / drain doped region 150 be etched, but the filling dielectric layer 190 located on the bottom plug 210 can also be etched at the same time. This helps to reduce the etching difference in forming the interconnect trench 200 and reduce the etching damage to the source / drain doped region 150. Correspondingly, the process window for forming the interconnect trench 200 is increased, and the uniformity of the key dimensions and cross-sectional morphology of the interconnect trench 200 is improved.

[0068] In this embodiment, the etching process for the interlayer dielectric layer 160 and the filling dielectric layer 190 includes anisotropic dry etching. Anisotropic dry etching offers high control over the etching profile and etching precision, which is beneficial for improving the accuracy of pattern transfer.

[0069] refer to Figures 22 to 24 , Figure 22 This is a top view. Figure 23 for Figure 22 Cross-sectional view along the AA direction. Figure 24 for Figure 22 In the cross-sectional view at the BB position, the top via 82 and the interconnect trench 200 are filled to form a top plug 220 located in the top via 82 and in contact with the bottom plug 210, and a source / drain interconnect layer 230 located in the interconnect trench 200 and in contact with the source / drain doped region 150. The top plug 220 and the bottom plug 210 are used to form a conductive plug 300.

[0070] As described above, this embodiment increases the process window for forming the interconnect trench 200 and the conductive via 180, improves the uniformity of the critical dimensions and cross-sectional morphology of the interconnect trench 200, thereby increasing the process window for forming the conductive plug 300 and the source-drain interconnect layer 230, and improving the formation quality of the conductive plug 300 and the source-drain interconnect layer 230, thus enhancing the performance of the semiconductor structure. Furthermore, in this embodiment, the depth difference between the top via 82 and the interconnect trench 200 is small, which also helps improve the consistency of filling during the filling process of the top via 82 and the interconnect trench 200.

[0071] The conductive plug 300 contacts the power rail 120, thereby establishing an electrical connection between the power rail 120 and external circuits or other interconnect structures. The source / drain interconnect layer 230 contacts the source / drain doped region 150, thereby establishing an electrical connection between the source / drain doped region 150 and external circuits or other interconnect structures.

[0072] In this embodiment, the top through-hole 82 and the interconnect trench 200 are connected. Therefore, by filling the top through-hole 82 and the interconnect trench 200, the top plug 220 and the source / drain interconnect layer 230 are integrated into a single structure. This not only enables electrical connection between the source / drain doped region 150 and the power rail line 120, but also allows the source / drain doped region 150 to be powered through the power rail line 120 when the device is working. It also helps to improve the contact performance between the conductive plug 250 and the source / drain interconnect layer 260.

[0073] Accordingly, in this embodiment, the top plug 220 and the source / drain interconnect layer 230 are made of the same material. In this embodiment, the materials of the top plug 220 and the source / drain interconnect layer 230 include one or more of W, Co, Ru, and Ni. In this embodiment, the process for forming the top plug 220 and the source / drain interconnect layer 230 includes one or more of chemical vapor deposition, physical vapor deposition, and electrochemical plating.

[0074] Accordingly, the present invention also provides a semiconductor structure. (See reference) Figures 22 to 24 , Figure 22This is a top view. Figure 23 yes Figure 22 Cross-sectional view along the AA direction. Figure 24 yes Figure 22 The cross-sectional view at position BB shows a schematic diagram of an embodiment of the semiconductor structure of the present invention.

[0075] The semiconductor structure includes: a substrate 100, comprising a device region I and a power rail region II; a channel structure 110, discretely disposed on the substrate 100 of the device region I; and a power rail line 120, located in the substrate 100 of the power rail region II, wherein the extension direction of the power rail line 120 is (e.g., Figure 22 (As shown in the x-direction) Parallel to the extension direction of the channel structure 110; Gate structure 140, located on the substrate 100 and spanning the channel structure 110; Source / drain doped regions 150, located in the channel structures 110 on both sides of the gate structure 140; Interlayer dielectric layer 160, located on the substrate 100 on the side of the gate structure 140 and covering the source / drain doped regions 150; Conductive plug 300, penetrating the interlayer dielectric layer 160 above the power track line 120 and in contact with the power track line 120. The conductive plug 300 includes a bottom plug 210 and a top plug 220 located on the bottom plug 210. The top surface of the bottom plug 210 is lower than the top surface of the interlayer dielectric layer 160. The source-drain interconnect layer 230 penetrates the interlayer dielectric layer 160 above the source-drain doped region 150 and is in contact with the source-drain doped region 150. In the extension direction of the source-gate structure 140, the source-drain interconnect layer 230 is in contact with the top plug 220, and the source-drain interconnect layer 230 and the top plug 220 are an integral structure.

[0076] In this embodiment, the conductive plug 300 includes a bottom plug 210 and a top plug 220 located on the bottom plug 210, and the source / drain interconnect layer 230 and the top plug 220 are integrally formed. This is because a conductive via, including a bottom via and a top via located on the bottom via, is formed first, then the bottom plug 210 is formed in the bottom via, and a filling dielectric layer filling the top via is formed on the bottom plug 210. This provides a flat surface for the photolithography and etching processes of forming interconnect trenches, which helps to reduce the process difficulty of forming interconnect trenches, increase the process window for forming interconnect trenches, and improve the process of forming interconnect trenches. In this process, not only is the interlayer dielectric layer 160 located on top of the source / drain doped region 150 etched, but the filling dielectric layer located on the bottom plug 210 is also etched simultaneously. This helps to reduce etching differences in forming interconnect trenches and reduce damage to the source / drain doped region 150, thereby increasing the process window for forming interconnect trenches and improving the uniformity of critical dimensions and cross-sectional morphology of interconnect trenches. The source / drain interconnect layer 230 is formed in the interconnect trench, which further increases the process window for forming the conductive plug 300 and the source / drain interconnect layer 230, and improves the formation quality of the conductive plug 300 and the source / drain interconnect layer 230, thereby enhancing the performance of the semiconductor structure.

[0077] In this embodiment, the substrate 100 is a silicon substrate. The substrate 100 of device region I is used to form transistors, such as one or both of PMOS and NMOS transistors.

[0078] When the device is in operation, the channel structure 110 is used to provide a conductive channel for the transistor. In this embodiment, there are multiple channel structures 110, which are arranged in parallel and spaced apart.

[0079] As an example, the channel structure 110 is a fin. Accordingly, a FinFET is formed on the substrate 100 of the device region I. In this embodiment, the material of the fin is the same as the material of the substrate 100, which is silicon. In other embodiments, the channel structure is spaced apart from the substrate, and the channel structure includes one or more spaced-apart channel layers, with a gate structure covering a portion of the top of the channel structure and surrounding the channel layers. Accordingly, a GAA transistor or a forksheet can be formed on the substrate of the device region.

[0080] Power rail region II is used to form power rail lines 120. Power rail lines 120 are used to provide power to different components of the chip. In this embodiment, power rail lines 120 are located in the substrate 100 of power rail region II. Power rail lines 120 are buried power rails (BPR), which helps to free up wiring resources for back-end interconnects and reduces the height of standard cells to meet the needs of continuous logic chip miniaturization. In addition, the buried power rails use pitch miniaturization to increase back-end (BEOL) resistance, which also helps to provide a lower resistance local current distribution.

[0081] The power track 120 is an elongated structure, extending parallel to the channel structure 110, with a gap between them. The power track 120 is made of a conductive material. In this embodiment, the power track 120 is made of a metallic material, including one or more of Co, W, Ni, and Ru. The low resistivity of the power track 120 material is beneficial for improving RC delay and increasing the chip's processing speed.

[0082] In this embodiment, the semiconductor structure further includes an insulating layer 125 located between the sidewall of the power track line 120 and the substrate 100. The insulating layer 125 is used to isolate the power track line 120 from the device region I substrate 100.

[0083] In this embodiment, the semiconductor structure further includes an isolation layer 130, which is located on the substrate 100 exposed by the channel structure 110 and covers the power track line 120, with the top surface of the isolation layer 130 being lower than the top surface of the channel structure 110.

[0084] The isolation layer 130 is used to isolate adjacent channel structures 110, and also to isolate the substrate 100 from the gate structure 140. In this embodiment, the channel structure 110 is a fin, and the portion of the fin exposed in the isolation layer 130 serves as an effective fin, which provides a conductive channel for device operation. The material of the isolation layer 130 is an insulating material, such as one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0085] The gate structure 140 serves as the device gate, controlling the opening and closing of the conductive channel during device operation. In this embodiment, the gate structure 140 is a metal gate structure. In this embodiment, the gate structure 140 is located on the isolation layer 130. The extension direction of the gate structure 140 (e.g., Figure 22 (As shown in the y-direction) Perpendicular to the extension direction of the channel structure 110 and the power track line 120.

[0086] In this embodiment, the semiconductor structure further includes a gate cap layer 145, located on top of the gate structure 140. During the formation steps of the source-drain interconnect layer 230 and the conductive plug 300, the gate cap layer 145 serves to protect the top of the gate structure 140, thereby reducing the probability of damage to the gate structure 140 and short circuits between the gate structure 140 and the source-drain interconnect layer 230 or the conductive plug 300.

[0087] The gate cap layer 145 is made of a material that has etching selectivity with the interlayer dielectric layer 160. As an example, the material of the gate cap layer 145 is silicon nitride.

[0088] The semiconductor structure also includes: sidewall 170 (e.g. Figure 23 As shown in the diagram, the sidewall 170 is located on the sidewall of the gate structure 140 and the gate cap layer 145. In this embodiment, the material of the sidewall 170 is a low-k dielectric material or an ultra-low-k dielectric material. In this embodiment, for ease of illustration and explanation, only the sidewall 170 is shown. Figure 23 The diagram shows the side wall at 170.

[0089] The source / drain doped regions 150 are used to provide carrier sources during device operation. When forming an NMOS device, the source / drain doped regions 150 are doped with N-type ions; when forming a PMOS device, the source / drain doped regions 150 are doped with P-type ions. In this embodiment, the source / drain doped regions 150 located in the plurality of channel structures 110 are in contact with each other along the extension direction of the gate structure 140.

[0090] Interlayer dielectric layer 160 is used to isolate adjacent devices. In this embodiment, the material of interlayer dielectric layer 160 is silicon oxide. In this embodiment, interlayer dielectric layer 160 covers the sidewall of sidewall 170 and is located on the isolation layer 130 on the side of gate structure 140.

[0091] The conductive plug 300 contacts the power rail 120, thereby establishing an electrical connection between the power rail 120 and external circuits or other interconnection structures. In this embodiment, the conductive plug 300 penetrates the interlayer dielectric layer 160 and the isolation layer 130 at the top of a portion of the power rail 120.

[0092] The top surface of the bottom plug 210 is lower than the top surface of the interlayer dielectric layer 160, thereby exposing the top via and reserving space for forming a filling dielectric layer on the bottom plug 210 to fill the top via. This provides a flat surface for the photolithography and etching processes for forming the source-drain interconnect layer 230, which helps to reduce the process difficulty of forming the source-drain interconnect layer 230 and increase the process window for forming the source-drain interconnect layer 230.

[0093] Furthermore, by forming a bottom plug 210 in the bottom via 81, during the interconnect trench formation step, not only is the interlayer dielectric layer 160 on top of the source / drain doped region 150 etched, but the filling dielectric layer is also etched simultaneously. This helps to reduce etching differences during interconnect trench formation and reduce damage to the source / drain doped region 150, thereby increasing the process window for interconnect trench formation, improving the uniformity of critical dimensions and cross-sectional morphology of the interconnect trench, and further increasing the process window for forming the conductive plug 300 and the source / drain interconnect layer 230, improving the formation quality of the conductive plug 300 and the source / drain interconnect layer 230, and enhancing the performance of the semiconductor structure.

[0094] The bottom plug 210 is made of a conductive material. In this embodiment, the bottom plug 210 is made of a metallic material, including one or more of Co, W, Ni, and Ru. The low resistivity of the bottom plug 210 material is beneficial for improving RC delay and increasing the chip's processing speed.

[0095] The distance between the top surface of the bottom plug 210 and the top surface of the source / drain doped region 150 should not be too large; otherwise, the effect of reducing etching differences during interconnect formation and reducing damage to the source / drain doped region 150 will be insignificant. Therefore, in this embodiment, during the formation of the bottom plug 210, the distance between the top surface of the bottom plug 210 and the top surface of the source / drain doped region 150 is less than or equal to 100 Å.

[0096] As an example, the bottom plug 210 is flush with the top surface of the source / drain doped region 150. Therefore, the good height consistency between the bottom plug 210 and the top surface of the source / drain doped region 150 is beneficial to making the reduction of etching differences in interconnect formation and etching damage to the source / drain doped region 150 more significant.

[0097] The top plug 220 and the source / drain interconnect layer 230 are integrally structured, which not only enables electrical connection between the source / drain doped region 150 and the power rail 120, allowing power to be supplied to the source / drain doped region 150 through the power rail 120 during device operation, but also improves the contact performance between the conductive plug 250 and the source / drain interconnect layer 260. In this embodiment, the top plug 220 and the bottom plug 210 are made of the same material.

[0098] In this embodiment, along the extension direction of the gate structure 140, the conductive plug 300 is located in the interlayer dielectric layer 160 and the isolation layer 130 at the end of the source / drain doped region 150, so that the conductive plug 300 can contact the source / drain interconnect layer 230 along the extension direction of the gate structure 140.

[0099] The source / drain interconnect layer 230 is in contact with the source / drain doped region 150, thereby enabling electrical connection between the source / drain doped region 150 and external circuitry or other interconnect structures. Accordingly, in this embodiment, the top plug 220 and the source / drain interconnect layer 230 are made of the same material. In this embodiment, the materials of the top plug 220 and the source / drain interconnect layer 230 include one or more of W, Co, Ru, and Ni.

[0100] The semiconductor structure can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0101] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises: providing a substrate, including a device region and a power rail region, a discrete channel structure is formed on the substrate of the device region, a power rail line is formed in the substrate of the power rail region, the extending direction of the power rail line is parallel to the extending direction of the channel structure, a gate structure is formed on the substrate across the channel structure, source / drain doped regions are formed in the channel structure on both sides of the gate structure, an interlayer dielectric layer is formed on the substrate and the power rail line on the side of the gate structure covering the source / drain doped regions; forming a conductive via through the interlayer dielectric layer on part of the power rail line, including a bottom via exposing the bottom of the power rail line and a top via on the bottom via; forming a bottom plug in the bottom via in contact with the power rail line, the top surface of the bottom plug is lower than the top surface of the interlayer dielectric layer; forming a filling dielectric layer filling the top via on the bottom plug; etching the interlayer dielectric layer and the filling dielectric layer to form an interconnection groove through the interlayer dielectric layer on the top of the source / drain doped regions and expose the top via, the interconnection groove is in communication with the top via along the extending direction of the gate structure; filling the top via and the interconnection groove to form a top plug in the top via in contact with the bottom plug and a source / drain interconnection layer in the interconnection groove in contact with the source / drain doped regions, the top plug and the bottom plug are used to form a conductive plug.

2. The method of forming a semiconductor structure of claim 1, wherein, The step of forming the bottom plug includes: using a selective deposition process to form the bottom plug in the bottom via; Alternatively, forming an initial plug filling in the conductive via; etching part of the thickness of the initial plug, the remaining initial plug in the bottom via is used as the bottom plug.

3. The method of forming a semiconductor structure of claim 2, wherein, The selective deposition process includes a selective chemical vapor deposition process or a selective electroless metal deposition process.

4. The method of forming a semiconductor structure of claim 2, wherein, The process of forming the initial plug includes one or more of a chemical vapor deposition process, a physical vapor deposition process and an electrochemical plating process.

5. The method of forming a semiconductor structure of claim 2, wherein, The process of etching part of the thickness of the initial plug includes a dry etching process.

6. The method of forming a semiconductor structure of claim 1, wherein, During the process of forming the bottom plug, the distance between the top surface of the bottom plug and the top surface of the source / drain doped regions is less than or equal to 100 Å.

7. The method of forming a semiconductor structure of claim 1, wherein, During the process of forming the bottom plug, the top surface of the bottom plug is flush with the top surface of the source / drain doped regions.

8. The method of forming a semiconductor structure of claim 1, wherein, The step of forming the filling dielectric layer includes: forming a dielectric material layer filling in the top via, the dielectric material layer is also on the interlayer dielectric layer; using a planarization process to remove the dielectric material layer higher than the top surface of the interlayer dielectric layer, the remaining dielectric material layer in the top via is used as the filling dielectric layer.

9. The method of forming a semiconductor structure of claim 1, wherein, The material of the filling dielectric layer includes one or more of silicon oxide, silicon oxynitride, silicon nitride, amorphous silicon, silicon carbide, silicon oxycarbide, silicon oxycarbinitride, spin-on carbon, amorphous carbon, an organic dielectric layer, a bottom anti-reflective coating, a silicon-containing anti-reflective layer, a deep ultraviolet light absorbing oxide layer, a dielectric anti-reflective coating and an advanced photoresist film.

10. The method of forming a semiconductor structure of claim 1, wherein, The material of the filling medium layer is the same as the material of the interlayer medium layer.

11. The method of forming a semiconductor structure of claim 1, wherein The process of etching the interlayer medium layer and the filling medium layer includes an anisotropic dry etching process.

12. The method of forming a semiconductor structure of claim 1, wherein, The process of forming the top plug and the source-drain interconnection layer includes one or more of a chemical vapor deposition process, a physical vapor deposition process, and an electrochemical plating process.

13. The method of forming a semiconductor structure of claim 1, wherein, The channel structure is a fin; or, the channel structure is spaced apart from the substrate, the channel structure includes one or more spaced-apart channel layers, and the gate structure covers part of the top of the channel structure and surrounds the channel layers.

14. The method of forming a semiconductor structure of claim 1, wherein, In the step of providing the substrate, an isolation layer covering the power rail line is further formed on the substrate exposed by the channel structure, a top surface of the isolation layer is lower than a top surface of the channel structure, the gate structure is on the isolation layer, and the interlayer medium layer is on the isolation layer at the side of the gate structure. In the step of forming the conductive via, the conductive via penetrates the interlayer medium layer and the isolation layer on part of the top of the power rail line.

15. A semiconductor structure, characterized by Comprise: a substrate including a device region and a power rail region; a channel structure on the substrate in the device region; a power rail line in the substrate in the power rail region, an extension direction of the power rail line being parallel to an extension direction of the channel structure; a gate structure on the substrate and across the channel structure; source-drain doped regions in the channel structure on both sides of the gate structure; an interlayer medium layer on the substrate at the side of the gate structure and covering the source-drain doped regions; a conductive plug penetrating the interlayer medium layer above the power rail line and contacting the power rail line, the conductive plug including a bottom plug and a top plug on the bottom plug, a top surface of the bottom plug being lower than a top surface of the interlayer medium layer; a source-drain interconnection layer penetrating the interlayer medium layer on the top of the source-drain doped regions and contacting the source-drain doped regions, along the extension direction of the gate structure, the source-drain interconnection layer contacting the top plug, and the source-drain interconnection layer and the top plug being in an integral structure; wherein a filling medium layer is provided between the bottom plug and the top plug, the filling medium layer being etched away before the source-drain interconnection layer is formed.

16. The semiconductor structure of claim 15, wherein, A distance between the top surface of the bottom plug and the top surface of the source-drain doped regions is less than or equal to 100 Å.

17. The semiconductor structure of claim 15, wherein, The top surface of the bottom plug is flush with the top surface of the source-drain doped regions.

18. The semiconductor structure of claim 15, wherein, The material of the bottom plug includes one or more of W, Co, Ru, and Ni.

19. The semiconductor structure of claim 15, wherein, The channel structure is a fin; or, the channel structure is spaced apart from the substrate, the channel structure includes one or more spaced-apart channel layers, and the gate structure covers part of the top of the channel structure and surrounds the channel layers.

20. The semiconductor structure of claim 15, wherein, The semiconductor structure further comprises: an isolation layer on the substrate exposed by the channel structure and covering the power rail line, a top surface of the isolation layer being lower than a top surface of the channel structure; the gate structure is on the isolation layer; the interlayer medium layer is on the isolation layer at the side of the gate structure; The conductive plug penetrates through the interlayer dielectric layer and the isolation layer on top of the power rail line. The conductive plug penetrates through the interlayer dielectric layer and the isolation layer on top of the power rail line.

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