Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the forming method comprising: providing a substrate, a discrete channel structure is formed on the substrate in a device region, a power rail line is formed in the substrate in a power rail region, a gate structure is formed on the substrate across the channel structure, source / drain doped regions are formed in the channel structure on both sides of the gate structure, and an interlayer dielectric layer is formed on the substrate and the power rail line on the side of the gate structure; forming a conductive via penetrating through the interlayer dielectric layer on part of the power rail line to expose the power rail line; filling a protection layer in the conductive via; forming an interconnection groove penetrating through the interlayer dielectric layer on top of the source / drain doped regions, the sidewall of the interconnection groove exposing the protection layer; forming a conductive plug in the conductive via and a source / drain interconnection layer in the interconnection groove, the source / drain interconnection layer being in contact with the sidewall of the conductive plug. The embodiment of the present application is beneficial to increase the process window for forming the conductive via and the interconnection groove.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method of forming the same. BACKGROUND

[0002] Logic chips are composed of standard cells. The size of a standard cell depends on the metal pitch, the standard cell height, the poly pitch, and whether it is a single diffusion break (SDB) or a double diffusion break (DDB). Chip miniaturization has been driven by metal pitch (MP) and poly pitch (PP) scaling for many years, but MP scaling faces challenges of lithography process limits and increased resistance. And poly pitch scaling has slowed down due to device issues. The introduction of design technology co-optimization (DTCO) makes compressing the standard cell height a major scaling option. As the cell height is gradually reduced, the number of fins for each cell of a single device is also gradually reduced, which will also result in a decrease in drive current.

[0003] The width of the power rails (Vdd and Vss) of a standard cell is usually weighted into the value of MP. The power rails provide power for different components of a chip, and are generally provided by metal layers in the back end of line (BEOL) process. However, the power rails occupy a lot of space.

[0004] In order to meet the needs of continuous logic chip miniaturization, in order to optimize the power supply capability when the metal pitch is very tight, one method is to move the power rail downward into the Si substrate to form a buried power rail (BPR).

[0005] In a buried power rail structure, the power rail is buried in the substrate and extends into a shallow trench isolation (STI) module, thereby facilitating the release of interconnection routing resources. Moreover, the buried power rail provides a lower resistance local current distribution for technologies that increase BEOL resistance with pitch miniaturization. In addition, the buried power rail is also beneficial to reduce the impact of grid-like distribution of VDD, VSS, word lines and bit lines on routing congestion and resistance degradation, and to improve write margin and read speed.

[0006] In a device with a buried power rail structure, it is usually also necessary to connect the buried power rail out using a conductive plug. However, there are currently great challenges in forming a conductive plug (Via-BPR) for electrically connecting the buried power rail. SUMMARY

[0007] The embodiment of the present application solves the problem of providing a semiconductor structure and a forming method thereof, which is beneficial to increase the process window of forming a conductive via and an interconnection trench, and correspondingly increase the process window of forming a conductive plug (Via-BPR) for electrically connecting a buried power rail.

[0008] To solve the above problem, the embodiment of the present application provides a forming method of a semiconductor structure, which comprises the following steps: providing a substrate, which comprises a device region and a power rail region; forming discrete channel structures on the substrate of the device region; forming a power rail line in the substrate of the power rail region, the extending direction of the power rail line being parallel to the extending direction of the channel structures; forming a gate structure on the substrate and across the channel structures; forming source / drain doping regions in the channel structures on both sides of the gate structure; forming an interlayer dielectric layer on the substrate on the side of the gate structure and covering the source / drain doping regions; forming a conductive via penetrating through the interlayer dielectric layer on part of the power rail line and exposing the power rail line; filling a protective layer in the conductive via; forming an interconnection trench penetrating through the interlayer dielectric layer on the top of the source / drain doping regions, the sidewall of the interconnection trench exposing the protective layer along the extending direction of the gate structure; forming a conductive plug in the conductive via and in contact with the power rail line, and a source / drain interconnection layer in the interconnection trench and in contact with the source / drain doping regions, the source / drain interconnection layer being in contact with the sidewall of the conductive plug.

[0009] Correspondingly, the embodiment of the present application also provides a semiconductor structure, which comprises: a substrate comprising a device region and a power rail region; channel structures being discrete on the substrate of the device region; a power rail line being in the substrate of the power rail region, the extending direction of the power rail line being parallel to the extending direction of the channel structures; a gate structure being on the substrate and across the channel structures; source / drain doping regions being in the channel structures on both sides of the gate structure; an interlayer dielectric layer being on the substrate on the side of the gate structure and covering the source / drain doping regions; a conductive via penetrating through the interlayer dielectric layer on part of the power rail line and exposing the power rail line; a protective layer being filled in the conductive via; an interconnection trench penetrating through the interlayer dielectric layer on the top of the source / drain doping regions, the sidewall of the interconnection trench exposing the protective layer along the extending direction of the gate structure.

[0010] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0011] The forming method of the semiconductor structure provided by the embodiment of the present application comprises the following steps: forming a conductive via, filling a protective layer in the conductive via, and then forming an interconnection groove. Therefore, in the step of forming the conductive via, the photoetching and etching processes are performed on the flat top surface, which is beneficial to increase the process window of forming the conductive via. By filling the protective layer in the conductive via, a flat surface can be provided for the process of forming the interconnection groove, which is beneficial to reduce the difficulty of the photoetching and etching processes of forming the interconnection groove and increase the process window of forming the interconnection groove. Compared with the scheme of forming the interconnection groove first and then forming the conductive via, the embodiment of the present application is also beneficial to avoid the problem that the height difference of the top surface of the filling layer filled in the interconnection groove is too large in different pattern density areas, which leads to the large difference of the etching rate and etching time of the conductive via. Accordingly, the embodiment of the present application is beneficial to improve the consistency of the opening size and cross-sectional morphology of the conductive via. In addition, the protective layer can also protect the power rail and the conductive via during the process of forming the interconnection groove, which is beneficial to accurately control the opening size and cross-sectional morphology of the conductive via and reduce the probability of damaging the power rail. In summary, the embodiment of the present application is beneficial to increase the process window of forming the conductive via and the interconnection groove, accordingly improve the consistency of the critical dimension and cross-sectional morphology of the conductive via, increase the process window of forming the conductive plug (Via-BPR) for electrically connecting the buried power rail, and further improve the forming quality of the conductive plug and optimize the performance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figures 1-5 is a structure diagram corresponding to each step in a forming method of a semiconductor structure.

[0013] Figures 6-7 is a structure diagram corresponding to each step in another forming method of a semiconductor structure.

[0014] Figures 8-24 is a structure diagram corresponding to each step in a forming method of a semiconductor structure. DETAILED DESCRIPTION

[0015] As known from the background, it is currently a great challenge to form a conductive plug (Via-BPR) for connecting a buried power rail.

[0016] Now, the reasons why it is a great challenge to form the conductive plug (Via-BPR) will be analyzed in combination with a forming method of a semiconductor structure. Figures 1-5 is a structure diagram corresponding to each step in a forming method of a semiconductor structure.

[0017] Reference Figure 1 and Figure 2 , Figure 1 is a top view, Figure 2is Figure 1 A cross-sectional view along the direction of aa, providing a substrate (not shown) including a device region 10a and a power rail region 10b, the substrate of the device region 10a having a discrete channel structure 1 formed thereon, the substrate of the power rail region 10b having a power rail line 2 formed therein, the power rail line 2 extending in parallel with the channel structure 1, the substrate exposed by the channel structure 1 having an isolation layer 3 formed thereon covering the power rail line 2, the top surface of the isolation layer 3 being lower than the top surface of the channel structure 1, the isolation layer 3 having a gate structure 4 formed thereon across the channel structure 1, the channel structure 1 on both sides of the gate structure 4 having a source / drain doped region 5 formed therein, the isolation layer 3 on the side of the gate structure 4 having an interlayer dielectric layer 6 formed thereon covering the source / drain doped region 5.

[0018] Referring to Figure 3 , an initial conductive via 7 through the interlayer dielectric layer 6 above the power rail line 2 and an interconnection trench 8 through above the source / drain doped region 5 are formed, the interconnection trench 8 and the initial conductive via 7 being in communication along the extension direction of the gate structure 4.

[0019] Referring to Figure 4 , the isolation layer 3 below the initial conductive via 7 is etched so that the initial conductive via 7 forms a conductive via 9 exposing the power rail line 2.

[0020] The step of etching the isolation layer 3 below the initial conductive via 7 includes: forming a filling layer (not shown) filling the initial conductive via 7 and the interconnection trench 8, the filling layer also covering the interlayer dielectric layer 6 and the gate structure 4; etching the filling layer in the initial conductive via 7 and the isolation layer 3 below the initial conductive via 7 to form the conductive via 9; and removing the filling layer.

[0021] Referring to Figure 5 , the interconnection trench 8 and the conductive via 9 are filled with a conductive material to form a source / drain interconnection layer 81 in the interconnection trench 8 and a conductive plug 91 in the conductive via 9.

[0022] In the above method, in the step of forming the filling layer, due to the different densities of the interconnection grooves 8 and the initial conductive vias 7 in the dense area and the sparse area, the number of the interconnection grooves 8 and the initial conductive vias 7 in the sparse area is less than that in the dense area, and in the step of forming the filling layer, the filling rate of the filling layer in the sparse area is greater than that in the dense area, so that the top surface of the filling layer in the sparse area is higher than that in the dense area, the height consistency of the top surface of the filling layer in different areas with different densities is poor, in the step of etching the filling layer in the initial conductive vias 7 and the isolation layer 3 below the initial conductive vias 7, the thickness of the filling layer to be etched in different areas with different densities is different, which leads to different etching time and etching amount of the isolation layer 3 in different areas with different densities, and further leads to poor consistency of the opening size and cross-sectional morphology of the conductive via 9 in different areas with different densities, and accordingly leads to poor consistency of the key size and cross-sectional morphology of the conductive plug 91 formed, and the process window of the Via-BPR is small.

[0023] There is another method for forming a conductive plug. Figures 6-7 is another schematic diagram of the structure corresponding to each step in the method of forming a semiconductor structure. The same parts of the method as the previous method will not be described again, and the different parts of the method from the previous method are as follows:

[0024] Referring to Figure 6 After providing a substrate (not shown), a channel structure (not shown), a power rail line 11, an isolation layer 12, a gate structure 13, a source-drain doped region 14, and an interlayer dielectric layer 15, a conductive via 16 is formed through the top of the power rail line 11, the interlayer dielectric layer 15, and the isolation layer 12.

[0025] Referring to Figure 7 After forming the conductive via 16, an interconnection groove 17 is formed through the top of the interlayer dielectric layer 15 of the source-drain doped region 14.

[0026] However, in the above method, in the step of forming the interconnection groove 17 through the top of the interlayer dielectric layer 15 of the source-drain doped region 14, the conductive via 16 is exposed to the etching process environment, which easily causes double etching to the sidewall and bottom of the conductive via 16, thereby making it difficult to control the opening size and depth of the conductive via 16, leading to poor consistency of the cross-sectional morphology and opening size of the conductive via 16, and also easily causing damage to the power rail line 11 at the bottom of the conductive via 16, making it difficult to form the Via-BPR.

[0027] To solve the technical problem, the forming method of the semiconductor structure provided by the embodiment of the present application comprises the following steps: forming a conductive via, filling a protective layer in the conductive via, and then forming an interconnection groove.

[0028] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0029] Figures 8-24 is a structure diagram corresponding to each step in the forming method of the semiconductor structure in an embodiment of the present application.

[0030] Reference Figures 8-10 , Figure 8 is a top view, Figure 9 is Figure 8 is a sectional view along the AA direction, Figure 10 is Figure 8At the cross-sectional view at the BB position, a substrate 100 is provided, including a device region I and a power rail region II, the substrate 100 of the device region I has a discrete channel structure 110 formed thereon, the substrate 100 of the power rail region II has a power rail line 120 formed therein, the power rail line 120 extends in parallel with the channel structure 110, the substrate 100 has a gate structure 140 formed thereon across the channel structure 110, the channel structure 110 on both sides of the gate structure 140 has a source / drain doped region 150 formed therein, and the substrate 100 on the side of the gate structure 140 has an interlayer dielectric layer 160 formed thereon covering the source / drain doped region 150.

[0031] The substrate 100 is used to provide a process platform for subsequent processes.

[0032] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, or other materials, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0033] The substrate 100 of the device region I is used to form a transistor, such as one or both of a PMOS transistor and an NMOS transistor.

[0034] In operation of the device, the channel structure 110 is used to provide a conductive channel of the transistor. In this embodiment, the number of channel structures 110 is multiple, and the multiple channel structures 110 are arranged in parallel and spaced apart.

[0035] As an example, the channel structure 110 is a fin. Accordingly, a fin field effect transistor (FinFET) is formed on the substrate 100 of the device region I. In this embodiment, the material of the fin is the same as the material of the substrate 100, and the material of the fin is silicon. In other embodiments, the material of the fin can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, or other semiconductor materials suitable for forming a fin, and the material of the fin can also be different from the material of the substrate.

[0036] In other embodiments, the channel structure is spaced apart from the substrate, the channel structure includes one or more spaced-apart channel layers, and the gate structure covers part of the top of the channel structure and surrounds the channel layer. Accordingly, a gate-all-around (GAA) transistor or a fork sheet transistor can be formed on the substrate of the device region.

[0037] The power rail region II is used to form a power rail line 120. The power rail line 120 is used to provide power for different components of the chip. In this embodiment, the power rail line 120 is located in the substrate 100 of the power rail region II, and the power rail line 120 is a buried power rail (BPR), which is beneficial to release the wiring resource of the back end of line (BEOL) and reduce the height of the standard cell to meet the needs of continuous logic chip miniaturization. In addition, the buried power rail is beneficial to provide a lower resistance local current distribution by using pitch miniaturization to increase the BEOL resistance.

[0038] The power rail line 120 has a long strip structure, and the extension direction (indicated by the middle x direction) of the power rail line 120 is parallel to the extension direction of the channel structure 110, and there is a gap between the power rail line 120 and the channel structure 110. Figure 8

[0039] The material of the power rail line 120 is a conductive material. In this embodiment, the material of the power rail line 120 is a metal material, including one or more of Co, W, Ni, and Ru. The resistivity of the material of the power rail line 120 is low, which is beneficial to improve the RC delay and improve the processing speed of the chip.

[0040] It should be noted that in this embodiment, an insulating layer 125 is also formed between the sidewall of the power rail line 120 and the substrate 100, and the insulating layer 125 is used to realize the insulation between the power rail line 120 and the device region I substrate 100. Therefore, the material of the insulating layer 125 is an insulating material, such as silicon oxide, silicon oxynitride, or silicon nitride.

[0041] In this embodiment, the exposed substrate 100 of the channel structure 110 also has an isolation layer 130 covering the power rail line 120, and the top surface of the isolation layer 130 is lower than the top surface of the channel structure 110.

[0042] The isolation layer 130 is used to isolate adjacent channel structures 110, and the isolation layer 130 is also used to isolate the substrate 100 and the gate structure 140. In this embodiment, the channel structure 110 is a fin, and the part of the fin exposed to the isolation layer 130 is used as an active fin, which is used to provide a conductive channel during device operation.

[0043] In this embodiment, the isolation layer 130 is a shallow trench isolation structure (STI), and the material of the isolation layer 130 is an insulating material, such as one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0044] ​The gate structure 140 serves as a device gate, and is used to control the opening or closing of the conductive channel during device operation. In this embodiment, the gate structure 140 is a metal gate structure.

[0045] In this embodiment, the gate structure 140 is located on the isolation layer 130. The extension direction of the gate structure 140 (e.g., the y direction in FIG. 1) is perpendicular to the extension direction of the channel structure 110 and the power rail line 120. Figure 8

[0046] In this embodiment, a gate cap layer 145 is further formed on the top of the gate structure 140. When the interconnection slot of the interlayer dielectric layer 160 is formed later, the gate cap layer 145 is used to protect the top of the gate structure 140, thereby reducing the probability of damage to the gate structure 140 and short circuit between the gate structure 140 and the source-drain interconnection layer.

[0047] The gate cap layer 145 is made of a material that has etching selectivity with the interlayer dielectric layer 160, so as to ensure that the gate cap layer 145 can protect the gate structure 110. In this embodiment, the material of the gate cap layer 145 includes one or more of silicon nitride, silicon carbide, silicon carbon nitride, silicon carbon nitrogen oxide, silicon nitrogen oxide, boron nitride, and boron carbon nitride. As an example, the material of the gate cap layer 145 is silicon nitride.

[0048] In this embodiment, a side wall 170 is further formed on the sidewall of the gate structure 140 and the gate cap layer 145.

[0049] The side wall 170 is used to define the formation position of the source-drain doped region 150, and is located on the sidewall of the gate structure 140. In addition, the side wall 170 is used to protect the sidewall of the gate structure 140. Furthermore, when the source-drain interconnection layer is formed later, the side wall 170 is located between the source-drain interconnection layer and the gate structure 140, and is used to isolate the source-drain interconnection layer and the gate structure 140.

[0050] In this embodiment, the material of the side wall 170 is a low-k dielectric material or an ultra-low-k dielectric material, so as to facilitate the reduction of the effective capacitance between the source-drain interconnection layer and the gate structure 140.

[0051] In this embodiment, for the convenience of illustration and description, only the side wall 170 is schematically shown in FIG. 1. Figure 9

[0052] ​​The source / drain doping region 150 is used to provide a carrier source when the device is in operation. When an NMOS device is formed, N-type ions are doped in the source / drain doping region 150; when a PMOS device is formed, P-type ions are doped in the source / drain doping region 150. In this embodiment, the source / drain doping region 150 is located in the channel structure 110 on both sides of the gate structure 140 and the sidewall 170.

[0053] In this embodiment, the source / drain doping region 150 in the plurality of channel structures 110 is in contact along the extension direction of the gate structure 140 (as shown in Figure 8 and Figure 10 ).

[0054] The interlayer dielectric layer 160 is used to isolate adjacent devices. The material of the interlayer dielectric layer 160 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the interlayer dielectric layer 160 is silicon oxide.

[0055] In this embodiment, the interlayer dielectric layer 160 covers the sidewall of the sidewall 170, and the interlayer dielectric layer 160 is located on the isolation layer 130 at the side of the gate structure 140.

[0056] In this embodiment, a contact etch stop layer (CESL) (not shown in the figure) is further formed between the source / drain doping region 150 and the interlayer dielectric layer 160, and between the isolation layer 130 and the interlayer dielectric layer 160. In the subsequent step of forming an interconnection slot, the contact etch stop layer is used to temporarily define the stop position of etching, thereby improving the consistency of etching and reducing the probability of damage to the source / drain doping region 150. In this embodiment, the material of the contact etch stop layer is silicon nitride.

[0057] Reference is made to Figures 11-13 , Figure 11 is a top view, Figure 12 is Figure 11 is a sectional view along the AA direction, Figure 13 is Figure 11 is a sectional view at the BB position, a conductive via 180 is formed through the interlayer dielectric layer 160 on part of the power rail line 120, exposing the power rail line 120.

[0058] The conductive via 180 provides a spatial position for the subsequent formation of a conductive plug in contact with the power rail line 120. In this embodiment, the conductive via 180 penetrates the interlayer dielectric layer 160 and the isolation layer 130 on part of the top of the power rail line 120.

[0059] The conductive via 180 is formed first in the embodiment. The step of forming the conductive via 180 includes a process of performing a photoetching process and an etching process. Therefore, in the step of forming the conductive via 180, the photoetching and etching processes are performed on the flat top surface, which is advantageous to increase the process window of forming the conductive via 180 and reduce the difficulty of the photoetching and etching processes, and correspondingly, is advantageous to improve the profile control of the conductive via 180.

[0060] In the embodiment, the conductive via 180 is located in the interlayer dielectric layer 160 and the isolation layer 130 at the end of the source-drain doped region 150 along the extension direction of the gate structure 140, so that after the interconnection groove is formed through the top of the source-drain doped region 150 and the interlayer dielectric layer 160, the interconnection groove can be connected with the conductive via 180 along the extension direction of the gate structure 140.

[0061] In the embodiment, the step of forming the conductive via 180 includes: forming, on the interlayer dielectric layer 160 and the gate cap layer 145, a flat layer (not shown in the figure), an anti-reflection layer (not shown in the figure), and a pattern layer (not shown in the figure) stacked in sequence from bottom to top, the pattern layer being provided with a pattern opening (not shown in the figure) located above part of the power rail line 120; etching the interlayer dielectric layer 160 and the isolation layer 130 in sequence along the pattern opening to form the conductive via 180 exposing the power rail line 120; and removing the flat layer, the anti-reflection layer, and the pattern layer.

[0062] The flat layer is used to provide a flat surface for forming the pattern layer, thereby improving the pattern accuracy of the pattern layer. In the embodiment, the material of the flat layer is spin-on carbon (SOC).

[0063] The anti-reflection layer is used to reduce the reflection effect during exposure, thereby improving the transfer accuracy of the pattern. In the embodiment, the material of the anti-reflection layer is a BARC (Bottom Anti-reflective coating) material.

[0064] The pattern layer is used as a mask for etching the interlayer dielectric layer 160 and the isolation layer 130.

[0065] In the embodiment, the material of the pattern layer is photoresist, and the process of forming the pattern layer is a photoetching process. In the embodiment, the flat layer and the anti-reflection layer are both formed on a flat surface. Therefore, the thickness consistency of the flat layer and the thickness consistency of the anti-reflection layer are high, which correspondingly provides a flat surface for forming the pattern layer, thereby being advantageous to improve the pattern transfer accuracy in the photoetching process, and further improving the pattern accuracy and topography quality of the pattern opening.

[0066] In this embodiment, an anisotropic dry etching process is used to sequentially etch the interlayer dielectric layer 160 and the isolation layer 130 along the pattern opening, which helps to improve the control of the etching profile and the accuracy of pattern transfer. The process for removing the planarization layer, anti-reflection layer and pattern layer includes one or both of ashing and wet resist removal processes.

[0067] In this embodiment, subsequent steps further include: filling the conductive via 180 with a protective layer, and removing the protective layer after forming the interconnect trench and before forming the conductive plug and source / drain interconnect layer. (Refer to reference...) Figure 14 and Figure 15 , Figure 14 Based on Figure 12 sectional view, Figure 15 Based on Figure 13 The cross-sectional view shows that after forming the conductive via 180 and before forming the protective layer, the method for forming the semiconductor structure further includes forming a pad layer 210 at the bottom and sidewalls of the conductive via 180.

[0068] After the protective layer is filled into the conductive via 180, the pad layer 210 is located between the bottom of the protective layer and the power track line 120. In the subsequent step of removing the protective layer, the pad layer 210 can define the etching stop position, which helps to improve the etching consistency, prevent damage to the power track line 120, and enable precise control of the opening size and cross-sectional morphology of the conductive via 180. It also helps to reduce the difficulty of subsequent removal of the protective layer.

[0069] In this embodiment, the pad layer 210 is also formed on the interlayer dielectric layer 160 and the gate cap layer 145.

[0070] In this embodiment, the pad layer 210 is made of a dielectric material, and its material differs from that of the power track line 120. During the subsequent removal of the pad layer 210 located at the bottom of the conductive via 180, a higher etching selectivity ratio is achieved for the power track line 120. This helps ensure the protective effect of the pad layer 210 on the power track line 120, thereby preventing damage to the power track line 120 and reducing the difficulty of removing the pad layer 210 located at the bottom of the conductive via 180. Furthermore, in this embodiment, the subsequent protective layer is made of a metallic material, while the pad layer 210 is made of a dielectric material. This ensures a high etching selectivity ratio between the pad layer 210 and the protective layer during the subsequent removal process, thus ensuring that the pad layer 210 can define the etching stop position.

[0071] The material of the padding layer 210 includes one or more of silicon nitride, silicon oxide, and silicon oxynitride. As an example, the material of the padding layer 210 is silicon nitride.

[0072] The thickness of the pad layer 210 should not be too small, otherwise the effect of the pad layer 210 for defining the etching stop position and the protection effect on the power rail line 120 will be reduced; the thickness of the pad layer 210 should not be too large, otherwise the remaining space and the remaining opening size of the conductive via 180 will be too small, which will increase the difficulty of filling the protective layer in the conductive via 180. Therefore, in the embodiment, the thickness of the pad layer is 2 nm to 5 nm.

[0073] In the embodiment, the process for forming the pad layer 210 includes an atomic layer deposition process. Atomic layer deposition has high step coverage, so that the pad layer 210 is easily formed at the bottom and the sidewall of the conductive via 180, and the thickness uniformity and the density of the pad layer 210 are improved.

[0074] Reference is made to Figure 16 and Figure 17 , Figure 16 is based on Figure 14 the cross-sectional view, Figure 17 is based on Figure 15 the cross-sectional view, and the protective layer 200 is filled in the conductive via 180.

[0075] By filling the protective layer 200 in the conductive via 180, a flat surface is provided for the subsequent process of forming the interconnection groove, which is beneficial to reduce the difficulty of the photolithography and etching process for forming the interconnection groove, and to increase the process window for forming the interconnection groove. Moreover, the protective layer 200 can also protect the power rail line 120 and the conductive via 180 during the process of forming the interconnection groove, so as to facilitate the accurate control of the opening size and the cross-sectional profile of the conductive via 180, and to reduce the probability of damage to the power rail line 120.

[0076] In the embodiment, the protective layer 200 is also used to occupy a space position for the subsequent formation of a conductive plug.

[0077] In the embodiment, the top surface of the protective layer 200 is flush with the top surface of the interlayer dielectric layer 160 and the gate cap layer 145. In the embodiment, the protective layer 200 is formed on the pad layer 210.

[0078] In the embodiment, the material of the protection layer 200 includes a metal material. After the protection layer 200 is formed, the top surface of the semiconductor structure exposed by the protection layer 200 includes the top surface of the interlayer dielectric layer 160, the top surface of the gate cap layer 145, and the top surface of the sidewall 170, the material of the interlayer dielectric layer 160, the gate cap layer 145, and the sidewall 170 is a non-metal material, specifically, the material of the interlayer dielectric layer 160, the gate cap layer 145, and the sidewall 170 is a dielectric material, and a high etching selectivity can be easily achieved between the non-metal material and the metal material. Therefore, by making the material of the protection layer 200 include the metal material, the protection layer 200 is not easily etched by mistake in the subsequent process of forming the interconnection groove. Moreover, the protection layer 200 is removed in the subsequent process, and the other film layer structures (for example, the interlayer dielectric layer 160, the gate cap layer 145, and the sidewall 170) are not easily etched by mistake in the process of removing the protection layer 200, which not only helps to improve the protection of the conductive via 180 and the power rail line 120 by the protection layer 200, but also helps to reduce the process difficulty of removing the protection layer 200 in the subsequent process. In addition, the metal material has a certain mechanical strength, and a flat and smooth surface can be easily formed by a planarization process, which helps to improve the top surface height consistency of the protection layer 200 with the interlayer dielectric layer 160 and the gate cap layer 145, so as to provide a flat surface for forming the interconnection groove.

[0079] Specifically, the material of the protection layer 200 includes one or more of W, Co, Ru, Ti, TiN, Ta, TaN, and Ni. As an example, the material of the protection layer 200 is W.

[0080] In other embodiments, in the step of forming the protection layer, the material of the protection layer is a conductive material, and the protection layer is in contact with the power rail line; and the step of forming the conductive plug includes using the protection layer in the conductive via as the conductive plug. In this embodiment, in order to reduce the resistance of the conductive plug to reduce the RC delay, the material of the protection layer is a material with low resistivity, including one or more of W, Co, Ru, and Ni.

[0081] In the embodiment, the step of forming the protection layer 200 includes forming a protection material layer (not shown in the figure) in the conductive via 180, and the protection material layer also covers the interlayer dielectric layer 160; and a planarization process is used to remove the protection material layer higher than the top surface of the interlayer dielectric layer 160, and the remaining protection material layer in the conductive via 180 is used as the protection layer 200.

[0082] The process of forming the protection material layer includes one or more of physical vapor deposition, chemical vapor deposition, and electrochemical plating. In the embodiment, the chemical vapor deposition process is used to form the protection material layer.

[0083] In the embodiment, the protective material layer is formed on the liner layer 210, and in the step of removing the protective material layer above the top surface of the interlayer dielectric layer 160, the liner layer 210 above the top surface of the interlayer dielectric layer 160 is also removed, so as to expose the top surface of the interlayer dielectric layer 160, to facilitate subsequent etching of the interlayer dielectric layer 160 to form the interconnection groove exposing the source / drain doped region 150, and in the same step, the protective material layer and the liner layer 210 above the top surface of the interlayer dielectric layer 160 are removed, which is also conducive to improving the process integration.

[0084] In the embodiment, the planarization process includes a chemical mechanical planarization process. The chemical mechanical planarization process is a global planarization process, which is conducive to reducing the difficulty of removing the protective material layer above the top surface of the interlayer dielectric layer 160, and improving the top surface height consistency of the planarized protective material layer and the interlayer dielectric layer 160 and the gate cap layer 145, so as to provide a high flatness surface for subsequent formation of the interconnection groove.

[0085] Reference Figures 18-20 , Figure 18 is a top view, Figure 19 is Figure 18 is a sectional view along the AA direction, Figure 20 is Figure 18 is a sectional view at the BB position, the interconnection groove 220 penetrating the interlayer dielectric layer 160 on the top of the source / drain doped region 150 is formed, and the sidewall of the interconnection groove 220 exposes the protective layer 200 along the extension direction of the gate structure 140. The interconnection groove 220 is used to provide a spatial position for forming a source / drain interconnection layer.

[0086] As known from the foregoing, in the embodiment, the protective layer 200 is filled in the conductive via 180, so as to provide a flat surface for the process of forming the interconnection groove 220, which is conducive to reducing the difficulty of photolithography and etching process for forming the interconnection groove 220, increasing the process window for forming the interconnection groove 220, and correspondingly improving the profile uniformity and opening size uniformity of the interconnection groove 220. Moreover, compared with the scheme of forming the interconnection groove first and then forming the conductive via, the embodiment is also conducive to avoiding the problem that the top surface height difference of the filling layer filled in the interconnection groove in different pattern density areas is too large, which leads to a large difference in etching rate and etching time of the conductive via, and correspondingly is conducive to improving the opening size and profile uniformity of the conductive via 180.

[0087] Along the extending direction of the gate structure 140, the sidewall of the interconnection groove 220 exposes the protection layer 200, so that after the protection layer 200 is removed and the source-drain interconnection layer in the interconnection groove 220 and the conductive plug in the conductive via 180 are formed, the source-drain interconnection layer can be in contact with the sidewall of the conductive plug, thereby realizing electrical connection between the source-drain interconnection layer and the conductive plug.

[0088] In the embodiment, the interconnection groove 220 also penetrates the part of the liner layer 210 on the sidewall of the protection layer 200, thereby exposing part of the sidewall of the protection layer 200.

[0089] In the embodiment, the step of forming the interconnection groove 220 includes: forming a metal hard mask layer 230 (as shown in FIG. 6) on the interlayer dielectric layer 160, wherein the metal hard mask layer 230 has a mask opening 240 (as shown in FIG. 6) formed above the source-drain doped region 150; and etching the interlayer dielectric layer 160 below the mask opening 240 with the metal hard mask layer 230 as a mask. Figure 20 Figure 20

[0090] The metal hard mask layer 230 is used as a mask for etching the interlayer dielectric layer 160. In the embodiment, the material of the metal hard mask layer 230 is TiN.

[0091] In the embodiment, the step of forming the metal hard mask layer 230 includes: forming a hard mask material layer (not shown in the figure) on the interlayer dielectric layer 160, the gate cap layer 145, and the protection layer 200; forming an organic mask layer on the hard mask material layer; and patterning the hard mask material layer with the organic mask layer as a mask.

[0092] In the embodiment, the hard mask material layer is formed on a flat surface, so that the process window for patterning the hard mask material layer to form the metal hard mask layer 230 is large, which is beneficial to improving the accuracy of pattern transfer and the consistency of the opening size and profile of the mask opening 240.

[0093] In the embodiment, the interlayer dielectric layer 160 below the mask opening 240 is etched with the metal hard mask layer 230 as a mask and by using an anisotropic dry etching process.

[0094] The method for forming the semiconductor structure further includes: removing the metal hard mask layer 230.

[0095] In combination with reference to Figure 21 and Figure 22 , Figure 21 is a sectional view based on Figure 19 , Figure 22 is a sectional view based on Figure 20 ​​In the embodiment, the method further includes removing the protection layer 200 to expose the conductive via 180, so as to prepare for forming the conductive plug which contacts the power track 120.

[0096] In the embodiment, the protection layer 200 is exposed to the etching environment for forming the interconnection groove 220, and the surface smoothness and interface quality of the protection layer 200 are relatively low. In order to improve the forming quality of the conductive plug and the contact performance between the conductive plug and the source-drain interconnection layer, the protection layer 200 is removed.

[0097] In the embodiment, the conductive via 180 is exposed in the step of removing the protection layer 200, and the conductive via 180 is in communication with the interconnection groove 220.

[0098] In the embodiment, the method further includes removing the metal hard mask layer 230 in the step of removing the protection layer 200.

[0099] By removing the metal hard mask layer 230 and the protection layer 200 in the same step, the process of removing the protection layer 200 is compatible with the existing process, which is beneficial to improve the process integration and simplify the process flow.

[0100] In the embodiment, the process of removing the protection layer 200 and the metal hard mask layer 230 includes a wet etching process, and the etching solution of the wet etching process includes a mixed solution of concentrated sulfuric acid and hydrogen peroxide (SPM).

[0101] The SPM solution has extremely high corrosiveness to metal and metal-containing compound materials, so that the protection layer 200 and the metal hard mask layer 230 can be removed, and the etching selectivity of the SPM solution to other film layers (for example, the interlayer dielectric layer 160, the liner layer 210, and the source-drain doped region 150) is relatively high.

[0102] It should be noted that, in the embodiment, the solution temperature of the concentrated sulfuric acid is 50-200°C, so as to ensure a relatively high etching rate of the protection layer 200 and the metal hard mask layer 230, and prevent damage to the device caused by excessively high temperature.

[0103] In the embodiment, after the protection layer 200 is removed, the liner layer 210 of the bottom and sidewall of the conductive via 180 is exposed. Therefore, in combination with the cross-sectional view of Figure 23 and Figure 24 , Figure 23 is based on Figure 21 the cross-sectional view, Figure 24 is based on Figure 22Figure 2 is a cross-sectional view of the semiconductor structure after removing the protective layer 200, and the method for forming the semiconductor structure further includes removing the liner layer 210 at the bottom of the conductive via 180 to expose the top surface of the power rail line 120 so that a subsequent conductive plug can contact the power rail line 120.

[0104] In this embodiment, the process for removing the liner layer 210 at the bottom of the conductive via 180 includes an anisotropic etching process. By using the anisotropic etching process, the liner layer 210 at the bottom of the conductive via 180 can be etched and removed, and correspondingly, the liner layer 210 at the sidewall of the conductive via 180 is retained. Since the material of the liner layer 210 is a dielectric material, the performance of the semiconductor structure is not affected.

[0105] Specifically, the anisotropic etching process includes a blanket dry etch process. The blanket dry etch process does not need to use a mask, which is advantageous for saving cost and reducing process complexity.

[0106] In other embodiments, the process for removing the liner layer at the bottom of the conductive via includes a wet etching process. The wet etching process has the characteristic of isotropic etching, and can remove the liner layer at the bottom and sidewall of the conductive via. Since the thickness of the liner layer is small, the difficulty of removing the liner layer is small, and the time required for removing the liner layer is short.

[0107] Specifically, in the semiconductor field, before forming a conductive plug and a source / drain interconnection layer, the bottom and sidewall of the conductive via and the interconnection trench are usually pre-cleaned to remove impurities on the surface of the conductive via and the interconnection trench, and to provide a good surface state for forming the conductive plug and the source / drain interconnection layer. In the process of pre-cleaning, the liner layer can be removed, which is advantageous for improving process integration and process compatibility.

[0108] Continuing to refer to Figure 23 and Figure 24 , a conductive plug 250 is formed in the conductive via 180 and contacts the power rail line 120, and a source / drain interconnection layer 260 is formed in the interconnection trench 220 and contacts the source / drain doped region 150. The source / drain interconnection layer 160 contacts the sidewall of the conductive plug 250.

[0109] As known from the foregoing, the process window for forming the conductive via 180 and the interconnection groove 220 is large, the profile and opening size consistency of the conductive via 180 is high, and accordingly, the profile and size consistency of the conductive plug 250 is improved, the profile and opening size consistency of the interconnection groove 220 is high, and the profile and size consistency of the source-drain interconnection layer 260 is also improved. In summary, the embodiment is beneficial to improve the performance of the semiconductor structure.

[0110] The conductive plug 250 is in contact with the power rail line 120, so that the power rail line 120 is electrically connected with an external circuit or other interconnection structure. The source-drain interconnection layer 260 is in contact with the source-drain doped region 150, so that the source-drain doped region 150 is electrically connected with an external circuit or other interconnection structure.

[0111] In the embodiment, the source-drain interconnection layer 160 is in contact with the sidewall of the conductive plug 250, so that the source-drain doped region 150 is electrically connected with the power rail line 120, and in turn, the source-drain doped region 150 can be powered by the power rail line 120 during device operation.

[0112] In the embodiment, the source-drain interconnection layer 160 and the power rail line 120 are made of the same material, including one or more of Co, W, Ni and Ru.

[0113] In the embodiment, the step of forming the conductive plug 250 and the source-drain interconnection layer 260 includes: filling the conductive material into the conductive via 180 and the interconnection groove 220 in the same step, to form the conductive plug 250 in the conductive via 180 and the source-drain interconnection layer 260 in the interconnection groove 220.

[0114] By forming the conductive plug 250 and the source-drain interconnection layer 260 in the same step, the process integration is improved, the process is simplified, and the conductive plug 250 and the source-drain interconnection layer 260 are integrated, so that the contact performance between the conductive plug 250 and the source-drain interconnection layer 260 is improved.

[0115] In other embodiments, according to actual process requirements, the conductive plug and the source-drain interconnection layer can also be formed in different steps.

[0116] In some other embodiments, according to actual process, when the protective layer is in contact with the power rail line and the protective layer is made of a material with low resistivity, the protective layer can also be removed. Accordingly, the step of forming the conductive plug includes: using the protective layer in the conductive via as the conductive plug.

[0117] Correspondingly, the application also provides a semiconductor structure. Referring to Figures 18-20 ,Figure 18 is a top view, Figure 19 is Figure 18 is a sectional view along AA direction, Figure 20 is Figure 18 is a sectional view at BB position, showing a schematic diagram of a structure of an embodiment of the semiconductor structure.

[0118] The semiconductor structure comprises: a substrate 100, comprising a device region I and a power rail region II; a channel structure 110, separated on the substrate 100 of the device region I; a power rail line 120, located in the substrate 100 of the power rail region II, the extension direction of the power rail line 120 is parallel to the extension direction of the channel structure 110; a gate structure 140, located on the substrate 100 and across the channel structure 110; a source-drain doped region 150, located in the channel structure 110 on both sides of the gate structure 140; an interlayer dielectric layer 160, located on the substrate 100 on the side of the gate structure 140 and covering the source-drain doped region 150; a conductive via 180, penetrating the interlayer dielectric layer 160 located on part of the power rail line 120; a protective layer 200, filled in the conductive via 180; an interconnection slot 220, penetrating the interlayer dielectric layer 160 on the top of the source-drain doped region 150, along the extension direction of the gate structure 140, the sidewall of the interconnection slot 220 exposes the protective layer 200.

[0119] The protective layer 200 filled in the conductive via 180 can provide a flat surface for the forming process of the interconnection slot 220, thereby facilitating to reduce the difficulty of photolithography and etching process for forming the interconnection slot 220 and increase the process window for forming the interconnection slot 220 in the forming process of the interconnection slot 220. Moreover, the conductive via 180 is formed before the interconnection slot 220 in the embodiment, which is also conducive to avoiding the problem that the height difference of the top surface of the filling layer filled in the interconnection slot in different pattern density areas is too large, resulting in a large difference in etching rate and etching time of the conductive via. Accordingly, it is conducive to improve the consistency of the opening size and cross-sectional morphology of the conductive via 180. Moreover, the protective layer 200 can also play a protective role for the power rail line 120 and the conductive via 180 in the process of forming the interconnection slot 220, thereby facilitating to accurately control the opening size and cross-sectional morphology of the conductive via 180 and reduce the probability of damage to the power rail line 120. In summary, the embodiment is conducive to increasing the process window for forming the conductive via 180 and the interconnection slot 220, and accordingly improving the key size and cross-sectional morphology consistency of the conductive via 180, thereby improving the formation quality of the conductive plug and optimizing the performance of the semiconductor structure.

[0120] The substrate 100 is used to provide a process platform for the process. In the embodiment, the substrate 100 is a silicon substrate.

[0121] The substrate 100 of the device region I is used to form transistors, such as one or both of a PMOS transistor and an NMOS transistor.

[0122] In operation of the device, the channel structure 110 is used to provide a conductive channel of the transistor.

[0123] In this embodiment, the number of the channel structures 110 is plural, and the plural channel structures 110 are arranged in parallel and spaced apart. As an example, the channel structure 110 is a fin. Accordingly, a fin field effect transistor (FinFET) is formed on the substrate 100 of the device region I.

[0124] In this embodiment, the material of the fin is the same as the material of the substrate 100, and the material of the fin is silicon.

[0125] In other embodiments, the channel structure is spaced apart from the substrate, and the channel structure includes one or more channel layers arranged in spaced apart, and the gate structure covers part of the top of the channel structure and surrounds the channel layer. Accordingly, a gate-all-around (GAA) transistor or a fork sheet transistor can be formed on the substrate of the device region.

[0126] The power rail region II is used to form a power rail line 120. The power rail line 120 is used to provide power supply for different components of the chip. In this embodiment, the power rail line 120 is located in the substrate 100 of the power rail region II, and the power rail line 120 is a buried power rail (BPR), which is beneficial to release the wiring resources of the back-end-of-line (BEOL) and to reduce the height of the standard cell to meet the needs of continuous logic chip miniaturization. In addition, the buried power rail adopts the technology of pitch miniaturization to increase the BEOL resistance, which is also beneficial to provide a lower resistance local current distribution.

[0127] The power rail line 120 is a long strip structure, and the extension direction (such as the x direction shown in the figure) of the power rail line 120 is parallel to the extension direction of the channel structure 110, and the power rail line 120 and the channel structure 110 are spaced apart. Figure 18

[0128] The material of the power rail line 120 is a conductive material. In this embodiment, the material of the power rail line 120 is a metal material, including one or more of Co, W, Ni, and Ru. The resistivity of the material of the power rail line 120 is low, which is beneficial to improve the RC delay and improve the processing speed of the chip.

[0129] ​In this embodiment, the semiconductor structure further comprises an insulating layer 125 between the sidewall of the power rail line 120 and the substrate 100, the insulating layer 125 is used to realize the insulation between the power rail line 120 and the device region I substrate 100. Therefore, the material of the insulating layer 125 is an insulating material.

[0130] In this embodiment, the semiconductor structure further comprises an isolation layer 130 on the substrate 100 exposed by the channel structure 110 and covering the power rail line 120, the top surface of the isolation layer 130 is lower than the top surface of the channel structure 110.

[0131] The isolation layer 130 is used to isolate adjacent channel structures 110, and the isolation layer 130 is also used to isolate the substrate 100 and the gate structure 140. In this embodiment, the channel structure 110 is a fin, and the part of the fin exposed to the isolation layer 130 is used as an effective fin, which is used to provide a conductive channel during device operation.

[0132] In this embodiment, the isolation layer 130 is a shallow trench isolation structure (STI), and the material of the isolation layer 130 is an insulating material, such as one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0133] The gate structure 140 serves as a device gate, which is used to control the opening or closing of the conductive channel during device operation. In this embodiment, the gate structure 140 is a metal gate structure.

[0134] In this embodiment, the gate structure 140 is located on the isolation layer 130. The extension direction (as shown in the y direction) of the gate structure 140 is perpendicular to the extension direction of the channel structure 110 and the power rail line 120. Figure 18

[0135] In this embodiment, the semiconductor structure further comprises a gate cap layer 145 on the top of the gate structure 140. In the forming step of the interconnection trench 220, the gate cap layer 145 is used to protect the top of the gate structure 140, thereby reducing the probability of damage to the gate structure 140 and short circuit between the gate structure 140 and the source-drain interconnection layer.

[0136] The gate cap layer 145 is selected to have etching selectivity with the interlayer dielectric layer 160, so as to ensure that the gate cap layer 145 can protect the gate structure 110. The material of the gate cap layer 145 includes one or more of silicon nitride, silicon carbide, silicon carbon nitride, silicon carbon oxynitride, silicon oxynitride, boron nitride, and boron carbon nitride.

[0137] ​In this embodiment, the semiconductor structure further comprises: a sidewall 170 on the sidewall of the gate structure 140 and the gate cap layer 145. The sidewall 170 is used to define the formation position of the source / drain doped region 150, and the sidewall 170 is also used to protect the sidewall of the gate structure 140. In addition, after the source / drain interconnection layer is formed in the interconnection trench 220, the sidewall 170 is located between the source / drain interconnection layer and the gate structure 140, and is also used to isolate the source / drain interconnection layer and the gate structure 140.

[0138] In this embodiment, the material of the sidewall 170 is a low-k dielectric material or an ultra-low-k dielectric material, so as to reduce the effective capacitance between the source / drain interconnection layer and the gate structure 140. In this embodiment, for the convenience of illustration and description, the sidewall 170 is only schematically shown in the interconnection trench 220. Figure 19

[0139] The source / drain doped region 150 is used to provide a carrier source when the device is working. When an NMOS device is formed, N-type ions are doped in the source / drain doped region 150; when a PMOS device is formed, P-type ions are doped in the source / drain doped region 150. In this embodiment, the source / drain doped region 150 is located in the channel structure 110 on both sides of the gate structure 140 and the sidewall 170.

[0140] In this embodiment, the source / drain doped regions 150 in the plurality of channel structures 110 are in contact along the extension direction of the gate structure 140.

[0141] The interlayer dielectric layer 160 is used to isolate adjacent devices. The material of the interlayer dielectric layer 160 is an insulating material. In this embodiment, the material of the interlayer dielectric layer 160 is silicon oxide. In this embodiment, the interlayer dielectric layer 160 covers the sidewall of the sidewall 170, and the interlayer dielectric layer 160 is located on the isolation layer 130 at the side of the gate structure 140.

[0142] In this embodiment, the semiconductor structure further comprises: a contact etching stop layer (not shown in the figure) located between the source / drain doped region 150 and the interlayer dielectric layer 160, and between the isolation layer 130 and the interlayer dielectric layer 160. In the formation step of the interconnection trench 220, the contact etching stop layer is used to temporarily define the stop position of etching, so as to improve the consistency of etching and reduce the probability of damage to the source / drain doped region 150. In this embodiment, the material of the contact etching stop layer is silicon nitride.

[0143] The conductive via 180 is used to provide a spatial position for the subsequent formation of a conductive plug. In this embodiment, the conductive via 180 penetrates the interlayer dielectric layer 160 and the isolation layer 130 located on the top of the partial power rail line 120.

[0144] ​In the embodiment, the conductive via 180 is located in the interlayer dielectric layer 160 and the isolation layer 130 at the end of the source-drain doped region 150 along the extending direction of the gate structure 140, so that the interconnection slot 220 can be connected with the conductive via 180 along the extending direction of the gate structure 140.

[0145] The protective layer 200 fills in the conductive via 180, and is used to provide a flat surface for the forming process of the interconnection slot 220, so as to facilitate reducing the difficulty of the photolithography and etching process for forming the interconnection slot 220, and increasing the process window for forming the interconnection slot 220. In addition, the protective layer 200 can also protect the power rail line 120 and the conductive via 180 during the forming process of the interconnection slot 220, so as to facilitate accurately controlling the opening size and cross-sectional profile of the conductive via 180, and reducing the probability of damaging the power rail line 120. The protective layer 200 also occupies a space position for forming the conductive plug.

[0146] Therefore, in the embodiment, the top surface of the protective layer 200 is flush with the top surfaces of the interlayer dielectric layer 160 and the gate cap layer 145.

[0147] In the embodiment, the material of the protective layer 200 includes a metal material. The exposed top surface of the semiconductor structure includes the top surface of the interlayer dielectric layer 160, the top surface of the gate cap layer 145, and the top surface of the sidewall 170. The materials of the interlayer dielectric layer 160, the gate cap layer 145, and the sidewall 170 are all non-metal materials, and specifically, the materials of the interlayer dielectric layer 160, the gate cap layer 145, and the sidewall 170 are all dielectric materials. A high etching selectivity is easily achieved between the non-metal material and the metal material. Therefore, by making the material of the protective layer 200 include a metal material, the protective layer 200 is not easily mis-etched during the forming process of the interconnection slot 220. In addition, the metal material has a certain mechanical strength, and is easy to form a flat and smooth surface through a planarization process, so as to facilitate improving the height consistency of the top surface of the protective layer 200 with the top surfaces of the interlayer dielectric layer 160 and the gate cap layer 145, so as to provide a flat surface for forming the interconnection slot 220.

[0148] In addition, the protective layer 200 will be removed subsequently in the embodiment, so that the other film layer structures (for example, the interlayer dielectric layer 160, the gate cap layer 145, and the sidewall 170) are not easily mis-etched during the subsequent removal process of the protective layer 200. This not only facilitates improving the protection of the protective layer 200 to the conductive via 180 and the power rail line 120, but also facilitates reducing the process difficulty of subsequently removing the protective layer 200.

[0149] Specifically, the material of the protective layer 200 includes one or more of W, Co, Ru, Ti, TiN, Ta, TaN and Ni. As an example, the material of the protective layer 200 is W.

[0150] In other embodiments, the material of the protective layer is a conductive material, and the protective layer is in contact with the power rail line; so that the protective layer in the conductive via can be used as a conductive plug. In this embodiment, in order to reduce the resistance of the conductive plug to reduce the RC delay, the material of the protective layer is a material with low resistivity, including one or more of W, Co, Ru and Ni.

[0151] In this embodiment, the semiconductor structure further includes a liner layer 210 between the sidewall of the protective layer 200 and the sidewall of the conductive via 180, and between the bottom of the protective layer 200 and the power rail line 120. Specifically, the liner layer 210 is between the sidewall of the protective layer 200 and the sidewall of the interlayer dielectric layer 160, between the sidewall of the protective layer 200 and the sidewall of the isolation layer 130, and between the bottom of the protective layer 200 and the power rail line 120.

[0152] In this embodiment, in the subsequent step of removing the protective layer 200, the liner layer 210 can define the stopping position of etching, which is beneficial to improve the etching consistency, prevent damage to the power rail line 120, and accurately control the opening size and cross-sectional morphology of the conductive via 180, and is also beneficial to reduce the difficulty of removing the protective layer 200.

[0153] In this embodiment, the material of the liner layer 210 is a dielectric material, and the material of the liner layer 210 is different from the material of the power rail line 120. In the subsequent process of removing the liner layer 210 at the bottom of the conductive via 180, a high etching selectivity of the power rail line 120 can be achieved, which is beneficial to ensure the protective effect of the liner layer 210 on the power rail line 120, and accordingly prevent damage to the power rail line 120 and reduce the process difficulty of removing the liner layer 210 at the bottom of the conductive via 180. In addition, in this embodiment, the material of the liner layer 210 is different from the material of the protective layer 200. Specifically, the material of the protective layer 200 is a metal material, and the material of the liner layer 210 is a dielectric material, so that in the subsequent process of removing the protective layer 200, the liner layer 210 and the protective layer 200 have a high etching selectivity, and accordingly the liner layer 210 can define the stopping position of etching.

[0154] The material of the liner layer 210 includes one or more of silicon nitride, silicon oxide and silicon oxynitride. As an example, the material of the liner layer 210 is silicon nitride.

[0155] The thickness of the pad layer 210 should not be too small, otherwise the effect of the pad layer 210 for defining the etching stop position and the protection effect on the power supply track line 120 will be reduced; the thickness of the pad layer 210 should not be too large, otherwise the remaining space and the remaining opening size of the conductive via hole 180 will be too small, which will increase the difficulty of filling the protective layer 200 in the conductive via hole 180. Therefore, in the embodiment, the thickness of the pad layer is 2nm to 5nm.

[0156] The semiconductor structure can be formed by the forming method described in the foregoing embodiments, or can be formed by other forming methods. For the specific description of the semiconductor structure of the embodiment, reference can be made to the corresponding description in the foregoing embodiments, which will not be described herein again.

[0157] Although the present application has been disclosed as above, the present application is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The semiconductor structure includes: a substrate, including a device region and a power rail region, the substrate of the device region being formed with discrete channel structures, the substrate of the power rail region being formed with power rail lines, the power rail lines extending in parallel with the channel structures, the substrate being formed with gate structures across the channel structures, the channel structures on both sides of the gate structures being formed with source / drain doped regions, the substrate on the sides of the gate structures and the power rail lines being formed with interlayer dielectric layers covering the source / drain doped regions; forming conductive vias penetrating the interlayer dielectric layers on the power rail lines, and exposing the power rail lines; filling the conductive vias with a protective layer; forming interconnection grooves penetrating the interlayer dielectric layers on the top of the source / drain doped regions, the sidewalls of the interconnection grooves exposing the protective layer along the extension direction of the gate structures; forming conductive plugs in the conductive vias and in contact with the power rail lines, and source / drain interconnection layers in the interconnection grooves and in contact with the source / drain doped regions, the source / drain interconnection layers being in contact with the sidewalls of the conductive plugs; in the step of forming the protective layer, the material of the protective layer is a conductive material, and the protective layer is in contact with the power rail lines; the step of forming the conductive plugs includes using the protective layer in the conductive vias as the conductive plugs.

2. The method of forming a semiconductor structure of claim 1, wherein, The method for forming the semiconductor structure further includes, after forming the interconnection grooves and before forming the conductive plugs and the source / drain interconnection layers, removing the protective layer to expose the conductive vias; the step of forming the conductive plugs includes filling the conductive vias with a conductive material to form the conductive plugs in the conductive vias.

3. The method of forming a semiconductor structure of claim 2, wherein After forming the conductive vias and before forming the protective layer, the method for forming the semiconductor structure further includes forming a liner layer on the bottom and sidewalls of the conductive vias; in the step of forming the interconnection grooves, the interconnection grooves also penetrate the liner layer on the sidewalls of the protective layer; after removing the protective layer and before forming the conductive plugs and the source / drain interconnection layers, the method for forming the semiconductor structure further includes removing the liner layer on the bottom of the conductive vias to expose the top surface of the power rail lines.

4. The method of forming a semiconductor structure of claim 3, wherein, The material of the liner layer is a dielectric material.

5. The method of forming a semiconductor structure of claim 3, wherein, The thickness of the liner layer is 2-5 nm.

6. The method of forming a semiconductor structure of claim 3, wherein, The process of removing the liner layer on the bottom of the conductive vias includes a wet etching process or an anisotropic dry etching process.

7. The method of forming a semiconductor structure of claim 2, wherein, The material of the protective layer is a metal material; the metal material includes one or more of W, Co, Ru, Ti, TiN, Ta, TaN, and Ni.

8. The method of forming a semiconductor structure of claim 2, wherein, In the step of removing the protective layer, the conductive vias are exposed, and the conductive vias are in communication with the interconnection grooves; the step of forming the conductive plugs and the source / drain interconnection layers includes filling the conductive vias and the interconnection grooves with a conductive material in the same step to form the conductive plugs in the conductive vias and the source / drain interconnection layers in the interconnection grooves.

9. The method of forming a semiconductor structure of claim 2, wherein, The step of forming the interconnection trench comprises: forming a metal hard mask layer on the interlayer dielectric layer, the metal hard mask layer being formed with a mask opening above the source-drain doped region; and etching the interlayer dielectric layer below the mask opening with the metal hard mask layer as a mask. The method for forming the semiconductor structure further comprises: in the step of removing the protective layer, the metal hard mask layer is removed.

10. The method of forming a semiconductor structure of claim 9, wherein, The process for removing the protective layer and the metal hard mask layer comprises a wet etching process; and the etching solution of the wet etching process comprises a mixed solution of concentrated sulfuric acid and hydrogen peroxide.

11. The method of forming a semiconductor structure of claim 10, wherein, The solution temperature of the concentrated sulfuric acid is 50-200°C.

12. The method of forming a semiconductor structure of claim 1, wherein, The step of forming the protective layer comprises: forming a protective material layer in the conductive via, the protective material layer also covering the interlayer dielectric layer. The planarization process is used to remove the protective material layer above the top surface of the interlayer dielectric layer, and the remaining protective material layer in the conductive via is used as the protective layer.

13. The method of forming a semiconductor structure of claim 1, wherein, The channel structure is a fin, or the channel structure is spaced apart from the substrate, the channel structure comprising one or more spaced-apart channel layers, and the gate structure covering part of the top of the channel structure and surrounding the channel layers.

14. The method of forming a semiconductor structure of claim 1, wherein, In the step of providing the substrate, an isolation layer covering the power rail line is further formed on the exposed substrate of the channel structure, the top surface of the isolation layer being lower than the top surface of the channel structure, the gate structure being on the isolation layer, and the interlayer dielectric layer being on the isolation layer at the side of the gate structure. In the step of forming the conductive via, the conductive via penetrates the interlayer dielectric layer and the isolation layer on part of the top of the power rail line.

15. A semiconductor structure, characterized by Comprise: a substrate comprising a device region and a power rail region; a channel structure on the substrate in the device region; a power rail line in the substrate in the power rail region, the extension direction of the power rail line being parallel to the extension direction of the channel structure; a gate structure on the substrate and across the channel structure; a source-drain doped region in the channel structure on both sides of the gate structure; an interlayer dielectric layer on the substrate at the side of the gate structure and covering the source-drain doped region; a conductive via penetrating the interlayer dielectric layer on part of the power rail line and exposing the power rail line; a protective layer filled in the conductive via, the protective layer being in contact with the power rail line, the material of the protective layer being a conductive material, and the protective layer in the conductive via being used as a conductive plug; an interconnection trench penetrating the interlayer dielectric layer on the top of the source-drain doped region, along the extension direction of the gate structure, the sidewall of the interconnection trench exposing the protective layer, and the interconnection trench exposing the top of the source-drain doped region.

16. The semiconductor structure of claim 15, wherein, The material of the protective layer comprises a metal material; and the metal material comprises one or more of W, Co, Ru, Ti, TiN, Ta, TaN and Ni.

17. The semiconductor structure of claim 16, wherein, The semiconductor structure further comprises: a liner layer between the sidewall of the protective layer and the sidewall of the conductive via, and between the bottom of the protective layer and the power rail line; and the material of the liner layer is a dielectric material.

18. The semiconductor structure of claim 15, wherein, The material of the protective layer comprises one or more of W, Co, Ru and Ni.

19. The semiconductor structure of claim 15, wherein, The channel structure is a fin; or, the channel structure is spaced apart from the substrate, the channel structure comprises one or more spaced apart channel layers, and the gate structure covers part of the top of the channel structure and surrounds the channel layers.

20. The semiconductor structure of claim 15, wherein, The semiconductor structure further comprises an isolation layer on the substrate exposed by the channel structure and covering the power rail line, the top surface of the isolation layer being lower than the top surface of the channel structure; The gate structure is on the isolation layer; The interlayer dielectric layer is on the isolation layer on the side of the gate structure; The conductive via penetrates the interlayer dielectric layer and the isolation layer on part of the top of the power rail line.

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