Semiconductor device

Abstract

A semiconductor device having excellent reliability is provided, and includes, from the bottom, a first nitride semiconductor layer, a second nitride semiconductor layer having a larger band gap than the first nitride semiconductor layer, a first electrode electrically connected to the first nitride semiconductor layer, a second electrode above the first nitride semiconductor layer and electrically connected thereto, a gate electrode between the first electrode and the second electrode, a gate field plate electrode above the gate electrode and electrically connected thereto, a first field plate electrode between the gate field plate electrode and the second electrode, electrically connected to the first electrode, and a second field plate electrode between the first field plate electrode and the gate field plate electrode, electrically connected to the first electrode. A bottom surface of the second field plate electrode is closer to the first nitride semiconductor layer than a bottom surface of a portion of the gate field plate electrode that protrudes most toward the second electrode, and is closer to the first nitride semiconductor layer than a bottom of an end surface of the first field plate electrode on the first electrode side.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2020-159720 (filed on September 24, 2020). This application includes all contents of the basic application by reference to that basic application. Technical Field

[0003] Embodiments of the present invention relate to semiconductor devices. Background Technology

[0004] Semiconductor components such as transistors and diodes are used in circuits such as switching power supplies and inverters. These semiconductor components are required to have high voltage withstand capability and low on-resistance. Moreover, there is a trade-off between voltage withstand capability and on-resistance determined by the component material.

[0005] With advancements in technology, semiconductor devices have achieved on-resistance levels approaching the limits of silicon, the primary material for these devices. To further increase voltage withstand and reduce on-resistance, changes in device materials are necessary. By using nitride semiconductors such as gallium nitride and aluminum gallium nitride as the material for semiconductor devices, the trade-offs determined by the material can be improved. Therefore, leaps in high voltage withstand and low on-resistance semiconductor devices can be achieved.

[0006] Field plate electrodes are used to mitigate lateral electric field concentration in transistors employing nitride semiconductors. Even with field plate electrodes, electric field concentration can still lead to damage to the interlayer insulating film. Summary of the Invention

[0007] The embodiments of the present invention provide a semiconductor device with high reliability.

[0008] The semiconductor device of the embodiment includes: a first nitride semiconductor layer; a second nitride semiconductor layer located on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer; a first electrode located on the second nitride semiconductor layer and electrically connected to the first nitride semiconductor layer; a second electrode located on the first nitride semiconductor layer and electrically connected to the first nitride semiconductor layer; a gate electrode located between the first electrode and the second electrode; a gate field plate electrode located on the gate electrode and electrically connected to the gate electrode; a first field plate electrode located on the second nitride semiconductor layer and located between the gate field plate electrode and the second electrode, and electrically connected to the first electrode; and a second field plate electrode located between the first field plate electrode and the gate field plate electrode and electrically connected to the first electrode. The distance between the bottom surface of the second field plate electrode and the first nitride semiconductor layer is shorter than the distance between the bottom surface of the portion of the gate field plate electrode that protrudes most towards the second electrode and the first nitride semiconductor layer, and the distance between the bottom surface of the second field plate electrode and the first nitride semiconductor layer is shorter than the distance between the bottom of the end face of the first electrode side of the first field plate electrode and the first nitride semiconductor layer. Attached Figure Description

[0009] Figure 1 This is a schematic cross-sectional view of the semiconductor device according to the implementation method.

[0010] Figure 2 This is a schematic cross-sectional view of the semiconductor device according to the implementation method.

[0011] Figure 3 This is a schematic cross-sectional view of the semiconductor device according to the implementation method.

[0012] Figure 4 This is a schematic cross-sectional view of the semiconductor device according to the implementation method. Detailed Implementation

[0013] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, in the following description, the same reference numerals are used to denote the same or similar components, and descriptions of components that have already been described once are omitted.

[0014] In this specification, "nitride semiconductor layer" includes "GaN-type semiconductor". "GaN-type semiconductor" refers to a general term for semiconductors including gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and intermediate components thereof.

[0015] In this specification, "undoped" means an impurity concentration of 2 × 10⁻⁶. 16 cm －3 the following.

[0016] In this specification, to indicate the positional relationship of components, the upper direction in the attached drawings is referred to as "upper," and the lower direction is referred to as "lower." In this specification, the concepts of "upper" and "lower" do not necessarily indicate a relationship with the direction of gravity.

[0017] (First Implementation)

[0018] The semiconductor device according to the first embodiment includes: a first nitride semiconductor layer; a second nitride semiconductor layer located on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer; a first electrode located on the second nitride semiconductor layer and electrically connected to the first nitride semiconductor layer; a second electrode located on the first nitride semiconductor layer and electrically connected to the first nitride semiconductor layer; a gate electrode located between the first electrode and the second electrode; a gate field plate electrode located on the gate electrode and electrically connected to the gate electrode; a first field plate electrode located on the second nitride semiconductor layer, located between the gate field plate electrode and the second electrode, and electrically connected to the first electrode; and a second field plate electrode located between the first field plate electrode and the gate field plate electrode and electrically connected to the first electrode.

[0019] Figure 1 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment. The semiconductor device is a HEMT (High Electron Mobility Transistor) 100 using GaN-type semiconductors.

[0020] HEMT100 includes a substrate 1, a buffer layer 2, a channel layer 3 (a first nitride semiconductor layer), a barrier layer 4 (a second nitride semiconductor layer), a source electrode 5 (a first electrode), a gate electrode 6, a drain electrode 7 (a second electrode), a gate field plate electrode 8, a first field plate electrode 9, a second field plate electrode 10, a third field plate electrode 11, and an interlayer insulating layer 12.

[0021] The substrate 1 is formed of silicon (Si), for example. In addition to silicon, sapphire (Al2O3) or silicon carbide (SiC) can also be used.

[0022] A buffer layer 2 is disposed on the substrate 1. The buffer layer 2 has the function of mitigating the lattice mismatch between the substrate 1 and the channel layer 3. The buffer layer 2 is, for example, made of aluminum gallium nitride (Al). W Ga 1－W The multilayer structure of N(0<W≤1) is formed.

[0023] Channel layer 3 is disposed on buffer layer 2. Channel layer 3 is also called electron transit layer. Channel layer 3 is, for example, undoped aluminum gallium nitride (Al₂O₃). X Ga 1－XN (0 ≤ X < 1). More specifically, for example, undoped gallium nitride (GaN). The thickness of the channel layer 3 is, for example, 0.1 μm to 10 μm. In the embodiment, the thickness is the length (height) of each component in the stacking direction of the channel layer 3, including the channel layer 3, and the barrier layer 4.

[0024] A barrier layer 4 is disposed on the channel layer 3. The barrier layer 4 is also called an electron supply layer. The band gap of the barrier layer 4 is larger than that of the channel layer 3. The barrier layer 4 is, for example, undoped aluminum gallium nitride (Al₂O₃). Y Ga 1－Y N (0 < Y ≤ 1, X < Y)). More specifically, for example, undoped Al. 0.25 Ga 0.75 N. The thickness of the barrier layer 4 is, for example, more than 2 nm and less than 100 nm.

[0025] The channel layer 3 and the barrier layer 4 form a heterojunction interface. A two-dimensional electron gas (2DEG) is formed at the heterojunction interface, which becomes the charge carrier of HEMT100.

[0026] The first electrode 5 is, for example, a source electrode. The source electrode 5 is disposed on the channel layer 3 and the barrier layer 4. The source electrode 5 is electrically connected to the channel layer 3 and the barrier layer 4. The source electrode 5 is, for example, directly connected to the barrier layer 4.

[0027] The source electrode 5 is, for example, a metal electrode. The source electrode 5 is, for example, a stacked structure of titanium (Ti) and aluminum (Al). Ideally, there should be an ohmic contact between the source electrode 5 and the barrier layer 4.

[0028] The gate electrode 6 is disposed on the channel layer 3 and the barrier layer 4. The gate electrode 6 is electrically connected to the channel layer 3 and the barrier layer 4. For example, the gate electrode 6 is directly connected to the barrier layer 4. The gate electrode 6 is disposed between the source electrode 5 and the drain electrode 7.

[0029] Gate electrode 6 is, for example, titanium nitride (TiN).

[0030] Alternatively, a gate insulating film (not shown) can be provided between the gate electrode 6 and the barrier layer, making the semiconductor device 100 a MIS (Metal Insulator Semiconductor) type HEMT. The gate insulating layer can be, for example, an oxide or an oxide nitride. Examples of gate insulating layers include silicon oxide, aluminum oxide, silicon oxynitride, or aluminum oxynitride.

[0031] The drain electrode 7 is disposed on the channel layer 3 and the barrier layer 4. The drain electrode 7 is electrically connected to the channel layer 3 and the barrier layer 4. For example, the drain electrode 7 is connected to the barrier layer 4.

[0032] The drain electrode 7 is, for example, a metal electrode. The drain electrode 7 is, for example, a laminated structure of titanium (Ti) and aluminum (Al). An ohmic contact is desired between the drain electrode 7 and the barrier layer 4.

[0033] The distance between the source electrode 5 and the drain electrode 7 is, for example, more than 5 μm and less than 30 μm.

[0034] In addition, the source electrode 5 and the drain electrode 7 can also be constructed to be directly connected to the channel layer 3.

[0035] The gate field plate electrode 8 is located on the gate electrode 6. The gate field plate electrode 8 is connected to the gate electrode 6. By setting the gate field plate electrode 8, the lateral electric field concentration of the gate electrode 6 can be mitigated.

[0036] The gate field plate electrode 8 is not a flat conductive film, but has steps. The gate field plate electrode 8 includes a portion that extends upward from the gate electrode 6. The side of the second field plate electrode 10 (drain electrode 7 side) of the gate field plate electrode 8 is a stepped, non-flat surface.

[0037] Gate field plate electrode 8 can also be like Figure 2 It can be configured as two layers, or three or more layers. In this embodiment, the bottom surface (the surface facing the channel layer 3) of the portion of the gate field plate electrode 8 protruding towards the drain electrode 7 separates from the top of the gate electrode 6. When the gate field plate electrode 8 has three or more layers, there are two or more bottom surfaces of the gate field plate electrode 8 that are separated from the gate electrode 6.

[0038] exist Figure 1 In this configuration, the side of the portion of the gate field plate electrode 8 protruding towards the drain electrode 7 (the side facing the drain electrode 7) is located closer to the source electrode 5 than the side of the second field plate electrode 10 of the gate electrode 6. Additionally, in Figure 1 In this configuration, the side of the portion of the gate field plate electrode 8 that protrudes toward the source electrode 5 (the side facing the source electrode 5) is located closer to the source electrode 5 than the side of the gate electrode 6 that faces the source electrode 5.

[0039] The first field plate electrode 9 is located on the barrier layer 4. The first field plate electrode 9 is separated from the barrier layer 4, and the bottom surface of the first field plate electrode 9 is located above the barrier layer 4, for example, on the side of the third field plate electrode 11.

[0040] The first field plate electrode 9 is electrically connected to the source electrode 5. The first field plate electrode 9 mitigates the transverse electric field. Figure 1 In this configuration, the first field plate electrode 9 is directly connected to the barrier layer 4, but a layer can also be sandwiched between the barrier layer 4 and the first field plate electrode 9. Figure 1The layer is not shown in the diagram. The first field plate electrode 9 is physically separated from the gate electrode 6 and the drain electrode 7. The first field plate electrode 9 is located between the gate electrode 6 and the drain electrode 7 and is positioned closer to the drain electrode 7 compared to the second field plate electrode 10.

[0041] The second field plate electrode 10 is electrically connected to the source electrode 5. The second field plate electrode 10 has a portion extending towards the barrier layer 4 between the gate field plate electrode 8 and the first field plate electrode 9. The bottom surface of the second field plate electrode 10 is the bottom surface of the extended portion, located between the gate field plate electrode 8 and the first field plate electrode 9. The bottom surface of the second field plate electrode 10 is separated from the barrier layer 4.

[0042] The distance between the bottom of the second field plate electrode 10 and the channel layer 3 is set as d1, the distance between the bottom surface of the portion of the gate field plate electrode 8 protruding towards the drain electrode 7 and the channel layer 3 is set as d2, and the distance between the bottom of the end face of the source electrode 5 side of the first field plate electrode 9 and the channel layer 3 is set as d3. In this case, it is preferable that d1 is shorter than d2 and d3 is shorter than d3.

[0043] Without the second field plate electrode 10, electric field concentration is easily generated at the end of the gate electrode 6 on the side of the first field plate electrode 9, the end of the gate field plate electrode 8 on the side of the first field plate electrode 9, and the gate electrode 6 side of the first field plate electrode 9. Therefore, if a second field plate electrode 10 electrically connected to the source electrode 5 is provided between the gate field plate electrode 8 and the first field plate electrode 9, each electric field concentration can be mitigated. However, when d1 is greater than d2 or greater than d3, the electric field concentration at the end of the gate electrode 6 is not easily mitigated. Therefore, if the thickness of the interlayer insulating film 12 between the second field plate electrode 10 and the barrier layer 4 is made very thin, such that d1 is shorter than d2 and shorter than d3, the electric field concentration at the end of the gate electrode 6 can be effectively mitigated.

[0044] When the end of the gate electrode 6 on the drain electrode 7 side is located between the end of the source electrode 5 side of the bottom surface of the second field plate electrode 10 and the end of the drain electrode 7 side of the bottom surface of the second field plate electrode 10, the electric field concentration on the end face of the gate electrode 6 on the drain electrode 7 side caused by the setting of the second field plate electrode 10 can be more effectively mitigated.

[0045] If the end face of the drain electrode 7 side of the second field plate electrode 10 is located closer to the drain electrode 7 side than the end face of the source electrode 5 side of the first field plate electrode 9, the electrolytic concentration on the gate electrode 6 side of the first field plate electrode 9 can be mitigated more effectively.

[0046] If the distance between the upper end face of the second field plate electrode 10 and the channel layer 3 is longer than the distance between the upper end face of the second field plate electrode 9 side of the gate field plate electrode 8 and the channel layer 3, the electrolytic concentration at the upper end of the drain electrode 7 side of the gate field plate electrode 8 can be effectively mitigated.

[0047] If the distance between the upper end face of the second field plate electrode 10 and the channel layer 3 is longer than the distance between the upper end face of the first field plate electrode 9 and the channel layer 3, the electric field concentration at the end of the source electrode 5 side of the first field plate electrode 9 can be effectively mitigated.

[0048] The third field plate electrode 11 is electrically connected to the source electrode 5, extends along the drain electrode 7, and is located above the gate electrode 6. The third field plate electrode 11 mitigates the lateral electric field. The third field plate 10 is at the same potential as the source electrode 5. The gate electrode 5, the first field plate electrode 9, and the second field plate electrode 10 are located between the extension of the third field plate electrode 11 and the second nitride semiconductor layer 4. In the stacking direction of the channel layer 3 and the barrier layer 4, the second field plate electrode 10 is located between the first field plate electrode 9 and the third field plate electrode 11. The end face of the third field plate electrode 11 on the drain electrode 7 side is closer to the drain electrode 7 side than the end face of the first field plate electrode 8 on the drain electrode 7 side. The end face of the third field plate electrode 11 on the drain electrode 7 side is closer to the drain electrode 7 side than the end face of the second field plate electrode 10 on the drain electrode 7 side.

[0049] The first to third field plate electrodes in the embodiments are all in Figure 1 The cross-sections shown are not directly connected to each other. Figure 1 The cross-section shown is a plane parallel to the thickness direction of substrate 1 (a plane perpendicular to the side of the barrier layer 4 of the channel layer 3, including the line segment extending from the source electrode 5 to the drain electrode 7), and includes the gate electrode 6, the first field plate electrode 9, and the second field plate electrode 10. The source electrode 5 is connected to a source pad (not shown), and in the embodiment, the field plate electrode is connected to the source pad, for example.

[0050] The interlayer insulating film 12 is, for example, an oxide or a nitride. The interlayer insulating film 12 is, for example, silicon oxide (SiO2), silicon nitride (SiN), or a high-k material. Examples of high-k materials include hafnium oxide (HfO2).

[0051] The types and concentrations of elements in the semiconductor layer and semiconductor regions can be determined, for example, using SIMS (Secondary Inon Mass Spectrometry) or EDX (Energy Dispersive X-ray Spectroscopy). Furthermore, the relative levels of element concentration can be determined, for example, based on the carrier concentration obtained from SCM (Scanning Capacitance Microscopy). Additionally, the depth, thickness, width, and spacing of impurity regions can be determined, for example, using SIMS. Moreover, the depth, thickness, width, and spacing of impurity regions can also be determined, for example, by comparing SCM images with atom probe microanalysis images.

[0052] Compared to a comparison method that does not include the gate field plate electrode 8, the first field plate electrode 9, and the second field plate electrode 10, the electric field concentration towards the gate electrode 6 is more moderate.

[0053] (Second Implementation)

[0054] The semiconductor device of the second embodiment is a variation of the semiconductor device of the first embodiment. Figure 2 The diagram shows a schematic cross-sectional view of the semiconductor layer 101 according to the second embodiment. The semiconductor device 101 of the second embodiment is identical to the semiconductor device 100 of the first embodiment, except that the gate field plate electrode 8 is multilayered, the first field plate electrode 9 is multilayered, the extension portion of the second field plate electrode 10 towards the barrier layer 4 is U-shaped and extends further towards the drain electrode 7 than the first field plate electrode 9, and an insulating film 12 is provided on the fourth field plate electrode 13 between the first field plate electrode 9 and the drain electrode 7. In embodiments including variations of the first embodiment, some or all of the modified or added configurations can be adopted in other embodiments. Descriptions of common elements between embodiments are omitted. In the second embodiment, as in the first embodiment, a semiconductor device 101 with mild lateral electric field concentration and excellent reliability can be provided.

[0055] The gate field plate electrode 8 can be multilayered, and the first field plate electrode 9 can be multilayered. By making the field plate electrodes multilayered, electrolytic concentration can be further mitigated. When the gate field plate electrode 8 is multilayered, the distance between the bottom surface of the uppermost layer and the channel layer 3 is d2. Furthermore, when the first field plate electrode 9 is multilayered, the distance between the bottom surface of the lowermost layer of the first field plate electrode 9 and the channel layer 3 is d3.

[0056] Even though the extension portion of the second field plate electrode 10 toward the barrier layer 4 is U-shaped, the extension portion becomes very deep on the side of the gate electrode 6, so it can satisfy d1 < d2 and d1 < d3, which can alleviate the electric field concentration of the gate electrode 6, the gate field plate electrode 8 and the first field plate electrode 9.

[0057] exist Figure 3 In the semiconductor device 101, the end of the second field plate electrode 10 on the drain electrode 7 side is located closer to the drain electrode 7 side than the end of the first field plate electrode 9 on the drain electrode 7 side. By extending the second field plate electrode 10 towards the drain electrode 7 side and providing a fourth field plate electrode 13 between the first field plate electrode 9 and the drain electrode 7, electric field concentration can be mitigated, and the gate-drain capacitance can be reduced. Furthermore, this configuration ensures stable high-speed operation. The fourth field plate electrode 13 can also be electrically connected to the source electrode 5 and connected to the second field plate electrode 10.

[0058] (Third Implementation)

[0059] The semiconductor device of the third embodiment is a variation of the semiconductor device of the first embodiment or the semiconductor device of the second embodiment. Figure 3 The diagram shows a schematic cross-sectional view of the semiconductor layer 102 according to the third embodiment. The semiconductor device 102 of the third embodiment is identical to the semiconductor device 100 of the first embodiment or the semiconductor device 101 of the second embodiment, except that the second field plate electrode 10 extends towards the source electrode 5. In embodiments that include variations of the first embodiment, some or all of the modified or added configurations can be adopted in other embodiments. Descriptions of common elements between embodiments are omitted. In the third embodiment, as in the first embodiment, a semiconductor device 102 with mild lateral electric field concentration and excellent reliability can be provided.

[0060] exist Figure 3 In the semiconductor device 102, the end of the second field plate electrode 10 on the source electrode 5 side is located closer to the source electrode 5 side than the end of the gate field plate electrode 8 on the source electrode 5 side. If the second field plate electrode 10 extends towards the source electrode 5 side, the gate-source capacitance increases, but the potential remains stable. The second field plate electrode 10 can also be further extended to connect with the source electrode 5 or the third field plate electrode 11.

[0061] (Fourth Implementation)

[0062] The semiconductor device of the fourth embodiment is a variation of the semiconductor device of the first embodiment to the semiconductor device of the third embodiment. Figure 4The diagram shows a schematic cross-sectional view of the semiconductor layer 103 according to the fourth embodiment. The semiconductor device 103 of the fourth embodiment is the same as the semiconductor device 100 of the first embodiment, except that it has a trench (recess) in which the bottom surface of the gate electrode 6 is located in the channel layer 3, a gate insulating film 14 is provided between the gate electrode 6 and the barrier layer 4, and the gate electrode 6 is located within the trench. By placing the bottom surface of the trench within the channel layer 3, the two-dimensional electron gas under the gate electrode 6 disappears. By employing this method, the semiconductor device 103 can achieve normally-off operation. In the fourth embodiment, with a different structure of the gate electrode 6, the semiconductor device 104, which is similar to the first embodiment, provides a lateral electric field concentration that is mitigated and has excellent reliability.

[0063] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, the constituent elements of one embodiment can be substituted or modified with the constituent elements of other embodiments. These embodiments and their variations are included in the scope and spirit of the invention, and are included in the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device comprising: a first nitride semiconductor layer; a second nitride semiconductor layer located on a surface of the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer; a first electrode located on the second nitride semiconductor layer and electrically connected to the first nitride semiconductor layer; a second electrode located on the first nitride semiconductor layer and electrically connected to the first nitride semiconductor layer; a gate electrode having a flat portion and located between the first electrode and the second electrode in a first direction parallel to the surface of the first nitride semiconductor layer; a gate field plate electrode located on the gate electrode and electrically connected to the gate electrode, the gate field plate electrode having a central portion located directly above the gate electrode in a second direction perpendicular to the surface of the first nitride semiconductor layer; a first field plate electrode located on the second nitride semiconductor layer in the second direction and between the gate field plate electrode and the second electrode in the first direction, the first field plate electrode being electrically connected to the first electrode; and a second field plate electrode including an upper flat portion and a protruding portion extending from the upper flat portion toward the first nitride semiconductor layer in the second direction, the protruding portion being electrically connected to the first electrode and located between the first field plate electrode and the gate field plate electrode in the first direction, a bottom surface of the protruding portion of the second field plate electrode being closer to the first nitride semiconductor layer than a bottom surface of an outermost end portion of the gate field plate electrode protruding most toward the second electrode in the first direction, a distance between the bottom surface of the protruding portion of the second field plate electrode and the first nitride semiconductor layer being greater than zero but shorter than a distance between a bottom of an end surface of the first electrode side of the first field plate electrode and the first nitride semiconductor layer, the bottom surface of the protruding portion of the second field plate electrode being separated from the second nitride semiconductor layer by an interlayer insulating layer, and an end portion of the flat portion of the gate electrode overlapping the protruding portion of the second field plate electrode in the second direction and being located between the protruding portion of the second field plate electrode and the second nitride semiconductor layer in the second direction.

2. The semiconductor device according to claim 1, wherein an end surface of the first electrode side of the second field plate electrode is located closer to the first electrode side than an end surface of the second electrode side of the gate field plate electrode, and an end surface of the second electrode side of the second field plate electrode is located closer to the second electrode side than an end surface of the first electrode side of the first field plate electrode.

3. The semiconductor device according to claim 1 or 2, wherein an upper end surface of the second field plate electrode is farther from the first nitride semiconductor layer than an upper end surface of the second electrode side of the gate field plate electrode. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The upper end surface of the second field plate electrode is farther from the first nitride semiconductor layer than the upper end surface of the first field plate electrode.

4. The semiconductor device according to claim 1 or 2, having a third field plate electrode above the second field plate electrode and connected to the first electrode.

5. The semiconductor device according to claim 1 or 2, having a fourth field plate electrode between the first field plate electrode and the second electrode and connected to the first electrode.

6. The semiconductor device according to claim 1 or 2, the second-electrode-side end of the second field plate electrode is located farther to the second-electrode side than the second-electrode-side end of the first field plate electrode.

7. The semiconductor device according to claim 1 or 2, the first-electrode-side end of the second field plate electrode is located farther to the first-electrode side than the first-electrode-side end of the gate field plate electrode.

8. The semiconductor device according to claim 1 or 2, the second-electrode-side end of the gate electrode is located between the first-electrode-side end of the bottom surface of the second field plate electrode and the second-electrode-side end of the bottom surface of the second field plate electrode.

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