Voltage detection chip, battery and electronic equipment

Abstract

The present application provides a voltage detection chip, a battery and an electronic device, wherein the voltage detection chip includes: a first voltage generating circuit, a second voltage generating circuit, a third voltage generating circuit and a fourth voltage generating circuit, which are respectively used to output a first output signal, a second output signal, a third output signal and a fourth output signal, wherein the first output signal, the third output signal and a reference positive voltage signal controlled by a first switch circuit are input to a first input terminal of a comparison circuit, and the second output signal and the fourth output signal are input to a second input terminal of the comparison circuit; the second switch circuit controls the on-off between the second input terminal and the output terminal of the comparison circuit; the comparison circuit outputs a detection signal according to the difference between the voltage signal received at the first input terminal and the voltage signal received at the second input terminal, which is used to indicate whether the battery is over-voltage during the charging and discharging process. The present application provides a voltage detection chip, a battery and an electronic device that realizes high-voltage detection, reduces power consumption and has a small size.

Description

Technical Field

[0001] The present application relates to the field of fast charging technology, and in particular to a voltage detection chip, a battery and an electronic device. Background Art

[0002] In the fast charging technology of batteries, the protection of overvoltage charging and overvoltage discharging of batteries is particularly important. The voltage of the battery is often at a high voltage during the fast charging process. Or, in the process of connecting multiple battery cells in series, some battery cells are at a high voltage. Therefore, voltage detection at the high voltage end has become an increasingly important research focus. How to provide a chip that can reduce power consumption and miniaturize the size to achieve high voltage detection of the battery has become a technical problem that needs to be solved. Summary of the invention

[0003] The present application provides a voltage detection chip, a battery and an electronic device that realize high voltage detection, reduce power consumption and miniaturize size.

[0004] In a first aspect, an embodiment of the present application provides a voltage detection chip for overvoltage detection of a battery during charging and discharging, including:

[0005] A first voltage generating circuit, configured to select one of a battery positive voltage signal and a battery negative voltage signal and generate a first output signal;

[0006] a second voltage generating circuit, configured to select the other of the battery positive voltage signal and the battery negative voltage signal and generate a second output signal;

[0007] a third voltage generating circuit, configured to select one of a reference positive voltage signal and a reference negative voltage signal and generate a third output signal;

[0008] a fourth voltage generating circuit, configured to select the other of the reference positive voltage signal and the reference negative voltage signal to generate a fourth output signal;

[0009] a comparison circuit, wherein a first input terminal of the comparison circuit is electrically connected to an output terminal of the first voltage generating circuit and to an output terminal of the third voltage generating circuit, and a second input terminal of the comparison circuit is electrically connected to an output terminal of the second voltage generating circuit and to an output terminal of the fourth voltage generating circuit;

[0010] A first switch circuit, the first switch circuit is electrically connected to a first input terminal of the comparison circuit to control the reference positive pressure signal to be input to the first input terminal; and

[0011] a second switch circuit, wherein two ends of the second switch circuit are electrically connected to the second input end of the comparison circuit and the output end of the comparison circuit respectively, so as to control the on-off between the second input end of the comparison circuit and the output end of the comparison circuit;

[0012] The comparison circuit is used to output a detection signal according to the difference between the voltage signal received by the first input terminal and the voltage signal received by the second input terminal, so as to indicate whether the battery is over-voltage during the charging and discharging process.

[0013] In a second aspect, an embodiment of the present application provides a battery, comprising a plurality of battery cells, a battery selection circuit, a reference generating circuit and the voltage detection chip, wherein the battery cells are used to generate a battery positive pressure signal and a battery negative pressure signal, the battery selection circuit is used to select one of the plurality of battery cells to be electrically connected to the voltage detection chip, and the reference generating circuit is used to generate a reference positive pressure signal and a reference negative pressure signal.

[0014] In a third aspect, an embodiment of the present application provides an electronic device, comprising the battery.

[0015] In the embodiment of the present application, a voltage detection chip is designed, and the first voltage generating circuit and the second voltage generating circuit can receive and generate high-level signals to form a high-voltage device; the third voltage generating circuit, the fourth voltage generating circuit, the first switch circuit, the second switch circuit and the comparison circuit are all low-voltage devices. In this way, the voltage detection chip provided by the present application uses fewer high-voltage devices, and the high-voltage devices require a larger area of ​​the voltage detection chip due to the need to set up isolation devices. Therefore, by setting up fewer high-voltage devices, the area of ​​the voltage detection chip can be effectively reduced. Moreover, there is no need to set up a high-voltage to low-voltage circuit, so there is no need to introduce additional power consumption and errors, which can effectively improve the accuracy of voltage detection, reduce power consumption and reduce chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 This is a structural diagram of an application scenario of an electronic device combined with a charging cable and a charger provided in an embodiment of the present application;

[0018] Figure 2 is a schematic diagram of the structure of a battery provided in an embodiment of the present application;

[0019] Figure 3 It is a circuit structure diagram of a voltage detection chip provided in an embodiment of the present application;

[0020] Figure 4is a circuit structure diagram of another voltage detection chip provided in an embodiment of the present application;

[0021] Figure 5 yes Figure 4 The clock signal diagram of the voltage detection chip provided;

[0022] Figure 6 Schematic diagram of the circuit structure of the high-voltage selection switch circuit provided in the embodiment of the present application. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. The embodiments listed in the present application can be appropriately combined with each other without conflicting with each other.

[0024] With the development of technology, the functions of electronic devices (such as smartphones, wearable devices, tablets, etc.) have become more and more powerful. Users can use electronic devices for work and entertainment, so that electronic devices have become an indispensable part of people's daily life. However, the battery life of electronic devices is limited, and users need to charge them continuously. In order to ensure that users can use electronic devices normally, fast charging has become a mainstream charging solution.

[0025] At present, common fast charging technologies can be divided into two categories: low-voltage high-current fast charging technology and high-voltage low-current fast charging technology. Regardless of low-voltage high-current fast charging or high-voltage low-current fast charging, when input to the battery in the charging circuit of the electronic device, it will be converted into a larger charging current (the charging current cannot exceed the maximum safe charging current carried by the battery or the safe charging current that does not damage the battery life). At this time, it is particularly important to ensure the charging safety of fast charging when charging the battery with a large current. It should be noted that high voltage is a voltage greater than 5V.

[0026] See also Figure 1 , Figure 1 This is an application scenario applicable to the embodiments of the present application. Figure 1The scene shown includes an electronic device 100, a charging cable 200 and a charger 300. The electronic device 100 includes, but is not limited to, rechargeable electronic products such as mobile phones, laptops, PDAs, rechargeable headphones, rechargeable speakers, rechargeable wearable devices, robots, rechargeable home appliances, rechargeable vehicles, and rechargeable transportation vehicles. The charger 300 is electrically connected to the electronic device 100 through the charging cable 200. The electronic device 100 includes at least a battery 10, a connection interface 20, a charging management chip 30, and a load 40. The connection interface 20 is electrically connected to the charging management chip 30. The battery 10 is electrically connected to the charging management chip 30 and the load 40, respectively. Among them, the battery 10 includes a battery protection board 101 and a battery cell 102. The load 40 can be a power-consuming device in the electronic device 100. For example, the load 40 can be various power-consuming devices such as microphones, cameras, display screens, motors, etc. The charging management chip 30 is a chip that manages the charging of the battery 10. During charging, the current flows as follows: charger 300 → charging line 200 → connection interface 20 → charging management chip 30 → battery protection board 101 → battery cell 102. During discharging, the current flows as follows: battery cell 102 → battery protection board 101 → load 40.

[0027] During the charging and discharging process of the battery 10, especially in the field of fast charging technology, voltage detection of the battery 10 becomes a research focus. Generally, a voltage detection chip is designed to detect the voltage of the battery 10 during the charging and discharging process.

[0028] See also Figure 2 The present application provides a voltage detection chip 1, which is suitable for high-voltage detection fields such as protection of one or more batteries 10. The batteries 10 include but are not limited to lithium-ion batteries, metal lithium batteries, etc. In particular, for voltage detection in the protection of multiple batteries 10, since the potential of the multiple batteries 10 is relatively high, the voltage detection needs to be performed at the high-voltage end or compared at the low-voltage end through a high-voltage to low-voltage circuit. High-voltage end detection requires a high-voltage reference and a high-voltage comparator. High-voltage devices waste area. The high-voltage reference requires additional circuits to generate and consumes additional power. The high-voltage to low-voltage circuit also consumes additional power and introduces certain errors. Under the current background trend of low-power applications, reducing power consumption and reducing chip area are both of great significance.

[0029] See also Figure 2 The voltage detection chip 1 can be disposed on the battery protection board 101 of the battery 10, or can be disposed in the electronic device 100 and located outside the battery 10 (for example, on the main board of the electronic device 100), or can be disposed in the charger 300 (see Figure 1). The embodiment of the present application takes the voltage detection chip 1 as an example of being arranged on the battery protection board 101. The voltage detection chip 1 is used to monitor the voltage information of the battery 10, and when the voltage reaches the protection threshold, the corresponding charge and discharge transistor is turned off to achieve the purpose of protecting the battery 10.

[0030] See also Figure 3 A voltage detection chip 1 provided in an embodiment of the present application can be used for overvoltage detection during the charging and discharging processes of a battery 10.

[0031] See also Figure 3 The voltage detection chip 1 at least includes a first voltage generating circuit 11 , a second voltage generating circuit 12 , a third voltage generating circuit 13 , a fourth voltage generating circuit 14 , a comparison circuit 15 , a first switch circuit 16 and a second switch circuit 17 .

[0032] The first voltage generating circuit 11 is used to select one of the battery positive voltage signal CELLP and the battery negative voltage signal CELLN and generate a first output signal. The second voltage generating circuit 12 is used to select the other of the battery positive voltage signal CELLP and the battery negative voltage signal CELLN and generate a second output signal. The third voltage generating circuit 13 is used to select one of the reference positive voltage signal VREFP and the reference negative voltage signal VREFN and generate a third output signal. The fourth voltage generating circuit 14 is used to select the other of the reference positive voltage signal VREFP and the reference negative voltage signal VREFN and generate a fourth output signal.

[0033] It can be understood that the battery positive pressure signal CELLP is a signal output from the positive terminal of the battery cell 102 , and the battery negative pressure signal CELLN is a signal output from the negative terminal of the battery cell 102 .

[0034] Optionally, the first voltage generating circuit 11 selects the battery positive voltage signal CELLP and outputs a first output signal. The first output signal may be the battery positive voltage signal CELLP, or may be generated by the battery positive voltage signal CELLP. The second voltage generating circuit 12 selects the battery negative voltage signal CELLN and outputs a second output signal. The second output signal may be the battery negative voltage signal CELLN, or may be generated by the battery negative voltage signal CELLN.

[0035] Optionally, the first voltage generating circuit 11 selects the battery negative voltage signal CELLN and outputs a first output signal. The first output signal may be the battery negative voltage signal CELLN, or may be generated by the battery negative voltage signal CELLN. The second voltage generating circuit 12 selects the battery positive voltage signal CELLP and outputs a second output signal. The second output signal may be the battery positive voltage signal CELLP, or may be generated by the battery positive voltage signal CELLP.

[0036] Optionally, the third voltage generating circuit 13 selects the reference positive voltage signal VREFP and outputs a third output signal. The third output signal may be the reference positive voltage signal VREFP, or may be generated by the reference positive voltage signal VREFP. The fourth voltage generating circuit 14 selects the reference negative voltage signal VREFN and outputs a fourth output signal. The fourth output signal may be the reference negative voltage signal VREFN, or may be generated by the reference negative voltage signal VREFN.

[0037] Optionally, the third voltage generating circuit 13 selects the reference negative voltage signal VREFN and outputs a third output signal. The third output signal may be the reference negative voltage signal VREFN, or may be generated by the reference negative voltage signal VREFN. The fourth voltage generating circuit 14 selects the reference positive voltage signal VREFP and outputs a fourth output signal. The fourth output signal may be the reference positive voltage signal VREFP, or may be generated by the reference positive voltage signal VREFP.

[0038] Optional, see Figure 3 , the comparison circuit 15 is a comparator. The comparison circuit 15 includes a first input terminal 151, a second input terminal 152 and an output terminal 153. Optionally, the first input terminal 151 is a positive input terminal, and the second input terminal 152 is a negative input terminal; or, the first input terminal 151 is a negative input terminal, and the second input terminal 152 is a positive input terminal. In the embodiment of the present application, the first input terminal 151 is a positive input terminal, and the second input terminal 152 is a negative input terminal.

[0039] See also Figure 3 , the first input terminal 151 of the comparison circuit 15 is electrically connected to the output terminal of the first voltage generating circuit 11, and the first input terminal 151 of the comparison circuit 15 is electrically connected to the output terminal of the third voltage generating circuit 13. The second input terminal 152 of the comparison circuit 15 is electrically connected to the output terminal of the second voltage generating circuit 12, and the second input terminal 152 of the comparison circuit 15 is electrically connected to the output terminal of the fourth voltage generating circuit 14. In this way, the first output signal and the third output signal are combined to form the voltage signal of the first input terminal 151 of the comparison circuit 15. The second output signal and the fourth output signal are combined to form the voltage signal of the second input terminal 152 of the comparison circuit 15.

[0040] See also Figure 3, the first switch circuit 16 is electrically connected to the first input terminal 151 of the comparison circuit 15 to control the reference positive voltage signal VREFP to be input to the first input terminal 151. When the first switch circuit 16 is turned on, the first input terminal 151 is loaded with the reference positive voltage signal VREFP; when the first switch circuit 16 is turned off, the first input terminal 151 is no longer loaded with the reference positive voltage signal VREFP from the first switch circuit 16. In this way, when the first switch circuit 16 is turned on, the first switch circuit 16 is turned on and loaded with the reference positive voltage signal VREFP, the first output signal and the third output signal to synthesize the voltage signal of the first input terminal 151 of the comparison circuit 15.

[0041] See also Figure 3 , two ends of the second switch circuit 17 are electrically connected to the second input end 152 of the comparison circuit 15 and the output end 153 of the comparison circuit 15, respectively, to control the on-off between the second input end 152 of the comparison circuit 15 and the output end 153 of the comparison circuit 15. When the second switch circuit 17 is turned on, the second input end 152 of the comparison circuit 15 is electrically connected to the output end 153 of the comparison circuit 15, and the comparison circuit 15 forms a feedback structure to sample the offset voltage of the comparison circuit 15 to eliminate the offset of the comparison circuit 15.

[0042] The comparison circuit 15 is used to output a detection signal according to the difference between the voltage signal received by the first input terminal 151 and the voltage signal received by the second input terminal 152, which is used to indicate whether the charging and discharging process of the battery 10 is overvoltage. Specifically, the comparison circuit 15 can compare the voltage signal received by the first input terminal 151 and the voltage signal received by the second input terminal 152, and output a detection signal when the voltage signal value of the first input terminal 151 is greater than the voltage signal of the second input terminal 152. The detection signal can be a high level or a low level. The detection signal is used to control the charging transistor of the charging and discharging circuit of the battery 10 to disconnect and the discharging transistor to turn on, so that the battery 10 ends the charging mode and converts to the dischargeable mode, so as to protect the battery 10 from charging overvoltage; or the detection signal is used to control the discharging transistor of the charging and discharging circuit of the battery 10 to disconnect and the charging transistor to turn on, so that the battery 10 ends the discharge mode and converts to the chargeable mode, so as to protect the battery 10 from discharging overvoltage.

[0043] Optionally, the battery positive pressure signal CELLP and the battery negative pressure signal CELLN are both high-level signals. Optionally, the frequency of the battery positive pressure signal CELLP is different from the frequency of the battery negative pressure signal CELLN. Optionally, the amplitude of the battery positive pressure signal CELLP is different from the amplitude of the battery negative pressure signal CELLN. Optionally, the amplitude and frequency of the battery positive pressure signal CELLP are different from the amplitude and frequency of the battery negative pressure signal CELLN. The reference positive pressure signal VREFP and the reference negative pressure signal VREFN are both low-level signals. Optionally, the frequency of the reference positive pressure signal VREFP is different from the frequency of the reference negative pressure signal VREFN. Optionally, the amplitude of the reference positive pressure signal VREFP is different from the amplitude of the reference negative pressure signal VREFN. Optionally, the amplitude and frequency of the reference positive pressure signal VREFP are different from the amplitude and frequency of the reference negative pressure signal VREFN.

[0044] In this way, the voltage detection chip 1 provided in the present application can perform high voltage detection. Among them, in this embodiment, a voltage signal less than 5V is a low-level signal, and a voltage signal greater than or equal to 5V is a high-level signal. Furthermore, the present application does not specifically limit the voltage values ​​of the battery positive pressure signal CELLP and the battery negative pressure signal CELLN, which can be 5V to 1000V. Of course, in other embodiments, the battery positive pressure signal CELLP and the battery negative pressure signal CELLN can also be low-level signals.

[0045] In the embodiment of the present application, by designing the voltage detection chip 1, only the first voltage generating circuit 11 and the second voltage generating circuit 12 receive and generate high-level signals, and are high-voltage devices; the third voltage generating circuit 13, the fourth voltage generating circuit 14, the first switch circuit 16, the second switch circuit 17 and the comparison circuit 15 are all low-voltage devices. In this way, the voltage detection chip 1 provided by the present application uses fewer high-voltage devices, and the high-voltage devices require a larger area of ​​the voltage detection chip 1 due to the need to set up isolation devices, etc. Therefore, by setting up fewer high-voltage devices, the area of ​​the voltage detection chip 1 can be effectively reduced. Moreover, there is no need to set up a high-voltage to low-voltage circuit, so there is no need to introduce additional power consumption and errors, which can effectively improve the accuracy of voltage detection, reduce power consumption and reduce chip area.

[0046] In one possible implementation, see Figure 4, the first voltage generating circuit 11 includes a first selection circuit 111 and a first storage capacitor 112. The first selection circuit 111 is used to select and output one of the battery positive voltage signal CELLP and the battery negative voltage signal CELLN. One end of the first storage capacitor 112 is electrically connected to the output end of the first selection circuit 111. The other end of the first storage capacitor 112 is electrically connected to the first input end 151 of the comparison circuit 15.

[0047] See also Figure 4 The second voltage generating circuit 12 includes a second selection circuit 121 and a second storage capacitor 122. The second selection circuit 121 is used to select and output the other of the battery positive voltage signal CELLP and the battery negative voltage signal CELLN. One end of the second storage capacitor 122 is electrically connected to the output end of the second selection circuit 121. The other end of the second storage capacitor 122 is electrically connected to the second input end 152 of the comparison circuit 15.

[0048] See also Figure 4 The third voltage generating circuit 13 includes a third selection circuit 131 and a third storage capacitor 132. The third selection circuit 131 is used to select and output one of the reference positive voltage signal VREFP and the reference negative voltage signal VREFN. One end of the third storage capacitor 132 is electrically connected to the output end of the third selection circuit 131. The other end of the third storage capacitor 132 is electrically connected to the first input end 151 of the comparison circuit 15.

[0049] See also Figure 4 The fourth voltage generating circuit 14 includes a fourth selection circuit 141 and a fourth storage capacitor 142. The fourth selection circuit 141 is used to select and output the other of the reference positive voltage signal VREFP and the reference negative voltage signal VREFN. One end of the fourth storage capacitor 142 is electrically connected to the output end of the fourth selection circuit 141. The other end of the fourth storage capacitor 142 is electrically connected to the second input end 152 of the comparison circuit 15.

[0050] The capacity C1 of the first storage capacitor 112 is equal to the capacity C2 of the second storage capacitor 122. The capacity C3 of the third storage capacitor 132 is equal to the capacity C4 of the fourth storage capacitor 142.

[0051] The first storage capacitor 112 combines with the first selection circuit 111 to sample between the battery positive voltage signal CELLP and the battery negative voltage signal CELLN. The second storage capacitor 122 combines with the second selection circuit 121 to sample between the battery positive voltage signal CELLP and the battery negative voltage signal CELLN. The sampling signals of the first storage capacitor 112 and the second storage capacitor 122 are different. Moreover, the capacity of the first storage capacitor 112 is equal to the capacity of the second storage capacitor 122, so that the first voltage generating circuit 11 and the second voltage generating circuit 12 form a fully differential structure to eliminate the common mode noise in the comparison circuit 15, improve the comparison result of the comparison circuit 15, and thereby improve the accuracy of the overvoltage protection threshold of the voltage detection chip 1, and reduce the overvoltage protection error.

[0052] Further, the third storage capacitor 132 combines with the third selection circuit 131 to sample between the reference positive voltage signal VREFP and the reference negative voltage signal VREFN. The fourth storage capacitor 142 combines with the fourth selection circuit 141 to sample between the reference positive voltage signal VREFP and the reference negative voltage signal VREFN. The sampling signals of the third storage capacitor 132 and the fourth storage capacitor 142 are different. Moreover, the capacity of the third storage capacitor 132 is equal to the capacity of the fourth storage capacitor 142, so that the first voltage generating circuit 11, the third voltage generating circuit 13 and the second voltage generating circuit 12, the fourth voltage generating circuit 14 form a fully differential structure to eliminate the common mode noise in the comparison circuit 15, improve the comparison result of the comparison circuit 15, and further improve the accuracy of the overvoltage protection threshold of the voltage detection chip 1, and reduce the overvoltage protection error.

[0053] See also Figure 4 , the first selection circuit 111 includes a third switch circuit 113 and a fourth switch circuit 114. One end of the third switch circuit 113 is used to receive the battery positive voltage signal CELLP. The other end of the third switch circuit 113 is electrically connected to the first storage capacitor 112. One end of the fourth switch circuit 114 is used to receive the battery negative voltage signal CELLN, and control the battery negative voltage signal CELLN to input into the first storage capacitor 112. When the third switch circuit 113 is turned on and the fourth switch circuit 114 is turned off, the first selection circuit 111 selects the battery positive voltage signal CELLP, and the first storage capacitor 112 inputs the battery positive voltage signal CELLP. When the third switch circuit 113 is turned off and the fourth switch circuit 114 is turned on, the first selection circuit 111 selects the battery negative voltage signal CELLN, and the first storage capacitor 112 inputs the battery negative voltage signal CELLN.

[0054] See also Figure 4, the second selection circuit 121 includes a fifth switch circuit 123 and a sixth switch circuit 124. One end of the fifth switch circuit 123 is used to receive the battery negative voltage signal CELLN. The other end of the fifth switch circuit 123 is electrically connected to the second storage capacitor 122. One end of the sixth switch circuit 124 is used to receive the battery positive voltage signal CELLP. The other end of the sixth switch circuit 124 is electrically connected to the second storage capacitor 122. When the fifth switch circuit 123 is turned on and the sixth switch circuit 124 is turned off, the second selection circuit 121 selects the battery negative voltage signal CELLN, and the first storage capacitor 112 inputs the battery negative voltage signal CELLN. When the fifth switch circuit 123 is turned off and the sixth switch circuit 124 is turned on, the second selection circuit 121 selects the battery positive voltage signal CELLP, and the second storage capacitor 122 inputs the battery positive voltage signal CELLP.

[0055] See also Figure 4 , the third selection circuit 131 includes a seventh switch circuit 133 and an eighth switch circuit 134. One end of the seventh switch circuit 133 is used to receive the reference positive voltage signal VREFP. The other end of the seventh switch circuit 133 is electrically connected to the third storage capacitor 132. One end of the eighth switch circuit 134 is used to receive the reference negative voltage signal VREFN. The other end of the eighth switch circuit 134 is electrically connected to the third storage capacitor 132. When the seventh switch circuit 133 is turned on and the eighth switch circuit 134 is turned off, the third selection circuit 131 selects the reference positive voltage signal VREFP, and the third storage capacitor 132 inputs the reference positive voltage signal VREFP. When the seventh switch circuit 133 is turned off and the eighth switch circuit 134 is turned on, the third selection circuit 131 selects the reference negative voltage signal VREFN, and the third storage capacitor 132 inputs the reference negative voltage signal VREFN.

[0056] See also Figure 4 , the fourth selection circuit 141 includes a ninth switch circuit 143 and a tenth switch circuit 144. One end of the ninth switch circuit 143 is used to receive the reference negative voltage signal VREFN. The other end of the ninth switch circuit 143 is electrically connected to the fourth storage capacitor 142. One end of the tenth switch circuit 144 is used to receive the reference positive voltage signal VREFP. The other end of the tenth switch circuit 144 is electrically connected to the fourth storage capacitor 142. When the ninth switch circuit 143 is turned on and the tenth switch circuit 144 is turned off, the fourth selection circuit 141 selects the reference negative voltage signal VREFN, and the fourth storage capacitor 142 inputs the reference negative voltage signal VREFN. When the ninth switch circuit 143 is turned off and the tenth switch circuit 144 is turned on, the fourth selection circuit 141 selects the reference positive voltage signal VREFP, and the fourth storage capacitor 142 inputs the reference positive voltage signal VREFP.

[0057] The embodiment of the present application designs a voltage detection chip 1, uses a high-voltage switch (third switch circuit 113, fourth switch circuit 114, fifth switch circuit 123, sixth switch circuit 124) to sample high voltage, and uses a low-voltage switch (first switch circuit 16, second switch circuit 17, seventh switch circuit 133, eighth switch circuit 134, ninth switch circuit 143, tenth switch circuit 144) to sample low voltage, and the voltage comparison is also in the comparison circuit 15 at the low voltage end, only a small number of high-voltage switches are used, and there is no need to use a high-voltage reference and a high-voltage comparator that occupy a large area, which can effectively reduce the area occupied by the entire detection circuit. Since the voltage comparison occurs at the low voltage end and there is no need to set a low-voltage conversion circuit, power consumption can be reduced. The voltage detection chip 1 has a simple structure, and only the high-voltage switch selection is used at the high voltage end, which greatly reduces the area of ​​the voltage detection chip 1, saves power consumption, and can also achieve a higher voltage detection accuracy.

[0058] Moreover, the voltage detection chip 1 uses a switch circuit and a storage capacitor to implement high voltage sampling and comparison. The switch circuit and the storage capacitor sampling are fully differential structures, that is, the third switch circuit 113, the fourth switch circuit 114, the seventh switch circuit 133, the eighth switch circuit 134 and the fifth switch circuit 123, the sixth switch circuit 124, the ninth switch circuit 143, and the tenth switch circuit 144 adopt a mirror symmetric design, the first storage capacitor 112 and the second storage capacitor 122 have the same capacity, and the third storage capacitor 132 and the fourth storage capacitor 142 have the same capacity, so as to eliminate the common mode noise in the comparison and improve the accuracy of the voltage comparison result.

[0059] See also Figure 5 , the voltage detection chip 1 also includes a clock signal generating circuit (not shown). The clock signal generating circuit is used to generate a first clock signal CK1 and a second clock signal CK2. The first clock signal CK1 and the second clock signal CK2 are signals with a phase difference of 180°. When the first clock signal CK1 is a low level signal, the second clock signal CK2 is a high level signal. When the first clock signal CK1 is a high level signal, the second clock signal CK2 is a low level signal.

[0060] See also Figure 5 , the first clock signal CK1 and the second clock signal CK2 are clock signals for triggering low-voltage devices. The first clock signal CK1 is amplified by voltage amplitude to form a clock signal CK1H that can trigger high-voltage devices. Among them, the clock signal CK1H is in phase with the first clock signal CK1. The second clock signal CK2 is amplified by voltage amplitude to form a clock signal CK2H that can trigger high-voltage devices. The clock signal CK2H is in phase with the second clock signal CK2. For ease of description, CK1H is named the third clock signal. CK2H is named the fourth clock signal.

[0061] The first clock signal CK1 is used to control the on and off of the first switch circuit 16 and the second switch circuit 17. Specifically, the first switch circuit 16 and the second switch circuit 17 are turned on or off under the action of the first clock signal CK1. The first switch circuit 16 can be a transistor or a pair of transistors. The second switch circuit 17 can be a transistor or a pair of transistors. The gate of the first switch circuit 16 and the gate of the second switch circuit 17 are electrically connected to the first output terminal of the clock signal generating circuit to receive the first clock signal CK1.

[0062] Optionally, when the first clock signal CK1 is a high-level signal, the first switch circuit 16 and the second switch circuit 17 are turned on, and "turned on" means that the source and the drain of the transistor are turned on; when the first clock signal CK1 is a low-level signal, the first switch circuit 16 and the second switch circuit 17 are turned off, and "turned off" means that the source and the drain of the transistor are turned off. Optionally, when the first clock signal CK1 is a low-level signal, the first switch circuit 16 and the second switch circuit 17 are turned on; when the first clock signal CK1 is a high-level signal, the first switch circuit 16 and the second switch circuit 17 are turned off. It should be noted that a high-level signal in a clock signal represents "1" in a digital logic circuit. A low-level signal in a clock signal represents "0" in a digital logic circuit, which will not be described in detail later.

[0063] The third clock signal CK1H is used to control the third switch circuit 113 and the fifth switch circuit 123; the first clock signal CK1 is also used to control the seventh switch circuit 133 and the ninth switch circuit 143, etc. Specifically, the third switch circuit 113 and the fifth switch circuit 123 are simultaneously turned on or off under the action of the third clock signal CK1H; the seventh switch circuit 133 and the ninth switch circuit 143 are simultaneously turned on or off under the action of the first clock signal CK1.

[0064] The third switch circuit 113, the fifth switch circuit 123, the seventh switch circuit 133, and the ninth switch circuit 143 can all be one transistor or two transistors. The third switch circuit 113, the fifth switch circuit 123, the seventh switch circuit 133, and the ninth switch circuit 143 are electrically connected to the second output terminal of the clock signal generating circuit to receive the third clock signal CK1H and the first clock signal CK1.

[0065] Optionally, when the first clock signal CK1 and the third clock signal CK1H are high-level signals, the third switch circuit 113, the fifth switch circuit 123, the seventh switch circuit 133, and the ninth switch circuit 143 are turned on; when the first clock signal CK1 and the third clock signal CK1H are low-level signals, the third switch circuit 113, the fifth switch circuit 123, the seventh switch circuit 133, and the ninth switch circuit 143 are turned off. Optionally, when the first clock signal CK1 and the third clock signal CK1H are low-level signals, the third switch circuit 113, the fifth switch circuit 123, the seventh switch circuit 133, and the ninth switch circuit 143 are turned on; when the first clock signal CK1 and the third clock signal CK1H are high-level signals, the third switch circuit 113, the fifth switch circuit 123, the seventh switch circuit 133, and the ninth switch circuit 143 are turned off.

[0066] The fourth clock signal CK2H is used to control the fourth switch circuit 114 and the sixth switch circuit 124; the second clock signal CK2 is used to control the eighth switch circuit 134 and the tenth switch circuit 144, etc. Specifically, the fourth switch circuit 114 and the sixth switch circuit 124 are simultaneously turned on or off under the action of the fourth clock signal CK2H; the eighth switch circuit 134 and the tenth switch circuit 144 are simultaneously turned on or off under the action of the second clock signal CK2.

[0067] The fourth switch circuit 114, the sixth switch circuit 124, the eighth switch circuit 134, and the tenth switch circuit 144 can all be one transistor or two transistors. The fourth switch circuit 114, the sixth switch circuit 124, the eighth switch circuit 134, and the tenth switch circuit 144 are electrically connected to the third output terminal of the clock signal generating circuit to receive the fourth clock signal CK2H and the second clock signal CK2.

[0068] Optionally, when the second clock signal CK2 and the fourth clock signal CK2H are high-level signals, the fourth switch circuit 114, the sixth switch circuit 124, the eighth switch circuit 134, and the tenth switch circuit 144 are turned on; when the second clock signal CK2 and the fourth clock signal CK2H are low-level signals, the fourth switch circuit 114, the sixth switch circuit 124, the eighth switch circuit 134, and the tenth switch circuit 144 are turned off. Optionally, when the second clock signal CK2 and the fourth clock signal CK2H are low-level signals, the fourth switch circuit 114, the sixth switch circuit 124, the eighth switch circuit 134, and the tenth switch circuit 144 are turned on; when the second clock signal CK2 and the fourth clock signal CK2H are high-level signals, the fourth switch circuit 114, the sixth switch circuit 124, the eighth switch circuit 134, and the tenth switch circuit 144 are turned off.

[0069] The action phases of the first clock signal CK1 and the second clock signal CK2 include the first phase t1 and the second phase t2 in sequence. The first clock signal CK1 acts on the first switch circuit 16 and the second switch circuit 17 slightly earlier than the third switch circuit 113 and the fifth switch circuit 123, so as to eliminate the charge injection caused by the conduction of the first switch circuit 16 and the second switch circuit 17 and improve the accuracy of voltage detection. The first phase t1 is the sampling phase. The second phase t2 is the voltage comparison phase.

[0070] The first stage t1: the first clock signal CK1 and the third clock signal CK1H are high level signals, and the second clock signal CK2 and the fourth clock signal CK2H are low level signals. The first clock signal CK1 is used to control the first switch circuit 16 to be turned on and the second switch circuit 17 to be turned on, so that the first input terminal 151 inputs the reference positive voltage signal VREFP. The second input terminal 152 inputs the reference positive voltage signal VREFP and the offset signal of the comparison circuit 15.

[0071] In the first stage t1, the third clock signal CK1H is used to control the third switch circuit 113 and the fifth switch circuit 123 to be turned on; the first clock signal CK1 is used to control the seventh switch circuit 133 and the ninth switch circuit 143 to be turned on. The fourth clock signal CK2H is used to control the fourth switch circuit 114 and the sixth switch circuit 124 to be turned off; the second clock signal CK2 is used to control the eighth switch circuit 134 and the tenth switch circuit 144 to be turned off.

[0072] In the first stage t1, the first storage capacitor 112 samples the battery positive voltage signal CELLP, and the second storage capacitor 122 samples the battery positive voltage signal CELLP. The third storage capacitor 132 samples the reference positive voltage signal VREFP, and the fourth storage capacitor 142 samples the reference positive voltage signal VREFP. At this time, the comparison circuit 15 forms a feedback structure. The output signal VOUT of the output terminal 153 of the comparison circuit 15 is connected to the second input terminal 152 of the comparison circuit 15. The offset voltage of the comparison circuit 15 is sampled to eliminate the offset of the comparison circuit 15. The input signal of the first input terminal 151 of the comparison circuit 15 is VREFP. The input signal of the second input terminal 152 of the comparison circuit 15 is VREFP+VOS. Among them, VOS is the offset voltage of the comparison circuit 15.

[0073] Second stage t2: Optionally, the first clock signal CK1 and the third clock signal CK1H are low-level signals, and the second clock signal CK2 and the fourth clock signal CK2H are high-level signals. The first clock signal CK1 is used to control the first switch circuit 16 to be disconnected and the second switch circuit 17 to be disconnected. The third clock signal CK1H is used to control the third switch circuit 113 and the fifth switch circuit 123 to be disconnected. The first clock signal CK1 is also used to control the seventh switch circuit 133 and the ninth switch circuit 143 to be disconnected. The fourth clock signal CK2H is used to control the fourth switch circuit 114 and the sixth switch circuit 124. The second clock signal CK2 is used to control the eighth switch circuit 134 and the tenth switch circuit 144 to be turned on.

[0074] When the output voltage of the first selection circuit 111 changes from the battery positive voltage signal CELLP to the battery negative voltage signal CELLN, the voltage signal at the input end of the first storage capacitor 112 changes to the battery negative voltage signal CELLN. The charge change amount of the first storage capacitor 112 is C1*(CELLN-CELLP). When the output voltage of the third selection circuit 131 changes from the reference positive voltage signal VREFP to the reference negative voltage signal VREFN, the voltage signal at the input end of the third storage capacitor 132 changes to the reference negative voltage signal VREFN. The charge change amount of the third storage capacitor 132 is C3*(VREFN-VREFP). When the output voltage of the second selection circuit 121 changes from the battery negative voltage signal CELLN to the battery positive voltage signal CELLP, the voltage signal at the input end of the second storage capacitor 122 changes to the battery positive voltage signal CELLP, and the charge change amount of the second storage capacitor 122 is C2*(CELLP-CELLN). When the output voltage of the fourth selection circuit 141 changes from the reference negative voltage signal VREFN to the reference positive voltage signal VREFP, the voltage signal at the input end of the fourth storage capacitor 142 changes to the reference positive voltage signal VREFP. The charge change amount of the fourth storage capacitor 142 is C4*(VREFP-VREFN). According to the charge conservation law, the voltage of the first input end 151 of the comparison circuit 15 becomes:

[0075] VREFP+C1*(CELLN-CELLP) / (C1+C3)+C3*(VREFN-VREFP) / (C1+C3)

[0076] The voltage at the second input terminal 152 of the comparison circuit 15 becomes:

[0077] VREFP+C2*(CELLP-CELLN) / (C2+C4)+C4*(VREFP-VREFN) / (C2+C4)+VOS

[0078] Among them, C1=C2, C3=C4.

[0079] The voltage at the second input terminal 152 of the comparison circuit 15 becomes:

[0080] VREFP+C1*(CELLP-CELLN) / (C1+C3)+C3*(VREFP-VREFN) / (C1+C3)+VOS

[0081] When the first input terminal 151 of the comparison circuit 15 differs from the second input terminal 152 of the comparison circuit 15 by the offset voltage VOS, the comparison circuit 15 flips. Therefore, the flip point of the voltage CELLP-CELLN is: (VREFP-VREFN)*(C3 / C1). The “flip” means that the level of the output terminal 153 of the comparison circuit 15 is converted from a low level to a high level or from a high level to a low level.

[0082] As can be seen from the above, the voltage detection chip 1 realizes the voltage detection function, that is, it can be flipped when the voltage at the first input terminal 151 of the comparison circuit 15 differs from the voltage at the second input terminal 152 of the comparison circuit 15 by an offset voltage. Moreover, the flip point is determined by the ratio of the reference positive voltage signal VREFP, the reference negative voltage signal VREFN, the capacity C3 of the third storage capacitor 132, and the capacity C1 of the first storage capacitor 112. Since the reference positive voltage signal VREFP and the reference negative voltage signal VREFN are calibrated signals with high accuracy, and C3 and C1 are also determined values, the flip point of the comparison circuit 15 has high accuracy, so that the overvoltage protection of the voltage detection chip 1 is more accurate, and the reliability of the battery 10 is improved.

[0083] Furthermore, by adjusting the values ​​of C3 and C1, the voltage detection flip point can be adjusted to adjust the flexibility of the flipping of the comparison circuit 15.

[0084] The voltage detection chip 1 provided in the present application adopts a low-voltage circuit to implement the comparison circuit 15 and the sampling switch circuit for selecting the reference positive voltage signal VREFP and the reference negative voltage signal VREFN. Compared with setting a high-voltage circuit, the area occupied by the voltage detection chip 1 provided in the present application is reduced, there is no need to set a low-voltage conversion circuit, and power consumption is reduced.

[0085] In one possible implementation, see Figure 6 The voltage detection chip 1 further includes a first charge pump capacitor 21 , a second charge pump capacitor 22 , a third charge pump capacitor 23 and a fourth charge pump capacitor 24 .

[0086] See also Figure 6, the first charge pump capacitor 21 is used to receive the first clock signal CK1, and generate a first excitation signal under the stimulation of the first clock signal CK1, and transmit the first excitation signal to the fourth switch circuit 114 and the fifth switch circuit 123. Specifically, the first charge pump capacitor 21 is also called a switched capacitor voltage converter. The first charge pump capacitor 21 is used to increase the voltage amplitude of the first clock signal CK1 to generate a first excitation signal. The first excitation signal may be a third clock signal CK1H. It can be understood that the voltage amplitudes of the first clock signal CK1 and the second clock signal CK2 are relatively low-level signals. Through the charge pump capacitor, a clock signal with a higher voltage amplitude, the third clock signal CK1H, can be generated to trigger the conduction and disconnection of the transistor in the high-voltage switch circuit. When the first clock signal CK1 is a relatively low-amplitude voltage signal, the first charge pump capacitor 21 generates a first excitation signal with a relatively high voltage amplitude by increasing the amplitude of the first clock signal CK1. Optionally, the voltage amplitude of the first clock signal CK1 is less than 5V, and the voltage amplitude of the first excitation signal is 5V.

[0087] See also Figure 6 , the second charge pump capacitor 22 is used to receive the first clock signal CK1, and generate a second excitation signal under the stimulation of the first clock signal CK1, and transmit the second excitation signal to the third switch circuit 113 and the sixth switch circuit 124. Specifically, the second charge pump capacitor 22 is also called a switched capacitor voltage converter. The second charge pump capacitor 22 is used to increase the amplitude of the first clock signal CK1 to generate a second excitation signal. The second excitation signal may be the third clock signal CK1H. When the first clock signal CK1 is a relatively low amplitude voltage signal, the second charge pump capacitor 22 generates a relatively high voltage second excitation signal by increasing the amplitude of the first clock signal CK1. Optionally, the voltage amplitude of the first clock signal CK1 is less than 5V, and the voltage amplitude of the second excitation signal is 5V.

[0088] See also Figure 6, the third charge pump capacitor 23 is used to receive the second clock signal CK2, and generate a third excitation signal under the stimulation of the second clock signal CK2, and transmit the third excitation signal to the fourth switch circuit 114 and the fifth switch circuit 123. Specifically, the third charge pump capacitor 23 is also called a switched capacitor voltage converter. The third charge pump capacitor 23 is used to increase the amplitude of the second clock signal CK2 to generate a third excitation signal. The third excitation signal may be the fourth clock signal CK2H. When the second clock signal CK2 is a relatively low-amplitude voltage signal, the third charge pump capacitor 23 generates a third excitation signal with a relatively high voltage amplitude by increasing the amplitude of the second clock signal CK2. Optionally, the voltage amplitude of the second clock signal CK2 is less than 5V, and the voltage amplitude of the third excitation signal is 5V.

[0089] See also Figure 6 , the fourth charge pump capacitor 24 is used to receive the second clock signal CK2, and generate a fourth excitation signal under the stimulation of the second clock signal CK2, and transmit the fourth excitation signal to the third switch circuit 113 and the sixth switch circuit 124. Specifically, the fourth charge pump capacitor 24 is also called a switched capacitor voltage converter. The fourth charge pump capacitor 24 is used to increase the amplitude of the second clock signal CK2 to generate a fourth excitation signal. The fourth excitation signal may be a fourth clock signal CK2H. When the second clock signal CK2 is a relatively low voltage amplitude signal, the fourth charge pump capacitor 24 generates a fourth excitation signal with a relatively high voltage amplitude by increasing the amplitude of the second clock signal CK2. Optionally, the voltage amplitude of the second clock signal CK2 is less than 5V, and the voltage amplitude of the fourth excitation signal is 5V.

[0090] See also Figure 6 , the fourth switch circuit 114 includes a first switch tube 115 and a second switch tube 116. The source of the first switch tube 115 is electrically connected to the output end of the first charge pump capacitor 21 to receive the first excitation signal. The gate of the first switch tube 115 and the gate of the second switch tube 116 are both electrically connected to the output end of the third charge pump capacitor 23 to receive the third excitation signal. The drain of the first switch tube 115 and the source of the second switch tube 116 are both used to receive the battery negative voltage signal CELLN. The drain of the second switch tube 116 is electrically connected to the input end of the first storage capacitor 112. The first switch tube 115 and the second switch tube 116 can receive and conduct high-level signals.

[0091] See also Figure 6, the third switch circuit 113 includes a third switch tube 117 and a fourth switch tube 118. The source of the third switch tube 117 is electrically connected to the output end of the third charge pump capacitor 23 to receive the third excitation signal. The gate of the third switch tube 117 and the gate of the fourth switch tube 118 are both electrically connected to the output end of the fourth charge pump capacitor 24 to receive the fourth excitation signal. The drain of the third switch and the source of the fourth switch tube 118 are both used to receive the battery positive voltage signal CELLP. The drain of the fourth switch tube 118 is electrically connected to the input end of the first storage capacitor 112. The third switch tube 117 and the fourth switch tube 118 can receive and conduct high-level signals.

[0092] See also Figure 6 , the fifth switch circuit 123 includes a fifth switch tube 125 and a sixth switch tube 126. The source of the fifth switch tube 125 is electrically connected to the output end of the third charge pump capacitor 23 to receive the third excitation signal. The gate of the fifth switch tube 125 and the gate of the sixth switch tube 126 are both electrically connected to the output end of the first charge pump capacitor 21 to receive the first excitation signal. The drain of the fifth switch tube 125 and the source of the sixth switch tube 126 are both used to receive the battery negative voltage signal CELLN. The drain of the sixth switch tube 126 is electrically connected to the input end of the second storage capacitor 122. The fifth switch tube 125 and the sixth switch tube 126 can receive and conduct high-level signals.

[0093] See also Figure 6 , the sixth switch circuit 124 includes a seventh switch tube 127 and an eighth switch tube 128. The source of the seventh switch tube 127 is electrically connected to the output end of the fourth charge pump capacitor 24 to receive the fourth excitation signal. The gate of the seventh switch tube 127 and the gate of the eighth switch tube 128 are both electrically connected to the output end of the second charge pump capacitor 22 to receive the second excitation signal. The drain of the seventh switch and the source of the eighth switch tube 128 are both used to receive the battery positive voltage signal CELLP. The drain of the eighth switch tube 128 is electrically connected to the input end of the second storage capacitor 122. The seventh switch tube 127 and the eighth switch tube 128 can receive and conduct high-level signals.

[0094] The first clock signal CK1 and the second clock signal CK2 are both voltage signals with an amplitude less than 5 V. The first clock signal CK1 is excited by the first charge pump capacitor 21 to generate a voltage signal with an amplitude greater than or equal to 5 V, which is recorded as the first excitation signal. For example, the voltage amplitude of the first excitation signal is 5 V. The second clock signal CK2 is excited by the third charge pump capacitor 23 to generate a voltage signal with an amplitude greater than or equal to 5 V, which is recorded as the third excitation signal. For example, the voltage amplitude of the third excitation signal is 5 V.

[0095] The first switch tube 115 to the eighth switch tube 128 can be one of an N-type transistor and a P-type transistor. In this embodiment, the first switch tube 115, the second switch tube 116, the fifth switch tube 125 and the sixth switch tube 126 are all NMOS switches. The third switch tube 117, the fourth switch tube 118, the seventh switch tube 127 and the eighth switch tube 128 are all PMOS switches.

[0096] The battery positive voltage signal CELLP is selected by the third switch 117 , the fourth switch 118 , the seventh switch 127 and the eighth switch 128 , while the battery negative voltage signal CELLN is selected by the first switch 115 , the second switch 116 , the fifth switch 125 and the sixth switch 126 .

[0097] The clock generating circuit generates a first clock signal CK1 with a low amplitude voltage and a second clock signal CK2 with a low amplitude voltage, and generates a high level clock signal (VH) through the first charge pump capacitor 21 to the fourth charge pump capacitor 24 .

[0098] In other words, in the first stage t1, the first clock signal CK1 controls the switch tube of the seventh switch circuit 133 to be turned on, and the first clock signal CK1 controls the switch tube of the eighth switch circuit 134 to be turned off, so that the input end INP of the second storage capacitor 122 receives the battery negative pressure signal CELLN; the first clock signal CK1 controls the switch tube of the third switch circuit 113 to be turned on, and the first clock signal CK1 controls the switch tube of the fourth switch circuit 114 to be turned off, so that the input end INN of the first storage capacitor 112 receives the battery positive pressure signal CELLP.

[0099] In the second stage t2, the first clock signal CK1 controls the switch tube of the seventh switch circuit 133 to be disconnected, and the first clock signal CK1 controls the switch tube of the eighth switch circuit 134 to be turned on, so that the input end INP of the second storage capacitor 122 receives the battery positive pressure signal CELLP; the first clock signal CK1 controls the switch tube of the third switch circuit 113 to be disconnected, and the first clock signal CK1 controls the switch tube of the fourth switch circuit 114 to be turned on, so that the input end INN of the first storage capacitor 112 receives the battery negative pressure signal CELLN.

[0100] This structure realizes Figure 3 The high voltage switches in the third switch circuit 113, the fourth switch circuit 114, the fifth switch circuit 123 and the sixth switch circuit 124.

[0101] The embodiment of the present application also provides a battery 10. The battery 10 includes a plurality of battery cells (not shown), a battery selection circuit (not shown), a reference generation circuit (not shown) and the voltage detection chip 1. The battery cell may be a battery cell 102, or a battery after the battery cell 102 is packaged. In this embodiment, the battery cell is a battery cell 102. The plurality of battery cells may be arranged in series, or a part of the battery cells may be arranged in series and another part of the battery cells may be arranged in parallel, or the plurality of battery cells may be arranged in parallel. The battery cell is used to generate a battery positive voltage signal CELLP and a battery negative voltage signal CELLN. The battery selection circuit electrically connects the plurality of battery cells and the voltage detection chip 1. The battery selection circuit is used to select at least one of the plurality of battery cells to be electrically connected to the voltage detection chip 1. When the battery selection circuit selects one of the plurality of battery cells to be electrically connected to the voltage detection chip 1, the positive and negative electrodes of the selected battery cell generate a battery positive voltage signal CELLP and a battery negative voltage signal CELLN, respectively. The reference generation circuit is electrically connected to the third selection circuit 131 and the fourth selection circuit 141. The reference generating circuit is used for generating a reference positive voltage signal VREFP and a reference negative voltage signal VREFN.

[0102] In a possible application process, the battery selection circuit can periodically select each battery cell to be electrically connected to the voltage detection chip 1 under the control signal to perform voltage detection on each battery cell. In other embodiments, voltage detection can also be performed selectively on one battery cell.

[0103] The above is part of the implementation methods of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications are also considered to be within the scope of protection of the present application.

Claims

1. A voltage detection chip, used for overvoltage detection of a battery during charging and discharging, characterized in that: include: A first voltage generating circuit, configured to generate a first output signal according to one of a battery positive voltage signal and a battery negative voltage signal; a second voltage generating circuit, configured to generate a second output signal according to the other of the battery positive voltage signal and the battery negative voltage signal; A third voltage generating circuit, configured to generate a third output signal according to one of a reference positive voltage signal and a reference negative voltage signal; a fourth voltage generating circuit, configured to generate a fourth output signal according to the other of the reference positive voltage signal and the reference negative voltage signal; a comparison circuit, wherein a first input terminal of the comparison circuit is electrically connected to an output terminal of the first voltage generating circuit and to an output terminal of the third voltage generating circuit, and a second input terminal of the comparison circuit is electrically connected to an output terminal of the second voltage generating circuit and to an output terminal of the fourth voltage generating circuit; a first switch circuit, the first switch circuit being electrically connected to a first input terminal of the comparison circuit to control the reference positive pressure signal to be input to the first input terminal; and a second switch circuit, wherein two ends of the second switch circuit are electrically connected to the second input end of the comparison circuit and the output end of the comparison circuit respectively, so as to control the on-off between the second input end of the comparison circuit and the output end of the comparison circuit; The comparison circuit is used to output a detection signal according to the difference between the voltage signal received by the first input terminal and the voltage signal received by the second input terminal, and the detection signal is used to indicate whether the battery is over-voltage during the charging and discharging process.

2. The voltage detection chip according to claim 1, characterized in that: The battery positive pressure signal and the battery negative pressure signal are high-level signals with different frequencies and / or amplitudes, and the reference positive pressure signal and the reference negative pressure signal are low-level signals with different frequencies and / or amplitudes.

3. The voltage detection chip according to claim 1 or 2, characterized in that: The first voltage generating circuit includes a first selection circuit and a first storage capacitor, the first selection circuit is used to select and output one of a battery positive voltage signal and a battery negative voltage signal, one end of the first storage capacitor is electrically connected to the output end of the first selection circuit, and the other end of the first storage capacitor is electrically connected to the first input end; The second voltage generating circuit includes a second selection circuit and a second storage capacitor, the second selection circuit is used to select and output the other of the battery positive voltage signal and the battery negative voltage signal, the second storage capacitor is electrically connected to the output end of the second selection circuit, and the other end of the second storage capacitor is electrically connected to the second input end; The third voltage generating circuit comprises a third selection circuit and a third storage capacitor, wherein the third selection circuit is used to select and output one of the reference positive voltage signal and the reference negative voltage signal, the third storage capacitor is electrically connected to the output end of the third selection circuit, and the other end of the third storage capacitor is electrically connected to the first input end; The fourth voltage generating circuit includes a fourth selection circuit and a fourth storage capacitor. The fourth selection circuit is used to select and output the other of the reference positive voltage signal and the reference negative voltage signal. The fourth storage capacitor is electrically connected to the output end of the fourth selection circuit, and the other end of the fourth storage capacitor is electrically connected to the second input end.

4. The voltage detection chip as claimed in claim 3, characterized in that: The capacity of the first storage capacitor is equal to the capacity of the second storage capacitor, and the capacity of the third storage capacitor is equal to the capacity of the fourth storage capacitor.

5. The voltage detection chip as claimed in claim 3, characterized in that: The first selection circuit includes a third switch circuit and a fourth switch circuit, one end of the third switch circuit is used to receive the battery positive pressure signal, and the other end of the third switch circuit is electrically connected to the first storage capacitor; one end of the fourth switch circuit is used to receive the battery negative pressure signal, and the other end of the fourth switch circuit is electrically connected to the first storage capacitor; The second selection circuit includes a fifth switch circuit and a sixth switch circuit, one end of the fifth switch circuit is used to receive the battery negative pressure signal, and the other end of the fifth switch circuit is electrically connected to the second storage capacitor, and one end of the sixth switch circuit is used to receive the battery positive pressure signal, and the other end of the sixth switch circuit is electrically connected to the second storage capacitor; The third selection circuit includes a seventh switch circuit and an eighth switch circuit, one end of the seventh switch circuit is used to receive the reference positive voltage signal, and the other end of the seventh switch circuit is electrically connected to the third storage capacitor, and one end of the eighth switch circuit is used to receive the reference negative voltage signal, and the other end of the eighth switch circuit is electrically connected to the third storage capacitor; The fourth selection circuit includes a ninth switch circuit and a tenth switch circuit, one end of the ninth switch circuit is used to receive the reference negative voltage signal, and the other end of the ninth switch circuit is electrically connected to the fourth storage capacitor, and one end of the tenth switch circuit is used to receive the reference positive voltage signal, and the other end of the tenth switch circuit is electrically connected to the fourth storage capacitor.

6. The voltage detection chip according to claim 5, characterized in that: The voltage detection chip also includes a clock signal generating circuit, which is used to generate a first clock signal, a second clock signal, a third clock signal and a fourth clock signal. The third clock signal is formed by amplifying the voltage amplitude of the first clock signal, and the fourth clock signal is formed by amplifying the voltage amplitude of the second clock signal.

7. The voltage detection chip according to claim 6, characterized in that: The first clock signal is also used to control the first switch circuit and the second switch circuit to be turned on in the first stage, so that the first input terminal inputs the reference positive voltage signal, and the second input terminal inputs the reference positive voltage signal and the offset signal of the comparison circuit; the third clock signal is used to control the third switch circuit and the fifth switch circuit to be turned on in the first stage; the first clock signal is also used to control the seventh switch circuit and the ninth switch circuit to be turned on in the first stage, and the fourth clock signal is used to control the fourth switch circuit and the sixth switch circuit to be turned off in the first stage; the fourth clock signal is used to control the eighth switch circuit and the tenth switch circuit to be turned off in the first stage.

8. The voltage detection chip according to claim 7, characterized in that: The first clock signal is also used to control the first switch circuit, the second switch circuit, the seventh switch circuit and the ninth switch circuit to be disconnected in the second stage, and the third clock signal is also used to control the third switch circuit and the fifth switch circuit to be disconnected in the second stage; the fourth clock signal is also used to control the fourth switch circuit and the sixth switch circuit to be turned on in the second stage; the second clock signal is also used to control the eighth switch circuit and the tenth switch circuit to be turned on in the second stage, wherein the second stage is located after the first stage.

9. A battery, characterized in that: It comprises a plurality of battery cells, a battery selection circuit, a reference generation circuit and a voltage detection chip as described in any one of claims 1 to 8, wherein the battery cells are used to generate a battery positive voltage signal and a battery negative voltage signal, the battery selection circuit is used to select one of the plurality of battery cells to be electrically connected to the voltage detection chip, and the reference generation circuit is used to generate a reference positive voltage signal and a reference negative voltage signal.

10. An electronic device, characterized in that: Comprising the battery as claimed in claim 9.

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