Fast discharge of power supply node

Abstract

The present disclosure relates to fast discharging of power supply nodes. A method and apparatus for fast discharging a power rail is disclosed. A circuit includes a power converter circuit including an inductor coupled between a switching node and a regulated power supply node. A first device is coupled between an input power supply node and the switching node, and a second device is coupled between the switching node and a ground node. The power converter is configured to produce a particular voltage level on the regulated power supply node by controlling the first device and the second device. The circuit further includes a control circuit that, in response to receiving a discharge command, repeatedly activates and deactivates the second device to discharge the regulated power supply node via the switching node and the inductor.

Description

Technical Field

[0001] This disclosure relates to electronic circuits, and more particularly to DC-DC converters. Background Technology

[0002] Voltage regulators are commonly used in a variety of electronic circuits to provide a desired voltage to a specific circuit. Therefore, a variety of voltage regulator circuits are available to meet a wide range of applications. Linear regulators are used in many different applications where the available supply voltage exceeds the suitable value for the circuit being powered. Another type of voltage regulator is the switching-mode regulator, more commonly called a switching power supply, or alternatively a DC-DC converter. Switching power supplies can be further subdivided into two categories: buck converters and boost converters. A buck converter gradually decreases the input voltage from its power supply to its load while gradually increasing the current. A boost converter gradually increases the input voltage from its power supply to its load while gradually decreasing the current.

[0003] This invention discloses a basic switching power supply comprising a switch and an energy storage element (such as an inductor). Operation in the basic switching power supply includes an on state (e.g., when the switch is in a first position) and an off state (e.g., when the switch is in a second position). During the on state, the energy storage element begins to store energy. For example, when the energy storage element is an inductor, the current increases and, in response, the inductor generates an opposite voltage across its terminals. During the off state, the switch is open and the inductor becomes a current source. Over time, the changing voltage of the switching power supply is averaged to a substantially DC voltage. Summary of the Invention

[0004] This invention discloses a method and apparatus for rapidly discharging a power rail. In one embodiment, the invention discloses a circuit including a power converter circuit comprising an inductor coupled between a switching node and a regulated power supply node. A first device is coupled between an input power supply node and a switching node, while a second device is coupled between the switching node and a ground node. The power converter is configured to generate a specific voltage level on the regulated power supply node by controlling the first and second devices. The circuit also includes control circuitry that, in response to receiving a discharge command, repeatedly activates and deactivates the second device to discharge the regulated power supply node via the switching node and the inductor.

[0005] In one embodiment, the power converter operates within a voltage range between a minimum voltage and a maximum voltage. Within this range, the voltage can be changed by altering the respective duty cycles of the first and second devices. In response to a discharge command, the power converter initially reduces the voltage at the regulated power node to a minimum voltage. Thereafter, repeated activation and deactivation of the second device can begin (while the first device remains inactive). In one embodiment, the second device can be activated and deactivated in a pulsed manner, where each pulse has a first fixed duration, and the inactive period between pulses may have a second fixed duration (which may differ from the first duration). In another embodiment, the current through the switching node can be monitored. The second device can remain active until the current reaches a threshold. Thereafter, the second device is deactivated for a specified duration. In various embodiments, discharging of the regulated power node can continue until the voltage on it drops to a value less than or equal to a target voltage value. Attached Figure Description

[0006] The following detailed description refers to the accompanying drawings, which will now be briefly described.

[0007] Figure 1 This is a schematic diagram of one implementation of a circuit including a power converter circuit and a discharge control circuit.

[0008] Figure 2 It is a block diagram of a system including a power converter circuit.

[0009] Figure 3 This is a diagram illustrating one implementation of a discharge procedure for a regulated power supply node.

[0010] Figure 4 This is a timing diagram illustrating one embodiment of the discharge procedure for a regulated power supply node.

[0011] Figure 5 This is a flowchart illustrating one embodiment of a method for discharging a regulated power supply node.

[0012] Figure 6 This is a block diagram of one implementation of an exemplary system. Detailed Implementation

[0013] This disclosure relates to a method and apparatus for discharging power rails in a switching power supply circuit (e.g., a buck regulator). In various electronic systems (such as some battery-powered portable systems), it is desirable to disconnect circuits that are not currently in use to save power. This, in turn, results in the discharge of the supply voltage nodes coupled to the circuits to be disconnected. This can be achieved by a circuit comprising transistors and resistors coupled, for example, between the switching nodes and ground. However, disconnecting power in this manner can be time-consuming.

[0014] In this disclosure, various parts of the switching regulator can be used to assist in discharging the supply voltage node or to perform the entire operation. For example, in a buck converter, this disclosure utilizes a low-side transistor coupled to the switching node as a discharge path. The operation of the low-side switch can be controlled by a discharge control circuit that alternately activates and deactivates the low-side transistor to discharge the switching node, thereby discharging the supply voltage node. This allows for controlled discharge of the corresponding supply voltage node, which can be performed in significantly less time than conventional methods using discharge circuits with transistors and resistors. Various embodiments of the switching power converter circuit and the method for discharging its corresponding supply voltage node will now be discussed in further detail below.

[0015] Figure 1 This is a schematic diagram of one embodiment of a circuit including a power converter circuit and a discharge control circuit. In the illustrated embodiment, the power converter circuit 100 is a DC-DC converter, and more specifically a z-converter, which receives an input voltage Vin and provides an output voltage less than the input voltage at the regulated supply voltage node Vout. The voltage provided at Vout is regulated because the power converter 100 operates to maintain this voltage at a specified value (although this specified value may vary during operation).

[0016] The power converter 100 includes a first switching device P1 coupled between a switching node 111 and an input voltage node Vin. The first switching device may be referred to as a high-side switch. A second switching device N1 is coupled between the switching node 111 and a ground node. In this embodiment, the first switching device P1 is a PMOS transistor, and the second switching device N1 is an NMOS device.

[0017] It should be noted that, as shown in the figure, in some implementations, N1 can be implemented using multiple transistors coupled in parallel but capable of being controlled independently of each other. The high-side switch implemented by P1 can be implemented in the same manner.

[0018] The corresponding drain terminals of P1 and N1 are coupled to switching node 111. Inductor L1 includes a first terminal coupled to switching node 111 and a second terminal coupled to the regulated supply voltage node Vout. Load circuit 135 is coupled to receive the regulated supply voltage via Vout. The load circuit can be virtually any type of circuit that can operate based on the regulated supply voltage, such as analog, digital, or mixed-signal circuits. Capacitor Cpd is also coupled in parallel with load circuit 135. In some embodiments, power converter circuit 100 is implemented together with load circuit 135 on an integrated circuit. In other embodiments, the power converter circuit and load circuit can be implemented on separate integrated circuit dies, and more generally, can be implemented independently of each other. Depending on the needs of a particular embodiment, capacitor Cpd can be an on-chip capacitor or an off-chip capacitor.

[0019] The corresponding gate terminals of P1 and N1 are coupled to a pre-drive circuit 110, which alternately activates and deactivates these two devices one at a time to control the output voltage level. When P1 is active, switch node 111 is effectively coupled to the input voltage node Vin, and inductor L1 is charged, thereby transferring energy to the output voltage node Vout. When N1 is active, switch node 111 is effectively coupled to ground, thereby discharging switch node 111 and inductor L1. The pre-drive circuit 110 can control the voltage level on the regulated supply voltage node Vout by controlling the corresponding duty cycles of P1 and N1. To increase the voltage transferred on Vout, the pre-drive circuit 110 can increase the duty cycle of P1 while correspondingly decreasing the duty cycle of N1. Conversely, to decrease the voltage on Vout, the pre-drive circuit 110 can decrease the duty cycle of P1 while increasing the duty cycle of N1. Since L1 is an energy storage device that alternately stores and releases energy, the voltage variation at switching node 111 can be largely averaged across Vout, thus enabling a substantially DC voltage to be supplied to load circuit 135. This averaging can be aided by the presence of capacitor Cpd.

[0020] Although not explicitly shown, the regulated supply voltage node Vout, or the voltage generated therefrom, can be fed back to other circuitry for comparison with a reference voltage. The reference voltage can be set according to the desired voltage level on Vout. In one embodiment, circuitry located in the power management unit (omitted here for simplicity) can compare the voltage level on Vout (or the voltage generated therefrom) with the reference voltage and, in response to the comparison result, generate a control signal to the pre-drive circuitry 110 to adjust the voltage level accordingly.

[0021] Optional discharge circuit 127 is included in the illustrated embodiment. Discharge circuit 127 shown herein includes a resistor Rdn and an NMOS transistor N2. The gate terminal of N2 may be coupled to receive an enable signal EnRdn, which serves as a discharge command. When this enable signal is asserted, transistor N2 can be used to discharge between switching node 111 and ground through resistor Rdn. Therefore, a power management unit (not shown) or other circuitry may assert the enable signal, for example, during a power outage of load circuit 135, to discharge both switching node 111 and Vout. However, as mentioned above, discharging in this manner can be slow and prevents switching node 111 and the regulated supply voltage node Vout from discharging within a satisfactory amount of time. Therefore, discharge control circuitry 105 is coupled to power converter 100 and configured to control the discharge of switching node 111 via transistor N1, thereby controlling the discharge of Vout.

[0022] As described above, N1 can be implemented as a plurality of individual, independently controllable transistors coupled in parallel between switching node 111 and ground. Therefore, as part of the discharge process, controlling the amount of discharge current between switching node 111 and ground may include activating only subgroups of the parallel-coupled transistors rather than activating the entire group. The number of transistors activated during any given pulse in the discharge process may further vary from pulse to pulse. Furthermore, if it is desirable to prevent inrush current, the transistors in this embodiment may be activated sequentially until all desired subgroups (or the entire group) are active. More generally, using a plurality of independently controllable transistors coupled in parallel to enable the low-side switch to provide an additional degree of control during normal operation and during the discharge process.

[0023] During the discharge process, transistor N1 can be activated for one pulse cycle, each pulse cycle having a specified duration. Regarding the discharge operation, a pulse can be defined herein as the time during which transistor N1 is active and thus provides a current path between switch node 111 and ground. Therefore, during each pulse, the energy stored in inductor L1 can be discharged to ground through switch node 111. In some embodiments, pulses may have the same duration, or in other embodiments, pulses may have a variable duration.

[0024] The activation of transistor N1 during the discharge process can vary depending on the implementation. In one implementation, transistor N1 may be activated by multiple pulses of equal duration. Similarly, the time between pulses may also have the same duration, although this duration is not necessarily the same as the pulse duration. In some implementations, the number of pulses may be predetermined based on determining the maximum amount of time required for the regulated supply voltage node Vout to reach a voltage level less than or equal to the target voltage. In another implementation, feedback from, for example, the regulated supply voltage node Vout may be monitored, and pulses may continue to be supplied until a voltage less than or equal to the target voltage has been detected on Vout.

[0025] In another implementation, the duration of the pulse may depend on the amount of current discharged to ground through switch node 111. For example... Figure 1 As shown, an optional current sensing circuit 117 is coupled to monitor the amount of current passing through the switching node 111. Transistor N1 may remain active until the amount of current sensed by the current sensing circuit 117 reaches or exceeds a threshold. Thereafter, transistor N1 may be in an inactive state for the duration of the next variable-duration activation pulse. Since the amount of energy stored in inductor L1 decreases during the discharge process, the amount of current discharged through the switching node 111 can also vary. Therefore, since the duration of each pulse in this embodiment depends on the amount of current discharged through the switching node 111, the pulse duration can be varied.

[0026] In the illustrated embodiment, the discharge process is controlled by a discharge control circuit 105. As shown here, the discharge control circuit is coupled to a selection circuit 108 (e.g., a multiplexer), which is also coupled to provide control signals to the pre-drive circuit 110. During normal (e.g., non-discharge) operation, when power is supplied to the load circuit 135, the selection signal (“select”) provided by the discharge control circuit 105 to the selection circuit 108 is set to select control signals from the power management unit (“PMU control”). In various embodiments, these control signals can be provided from any suitable source and may indicate the desired output voltage, desired duty cycle, etc., of transistors P1 and P2.

[0027] In response to receiving a discharge command in the form of an enable signal (“enable”) from the power management unit or other suitable source, the discharge control circuit 105 may set a selection signal to select a discharge control signal (“discharge control”). These signals are then transmitted to the pre-drive circuit 110 to control the discharge process.

[0028] During normal operation, the voltage supplied at the regulated supply voltage node Vout can vary within a specific voltage range (referred to herein as the operating range). The specific voltage supplied by the power converter 100 can depend on the corresponding duty cycles of P1 and N1. A longer duty cycle of P1 and a corresponding shorter duty cycle of N1 typically correspond to a higher voltage on Vout. A shorter duty cycle of P1 and a corresponding longer duty cycle of N2 typically correspond to a lower voltage on Vout. During the discharge process, the discharge control circuit 105 initially reduces the voltage on Vout to the lower end of this range by increasing the duty cycle of N1 and decreasing the duty cycle of P1 in the pre-drive circuit 110. When the voltage on Vout reaches the lower end of the operating range, the discharge control circuit 105 causes the pre-drive circuit 110 to stop activating P1 while activating N1 in the aforementioned pulsed manner. This operation can continue until the voltage on Vout drops to or below the target voltage, after which it can be considered effectively discharged and the load circuit 135 is effectively de-energized.

[0029] Figure 2 This is a block diagram of a system including power converter circuitry. In the illustrated embodiment, system 200 includes a power management unit 205, one embodiment of power converter 100, and a functional circuit block 210. The functional circuit block 210 in the illustrated embodiment is the load of power converter 100 and may include analog circuitry, digital circuitry, and / or mixed-signal circuitry. In some embodiments, system 200 may be implemented on a single integrated circuit die, or in other embodiments, it may be implemented across multiple integrated circuits.

[0030] The power management unit 205 in the illustrated embodiment includes circuitry that performs multiple different power management functions, including controlling the performance states of various functional circuit blocks, including functional circuit block 210. Controlling the performance states may include controlling the operating voltage of the functional circuit blocks and also controlling the frequency of one or more clock signals supplied to them. In this specific embodiment, according to the above description… Figure 1 The discussion points out that the control of the voltage provided by the power converter 100 can be achieved through the PMU control signal transmitted from the power management unit 205 to the power converter 100.

[0031] The power management unit 205 may also include circuitry configured to power off or power on various functional circuit blocks within the system. This may include powering off or powering on corresponding power supplies such as the power converter 100. Therefore, in the illustrated embodiment, the power management unit 205 can power off functional circuit block 210 by asserting an enable signal provided to the power converter 100. In response to receiving the asserted enable signal, the power converter 100 can initiate a discharge process discussed above and further in detail below.

[0032] Figure 3 This is an illustration of one embodiment of a discharge procedure for a regulated power supply node. The discharge example shown can be performed by various embodiments of the power converter 100 described above.

[0033] As previously described, various embodiments of the power converter 100 provide a regulated supply voltage Vout within a specified operating range, shown on a vertical axis. In this particular example, a supply voltage is provided at the upper end of the operating range, VU, until a discharge command (e.g., an enable signal) is received. Upon receiving a discharge command, the power converter can cause the switching node to discharge at a normal discharge rate (and thus the Vout node to discharge). This can be achieved by changing the high side (e.g., Figure 1 P1) switching devices and low-side (e.g., Figure 1 This is achieved by adjusting the corresponding duty cycle of the N1 switching device. This may involve increasing the duty cycle of the low-side switching device and correspondingly decreasing the duty cycle of the high-side switching device.

[0034] When the voltage on Vout drops to the minimum voltage VL of the operating range, the operation of the power converter changes. Specifically, the operation of the high-side switch stops, and discharge occurs through the low-side switch. Specifically, a discharge pulse is initiated by alternately turning the low-side switch on and off. When the low-side switch is on, a current path is provided between the switching node and ground, and therefore switching node 111 discharges. As mentioned above, the duration of the pulse can be fixed or variable, depending on the implementation. In the former, the pulse has a specified duration followed by a specified off time. In the latter, the duration of the pulse can depend on, for example, the amount of current flowing through the switching node sensed by the current sensing circuit 117, and therefore the duration of the pulse can vary. The discharge operation can continue until the voltage on Vout has dropped to at least the target voltage. Thereafter, the discharge operation can be considered complete, and the regulated supply voltage node Vout (and therefore any load configured to operate at that voltage) will be de-energized. The low-side switch can then be placed in the desired state until normal operation resumes (e.g., the power converter 100 is energized and supplies power to the load).

[0035] Figure 4 This is a timing diagram illustrating one embodiment of the discharge procedure for a regulated power supply node. More specifically, Figure 4 An embodiment is shown that provides pulses of the same duration to discharge the regulated supply voltage node. In the example shown, the voltage at the regulated supply voltage node of the power converter has been reduced to at least the minimum voltage of the operating voltage range (such as...). Figure 3The assertion of a pulse begins at or after (as shown). A pulse comprises the activation of a low-side switch including one or more transistors. In this example, each pulse has a fixed duration t0, which represents the amount of time the discharge path between the switching node and the ground node is active due to the activation of the low-side switch. The complete cycle of a single loop is time t1, which spans the duration from the start of one pulse to the start of the next. Therefore, in this particular example, the duration between pulses is also fixed. The pulse may continue to be asserted within time t2, providing sufficient time for the regulated supply voltage node to discharge to the target voltage or lower.

[0036] It should be noted that the number of pulses shown here is merely an example and is not intended to be limiting. Regarding time t2, this duration may vary in some embodiments or be fixed in others. When t2 is a fixed value, it can be set based on the time determined to allow the regulated supply voltage node to discharge to the desired level.

[0037] It should also be noted that in other embodiments, the duration of a given pulse can be variable. For example, as mentioned above, some embodiments may utilize current sensing, and the pulse duration may depend on the amount of current flowing through the switching node (where the pulse ends when the current reaches a threshold). In such embodiments, the duration between pulses can be fixed or variable.

[0038] Finally, since the low-side switch may include multiple independently controllable transistors coupled in parallel between the switching node and ground, it should be noted that in at least some embodiments, the activation time of at least a portion of these devices may be less than the full duration of a given pulse. Therefore, the pulse duration can represent the total amount of time the current path between the switching node and ground is active, even if the number of transistors providing the current path can vary within the pulse duration.

[0039] Figure 5 This is a flowchart illustrating one embodiment of a method for discharging a regulated power supply node. (Example) Figure 5 The method 500 shown and described below can be performed using various embodiments of the power converter described above. Power converters not explicitly disclosed herein but capable of performing method 500 may also be considered to fall within the scope of this disclosure.

[0040] Method 500 includes using a power converter to provide an output voltage to a load circuit at a regulated supply voltage node, wherein providing the output voltage includes the power converter operating a first device and a second device, the first device being coupled between a switching node and an input power node, and the second device being coupled between the switching node and a ground node (block 505). The method also includes receiving a discharge command at a control circuit (block 510). In one embodiment, the discharge command may be an enable signal that enables a discharge control circuit, such as the one referenced above. Figure 1 The method then includes, in response to receiving a discharge command, discharging the regulated supply voltage node to a voltage less than or equal to a target voltage level, wherein the discharge includes control circuitry repeatedly activating and deactivating a second device to cause the regulated supply voltage node to discharge via a switching node (block 515).

[0041] In some embodiments, discharging includes: activating the second device for a first specified duration, deactivating the second device for a second specified duration, and repeating the activation and deactivation until the voltage at the regulated supply voltage node has dropped to a level less than or equal to a target voltage level. The first and second specified durations are not necessarily equal in all embodiments, but may be equal in some embodiments. The pulsed operation of repeating activation and deactivation may continue for a third duration sufficient to discharge the regulated supply voltage node to the desired level.

[0042] The discharge process may include activating the second device and subsequently deactivating it in response to the current through the switching node exceeding a current threshold. This deactivation may also include the second device remaining inactive for a fixed duration. The method may also include repeated activation and deactivation until the voltage at the regulated supply voltage node has dropped to a level less than or equal to a target voltage level.

[0043] In various embodiments, operating the power converter includes providing an output voltage within a specified voltage range between a minimum specified voltage and a maximum specified voltage. In response to a discharge command received by the control circuitry, the method includes reducing the output voltage to the minimum specified voltage. Reducing the output voltage to the minimum specified voltage includes changing the respective duty cycles of the first and second devices. The method then includes initiating the discharge of the regulated supply voltage node in response to the output voltage reaching the minimum specified voltage.

[0044] Next turn Figure 6The diagram illustrates a block diagram of one embodiment of system 150. In the illustrated embodiment, system 150 includes at least one instance of integrated circuit 10 coupled to external memory 158. The integrated circuit 10 may include a memory controller coupled to external memory 158. The integrated circuit 10 is coupled to one or more peripheral devices 154 and external memory 158. A power supply 156 is also provided to supply a supply voltage to the integrated circuit 10 and to supply one or more supply voltages to memory 158 and / or peripheral devices 154. In some embodiments, more than one instance of integrated circuit 10 may be included (and more than one external memory 158 may also be included).

[0045] Depending on the type of system 150, peripheral device 154 may include any desired circuitry. For example, in one embodiment, system 150 may be a mobile device (e.g., a personal digital assistant (PDA), smartphone, etc.), and peripheral device 154 may include devices for various types of wireless communications, such as WiFi, Bluetooth, cellular, GPS, etc. Peripheral device 154 may also include additional storage devices, including RAM storage devices, solid-state storage devices, or disk storage devices. Peripheral device 154 may include user interface devices such as a display screen, including a touch screen or multi-touch screen, a keyboard or other input device, a microphone, speakers, etc. In other embodiments, system 150 may be any type of computing system (e.g., a desktop PC, laptop, workstation, tablet, etc.).

[0046] External memory 158 may include any type of memory. For example, external memory 158 may be SRAM, dynamic RAM (DRAM) (such as synchronous DRAM (SDRAM)), dual data rate (DDR, DDR2, DDR3, LPDDR1, LPDDR2, etc.) SDRAM, RAMBUS DRAM, etc. The external memory 158 may include one or more memory modules to which the memory device is mounted, such as single in-line memory modules (SIMM), dual in-line memory modules (DIMM), etc.

[0047] IC 10 in the embodiments shown herein may include one or more instances of a power converter, such as one of the various embodiments discussed above, wherein the power converter is configured to discharge a corresponding regulated supply voltage node as disclosed herein. Various peripheral devices in peripheral device 154 may also include one or more integrated circuits on which embodiments of power converter 100 are implemented. In the various instances of power converter 100 implemented in system 150, a discharge process, such as the discharge process discussed above, may be performed.

[0048] This disclosure includes references to “implementation” or groups of “implementation” (e.g., “some implementations” or “various implementations”). An implementation is a different specific implementation or instance of the disclosed concepts. References to “implementation,” “an implementation,” “a particular implementation,” etc., do not necessarily refer to the same implementation. A large number of possible implementations are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the substance or scope of this disclosure.

[0049] This disclosure may discuss potential advantages that may arise from the disclosed embodiments. Not all specific implementations of all these embodiments will necessarily exhibit any or all of the potential advantages. Whether a particular implementation achieves an advantage depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why an implementation falling within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular implementation may include other circuitry outside the scope of this disclosure, in conjunction with an embodiment of the disclosed embodiments, which negates or diminishes one or more of the disclosed advantages. Furthermore, suboptimal design execution of a particular implementation (e.g., the implementing technique or tool) may also negate or diminish the disclosed advantages. Even assuming an implementation of the technique, the realization of advantages may still depend on other factors, such as the environmental circumstances in which the implementation is deployed. For example, the inputs provided to a particular implementation may prevent one or more problems addressed in this disclosure from occurring in a particular context, and as a result, the benefits of its solution may not be realized. Given the existence of possible factors outside this disclosure, any potential advantages described herein should not be construed as a limitation of the claims that must be satisfied in order to prove infringement. Rather, the identification of such potential advantages is intended to illustrate one or more types of improvements available to a designer who benefits from this disclosure. Describing such advantages permanently (e.g., stating that a particular advantage "may occur") is not intended to convey a question about whether such advantages can actually be realized, but rather to recognize that the realization of such advantages often depends on the technological reality of additional factors.

[0050] Unless otherwise stated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on this disclosure, even where only a single example is described with respect to a particular feature. The embodiments disclosed in this invention are intended to be exemplary and not restrictive, without requiring any statement to the contrary in this invention. Therefore, this application is intended to allow for the coverage of the claims of the disclosed embodiments, as well as such alternatives, modifications, and equivalents, which will be apparent to those skilled in the art who are aware of the effective effects of this disclosure.

[0051] For example, features in this application can be combined in any suitable manner. Therefore, new claims may be made for any such combination of features during the proceedings of this patent application (or a patent application claiming priority thereto). Specifically, referring to the appended claims, features of dependent claims may be combined with features of other dependent claims, including claims dependent on other independent claims, where appropriate. Similarly, features from the respective independent claims may be combined where appropriate.

[0052] Therefore, while the appended dependent claims may be drafted such that each dependent claim is subordinate to a single other claim, additional dependent relationships are also contemplated. Any combination of dependent features conforming to this disclosure is contemplated, and such combinations may be protected by the claims in this patent application or another patent application. In short, the combinations are not limited to those specifically listed in the appended claims.

[0053] Where appropriate, it is also anticipated that claims drafted in one format or statutory type (e.g., apparatus) are intended to support corresponding claims in another format or statutory type (e.g., method).

[0054] Because this disclosure is a legal document, various terms and phrases are subject to administrative and judicial interpretation. It is hereby announced that the following paragraphs, as well as the definitions provided throughout this disclosure, will be used to determine how the claims drafted based on this disclosure should be interpreted.

[0055] Unless the context clearly specifies otherwise, references to the singular form of an item (i.e., nouns or noun phrases preceded by "an," "a," or "the") are intended to mean "one or more." Therefore, references to "item" in a claim do not exclude additional instances of that item without context. "A plurality of" items refers to a collection of two or more items.

[0056] This article uses the term “may” in the sense of permission (i.e., having the potential to be, being able to), rather than in the sense of mandatory (i.e., must).

[0057] The terms “include” and “including” and their forms are open-ended and mean “including but not limited to”.

[0058] When the term “or” is used in this disclosure in relation to a list of options, it will generally be understood to be used in an inclusive sense unless the context otherwise provides. Thus, the expression “x or y” is equivalent to “x or y, or both,” and therefore covers 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as “either x or y, but not both” make it clear that “or” is used in an exclusive sense.

[0059] The expressions “w, x, y, or z, or any combination thereof” or “...at least one of w, x, y, and z” are intended to cover all possibilities involving a single element up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase “...at least one of w, x, y, and z” therefore refers to at least one element in the set [w, x, y, z], thus covering all possible combinations of that list of elements. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0060] In this disclosure, various “labels” may precede nouns or noun phrases. Unless the context otherwise provides, different labels used for features (e.g., “first circuit,” “second circuit,” “specific circuit,” “given circuit,” etc.) refer to different instances of the feature. Furthermore, unless otherwise stated, the labels “first,” “second,” and “third” do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0061] The phrase "based on" is used to describe one or more factors that influence the determination. This term does not exclude the possibility that additional factors may influence the determination. That is, the determination may be based solely on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on another factor such as C. This phrase is also intended to cover implementations where A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on."

[0062] The phrases “responding to” and “responding” describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, whether these factors are used in conjunction with or independently of the specified factor. That is, the effect may respond solely to these factors, or it may respond to the specified factor along with other unspecified factors. Consider the phrase “responding to B to execute A.” This phrase specifies that B is a factor that triggers the execution of A or triggers a specific result of A. This phrase does not exclude that the execution of A may also respond to certain other factors, such as C. This phrase also does not exclude that the execution of A may be performed jointly in response to B and C. This phrase is also intended to cover implementation schemes where A is executed solely in response to B. As used herein, the phrase “responding” is synonymous with the phrase “at least partially responding.” Similarly, the phrase “responding to” is synonymous with the phrase “at least partially responding to.”

[0063] Within this disclosure, different entities (which may be referred to differently as “units,” “circuits,” other components, etc.) may be described or claimed to be “configured” to perform one or more tasks or operations. This expression—an [entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be said to be “configured” to perform a task even if the structure is not currently being operated. Therefore, an entity described or stated as “configured” to perform a task refers to a physical thing used to perform that task, such as a device, circuit, system with processor units, and memory storing executable program instructions. This phrase is not used herein to refer to intangible things.

[0064] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured" to perform those tasks / operations, even if not specifically stated.

[0065] The term "configured as" is not intended to mean "configurable as". For example, an unprogrammed FPGA is not considered "configured as" to perform a specific function. However, the unprogrammed FPGA may be "configurable as" to perform that function. After proper programming, the FPGA can then be considered "configured as" to perform a specific function.

[0066] For the purposes of this U.S. patent application, the statement in the claims that the structure is “configured” to perform one or more tasks is expressly intended for the claim elements. No Referencing 35 USC § 112(f). If an applicant wishes to invoke part 112(f) in the course of filing a U.S. patent application based on this disclosure, it will use the phrase “means for [performing functions]” to describe the elements of the claims.

[0067] Different “circuits” may be described in this disclosure. These circuits or “circuits” constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom-designed or taken from standard libraries. In various embodiments, circuits may, as appropriate, include digital components, analog components, or a combination of both. Certain types of circuits may generally be referred to as “cells” (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such cells also refer to circuits or circuitry.

[0068] Therefore, the circuits / units / components and other elements disclosed in the accompanying drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the function of that circuit. For example, a particular “decoding unit” can be described as having the function of executing “the opcode of a processing instruction and routing that instruction to one or more of a plurality of functional units,” meaning that the decoding unit is “configured” to perform that function. To those skilled in the art of computers, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0069] In various implementations, as discussed in the preceding paragraphs, the arrangement of circuits, cells, and other elements defined by the functions or operations they are configured to perform, relative to each other, and the manner in which such circuits / cells / components interact, forms a microarchitecture definition of hardware that is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, a microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations are derived, all of which fall within the broader structure described by the microarchitecture definition. That is, those skilled in the art, with the microarchitecture definition provided according to this disclosure, can implement this structure without excessive experimentation and using the application of a person of ordinary skill by encoding the description of the circuits / cells / components in a hardware description language (HDL) such as Verilog or VHDL. The HDL description is often expressed in a way that can be revealed as functional. However, for those skilled in the art, the HDL description is a way of translating the structure of a circuit, cell, or component into the details of the next level of implementation. Such HDL descriptions can take the following forms: behavioral code (which is typically non-synthesizable), Register Transfer Language (RTL) code (which is typically synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). HDL descriptions can be sequentially synthesized against a library of cells designed for a given integrated circuit manufacturing technology and can be modified for timing, power, and other reasons to obtain the final design database that is transferred to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuitry or portions thereof can also be custom-designed in a schematic editor and captured into the integrated circuit design along with the synthesized circuitry. The integrated circuit may include transistors and other circuit elements (e.g., passive components such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some implementations may implement multiple integrated circuits coupled together to implement the hardware circuitry, and / or discrete components may be used in some implementations. Alternatively, the HDL design can be synthesized into a programmable logic array such as a Field Programmable Gate Array (FPGA) and implemented in the FPGA. This decoupling between the design of a set of circuits and their subsequent low-level implementations often results in a situation where the circuit or logic designer never specifies a particular set of structures for the low-level implementation that goes beyond a description of what the circuit is configured to do, because that process is performed at different stages of the circuit implementation process.

[0070] The fact that a circuit of the same specifications can be implemented using many different low-level combinations of circuit elements results in a large number of equivalent circuit structures. As noted, these low-level circuit implementations can vary depending on the manufacturing technology, the foundry chosen to manufacture the integrated circuit, the cell library provided for a particular project, and so on. In many cases, the choice of different design tools or methods to produce these different implementations can be arbitrary.

[0071] Furthermore, for a given implementation, a single concrete implementation of the circuit's specific functional specifications typically involves a large number of devices (e.g., millions of transistors). Therefore, the shearing volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single implementation, let alone a large number of equivalent possible implementations. To this end, this disclosure describes the structure of a circuit using functional abbreviations commonly used in industry.

[0072] Once the above disclosure is fully understood, many variations and modifications will become apparent to those skilled in the art. This disclosure is intended to make the following claims interpretable as encompassing all such variations and modifications.

Claims

1. A circuit comprising: A power converter circuit includes a switching node coupled to a regulated power supply node via an inductor, a first device coupled between an input power supply node and the switching node, and a second device coupled between the switching node and a ground node, wherein the power converter circuit is configured to generate a specific voltage level on the regulated power supply node, the specific voltage level being in the range between a first voltage and a second voltage, wherein the second voltage is less than the first voltage. and In response to receiving a discharge command, the control circuit is configured to: The specific voltage level is reduced to the second voltage by changing the corresponding duty cycles of the first and second devices; as well as In response to the specific voltage level reaching the second voltage, the second device is repeatedly activated and deactivated to cause the regulated power node to discharge from the second voltage to the target voltage; The control circuit is configured to keep the first device inactive during repeated activation and deactivation of the second device.

2. The circuit of claim 1, wherein the control circuit is further configured to discharge the regulated power supply node to a voltage level less than or equal to the target voltage by activating and deactivating the second device.

3. The circuit of claim 1 further includes a selection circuit, wherein the control circuit is configured to select either a control signal from the power management unit or the discharge command to provide to the pre-drive circuit of the power converter circuit.

4. The circuit of claim 1, wherein when the second device is repeatedly activated and deactivated to discharge the regulated power supply node, the control circuit is configured such that the second device is in an active state for a first specified duration of a plurality of pulses, followed by a second specified duration of inactivity before the next pulse in the plurality of pulses.

5. The circuit of claim 1, wherein during repeated activation and deactivation of the second device to discharge the regulated power supply node, the control circuit is configured to activate the second device and subsequently deactivate it in response to the current through the switching node reaching a threshold, wherein the control circuit is further configured to keep the second device in an inactive state for a specified time before reactivation.

6. The circuit of claim 5 further includes a current sensing circuit configured to determine the amount of current passing through the switching node, and further configured to provide an indication to the control circuit in response to the current passing through the switching node reaching a threshold current value.

7. The circuit of claim 1 further includes a plurality of second devices coupled between the switching node and the grounding node, the plurality of second devices including the second devices.

8. The circuit of claim 7, wherein the control circuit is further configured to control the discharge rate by activating a selected second device among the plurality of second devices to discharge the regulated power supply node.

9. The circuit of claim 1, further comprising a pre-drive circuit coupled to control the first device and the second device, wherein the control circuit is configured to control the pre-drive circuit in response to receiving the discharge command.

10. A method comprising: Using a power converter to provide an output voltage to a load circuit at a regulated supply voltage node, wherein providing the output voltage includes the power converter operating a first device and a second device, the first device being coupled between a switching node and an input power node, and the second device being coupled between the switching node and a ground node, and further includes providing the output voltage within a specified voltage range between a minimum specified voltage and a maximum specified voltage; Receive the discharge command at the control circuit; In response to receiving the discharge command, the regulated power supply voltage node is discharged to a voltage less than or equal to the target voltage level, wherein the discharge includes: In response to the control circuit receiving the discharge command, the output voltage is reduced to the minimum specified voltage, wherein reducing the output voltage includes changing the respective duty cycles of the first device and the second device; and In response to the output voltage reaching the minimum specified voltage, the discharge of the regulated supply voltage node is initiated, wherein the discharge further includes the control circuit repeatedly activating and deactivating the second device to cause the regulated supply voltage node to discharge via the switching node, and also includes the control circuit keeping the first device inactive during the repeated activation and deactivation of the second device.

11. The method of claim 10, further comprising controlling the discharge rate of the regulated power supply voltage node by activating a selected device among a plurality of devices coupled between the switching node and the ground node, wherein the plurality of devices includes the second device.

12. The method of claim 10, wherein the discharge comprises: The second device is activated for a first specified duration; The second device is deactivated for a second specified duration; as well as Repeat the activation and deactivation process until the voltage at the regulated power supply node has dropped to a level less than or equal to the target voltage level.

13. The method of claim 12, further comprising repeating the activation and deactivation for a third duration.

14. The method of claim 10, wherein the discharge comprises: Activate the second device; The second device is deactivated in response to the current through the switching node exceeding a current threshold, wherein deactivation includes keeping the second device in an inactive state for a fixed duration; as well as Repeat the activation and deactivation process until the voltage at the regulated power supply node has dropped to a level less than or equal to the target voltage level.

15. The method of claim 10, further comprising: The amount of current passing through the switching node is sensed using a sensing circuit; as well as The control circuit is given an indication in response to the current through the switching node reaching a threshold current value.

16. An apparatus comprising: A load circuit, which is coupled to receive a regulated supply voltage at a regulated supply voltage node; A power converter configured to generate the regulated supply voltage, wherein the power converter includes: A first transistor is coupled between a switching node and an input supply voltage node; A second transistor, the second transistor being coupled between the switching node and the ground node; and An inductor coupled between the switching node and the output node, wherein the regulated supply voltage is provided at the output node; A power management circuit configured to generate a command instructing the load circuit to be powered off; and A control circuit configured to, in response to receiving the command, cause the output node to discharge via the switching node and the inductor, wherein when causing the output node to discharge, the control circuit is configured to: This reduces the regulated supply voltage to a minimum specified voltage, wherein reducing the regulated supply voltage includes changing the respective duty cycles of the first transistor and the second transistor; In response to the regulated supply voltage reaching the minimum specified voltage, the second transistor is repeatedly activated and deactivated to discharge the regulated supply voltage node to a voltage less than or equal to the target voltage; and The first transistor is kept inactive during repeated activation and deactivation of the second transistor.

17. The apparatus of claim 16, further comprising a current sensing circuit configured to sense the amount of current passing through the switching node.

18. The apparatus of claim 16, wherein the control circuitry is configured to: during the discharge at the output node: This causes the second transistor to remain activated for a first fixed duration; This causes the second transistor to be deactivated for a second fixed duration; and Repeating this process causes the second transistor to be activated and deactivated for the first fixed duration and the second fixed duration, respectively.

19. The apparatus of claim 18, wherein the control circuit is configured to repeatedly cause the second transistor to be activated and deactivated for the first fixed duration and the second fixed duration, respectively, for a duration sufficient to discharge the output node to a voltage less than or equal to the target voltage.

20. The apparatus of claim 16, wherein the control circuitry is configured to, during the discharge at the output node: This activates the second transistor; In response to the current flowing through the switching node reaching a threshold, the second transistor is deactivated for a fixed duration; and The second transistor is repeatedly activated and deactivated until the voltage at the output node is equal to or less than the target voltage.

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