Keyboard scanning circuit, keyboard key recognition method, chip and keyboard

Abstract

The application discloses a keyboard scanning circuit, a keyboard key recognition method, a chip and a keyboard. The keyboard scanning circuit comprises: a key value detection circuit connected with a keyboard scanning input interface and used for collecting a first level state corresponding to the keyboard scanning input interface; a state machine jump circuit used for outputting a current keyboard state; and an output decoding circuit connected with the key value detection circuit, the state machine jump circuit and a keyboard scanning output interface, used for controlling the keyboard scanning output interface to perform key scanning when the current keyboard state is an idle state and the first level state jumps from a high level to a low level; the key value detection circuit is further used for collecting a second level state corresponding to the keyboard scanning input interface after the keyboard scanning output interface is controlled to perform key scanning; and the output decoding circuit is further used for performing key recognition according to the second level state. The keyboard scanning circuit can realize key scanning and key recognition, has high reliability and does not need to additionally occupy keyboard MCU operation resources.

Description

Technical Field

[0001] This invention relates to the field of keyboard technology, and in particular to a keyboard scanning circuit, a keyboard key recognition method, a chip, and a keyboard. Background Technology

[0002] In current keyboard key recognition processes, a keyboard scanning program is usually executed on the keyboard MCU to scan keys, collect the change signals of the I / O interfaces corresponding to the keys, and then perform key recognition based on these change signals. This method of using the keyboard MCU to execute the keyboard scanning program for key scanning and recognition consumes the CPU resources of the keyboard MCU, affecting its operating efficiency. Summary of the Invention

[0003] This invention provides a keyboard scanning circuit, a keyboard key recognition method, a chip, and a keyboard to solve the problem of low operating efficiency caused by using a keyboard MCU for key scanning and key recognition.

[0004] This invention provides a keyboard scanning circuit, comprising:

[0005] A key value detection circuit is connected to the keyboard scanning input interface and is used to acquire the first level state corresponding to the keyboard scanning input interface.

[0006] A state machine transition circuit, connected to the key value detection circuit, is used to output the current keyboard state;

[0007] The output decoding circuit is connected to the key value detection circuit, the state machine jump circuit and the keyboard scanning output interface, and is used to control the keyboard scanning output interface to perform key scanning when the current keyboard state is idle and the first level state is transitioning from high level to low level.

[0008] The key value detection circuit is also used to acquire the second level state corresponding to the keyboard scanning input interface after the keyboard scanning output interface performs key scanning.

[0009] The output decoding circuit is also used for key recognition based on the second level state.

[0010] This invention provides a keyboard key recognition method, characterized by comprising:

[0011] Acquire the first voltage level corresponding to the keyboard scan input interface;

[0012] Output the current keyboard state;

[0013] When the current keyboard state is idle and the first level state transitions from high level to low level, the keyboard scanning output interface is controlled to perform key scanning.

[0014] After controlling the keyboard scan output interface to perform key scanning, the second level state corresponding to the keyboard scan input interface is acquired;

[0015] Key recognition is performed based on the second level state.

[0016] This invention provides a chip including the keyboard scanning circuit described above.

[0017] The present invention provides a keyboard, including keyboard keys and a keyboard MCU, and also includes the aforementioned keyboard scanning circuit, wherein the keyboard scanning circuit is connected to the keyboard keys and the keyboard MCU.

[0018] The aforementioned keyboard scanning circuit, keyboard key recognition method, chip, and keyboard only control the keyboard scanning output interface to perform key scanning when the current keyboard state is idle and the first level state transitions from high to low. This ensures that key scanning is only performed when a key is pressed, avoiding triggering key scanning when the condition of the current keyboard state being idle and the first level state transitioning from high to low is not met. This saves system power consumption and improves circuit reliability. An output decoding circuit controls the keyboard scanning output interface to perform key scanning, and completes key recognition based on the second level state corresponding to the keyboard scanning input interface. This allows the keyboard scanning circuit, as a hardware device, to complete the key scanning and key recognition process. When applied to the keyboard, the keyboard scanning circuit does not occupy the CPU resources of the keyboard MCU, thus helping to ensure the operating efficiency of the keyboard MCU. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a circuit diagram of a keyboard scanning circuit in one embodiment of the present invention;

[0021] Figure 2 This is another circuit diagram of the keyboard scanning circuit in one embodiment of the present invention;

[0022] Figure 3 This is another circuit diagram of the keyboard scanning circuit in one embodiment of the present invention;

[0023] Figure 4 This is another circuit diagram of the keyboard scanning circuit in one embodiment of the present invention;

[0024] Figure 5 This is another circuit diagram of the keyboard scanning circuit in one embodiment of the present invention;

[0025] Figure 6 This is another circuit diagram of the keyboard scanning circuit in one embodiment of the present invention;

[0026] Figure 7 This is a timing diagram of the keyboard scanning circuit in operation according to an embodiment of the present invention;

[0027] Figure 8 This is a flowchart of a keyboard key recognition method according to an embodiment of the present invention;

[0028] Figure 9 This is another flowchart of a keyboard key recognition method according to one embodiment of the present invention;

[0029] Figure 10 This is another flowchart of a keyboard key recognition method according to one embodiment of the present invention;

[0030] Figure 11 This is another flowchart of a keyboard key recognition method according to one embodiment of the present invention;

[0031] Figure 12 This is another flowchart of a keyboard key recognition method according to one embodiment of the present invention;

[0032] Figure 13 This is another flowchart of a keyboard key recognition method according to one embodiment of the present invention;

[0033] Figure 14 This is another flowchart of a keyboard key recognition method according to one embodiment of the present invention;

[0034] Figure 15 This is another flowchart of a keyboard key recognition method according to one embodiment of the present invention;

[0035] Figure 16 This is another flowchart of a keyboard key recognition method according to one embodiment of the present invention;

[0036] Figure 17 This is another flowchart of a keyboard key recognition method according to one embodiment of the present invention;

[0037] Figure 18 This is another flowchart of a keyboard key recognition method according to one embodiment of the present invention;

[0038] Figure 19 This is another flowchart of a keyboard key recognition method according to one embodiment of the present invention;

[0039] Figure 20This is another flowchart of a keyboard key recognition method according to one embodiment of the present invention;

[0040] Figure 21 This is another flowchart of a keyboard key recognition method in one embodiment of the present invention. Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0043] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0044] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0045] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0046] To fully understand this invention, detailed structures and steps will be presented in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0047] This invention provides a keyboard scanning circuit, such as... Figure 1 As shown, the keyboard scanning circuit includes:

[0048] The key value detection circuit is connected to the keyboard scanning input interface and is used to acquire the first level state corresponding to the keyboard scanning input interface.

[0049] The state machine transition circuit, connected to the key value detection circuit, is used to output the current keyboard state;

[0050] The output decoding circuit is connected to the key value detection circuit, the state machine jump circuit and the keyboard scanning output interface. It is used to control the keyboard scanning output interface to perform key scanning when the current keyboard state is idle and the first level state is transitioning from high level to low level.

[0051] The key value detection circuit is also used to acquire the second level state corresponding to the keyboard scanning input interface after the keyboard scanning output interface performs key scanning.

[0052] The output decoding circuit is also used for key recognition based on the second level state.

[0053] The Keyboard Scan Input (KSI) is an input interface connected to the keyboard keys. For example, an eight-channel parallel input can be used.

[0054] The key value detection circuit is connected to the keyboard scanning input interface and is used to detect the voltage level of the keyboard scanning input interface. Generally, when a key is pressed, the key value detection circuit detects a low voltage level at the keyboard scanning input interface; conversely, if the key is not pressed, the key value detection circuit detects a high voltage level at the keyboard scanning input interface.

[0055] The first level state refers to the level state of the keyboard scanning input interface acquired before key scanning is performed. The second level state refers to the level state of the keyboard scanning input interface acquired after key scanning is performed.

[0056] A state machine transition circuit is used to transition between the states of a keyboard key being pressed and not pressed. The current keyboard state reflects whether a keyboard key has been pressed at any given moment. Generally, the current key state can be either an idle state or a pressed state. Here, an idle state means no keyboard key is pressed, and a pressed state means a keyboard key is pressed.

[0057] The output decoding circuit is used to implement key scanning output and key recognition processing.

[0058] In one example, the keyboard scanning circuit implements the key recognition process as follows:

[0059] (1) The key value detection circuit connected to the keyboard scanning input interface needs to acquire the first level state corresponding to the keyboard scanning input interface in real time. When a keyboard key is not pressed, the first level state acquired by the key value detection circuit is high level; at the instant a keyboard key is pressed, the first level state acquired by the key value detection circuit changes from high level to low level. Understandably, the key value detection circuit acquires a first level state every unit of time. If the two first level states acquired at two consecutive moments are high level and low level respectively, that is, the key value detection circuit detects that the keyboard scanning input interface is high level and low level successively, and realizes the change from high level to low level, it can be determined that a keyboard key has been pressed.

[0060] (2) The state machine transition circuit needs to obtain the current keyboard state corresponding to the current time T1. This current keyboard state can reflect whether a keyboard key was pressed before the current time T1. For example, it can reflect whether a keyboard key was pressed in the previous time T0 before the current time T1. Specifically, it can be an idle state or a pressed state.

[0061] (3) The output decoding circuit can acquire the first level state collected by the key value detection circuit and the current keyboard state corresponding to the state machine jump circuit in real time. When the current keyboard state is idle, it means that no keyboard key was pressed at the previous moment T0, that is, the first level state collected at the previous moment T0 is high level. When the first level state changes from high level to low level, it means that the first level state collected at the previous moment T0 is high level and the first level state collected at the current moment T1 is low level. That is, the keyboard scanning input interface changes from high level to low level, indicating that a keyboard key is pressed at the current moment T1. Therefore, when the current keyboard state is idle and the first level state changes from high level to low level, it can be determined that a certain keyboard key is pressed at the current moment T1. At this time, it is necessary to control the keyboard scanning output interface to perform key scanning, that is, control the keyboard scanning output interface to output different levels that can realize key scanning according to specific rules. For example, control all keyboard scanning output interfaces to output low level in turn to complete the scanning of all keyboard keys so as to complete key recognition according to the second level state collected by the key value detection circuit.

[0062] Furthermore, the state machine transition circuit is also connected to the key value detection circuit to acquire the first level state collected by the key value detection circuit in real time. When the current keyboard state is idle and the first level state transitions from high level to low level, the current keyboard state can be updated to the pressed state.

[0063] (4) After the output decoding circuit controls the keyboard scanning output interface to perform key scanning, for example, after controlling all keyboard scanning output interfaces to output low level in turn, the key value detection circuit needs to collect the second level state corresponding to the keyboard scanning input interface in real time. This second level state can be high or low. In this example, each keyboard scanning output interface is matched with a keyboard scanning input interface, corresponding to the same keyboard key. For example, any keyboard key A is connected to the keyboard scanning circuit through the keyboard scanning input interface and the keyboard scanning output interface to ensure normal signal transmission.

[0064] (5) The output decoding circuit is also used to receive the second level state corresponding to the keyboard scanning input interface, which is collected in real time by the key value detection circuit, after the keyboard scanning output interface performs key scanning. This allows for key recognition based on the second level state. In this example, when there are S keyboard keys, the S keyboard scanning output interfaces need to be controlled to output low levels in turn. This allows the circuit to determine which key was pressed based on the second level state of each keyboard scanning output interface, thus identifying the key value corresponding to the pressed key. For example, when controlling the keyboard scanning output interface to perform key scanning specifically involves controlling all keyboard scanning output interfaces to output low levels in turn, after controlling the keyboard scanning output interface KSOi corresponding to the i-th key to output a low level, the output decoding circuit can collect the second level state corresponding to the keyboard scanning output interface KSIi corresponding to that keyboard scanning output interface KSOi. Based on the second level state, it can determine whether the i-th key was pressed. For example, when the second level is low, it is determined that the i-th keyboard key is pressed; when the second level is high, it is determined that the i-th keyboard key is not pressed, so as to identify the key value corresponding to the i-th keyboard key.

[0065] The keyboard scanning circuit provided in this embodiment only controls the keyboard scanning output interface to perform key scanning when the current keyboard state is idle and the first level state transitions from high to low. This ensures that key scanning is only performed when a key is pressed, avoiding triggering key scanning when the conditions of the current keyboard state being idle and the first level state transitioning from high to low are not met. This saves system power consumption and improves circuit reliability. An output decoding circuit controls the keyboard scanning output interface to perform key scanning, and completes key recognition based on the second level state corresponding to the keyboard scanning input interface. This allows the keyboard scanning circuit to complete the key scanning and key recognition process using only hardware. When applied to the keyboard, the keyboard scanning circuit does not occupy the CPU resources of the keyboard MCU, helping to ensure the operating efficiency of the keyboard MCU.

[0066] In one embodiment, such as Figure 2 As shown, the keyboard scanning circuit also includes a basic counter, an output change counter, and a scan count counter;

[0067] The base counter is used to update the current base value to the target base value when the target clock edge is received, and to control the current base value to be cleared when the output decoding circuit controls the keyboard scanning output interface to perform key scanning.

[0068] Output a change counter, which is connected to the base counter. It is used to update the current change count when the current base value is cleared. If the current change count reaches the target number of key presses, the current change count is cleared.

[0069] The scan count counter is connected to the output change counter. It is used to update the current scan count when the current change count is cleared. If the current scan count reaches the target scan count, it controls the current scan count to be cleared.

[0070] The output decoding circuit, connected to the base counter, output change counter, and scan count counter, is used to complete key scanning and key recognition based on the current base value, the current change count, and the current scan count.

[0071] The base counter is a counter set in the keyboard scanning circuit to record the level changes of each keyboard scanning output interface when it performs key scanning. For example, it can be a counter that records whether each keyboard scanning output interface outputs a low level. The target clock edge is a preset clock edge that controls the keyboard scanning output interface to perform key scanning; specifically, it is the clock edge that controls the keyboard scanning output interface to output a low level change. For example, the target clock edge can be a falling edge. The target base value is a preset base value, which can be set to 1.

[0072] As an example, this base counter is connected to the clock bus. It receives real-time information from the clock bus indicating that the current clock edge is the target clock edge. Upon this, the base counter is triggered to start counting, updating the current base value to the target base value (i.e., changing the current base value from 0 to 1). Then, when the base counter changes from 0 to 1, the output decoding circuit controls the keyboard scanning output interface to perform key scanning. Specifically, the output decoding circuit controls the keyboard scanning output interface corresponding to the i-th keyboard key to output a low level. In each scan control process, the output decoding circuit can control all keyboard scanning output interfaces to either all be pulled high or all be pulled low to achieve the keyboard scanning operation. Understandably, when the output decoding circuit controls the keyboard scanning output interface to output a low level, the key value detection circuit can acquire the second level state corresponding to the keyboard scanning input interface, so that key recognition can be completed subsequently based on the acquired second level state. Finally, when the basic counter detects that the output decoding circuit controls the keyboard scanning output interface to perform key scanning, that is, after controlling the keyboard scanning output interface to output a low level, it needs to control the current basic value to be cleared, that is, change the current basic value from 1 to 0, so that when the target clock edge is received next, the current basic value can be changed from 0 to 1, and then based on the current basic value, the keyboard scanning output interface can be controlled to output a low level, thereby ensuring the reliability of the keyboard scanning circuit.

[0073] Among them, the output change counter is a counter set in the keyboard scanning circuit for recording the number of times the keyboard scanning output interface has completed key scanning, specifically for recording the number of times the keyboard scanning output interface outputs a low level during the current scanning process. The current change count refers to the change count recorded by the output change counter at the current moment, which can be used to reflect the progress of each key scan, that is, in the process of each key scan, the state of how many keyboard keys have been scanned. This current change count can be set as N1. The target key number refers to the number of keyboard keys that need to be scanned in each key scan pre-set, and this target key number can be set as N.

[0074] As an example, the output change counter is connected to the basic counter and can monitor in real time whether the current basic value in the basic counter is cleared. Each time it is monitored that the current basic value is cleared, the current change count N1 needs to be updated, that is, add 1 to the current change count N0 at the previous moment to obtain the current change count N1 corresponding to the current moment, that is, N1 = N0 + 1. When the output change counter obtains the updated current change count N1, it needs to compare the current change count N, with the pre-set target key number N; if the current change count N1 reaches the target key number N (i.e., N1 = N), it is determined that this key scan is completed. At this time, it is necessary to control the current change count to be cleared so that when the next key scan is performed, it can be re-counted, thus ensuring the reliability of the keyboard scanning circuit. It can be understood that if the current change count N1 does not reach the target key number N (i.e., N1 < N), it is necessary to continue to monitor whether the current basic value is cleared.

[0075] Among them, the scan count counter is a counter set in the keyboard scanning circuit for recording how many scans have been completed. The current scan count refers to the number of scans that have been completed recorded by the scan count counter at the current moment, and this current change count can be set as M1. The target scan count is pre-set for controlling the number of scans required for each key scan, and this target scan count can be set as M.

[0076] As an example, the scan count counter is connected to the output change counter, and can monitor in real time whether the current change count in the output change counter is cleared. Each time it is monitored that the current change count is cleared, the current scan count M1 needs to be updated, that is, incremented by 1 based on the current scan count M0 at the previous moment, so as to obtain the current scan count M1 corresponding to the current moment, that is, M1 = M0 + 1. After the scan count counter obtains the updated current scan count M1, it needs to compare the current scan count M1 with the preset target scan count M; if the current scan count M1 reaches the target scan count M (i.e., M1 = M), it is determined that the key scan is completed. At this time, the current scan count can be cleared, so that when it is monitored next time that the current keyboard state is the idle state and the first level state changes from high level to low level, the key scan can be restarted, thus ensuring the reliability of the keyboard scan circuit. It can be understood that if the current scan count M1 does not reach the target scan count M (i.e., M1 < M), it is necessary to continue to monitor whether the current change count in the output change counter is cleared.

[0077] As an example, the output decoding circuit is connected to the basic counter, the output change counter and the scan count counter, and is used to complete key scanning and key recognition according to the current basic value, the current change count and the current scan count. For example, the output decoding circuit can control the keyboard scan output interface to output a low level according to the change of the current basic value to complete the key scan; it can also complete key recognition according to the current change count and the current scan count.

[0078] In the keyboard scan circuit provided in this embodiment, several counters such as the basic counter, the output change counter and the scan count counter are used to count according to the received target clock edge, so that the output decoding circuit can complete key scanning and key recognition for all keyboard keys according to the value changes in different counters. When the keyboard scan circuit is applied to the keyboard, it does not need to occupy the CPU resources of the keyboard MCU, which helps to ensure the operation efficiency of the keyboard MCU.

[0079] In one embodiment, the output decoding circuit is further used to control the keyboard scan output interface to output a low level when it is monitored that the current basic value is the target basic value, so as to implement key scanning;

[0080] The output decoding circuit is further used to obtain the second level state corresponding to the target key quantity when it is monitored that the current change count is cleared, and obtain the single scan result corresponding to the current scan count according to all the second level states;

[0081] The output decoding circuit is further used to obtain the single scan result corresponding to the target scan count when it is monitored that the current scan count is cleared, and obtain the key recognition result according to all the single scan results.

[0082] As an example, the output decoding circuit is connected to the base counter. When the output decoding circuit detects that the current base value recorded by the base counter is the target base value, it controls the keyboard scan output interface to output a low level, so that the key value detection circuit can acquire the second level state corresponding to the keyboard scan input interface. That is, every time the current base value of the base counter changes from 0 to 1, the output decoding circuit needs to control the keyboard scan output interface to output a low level once, realizing the scanning of a keyboard key. At this time, the key value detection circuit can acquire the second level state corresponding to the keyboard scan input interface that matches the keyboard scan output interface and feed this second level state back to the output decoding circuit. Understandably, when the second level state acquired by the key value detection circuit is low, it is determined that the keyboard key corresponding to the keyboard scan input interface is pressed; when the second level state acquired by the key value detection circuit is high, it is determined that the keyboard key corresponding to the keyboard scan input interface is not pressed, which is a release key.

[0083] As an example, the output decoding circuit is connected to the output change counter. When the output change counter is detected to be zero, the output decoding circuit determines that the current scan of the keyboard keys corresponding to the target key count N has been completed. At this point, it needs to obtain the current scan count recorded by the scan count counter. Based on the second-level states corresponding to the target key count N collected during the current scan, it determines whether a valid key has been identified, thus obtaining the single scan result corresponding to the current scan count. That is, based on whether N second-level states are high or low, it determines whether the scan is valid, obtaining a single scan result indicating whether the single scan is valid or invalid. If the single scan result is valid, the single scan key value can also be obtained. This single scan key value refers to the key value identified in this scan.

[0084] As an example, the output decoding circuit is connected to the scan count counter. When the current scan count is reset to zero, the output decoding circuit determines that a scan operation matching the target scan count M has been completed. Based on the acquired M single scan results, it completes the final key recognition, that is, it determines whether a valid key exists based on the M single scan results. If a valid key exists, it obtains the current valid key value corresponding to the valid key. Here, a valid key refers to the key that was determined to be pressed through key scanning, i.e., the key pressed when the first level state transitions from high to low. The current valid key value refers to the key value corresponding to the valid key.

[0085] In the keyboard scanning circuit provided in this embodiment, the output decoding circuit can control the keyboard scanning output interface to output a low level according to the current basic value to realize key scanning, and realize key recognition according to the current number of changes and the current number of scans. When the keyboard scanning circuit is applied to the keyboard, it does not need to occupy the CPU resources of the keyboard MCU, which helps to ensure the operating efficiency of the keyboard MCU.

[0086] In one embodiment, the output decoding circuit is further configured to acquire a second level state corresponding to the target number of keys when the current change count is detected to be zero; if all second level states are high, then an invalid single scan result is acquired; if there is a second level state that is low, then a valid single scan result is acquired.

[0087] As an example, when the output decoding circuit detects the current number of changes and resets it to zero, i.e., when one key scan is completed, it needs to perform the key recognition process based on the second level state corresponding to the keyboard scan input interface output by the key value detection circuit. The specific steps include the following:

[0088] (1) The output decoding circuit can determine that the current scan of N keyboard keys has been completed each time the current change count of the output change counter is cleared. It can obtain the second level state corresponding to the keyboard scan input interface of N keyboard keys. The second level state can be high level or low level.

[0089] (2) When the second level state corresponding to N keyboard keys is high, the output decoding circuit determines that none of the N keyboard keys were pressed in this scanning process, and thus determines that this scanning behavior is invalid. Therefore, the single scan result of invalid single scan can be obtained.

[0090] Furthermore, when the output decoding circuit detects that the current change count has been cleared to zero, and the result of a single scan is invalid, the current scan behavior is deemed invalid. The button recognition result of invalid single scan can be directly output without waiting for the current scan count to be cleared to zero, thus ending the current button scan and button recognition process. This helps to save waiting time, simplify the processing flow, and improve processing efficiency.

[0091] (3) When there is a low level in the second level state corresponding to the N keyboard keys, the output decoding circuit determines that one of the keyboard keys is in the pressed state during the current scan, and thus determines that the current scan behavior is a valid behavior. Therefore, a single scan result of a single scan can be obtained.

[0092] Furthermore, when the output decoding circuit detects that the current change count has been reset to zero, and its single scan result is valid, it needs to acquire the single scan key value. In this example, the output decoding circuit can identify the key identifier with a low second level as the target key identifier; then, based on the target key identifier, it determines the single scan key value corresponding to the target key identifier. Here, the key identifier is used to uniquely identify a specific keyboard key. In this example, both the keyboard scan output interface and the keyboard scan input interface corresponding to each keyboard key carry a key identifier, so that each acquired second level state also carries a key identifier. The target key identifier here refers to the key identifier corresponding to a low second level state. The single scan key value here is the key value determined by the key identifier in this scan.

[0093] In one embodiment, the output decoding circuit is further configured to output a key recognition result indicating that a single scan is invalid when there is a single scan result indicating that a single scan is invalid; and to obtain a single scan key value corresponding to the target number of scans when all single scan results are valid, and to obtain a key recognition result based on all single scan key values.

[0094] Among them, the currently valid key value is the key value identified for a single key press.

[0095] As an example, each time the output decoding circuit detects that the current scan count has been reset to zero, it completes a single scan operation corresponding to the current scan count and obtains a single scan result corresponding to the target scan count. When the target scan count is M, M single scan results can be obtained. Each single scan result can be either valid or invalid. Therefore, the output decoding circuit can perform one of the following operations based on all single scan results:

[0096] (1) When the output decoding circuit outputs the key recognition result of invalid single scan, the result of single scan is invalid.

[0097] In this example, if any of the M single scan results is invalid, the output decoding circuit determines that no corresponding single scan key value was identified after the single scan operation. At this time, it can directly output the key recognition result of invalid single scan without performing subsequent operations, thus ending the current key scan and key recognition process. This helps to save waiting time, simplify the processing flow, and improve processing efficiency.

[0098] (2) When all single scan results are valid, the output decoding circuit obtains the single scan key value corresponding to the target scan number, and obtains the key recognition result based on all single scan key values.

[0099] In this example, when all M single-scan results are valid, the output decoding circuit can obtain the single-scan key value identified in each scan, thus obtaining M single-scan key values. Since the M single-scan key values ​​may be the same or different, it is necessary to compare and analyze all single-scan results to determine the final key recognition result, thereby ensuring the accuracy of the key recognition result.

[0100] In one embodiment, the output decoding circuit is further configured to output an invalid key recognition result for a single scan when there are different key values ​​in a single scan; and to determine the current valid key value based on the single scan key value when all key values ​​in a single scan are the same, and output a key recognition result containing the current valid key value.

[0101] As an example, when all M single-scan results are valid, the output decoding circuit can obtain M single-scan key values. The M single-scan key values ​​can be the same or different. Therefore, the output decoding circuit can perform one of the following operations based on all single-scan key values.

[0102] (1) After the output decoding circuit acquires M single-scan key values, it needs to determine whether the M single-scan key values ​​are the same. If there are different single-scan key values, it cannot be determined which valid key value it corresponds to. Therefore, the key recognition result of invalid single scan can be output.

[0103] (2) After acquiring M single-scan key values, the output decoding circuit needs to determine whether the M single-scan key values ​​are the same. If all single-scan key values ​​are the same, then the single-scan key value is determined as the current valid key value, and the key recognition result containing the current valid key value is output to ensure the accuracy of the current valid key value. Understandably, when the target scan count is 1, it only acquires 1 single-scan key value, and this current scan key value can be directly determined as the current valid key value.

[0104] In one embodiment, the output decoding circuit is further configured to determine the historical valid key value when the key recognition result includes the current valid key value, obtain the key interval duration corresponding to the current valid key value and the historical valid key value, and determine the target valid key value based on the key interval duration and the current valid key value.

[0105] Among them, the target valid key value refers to the key value that is finally identified.

[0106] As an example, when the key recognition result is valid, the output decoding circuit outputs a currently valid key value for each key scan. Since there are also cases of key combinations during the current keyboard recognition process, such as the Ctrl+C shortcut on a computer keyboard, the output decoding circuit also needs to perform the following operation after recognizing and obtaining the key recognition result containing the currently valid key value to determine the final target valid key value:

[0107] (1) When the key recognition result includes the current valid key value, the output decoding circuit needs to obtain the historical valid key value corresponding to the current valid key value. The current valid key value can be understood as the key value of the keyboard key scanned and recognized at the current moment. Correspondingly, the historical valid key value can be understood as the key value of the keyboard key scanned and recognized at a previous moment. When determining the current valid key value and the historical valid key value, the output decoding circuit needs to obtain the current key value generation time corresponding to the current valid key value and the historical key value generation time corresponding to the historical valid key value, and determine the key interval duration as the time difference between the current key value generation time and the historical key value generation time. Understandably, the key interval duration can be understood as the time difference between the generation times of two valid key values. When there is only one historical valid key value, the key interval duration is the time difference between the current key value generation time and the historical key value generation time corresponding to the historical valid key value; when there are at least two historical valid key values, the key interval duration is the time difference between the current key value generation time and the historical key value generation time corresponding to the earliest historical valid key value.

[0108] After obtaining the key press interval duration, the output decoding circuit compares it with a target duration threshold. Based on this comparison result, it assesses whether the current valid key value and historical valid key values ​​could be a combination key press, thereby obtaining the final target valid key value and ensuring the accuracy of target valid key value recognition. The target duration threshold here is a pre-set threshold used to evaluate whether the combination key press condition is met.

[0109] In one embodiment, the output decoding circuit is further configured to determine the current valid key value as the target valid key value when the key interval duration is greater than the target duration threshold; and to determine whether the key combination rules are met based on the current valid key value and the historical valid key values ​​when the key interval duration is not greater than the target duration threshold, obtain the combination judgment result, and determine the target valid key value based on the combination judgment result.

[0110] As an example, after obtaining the key press interval duration, the output decoding circuit needs to compare the key press interval duration with a target duration threshold. If the key press interval duration is greater than the target duration threshold, it is determined that the key press interval duration between the current valid key value and the historical valid key value is too long, making it highly unlikely to be a combination key. That is, it is determined that the current valid key value is most likely a single key, and the current valid key value is identified as the target valid key value. For example, suppose the key press interval duration between the current valid key value and the historical valid key value is Ts, the target duration threshold is Tm, the current valid key value is C, and the historical valid key value is Ctrl. When Ts > Tm, it is determined that the key press interval duration between the user pressing the keyboard keys C and Ctrl is too long. Therefore, C can be identified as the target valid key value.

[0111] As an example, after obtaining the key press interval duration, the output decoding circuit needs to compare the key press interval duration with a target duration threshold. If the key press interval duration is not greater than the target duration threshold, it is determined that the key press interval duration between the current valid key value and the historical valid key value is small, which may indicate a key combination. In this case, based on the current valid key value and the historical valid key value, it is necessary to determine whether the key combination rule is met, obtain the combination judgment result, and then evaluate whether the current valid key value and the historical valid key value are a key combination to obtain the final target valid key value, thus ensuring the accuracy of the target valid key value recognition. The key combination rule here is a pre-configured rule used to reflect different key combinations so that they can complete specific function control.

[0112] In one embodiment, the output decoding circuit is further configured to determine a target valid key value based on the current valid key value and historical valid key values ​​when the combination judgment result satisfies the key combination rule; and to determine the current valid key value as the target valid key value when the combination judgment result does not satisfy the key combination rule.

[0113] As an example, the output decoding circuit determines whether a key combination rule is satisfied based on the current valid key value and historical valid key values. If the current valid key value and historical valid key value satisfy the key combination rule, it is determined that the current valid key value and historical valid key value can form a key combination. Based on the combination of the current valid key value and historical valid key values, the target valid key value can be determined so that the corresponding target control command can be generated. For example, if the current valid key value is C and the historical valid key value is Ctrl, then Ctrl+C satisfies the copy combination rule of the key combination rule, and Ctrl+C can be determined as the target valid key value.

[0114] As an example, the output decoding circuit determines whether a key combination rule is satisfied based on the current valid key value and the historical valid key values. If the current valid key value and the historical valid key value do not satisfy the key combination rule, it is determined that the current valid key value and the historical valid key value cannot form a key combination, and the current valid key value can be determined as the target valid key value. For example, if the current valid key value is Ctrl and the historical valid key value is C, it does not satisfy the key combination rule. Since C+Ctrl does not satisfy the key combination rule, the current valid key value and the historical valid key value can be determined as individual keys. Therefore, the current valid key value Ctrl can be determined as the target valid key value.

[0115] In this embodiment, the output decoding circuit can determine a single currently valid key value as the target valid key value based on the comparison result between the key interval duration and the target duration threshold, and whether it meets the key combination rules. Alternatively, it can determine the target valid key value based on historical valid key values ​​and the current valid key value, so as to ensure the accurate identification of the target valid key value and the accuracy of the function identification of the combination key.

[0116] In one embodiment, such as Figure 3 As shown, the keyboard scanning circuit also includes a glitch detection circuit, which is connected to the output decoding circuit.

[0117] The output decoding circuit is also used to, when the current scan number is detected to be the target scan number, if the single scan result corresponding to the current scan number is invalid, then obtain the glitch detection result if there is a glitch; if the single scan result corresponding to the current scan number is valid, then obtain the glitch detection result if there is no glitch.

[0118] The burr detection circuit is used to output a burr detection signal based on the burr detection results.

[0119] As an example, the output decoding circuit is connected to the output change counter. When the output change counter is detected to be zero, the output decoding circuit determines that the current scan of the keyboard keys corresponding to the target key count N has been completed. At this point, the current scan count can be updated. When the current scan count is updated from 0 to 1, the second level state corresponding to the target key count N collected during the current scan can be used to determine whether a valid key was detected in this scan, thus obtaining the single scan result corresponding to the current scan count, i.e., obtaining the first single scan result. In this example, if the first single scan result is invalid, it indicates that the keyboard likely has glitch issues, and a glitch detection result with glitch presence can be obtained; if the first single scan result is valid, it indicates that the keyboard likely does not have glitch issues, and a glitch detection result without glitch presence can be obtained.

[0120] As an example, the glitch detection circuit receives two glitch detection results: the presence of glitch and the absence of glitch. Based on this result, it determines the output glitch detection signal. For instance, a glitch detection signal of 1 can represent the presence of a glitch, and a glitch detection signal of 0 can represent the absence of a glitch. This allows for subsequent signal control based on the glitch detection signal, preventing glitch from affecting the control of keyboard keys. For example, when the glitch detection circuit communicates with the keyboard MCU, the keyboard MCU can determine whether there is a glitch on the current keyboard key based on the glitch detection signal output by the glitch detection circuit, thereby performing subsequent signal control and preventing glitch from affecting the control of keyboard keys.

[0121] In one embodiment, the output decoding circuit is further configured to output a first update instruction to the state machine transition circuit when the current keyboard state is idle and the first level state transitions from high level to low level.

[0122] The state machine transition circuit is also used to update the current keyboard state from idle state to pressed state according to the first update instruction;

[0123] The output decoding circuit is also used to output a second update instruction to the state machine jump circuit when the result of a single scan is invalid.

[0124] The state machine transition circuit is also used to update the current keyboard state from the pressed state to the idle state according to the second update instruction;

[0125] The output decoding circuit is also used to output a third update instruction to the state machine transition circuit after obtaining the key recognition result;

[0126] The state machine transition circuit is also used to update the current keyboard state from pressed state to idle state according to the third update instruction.

[0127] As an example, the output decoding circuit can generate a first update instruction when the current keyboard state is idle and the first level state transitions from high to low, and send the first update instruction to the state machine transition circuit. This first update instruction refers to the instruction generated by the output decoding circuit when the current keyboard state is idle and the first level state transitions from high to low, used to control the state machine transition circuit to perform a state update.

[0128] In this example, the state machine transition circuit in the idle state, after receiving the first update instruction sent by the output decoding circuit, can update the current keyboard state from the idle state to the pressed state to reflect that a keyboard key has been pressed at the current moment. This ensures that the current keyboard state is pressed until the output decoding circuit completes the current key scan and key recognition. As a result, when the output decoding circuit receives the first level state in the next moment, it will transition from a high level to a low level, and will not trigger a new key scan and key recognition. This helps to ensure the normal operation of the current key scan and key recognition, thereby ensuring the reliability of the circuit.

[0129] As an example, the state machine transition circuit is connected to the output decoding circuit. Each time the current change count is reset to zero, the output decoding circuit determines the single-scan result based on all the acquired second-level states. If the single-scan result is invalid, a second update instruction is generated and sent to the state machine transition circuit. This second update instruction refers to the instruction generated by the output decoding circuit when each single-scan result is invalid, used to control the state machine transition circuit to update its state.

[0130] In this example, the state machine transition circuit in the pressed state, after receiving the second update instruction sent by the output decoding circuit, can update the current keyboard state from the pressed state to the idle state to reflect that no keyboard key is pressed at the current moment. This allows the output decoding circuit to trigger a new key scan and key recognition when it receives the first level state transitioning from high level to low level at the next moment. This helps to ensure the normal operation of subsequent key scans and key recognition, thereby ensuring the reliability of the circuit.

[0131] As an example, the state machine transition circuit is connected to the output decoding circuit. Each time the output decoding circuit detects that the current scan count has been reset to zero, it needs to obtain the key recognition result based on the single scan result corresponding to the target scan count. This result can then form a third update instruction, which is sent to the state machine transition circuit. In this example, regardless of whether the key recognition result is an invalid single scan or contains a currently valid key value, since the key scan and key recognition corresponding to that key action have been completed when the key recognition result is obtained, a third update instruction can be formed to control the state machine transition circuit to update its state. This third update instruction refers to the instruction formed by the output decoding circuit after obtaining the key recognition result, used to control the state machine transition circuit to update its state.

[0132] In this example, the state machine transition circuit in the pressed state, after receiving the third update instruction sent by the output decoding circuit, can update the current keyboard state from the pressed state to the idle state to reflect that no keyboard key is pressed at the current moment. This allows the output decoding circuit to trigger a new key scan and key recognition when it receives the first level state transitioning from high level to low level in the next moment. This helps to ensure the normal operation of subsequent key scans and key recognition, thereby ensuring the reliability of the circuit.

[0133] In one embodiment, such as Figure 4 As shown, the keyboard scanning circuit also includes a timeout detection circuit, which is connected to the output decoding circuit and the state machine jump circuit. It is used to determine the waiting time for updating based on the current time and the instruction generation time corresponding to the target update instruction. If the waiting time for updating exceeds the timeout threshold, and the current keyboard state remains pressed, a timeout reset signal is generated and output to the state machine jump circuit.

[0134] The state machine transition circuit is also used to update the current keyboard state from the pressed state to the idle state based on the timeout reset signal;

[0135] The target update instruction is either the second update instruction or the third update instruction.

[0136] The target update instruction refers to the instruction used to control the state machine transition circuit to update its state, specifically the instruction used to control the state machine transition circuit to update from the pressed state to the idle state. In this example, the target update instruction can be either a second update instruction or a third update instruction. The instruction generation time refers to the moment when the output decoding circuit generates the target update instruction. The timeout duration threshold is a pre-set duration threshold used to evaluate whether the timeout standard has been met.

[0137] As an example, when the output decoding circuit generates a target update instruction such as a second update instruction or a third update instruction, it can record the instruction generation time of that target update instruction.

[0138] In this example, after the timeout detection circuit detects the output decoding circuit generating the target update instruction, it needs to obtain the time of instruction generation and then determine the time difference between the current time and the instruction generation time as the waiting update duration. The timeout detection circuit also needs to determine whether the real-time determined waiting update duration has reached the timeout duration threshold. If the waiting update duration reaches the timeout duration threshold, it needs to determine whether the current keyboard state has changed from a pressed state to an idle state. If the current keyboard state remains pressed, it means that the state machine transition circuit has not updated the state according to the target update instruction in a timely manner. At this time, the timeout detection circuit needs to generate a timeout reset signal and send this timeout reset signal to the state machine transition circuit. Understandably, this timeout reset signal is an indicator formed when the state machine transition circuit fails to update in a timely manner.

[0139] In this example, the state machine transition circuit can restore the current keyboard state from the pressed state to the default state, i.e., update it from the pressed state to the idle state, based on the timeout reset signal sent by the timeout detection circuit.

[0140] Furthermore, the timeout detection circuit can also send a timeout reset signal to other circuits such as the output decoding circuit, key value detection circuit, basic counter, output change counter, and scan count counter, so that the state of other circuits is restored to the default state. For example, the current basic value in the basic counter is cleared, the current change count in the output change counter is cleared, and the current scan count in the scan count counter is cleared, so as to ensure the reliability and anti-interference capability of the keyboard scanning circuit.

[0141] Understandably, using a timeout detection circuit for timeout detection allows the state machine jump circuit to be restored to the default state based on the generated timeout reset signal, thus ensuring the reliability and anti-interference capability of the keyboard scanning circuit.

[0142] In one embodiment, such as Figure 5 As shown, the keyboard scanning circuit also includes an asynchronous reset circuit. The asynchronous reset circuit is connected to the state machine transition circuit and the key value detection circuit. When the current keyboard state is updated from the pressed state to the idle state, the key value detection circuit acquires the third level state corresponding to the keyboard scanning input interface. If the third level state is a transition from high level to low level, an asynchronous reset signal is generated and output to the state machine transition circuit.

[0143] The state machine transition circuit is also used to reset the current keyboard state to the pressed state based on the asynchronous reset signal.

[0144] The asynchronous reset circuit is used to achieve asynchronous reset and synchronous release.

[0145] As an example, the output decoding circuit, upon generating a second or third update instruction (or similar target update instruction), can control the state machine transition circuit to update the current keyboard state from a pressed state to an idle state based on this target update instruction. The target update instruction is the instruction used to control the state machine transition circuit to update the state, specifically the instruction used to control the state machine transition circuit to update from a pressed state to an idle state. In this example, the target update instruction can be either a second or a third update instruction.

[0146] In this example, after the asynchronous reset circuit detects the output decoding circuit generating a target update instruction and controls the state machine transition circuit to update the current keyboard state from pressed to idle, the key value detection circuit acquires the third-level state corresponding to the keyboard scan input interface. Understandably, at the instant the current keyboard state changes from pressed to idle, as the third-level state transitions from high to low, the asynchronous reset circuit generates an asynchronous reset signal and sends this signal to the state machine transition circuit to reset the state.

[0147] In this example, the state machine transition circuit can reset the current keyboard state from idle to pressed state based on the asynchronous reset signal sent by the asynchronous reset circuit. Understandably, using an asynchronous reset circuit to control the state machine transition circuit for asynchronous reset ensures the reliability and anti-interference capability of the keyboard scanning circuit.

[0148] In one embodiment, such as Figure 6 As shown, the keyboard scanning circuit also includes a turn-by-turn control circuit, which is connected to the output decoding circuit and is used to output the first interval duration and the second interval duration to the output decoding circuit.

[0149] The output decoding circuit is used to alternately control the keyboard scanning output interface to output a low level according to the first interval duration and the second interval duration, so as to realize key scanning.

[0150] The first and second interval durations are both preset durations, which can be set from 10µs to 1ms. The first interval duration is specifically the interval used to control all keyboard scan output interfaces to go high after a certain keyboard scan input interface is pulled low. For example, when keyboard scan input interface KSI0 goes low, all keyboard scan output interfaces need to be pulled high after the first interval duration. The second interval duration is the interval used to control all keyboard scan output interfaces to output a low level in turn after all keyboard scan output interfaces have gone high. For example, after all keyboard scan output interfaces have gone high, every second interval duration, all keyboard scan output interfaces need to be controlled to output a low level in turn to ensure that the pulling high or low of all keyboard scan output interfaces does not occur simultaneously, thereby improving power supply integrity.

[0151] like Figure 7 In the timing diagram of the keyboard scanning circuit shown, the key scan output interfaces KSO0-KSO15 are all low by default. Assuming that a key corresponding to key scan output interface KSO0 and keyboard scan input interface KSI0 is pressed, keyboard scan input interface KSI0 is pulled low. After a first interval Tgap1 (configurable, 1ms, 3ms, 5ms, 7ms, 9ms, 11ms), key scan output interfaces KSO0-KSO15 are all pulled high. After a second interval Tgap2 (configurable, 25us, 50us, 75us, 100us), KSO low pulse signals are generated alternately (duration configurable, 15us, 20us, 25us, 30us) to achieve scan control operation. In this example, when key scan output interface KSO0 is pulled low, it detects that keyboard scan input interface KSI0 is low, thus completing the first scan recognition and determining the single scan key value corresponding to the first scan recognition. After the first scan and recognition is completed, and after a first interval of time Tgap1, the second scan begins, directly acquiring the single scan key value corresponding to the second scan and recognition. When the target scan count is two, if the two single scan key values ​​are the same, then the single scan key value can be considered the current valid key value.

[0152] In one embodiment, such as Figure 8 As shown, a keyboard key recognition method is provided, including:

[0153] S801: Acquires the first level state corresponding to the keyboard scan input interface;

[0154] S802: Get the current keyboard status;

[0155] S803: When the current keyboard state is idle and the first level state is transitioning from high to low, control the keyboard scan output interface to perform key scanning;

[0156] S804: After controlling the keyboard scan output interface to perform key scanning, acquire the second level state corresponding to the keyboard scan input interface;

[0157] S805: Performs key recognition based on the second level state.

[0158] As an example, in step S801, a key value detection circuit connected to the keyboard scanning input interface is used. This circuit needs to acquire the first level state corresponding to the keyboard scanning input interface in real time. When a keyboard key is not pressed, the first level state acquired by the key value detection circuit is high; at the instant a keyboard key is pressed, the first level state acquired by the key value detection circuit transitions from high to low. Understandably, the key value detection circuit acquires a first level state every unit of time. If the two first level states acquired at consecutive moments are high and low respectively, meaning the key value detection circuit detects the keyboard scanning input interface as high and low, and a transition from high to low is achieved, it can be determined that a keyboard key has been pressed.

[0159] As an example, in step S802, the current keyboard state output by the state machine transition circuit is obtained. This current keyboard state can reflect whether a keyboard key was pressed before the current time T1. For example, it can reflect whether a keyboard key was pressed at the previous time T0 before the current time T1. Specifically, it can be an idle state or a pressed state.

[0160] As an example, in step S803, the output decoding circuit processes the first level state acquired by the key value detection circuit and the current keyboard state corresponding to the state machine transition circuit. When the current keyboard state is idle, it means that no keyboard key was pressed at the previous moment T0, that is, the first level state acquired at the previous moment T0 was high. When the first level state transitions from high to low, it means that the first level state acquired at the previous moment T0 was high, and the first level state acquired at the current moment T1 is low, that is, the keyboard scanning input interface transitions from high to low. The transition to a low level indicates that a keyboard key has been pressed at the current time T1. Therefore, when the keyboard is currently idle and the first level transitions from high to low, it can be determined that a keyboard key has been pressed at the current time T1. At this point, it is necessary to control the keyboard scanning output interface to perform key scanning, that is, to control the keyboard scanning output interface to output different levels that can achieve key scanning according to specific rules. For example, control all keyboard scanning output interfaces to output low levels in turn to complete the scanning of all keyboard keys, so as to complete key recognition based on the second level state collected by the key value detection circuit.

[0161] As an example, in step S804, after the key value detection circuit controls the keyboard scanning output interface to perform key scanning (for example, after controlling all keyboard scanning output interfaces to output low level in turn), it is necessary to collect the second level state corresponding to the keyboard scanning input interface in real time. This second level state can be either high or low. In this example, each keyboard scanning output interface is matched with a keyboard scanning input interface, corresponding to the same keyboard key. For example, any keyboard key A is connected to the keyboard scanning circuit through the keyboard scanning input interface and the keyboard scanning output interface to ensure normal signal transmission.

[0162] As an example, in step S805, after the output decoding circuit controls the keyboard scanning output interface to perform key scanning, it receives the second level state corresponding to the keyboard scanning input interface, which is collected in real time by the key value detection circuit, so as to complete key recognition based on the second level state. In this example, when there are S keyboard keys, it is necessary to control the S keyboard scanning output interfaces to output low level in turn, so as to determine which keyboard key is pressed based on the second level state corresponding to the keyboard scanning output interface of each keyboard scanning output interface, and thus identify the key value corresponding to the pressed keyboard key. For example, when controlling the keyboard scanning output interface to perform key scanning specifically involves controlling all keyboard scanning output interfaces to output low level in turn, after the output decoding circuit controls the keyboard scanning output interface KSOi corresponding to the i-th keyboard key to output low level, it can collect the second level state corresponding to the keyboard scanning output interface KSIi corresponding to the keyboard scanning output interface KSOi, and determine whether the i-th keyboard key is pressed based on the second level state. For example, when the second level is low, it is determined that the i-th keyboard key is pressed; when the second level is high, it is determined that the i-th keyboard key is not pressed, so as to identify the key value corresponding to the i-th keyboard key.

[0163] In the keyboard key recognition method provided in this embodiment, key scanning is only performed by controlling the keyboard scanning output interface when the current keyboard state is idle and the first level state transitions from high to low. This ensures that key scanning is only executed when a key is pressed, avoiding triggering key scanning when the condition of the current keyboard state being idle and the first level state transitioning from high to low is not met. This saves system power consumption and improves circuit reliability. By controlling the keyboard scanning output interface to perform key scanning and completing key recognition based on the second level state corresponding to the keyboard scanning input interface, the key scanning and key recognition process can be completed. When the keyboard scanning circuit is applied to the keyboard, it does not need to occupy the CPU resources of the keyboard MCU, which helps to ensure the operating efficiency of the keyboard MCU.

[0164] In one embodiment, after step S803, after controlling the keyboard scanning output interface to perform key scanning, the keyboard key recognition method further includes:

[0165] S901: When the target clock edge is received, update the current base value to the target base value. When the output decoding circuit controls the keyboard scanning output interface to perform key scanning, control the current base value to be cleared to zero.

[0166] S902: When the current base value is detected to be zero, update the current number of changes. If the current number of changes reaches the target number of key presses, control the current number of changes to be zero.

[0167] S903: When the current change count is detected to be zero, update the current scan count. If the current scan count reaches the target scan count, control the current scan count to be zero.

[0168] S904: Based on the current base value, the current number of changes, and the current number of scans, complete the key scanning and key recognition.

[0169] As an example, in step S901, a base counter is used to receive the current clock edge in real time. When the current clock edge is the target clock edge, the base counter is first triggered to start counting, updating the current base value to the target base value, that is, changing the current base value from 0 to 1. Then, when the base counter changes the current base value from 0 to 1, the output decoding circuit can control the keyboard scanning output interface to perform key scanning. Specifically, the output decoding circuit can control the keyboard scanning output interface corresponding to the i-th keyboard key to output a low level. In each scanning control process, the output decoding circuit can control all keyboard scanning output interfaces to be pulled high or all low to realize the keyboard scanning operation. Understandably, when the output decoding circuit controls the keyboard scanning output interface to output a low level, the key value detection circuit can collect the second level state corresponding to the keyboard scanning input interface so that key recognition can be completed subsequently based on the collected second level state. Finally, when the basic counter detects that the output decoding circuit controls the keyboard scanning output interface to perform key scanning, that is, after controlling the keyboard scanning output interface to output a low level, it needs to control the current basic value to be cleared, that is, change the current basic value from 1 to 0, so that when the target clock edge is received next, the current basic value can be changed from 0 to 1, and then based on the current basic value, the keyboard scanning output interface can be controlled to output a low level, thereby ensuring the reliability of the keyboard scanning circuit.

[0170] As an example, in step S902, an output change counter is used to continuously monitor whether the current base value in the base counter is cleared to zero. Each time it is monitored that the current base value is cleared to zero, the current change count N1 needs to be updated, that is, incremented by 1 based on the current change count N0 at the previous moment, so as to obtain the current change count N1 corresponding to the current moment, that is, N1 = N0 + 1. When the output change counter obtains the updated current change count N1, it needs to compare the current change count N1 with a preset target key count N; if the current change count N1 reaches the target key count N (i.e., N1 = N), it is determined that the current key scan is completed. At this time, it is necessary to control the current change count to be cleared to zero so that when the key scan is performed next time, it can be re-counted, thus ensuring the reliability of the keyboard scan circuit. Understandably, if the current change count N1 does not reach the target key count N (i.e., N1 < N), it is necessary to continue to monitor whether the current base value is cleared to zero.

[0171] As an example, in step S903, a scan count counter is used to continuously monitor whether the current change count in the output change counter is cleared to zero. Each time it is monitored that the current change count is cleared to zero, the current scan count M1 needs to be updated, that is, incremented by 1 based on the current scan count M0 at the previous moment, so as to obtain the current scan count M1 corresponding to the current moment, that is, M1 = M0 + 1. After the scan count counter obtains the updated current scan count M1, it needs to compare the current scan count M1 with a preset target scan count M; if the current scan count M1 reaches the target scan count M (i.e., M1 = M), it is determined that the key scan is completed. At this time, the current scan count can be cleared to zero so that when it is monitored next time that the current keyboard state is the idle state and the first level state changes from high level to low level, the key scan can be re-performed, thus ensuring the reliability of the keyboard scan circuit. Understandably, if the current scan count M1 does not reach the target scan count M (i.e., M1 < M), it is necessary to continue to monitor whether the current change count in the output change counter is cleared to zero.

[0172] As an example, in step S904, an output decoding circuit is used to complete key scan and key recognition based on the current base value, the current change count, and the current scan count. For example, the output decoding circuit can control the keyboard scan output interface to output a low level according to the change of the current base value to complete the key scan; it can also complete key recognition according to the current change count and the current scan count.

[0173] In the keyboard key recognition method provided in this embodiment, the current base number, current number of changes, and current number of scans can be updated according to the received target clock edge, so that the output decoding circuit can complete the key scanning and key recognition of all keyboard keys according to the value changes in different counters. When the keyboard scanning circuit is applied to the keyboard, it does not need to occupy the CPU resources of the keyboard MCU, which helps to ensure the operating efficiency of the keyboard MCU.

[0174] In one embodiment, such as Figure 10 As shown, step S904, which involves completing key scanning and key recognition based on the current base value, the current number of changes, and the current number of scans, includes:

[0175] S1001: When the current base value is detected to be the target base value, the keyboard scan output interface is controlled to output a low level to realize key scanning;

[0176] S1002: When the current number of changes is detected to be zero, obtain the second level state corresponding to the target number of keys, and obtain the single scan result corresponding to the current number of scans based on all the second level states;

[0177] S1003: When the current scan count is detected to be zero, obtain the single scan result corresponding to the target scan count, and obtain the key recognition result based on all single scan results.

[0178] As an example, in step S1001, the output decoding circuit listens to the current basic value recorded by the basic counter. When the current basic value is the target basic value, the keyboard scanning output interface needs to be controlled to output a low level so that the key value detection circuit can collect the second level state corresponding to the keyboard scanning input interface. That is, every time the current basic value of the basic counter changes from 0 to 1, the output decoding circuit needs to control the keyboard scanning output interface to output a low level once to scan a keyboard key. At this time, the key value detection circuit can collect the second level state corresponding to the keyboard scanning input interface that matches the keyboard scanning output interface and feed the second level state back to the output decoding circuit. It can be understood that when the second level state collected by the key value detection circuit is low, it is determined that the keyboard key corresponding to the keyboard scanning input interface is pressed; when the second level state collected by the key value detection circuit is high, it is determined that the keyboard key corresponding to the keyboard scanning input interface is not pressed, which is a release key.

[0179] As an example, in step S1002, an output decoding circuit monitors the output change counter. When the output change counter is detected to be zero, it is determined that the current scan of the keyboard keys corresponding to the target key count N has been completed. At this time, it is necessary to obtain the current scan count recorded by the scan count counter. The second level states corresponding to the target key count N collected during the current scan can be used to determine whether a valid key has been identified in this scan, so as to obtain the single scan result corresponding to the current scan count. That is, based on whether the N second level states are high or low, it is determined whether the current scan is valid, so as to obtain the single scan result of single scan validity or single scan invalidity. When the single scan result is single scan validity, the single scan key value can also be obtained. This single scan key value refers to the key value identified in this scan.

[0180] As an example, an output decoding circuit is used to monitor the current scan count being reset to zero. When the current scan count is detected to be zero, it is determined that a scan operation matching the target scan count M has been completed. Based on the acquired M single scan results, the final key recognition is completed. That is, based on the M single scan results, it is determined whether a valid key exists. If a valid key exists, the current valid key value corresponding to the valid key is obtained. Here, a valid key refers to a key that has been determined to be pressed through key scanning, i.e., a key pressed when the first level state transitions from high to low. The current valid key value refers to the key value corresponding to the valid key.

[0181] In the keyboard key recognition method provided in this embodiment, the keyboard scanning output interface can be controlled to output a low level according to the current basic value to realize key scanning. Key recognition is realized according to the current number of changes and the current number of scans. When the keyboard scanning circuit is applied to the keyboard, it does not need to occupy the CPU resources of the keyboard MCU, which helps to ensure the operating efficiency of the keyboard MCU.

[0182] In one embodiment, such as Figure 11 As shown, step S1002, that is, when the current change count is detected to be zero, obtains the second level state corresponding to the target number of keys, and obtains the single scan result corresponding to the current scan count based on all the second level states, including:

[0183] S1101: When the current number of changes is detected to be zero, obtain the second level state corresponding to the target number of buttons;

[0184] S1102: If all second level states are high, then obtain the single scan result that is invalid for a single scan;

[0185] S1103: If there is a second level state that is low, then obtain the valid single scan result of the single scan.

[0186] As an example, in step S1101, the output decoding circuit is used to monitor the current number of changes of the output change counter. When the current number of changes of the output change counter is detected to be zero, it is determined that the scan of N keyboard keys has been completed. The second level state corresponding to the keyboard scan input interface of the N keyboard keys can be obtained. The second level state can be either high level or low level.

[0187] In one example, in step S1102, the output decoding circuit monitors the second level state corresponding to N keyboard keys. When the second level state corresponding to all N keyboard keys is high, it is determined that none of the N keyboard keys were pressed during the current scan, thus the scan is considered invalid. Therefore, a single scan result indicating invalidity can be obtained. Correspondingly, when the output decoding circuit detects that the current scan count has been reset to zero, and its single scan result is invalid, the scan is considered invalid, and the key recognition result indicating invalidity can be directly output. This eliminates the need to wait for the current scan count to reset to zero, thus ending the key scan and recognition process, saving waiting time, simplifying the processing flow, and improving processing efficiency.

[0188] As an example, in step S1103, the output decoding circuit is used to monitor the second level state corresponding to N keyboard keys. When there is a second level state that is low among the N keyboard keys, it is determined that one of the keyboard keys is in a pressed state during this scan, and thus the scan behavior is determined to be a valid behavior. Therefore, a single scan result that is valid can be obtained.

[0189] In one embodiment, such as Figure 12 As shown, in step 1003, based on all single scan results, the key recognition results are obtained, including:

[0190] S1201: If a single scan result is invalid, output the key recognition result of invalid single scan;

[0191] S1202: If all single scan results are valid, obtain the single scan key value corresponding to the target number of scans, and obtain the key recognition result based on all single scan key values.

[0192] Among them, the currently valid key value is the key value identified for a single key press.

[0193] Each time the output decoding circuit detects that the current scan count has been reset to zero, it completes a single scan operation corresponding to the current scan count and obtains a single scan result corresponding to the target scan count. When the target scan count is M, M single scan results can be obtained. Each single scan result can be either valid or invalid. Therefore, the output decoding circuit can perform one of the following operations based on all single scan results:

[0194] As an example, in step S1201, when the output decoding circuit outputs a key recognition result indicating that a single scan is invalid, it outputs a key recognition result indicating that the single scan is invalid. In this example, if any of the M single scan results is invalid, the output decoding circuit determines that no corresponding single scan key value was recognized after the single scan operation. In this case, it can directly output a key recognition result indicating that the single scan is invalid, without performing any subsequent operations, thus ending the current key scan and key recognition process. This helps save waiting time, simplify the processing flow, and improve processing efficiency.

[0195] As an example, in step S1202, when all single-scan results are valid, the output decoding circuit acquires the single-scan key value corresponding to the target number of scans, and obtains the key recognition result based on all single-scan key values. In this example, when M single-scan results are valid, the output decoding circuit can acquire the single-scan key value recognized in each scan, thus acquiring M single-scan key values. Since the M single-scan key values ​​may be the same or different, it is necessary to compare and analyze all single-scan results to determine the final key recognition result, thereby ensuring the accuracy of the key recognition result.

[0196] In one embodiment, such as Figure 13 As shown, in step S1202, based on all single-scan key values, the key recognition result is obtained, including:

[0197] S1301: If there are different key values ​​in a single scan, output the key recognition result of invalid single scan;

[0198] S1302: If all single scan key values ​​are the same, determine the current valid key value based on the single scan key value, and output the key recognition result containing the current valid key value.

[0199] When all M single-scan results are valid, the output decoding circuit can obtain M single-scan key values. The M single-scan key values ​​can be the same or different. Therefore, the output decoding circuit can perform one of the following operations based on all single-scan key values.

[0200] As an example, in step S1301, after the output decoding circuit obtains M single-scan key values, it needs to determine whether the M single-scan key values ​​are the same. If there are different single-scan key values, it cannot be determined which valid key value it corresponds to. Therefore, the key recognition result of invalid single scan can be output.

[0201] As an example, in step S1302, after acquiring M single-scan key values, the output decoding circuit needs to determine whether the M single-scan key values ​​are the same. If all single-scan key values ​​are the same, then the single-scan key value is determined as the current valid key value, and the key recognition result containing the current valid key value is output to ensure the accuracy of the current valid key value. Understandably, when the target scan count is 1, only 1 single-scan key value is acquired, and this current scan key value can be directly determined as the current valid key value.

[0202] In one embodiment, such as Figure 14 As shown, after step S1003, that is, after obtaining the key recognition results based on all single scan results, the keyboard key recognition method further includes:

[0203] S1401: When the key recognition result contains the current valid key value, determine the historical valid key value and obtain the key interval duration corresponding to the current valid key value and the historical valid key value;

[0204] S1402: Determine the target valid key value based on the key press interval duration and the currently valid key value.

[0205] Among them, the target valid key value refers to the key value that is finally identified.

[0206] As an example, when the key recognition result is valid, the output decoding circuit outputs a currently valid key value for each key scan. Since there are also cases of key combinations during the current keyboard recognition process, such as the Ctrl+C shortcut on a computer keyboard, the output decoding circuit also needs to perform the following operation after recognizing and obtaining the key recognition result containing the currently valid key value to determine the final target valid key value:

[0207] As an example, in step S1401, when the key recognition result includes the current valid key value, the output decoding circuit needs to obtain the historical valid key value corresponding to the current valid key value. Here, the current valid key value can be understood as the key value of the keyboard key scanned and recognized at the current moment. Correspondingly, the historical valid key value can be understood as the key value of the keyboard key scanned and recognized at a previous moment. When determining the current valid key value and the historical valid key value, the output decoding circuit needs to obtain the current key value generation time corresponding to the current valid key value and the historical key value generation time corresponding to the historical valid key value, respectively, and determine the key interval duration as the time difference between the current key value generation time and the historical key value generation time. Understandably, this key interval duration can be understood as the time difference between the generation times of two valid key values. When there is only one historical valid key value, the key interval duration is the time difference between the current key value generation time and the historical key value generation time corresponding to that historical valid key value; when there are at least two historical valid key values, the key interval duration is the time difference between the current key value generation time and the historical key value generation time corresponding to the earliest historical valid key value.

[0208] As an example, in step S1402, after obtaining the key interval duration, the output decoding circuit needs to compare the key interval duration with a target duration threshold. Based on the comparison result, it assesses whether the current valid key value and historical valid key values ​​could be a combination key, thereby obtaining the final target valid key value to ensure the accuracy of target valid key value recognition. Here, the target duration threshold is a pre-set duration threshold used to evaluate whether the combination key condition is met.

[0209] In one embodiment, such as Figure 15 As shown, step S1402, which determines the target valid key value based on the key press interval duration and the currently valid key value, includes:

[0210] S1501: If the key press interval duration is greater than the target duration threshold, then the current valid key value is determined as the target valid key value;

[0211] S1502: If the key press interval duration is not greater than the target duration threshold, then based on the current valid key value and the historical valid key value, determine whether the key press combination rule is met, obtain the combination judgment result, and determine the target valid key value according to the combination judgment result.

[0212] As an example, in step S1501, after obtaining the key press interval duration, the output decoding circuit needs to compare the key press interval duration with a target duration threshold. If the key press interval duration is greater than the target duration threshold, it is determined that the key press interval duration between the current valid key value and the historical valid key value is too long, and it is highly unlikely to be a combination key. That is, it is determined that the current valid key value is most likely a single key, and the current valid key value is determined as the target valid key value. For example, suppose the key press interval duration between the current valid key value and the historical valid key value is Ts, the target duration threshold is Tm, the current valid key value is C, and the historical valid key value is Ctrl. When Ts > Tm, it is determined that the key press interval duration between the user pressing the keyboard keys C and Ctrl is too long. Therefore, C can be determined as the target valid key value.

[0213] As an example, in step S1502, after obtaining the key interval duration, the output decoding circuit needs to compare the key interval duration with a target duration threshold. If the key interval duration is not greater than the target duration threshold, it is determined that the key interval duration between the current valid key value and the historical valid key value is small, which may indicate a combination key. In this case, it is necessary to determine whether the key combination rule is met based on the current valid key value and the historical valid key value, and obtain the combination judgment result. Based on this combination judgment result, it is necessary to evaluate whether the current valid key value and the historical valid key value are a combination key, thereby obtaining the final target valid key value to ensure the accuracy of target valid key value recognition. The key combination rule here is a pre-configured rule used to reflect different key combinations so that they can complete specific function control.

[0214] In one embodiment, such as Figure 16 As shown, in step S1502, the target valid key value is determined based on the combination judgment result, including:

[0215] S1601: If the combination judgment result is that the key combination rule is satisfied, then the target valid key value is determined based on the current valid key value and the historical valid key value;

[0216] S1602: If the combination judgment result is that the key combination rule is not met, then the current valid key value is determined as the target valid key value.

[0217] As an example, in step S1601, the output decoding circuit determines whether the key combination rules are satisfied based on the current valid key value and the historical valid key value. If the current valid key value and the historical valid key value satisfy the key combination rules, it is determined that the current valid key value and the historical valid key value can form a combination key. Based on the combination of the current valid key value and the historical valid key value, the target valid key value can be determined so that the corresponding target control command can be generated based on the target valid key value. For example, if the current valid key value is C and the historical valid key value is Ctrl, then Ctrl+C satisfies the copy combination rule of the key combination rules, and Ctrl+C can be determined as the target valid key value.

[0218] As an example, in step S1602, the output decoding circuit determines whether the key combination rules are satisfied based on the current valid key value and the historical valid key value. If the current valid key value and the historical valid key value do not satisfy the key combination rules, it is determined that the current valid key value and the historical valid key value cannot form a key combination, and the current valid key value can be determined as the target valid key value. For example, if the current valid key value is Ctrl and the historical valid key value is C, it does not satisfy the key combination rules. Since C+Ctrl does not satisfy the key combination rules, it can be determined that the current valid key value and the historical valid key value are each a single key. Therefore, the current valid key value Ctrl can be determined as the target valid key value.

[0219] In this embodiment, the output decoding circuit can determine a single currently valid key value as the target valid key value based on the comparison result between the key interval duration and the target duration threshold, and whether it meets the key combination rules. Alternatively, it can determine the target valid key value based on historical valid key values ​​and the current valid key value, so as to ensure the accurate identification of the target valid key value and the accuracy of the function identification of the combination key.

[0220] In one embodiment, such as Figure 17 As shown, after step S1003, that is, when the current change count is detected to be zero, the second level state corresponding to the target key count is obtained. After obtaining the single scan result corresponding to the current scan count based on all the second level states, the keyboard key recognition method further includes:

[0221] S1701: When the current scan count is detected to be the target scan count, if the single scan result corresponding to the current scan count is invalid, then obtain the burr detection result with burrs; if the single scan result corresponding to the current scan count is valid, then obtain the burr detection result without burrs.

[0222] S1702: Output burr detection signal based on burr detection results.

[0223] As an example, in step S1701, an output decoding circuit monitors the current scan count. When the current scan count is updated from 0 to the target scan count (e.g., 1), the second level state corresponding to the target number of keys N collected during the current scan is used to determine whether a valid key has been identified in this scan, thus obtaining the single scan result corresponding to the current scan count, i.e., obtaining the first single scan result. In this example, if the first single scan result is invalid, it indicates that there is a high probability of glitch on the keyboard, and a glitch detection result with glitch can be obtained; if the first single scan result is valid, it indicates that there is a high probability that there is no glitch on the keyboard, and a glitch detection result without glitch can be obtained.

[0224] As an example, in step S1702, a glitch detection circuit receives the glitch detection result. Based on this result, it determines the output glitch detection signal. For instance, a glitch detection signal 1 can indicate the presence of a glitch, and a glitch detection signal 0 can indicate the absence of a glitch. This allows for subsequent signal control based on the glitch detection signal, preventing glitch from affecting the control of the keyboard keys. For example, when the glitch detection circuit communicates with the keyboard MCU, the keyboard MCU can determine whether there is a glitch on the current keyboard key based on the glitch detection signal output by the glitch detection circuit, thereby performing subsequent signal control and preventing glitch from affecting the control of the keyboard keys.

[0225] In one embodiment, such as Figure 18 As shown, the keyboard key recognition method also includes:

[0226] S1801: When the current keyboard state is idle and the first level state transitions from high level to low level, output the first update instruction, and update the current keyboard state from idle state to pressed state according to the first update instruction;

[0227] S1802: When the result of a single scan is invalid, output a second update instruction and update the current keyboard state from the pressed state to the idle state according to the second update instruction;

[0228] S1803: After obtaining the key recognition result, output the third update instruction, and update the current keyboard state from the pressed state to the idle state according to the third update instruction.

[0229] As an example, in step S1801, the output decoding circuit can generate a first update instruction when the current keyboard state is idle and the first level state transitions from high to low, and send the first update instruction to the state machine transition circuit. Correspondingly, the state machine transition circuit in the idle state, upon receiving the first update instruction from the output decoding circuit, can update the current keyboard state from idle to pressed, reflecting that a key has been pressed. This ensures that the current keyboard state is pressed until the output decoding circuit completes the current key scan and key recognition. Consequently, if the output decoding circuit receives a first level state transitioning from high to low in the next moment, it will not trigger a new key scan and key recognition, thus helping to ensure the normal operation of the current key scan and key recognition, and thereby ensuring circuit reliability.

[0230] As an example, in step S1802, a state machine transition circuit monitors the current number of changes. Each time the current number of changes is reset to zero, the single scan result needs to be determined based on all the collected second-level states. If the single scan result is invalid, a second update instruction can be generated and sent to the state machine transition circuit. Correspondingly, the state machine transition circuit in the pressed state, upon receiving the second update instruction from the output decoding circuit, can update the current keyboard state from pressed to idle, reflecting that no keyboard key is currently pressed. This ensures that when the output decoding circuit receives the first-level state transitioning from high to low in the next moment, it will trigger a new key scan and key recognition, helping to ensure the normal operation of subsequent key scans and key recognition, thereby guaranteeing circuit reliability.

[0231] As an example, in step S1803, the output decoding circuit monitors the current scan count. Each time the current scan count is detected to be zero, the key recognition result is obtained based on the single scan result corresponding to the target scan count. This generates a third update instruction, which is then sent to the state machine transition circuit. Regardless of whether the key recognition result is an invalid single scan or includes a currently valid key value, since the key scan and key recognition corresponding to that key action have been completed when the key recognition result is obtained, a third update instruction can be generated to control the state machine transition circuit to update the state. Correspondingly, the state machine transition circuit in the pressed state, upon receiving the third update instruction from the output decoding circuit, can update the current keyboard state from pressed to idle, reflecting that no key is currently pressed. This ensures that when the output decoding circuit receives the first level state transitioning from high to low in the next moment, it will trigger a new key scan and key recognition, helping to ensure the normal operation of subsequent key scans and key recognition, thereby ensuring circuit reliability.

[0232] In one embodiment, such as Figure 19 As shown, the keyboard key recognition method also includes:

[0233] S1901: Determine the waiting time for update based on the current time and the instruction generation time corresponding to the target update instruction; if the waiting time for update exceeds the timeout threshold, and the current keyboard state remains pressed, generate a timeout reset signal and output the timeout reset signal.

[0234] S1902: Based on the timeout reset signal, update the current keyboard state from pressed state to idle state;

[0235] The target update instruction is either the second update instruction or the third update instruction.

[0236] As an example, in step S1901, after the timeout detection circuit detects that the output decoding circuit has generated a target update instruction, it needs to obtain the time of instruction generation and then determine the time difference between the current time and the instruction generation time as the waiting update duration. The timeout detection circuit also needs to determine whether the real-time determined waiting update duration has reached a timeout duration threshold. If the waiting update duration reaches the timeout duration threshold, it needs to determine whether the current keyboard state has been updated from a pressed state to an idle state. If the current keyboard state remains pressed, it indicates that the state machine transition circuit has not updated the state according to the target update instruction in a timely manner. At this time, the timeout detection circuit needs to generate a timeout reset signal and send this timeout reset signal to the state machine transition circuit. Understandably, this timeout reset signal is an indicator formed when the state machine transition circuit fails to update in a timely manner.

[0237] As an example, in step S1902, the state machine transition circuit can restore the current keyboard state from the pressed state to the default state, i.e., update it from the pressed state to the idle state, based on the timeout reset signal sent by the timeout detection circuit, so as to ensure the reliability and anti-interference capability of the keyboard scanning circuit.

[0238] In one embodiment, such as Figure 20 As shown, the keyboard key recognition method also includes:

[0239] S2001: When the current keyboard state is updated from pressed state to idle state, the third level state corresponding to the keyboard scanning input interface is obtained. If the third level state is a transition from high level to low level, an asynchronous reset signal is generated and output to the state machine transition circuit.

[0240] S2002: Reset the current keyboard state to the pressed state according to the asynchronous reset signal.

[0241] As an example, in step S2001, after the asynchronous reset circuit detects that the output decoding circuit generates a target update instruction and controls the state machine transition circuit to update the current keyboard state from the pressed state to the idle state, the key value detection circuit acquires the third level state corresponding to the keyboard scanning input interface. Understandably, at the instant the current keyboard state changes from the pressed state to the idle state, as the third level state transitions from high to low, the asynchronous reset circuit can generate an asynchronous reset signal and send this signal to the state machine transition circuit to reset the state.

[0242] As an example, in step S2002, the state machine transition circuit can reset the current keyboard state from idle to pressed state based on the asynchronous reset signal sent by the asynchronous reset circuit. Understandably, using the asynchronous reset circuit to control the state machine transition circuit for asynchronous reset ensures the reliability and anti-interference capability of the keyboard scanning circuit.

[0243] In one embodiment, such as Figure 21 As shown, the keyboard scanning output interface is controlled to perform key scanning, including:

[0244] S2101: Obtain the duration of the first interval and the duration of the second interval;

[0245] S2102: Based on the first interval duration and the second interval duration, the keyboard scanning output interface is controlled to output a low level alternately to realize key scanning;

[0246] The first interval duration is the interval duration used to control all keyboard scan output interfaces to output a high level; the second interval duration is the interval duration used to control all keyboard scan output interfaces to output a low level.

[0247] As an example, in step S2101, an output decoding circuit is used to obtain a preset first interval duration and a second interval duration. Specifically, the first interval duration is the interval used to control all keyboard scan output interfaces to go high after a certain keyboard scan input interface is pulled low. The second interval duration is the interval used to control all keyboard scan output interfaces to output a low level in turn after all keyboard scan output interfaces are pulled high.

[0248] As an example, in step S2102, when the keyboard scan input interface KSI0 is pulled low, the output decoding circuit needs to control all keyboard scan output interfaces to be pulled high after the first interval. Correspondingly, after all keyboard scan output interfaces are pulled high, the output decoding circuit needs to sequentially control all keyboard scan output interfaces to output a low level in turn after every second interval, so as to ensure that the pulling high or pulling low of all keyboard scan output interfaces does not occur simultaneously, thereby improving power supply integrity.

[0249] This invention also provides a chip including the keyboard scanning and recognition circuit of the above embodiment. This circuit only controls the keyboard scanning output interface to perform key scanning when the current keyboard state is idle and the first level state transitions from high to low. This ensures that key scanning is only performed when a key is pressed, avoiding triggering key scanning when the conditions of an idle keyboard state and a high-to-low transition are not met, thus saving system power consumption and improving circuit reliability. An output decoding circuit controls the keyboard scanning output interface to perform key scanning, and completes key recognition based on the second level state corresponding to the keyboard scanning input interface. This allows the keyboard scanning circuit to complete the key scanning and recognition process using only hardware, eliminating the need to occupy the keyboard MCU's CPU resources when applied to the keyboard, thus helping to ensure the keyboard MCU's operating efficiency.

[0250] This invention also provides a keyboard, which includes keyboard keys and a keyboard MCU, and further includes the keyboard scanning circuit described in the above embodiments. The keyboard scanning circuit is connected to the keyboard keys and the keyboard MCU. Key scanning is only performed on the keyboard scanning output interface when the current keyboard state is idle and the first level state transitions from high to low. This ensures that key scanning is only performed when a key is pressed, avoiding triggering key scanning when the condition of an idle keyboard state and a high-to-low transition is not met, thus saving system power consumption and improving circuit reliability. An output decoding circuit controls the keyboard scanning output interface to perform key scanning, and completes key recognition based on the second level state corresponding to the keyboard scanning input interface. This allows the keyboard scanning circuit, as a hardware device, to complete the key scanning and key recognition process without occupying the CPU resources of the keyboard MCU, thus helping to ensure the operating efficiency of the keyboard MCU.

[0251] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A keyboard scan circuit, characterized by The method comprises the following steps: The key value detection circuit is connected with the keyboard scan input interface, and is used to collect a first level state corresponding to the keyboard scan input interface; The state machine jump circuit is connected with the key value detection circuit, and is used to output a current keyboard state; The output decoding circuit is connected with the key value detection circuit, the state machine jump circuit and the keyboard scan output interface, and is used to control the keyboard scan output interface to perform key scanning when the current keyboard state is an idle state and the first level state jumps from a high level to a low level; The key value detection circuit is further used to collect a second level state corresponding to the keyboard scan input interface after the keyboard scan output interface is controlled to perform key scanning; The output decoding circuit is further used to perform key recognition according to the second level state; The base counter is used to update a current base value to a target base value when a target clock edge is received, and control the current base value to be cleared when the output decoding circuit controls the keyboard scan output interface to perform key scanning; The output change counter is connected with the base counter, and is used to update a current change number when the current base value is cleared, and control the current change number to be cleared when the current change number reaches a target key number; The scan number counter is connected with the output change counter, and is used to update a current scan number when the current change number is cleared, and control the current scan number to be cleared when the current scan number reaches a target scan number; The output decoding circuit is connected with the base counter, the output change counter and the scan number counter, and is used to complete key scanning and key recognition according to the current base value, the current change number and the current scan number.

2. The keyboard scan circuit of claim 1, wherein, The output decoding circuit is further used to control the keyboard scan output interface to output a low level to realize key scanning when the current base value is the target base value; The output decoding circuit is further used to obtain the second level state corresponding to the target key number when the current change number is cleared, obtain a single scan result corresponding to the current scan number according to all the second level states; The output decoding circuit is further used to obtain a single scan result corresponding to the target scan number when the current scan number is cleared, and obtain a key recognition result according to all the single scan results.

3. The keyboard scan circuit of claim 2, wherein, The output decoding circuit is further used to obtain the second level state corresponding to the target key number when the current change number is cleared; if all the second level states are high levels, a single scan invalid single scan result is obtained; if one of the second level states is a low level, a single scan valid single scan result is obtained.

4. The keyboard scan circuit of claim 3, wherein, The output decoding circuit is further configured to output a single-scan invalid key recognition result when the single-scan result is single-scan invalid; obtain single-scan key values corresponding to the target scan number when all the single-scan results are single-scan valid; and obtain a key recognition result based on all the single-scan key values.

5. The keyboard scan circuit of claim 4, wherein, The output decoding circuit is further configured to output a single-scan invalid key recognition result when the single-scan key values are different; and determine a current valid key value according to the single-scan key values and output a key recognition result containing the current valid key value when all the single-scan key values are the same.

6. The keyboard scan circuit of claim 2, wherein, The output decoding circuit is further configured to determine a historical valid key value when the key recognition result contains the current valid key value; obtain a key interval duration corresponding to the current valid key value and the historical valid key value; and determine a target valid key value according to the key interval duration and the current valid key value.

7. The keyboard scan circuit of claim 6, wherein, The output decoding circuit is further configured to determine the current valid key value as the target valid key value when the key interval duration is greater than a target duration threshold; and determine the target valid key value based on the current valid key value and the historical valid key value when the key interval duration is not greater than the target duration threshold.

8. The keyboard scan circuit of claim 7, wherein, The output decoding circuit is further configured to determine the target valid key value according to the current valid key value and the historical valid key value when the combination judgment result satisfies the key combination rule; and determine the current valid key value as the target valid key value when the combination judgment result does not satisfy the key combination rule.

9. The keyboard scan circuit of claim 2, wherein, The keyboard scanning circuit further comprises a glitch detection circuit connected to the output decoding circuit. The output decoding circuit is further configured to obtain a glitch detection result indicating that there is a glitch when the single-scan result corresponding to the current scan number is single-scan invalid; and obtain a glitch detection result indicating that there is no glitch when the single-scan result corresponding to the current scan number is single-scan valid. The glitch detection circuit is configured to output a glitch detection signal according to the glitch detection result.

10. The keyboard scan circuit of claim 2, wherein, The output decoding circuit is further configured to output a first update instruction to the state machine jump circuit when the current keyboard state is an idle state and the first level state jumps from a high level to a low level. The state machine jump circuit is further configured to update the current keyboard state from the idle state to a pressed state according to the first update instruction. The output decoding circuit is further configured to output a second update instruction to the state machine jump circuit when the single-scan result is single-scan invalid. The state machine jump circuit is further configured to update the current keyboard state from the pressed state to the idle state according to the second update instruction. The output decoding circuit is further configured to output a third update instruction to the state machine jump circuit after obtaining the key recognition result. The state machine jump circuit is further configured to update the current keyboard state from the pressed state to the idle state according to the third update instruction.

11. The keyboard scan circuit of claim 10, wherein, The keyboard scan circuit further comprises a timeout detection circuit connected to the output decoding circuit and the state machine jump circuit, configured to determine a waiting update duration according to a current time and an instruction generation time corresponding to the target update instruction; When the waiting update duration is greater than a timeout duration threshold, if the current keyboard state maintains the pressed state, a timeout reset signal is generated and output to the state machine jump circuit; The state machine jump circuit is further configured to update the current keyboard state from the pressed state to the idle state according to the timeout reset signal. The target update instruction is the second update instruction or the third update instruction.

12. The keyboard scan circuit of claim 10, wherein, The keyboard scan circuit further comprises an asynchronous reset circuit connected to the state machine jump circuit and the key value detection circuit, configured to acquire a third level state corresponding to the keyboard scan input interface collected by the key value detection circuit when the current keyboard state is updated from the pressed state to the idle state, and generate an asynchronous reset signal and output the asynchronous reset signal to the state machine jump circuit if the third level state jumps from high level to low level. The state machine jump circuit is further configured to reset the current keyboard state to the pressed state according to the asynchronous reset signal.

13. The keyboard scan circuit of claim 1, wherein, The keyboard scan circuit further comprises a turn-by-turn jump control circuit connected to the output decoding circuit, configured to output a first interval duration and a second interval duration to the output decoding circuit. The output decoding circuit is configured to alternately control the control keyboard scan output interface to output low level according to the first interval duration and the second interval duration, so as to realize key scanning. The first interval duration is an interval duration for controlling all keyboard scan output interfaces to output high level, and the second interval duration is an interval duration for controlling all keyboard scan output interfaces to output low level.

14. A method of identifying a key of a keyboard, characterized by comprises: acquiring a first level state corresponding to a keyboard scan input interface; outputting a current keyboard state; controlling a keyboard scan output interface to perform key scanning when the current keyboard state is an idle state and the first level state jumps from high level to low level; acquiring a second level state corresponding to the keyboard scan input interface after controlling the keyboard scan output interface to perform key scanning; updating a current base value to a target base value when a target clock edge is received; and controlling the current base value to be cleared when it is detected that the output decoding circuit controls the keyboard scan output interface to perform key scanning; updating a current change number when it is detected that the current base value is cleared; and controlling the current change number to be cleared when the current change number reaches a target key number; updating a current scan number when it is detected that the current change number is cleared; and controlling the current scan number to be cleared when the current scan number reaches a target scan number; and According to the second level state, the current base value, the current change number and the current scan number, key scanning and key recognition are completed.

15. The keyboard key recognition method of claim 14, wherein, The key scanning and key recognition according to the second level state, the current base value, the current change number and the current scan number comprises: When the current base value is monitored to be a target base value, a keyboard scanning output interface outputs a low level to realize key scanning; When the current change number is monitored to be zero, the second level state corresponding to a target key number is obtained, and a single scan result corresponding to the current scan number is obtained according to all the second level states; When the current scan number is monitored to be zero, a single scan result corresponding to the target scan number is obtained, and a key recognition result is obtained according to all the single scan results.

16. The keyboard key recognition method of claim 15, wherein, The obtaining of the second level state corresponding to the target key number and the single scan result corresponding to the current scan number according to all the second level states when the current change number is monitored to be zero comprises: When the current change number is monitored to be zero, the second level state corresponding to a target key number is obtained; If all the second level states are high levels, a single scan invalid single scan result is obtained; If one of the second level states is a low level, a single scan valid single scan result is obtained.

17. The keyboard key recognition method of claim 15, wherein, The obtaining of the key recognition result according to all the single scan results comprises: If the single scan result is single scan invalid, a single scan invalid key recognition result is outputted; If all the single scan results are single scan valid, a single scan key value corresponding to the target scan number is obtained, and a key recognition result is obtained based on all the single scan key values.

18. The keyboard key recognition method of claim 17, wherein, The obtaining of the key recognition result based on all the single scan key values comprises: If the single scan key values are different, a single scan invalid key recognition result is outputted; If all the single scan key values are the same, a current valid key value is determined according to the single scan key value, and a key recognition result containing the current valid key value is outputted.

19. The method of claim 15, wherein, After the obtaining of the key recognition result according to all the single scan results, the keyboard key recognition method further comprises: When the key recognition result contains a current valid key value, a historical valid key value is determined, a key interval duration corresponding to the current valid key value and the historical valid key value is obtained, and a target valid key value is determined according to the key interval duration and the current valid key value. The determination of the target valid key value according to the key interval duration and the current valid key value comprises:

20. The keyboard key recognition method of claim 19, wherein, If the key interval duration is greater than a target duration threshold, the current valid key value is determined as the target valid key value; If the key interval duration is not greater than the target duration threshold, whether a key combination rule is satisfied is judged based on the current valid key value and the historical valid key value, a combination judgment result is obtained, and the target valid key value is determined according to the combination judgment result. ​ 21. The keyboard key recognition method of claim 20, wherein, The method further comprises: if the combination judgment result satisfies the key combination rule, determining a target effective key value according to the current effective key value and the historical effective key value; if the combination judgment result does not satisfy the key combination rule, determining the target effective key value as the current effective key value.

22. The method of claim 15, wherein, After the current change number is cleared, the second level state corresponding to the target key number is obtained, and a single scan result corresponding to the current scan number is obtained according to all the second level states, the method further comprises: if the single scan result corresponding to the current scan number is invalid, a burr detection result of existing burr is obtained when the current scan number is the target scan number; if the single scan result corresponding to the current scan number is valid, a burr detection result of non-existing burr is obtained; a burr detection signal is output according to the burr detection result.

23. The keyboard key recognition method of claim 15, wherein, The method further comprises: when the current keyboard state is an idle state and the first level state jumps from a high level to a low level, a first update instruction is output, and the current keyboard state is updated from the idle state to a pressed state according to the first update instruction; when the single scan result is invalid, a second update instruction is output, and the current keyboard state is updated from the pressed state to the idle state according to the second update instruction; after the key recognition result is obtained, a third update instruction is output, and the current keyboard state is updated from the pressed state to the idle state according to the third update instruction.

24. The keyboard key recognition method of claim 23, wherein, The method further comprises: a waiting update duration is determined according to an instruction generation time corresponding to a target update instruction at a current time; when the waiting update duration is greater than a timeout duration threshold, a timeout reset signal is generated and output if the current keyboard state maintains the pressed state; the current keyboard state is updated from the pressed state to the idle state according to the timeout reset signal; wherein the target update instruction is the second update instruction or the third update instruction.

25. The keyboard key recognition method of claim 23, wherein, The method further comprises: when the current keyboard state is updated from the pressed state to the idle state, a third level state corresponding to the keyboard scan input interface is obtained, and an asynchronous reset signal is generated and output to a state machine jump circuit if the third level state jumps from a high level to a low level; the current keyboard state is reset to the pressed state according to the asynchronous reset signal.

26. The keyboard key recognition method of claim 23, wherein, The method further comprises: a first interval duration and a second interval duration are obtained; the control keyboard scan output interface outputs a low level in turn according to the first interval duration and the second interval duration, so as to realize key scanning; wherein the first interval duration is an interval duration for controlling all keyboard scan output interfaces to output a high level; and the second interval duration is an interval duration for controlling all keyboard scan output interfaces to output a low level.

27. A chip, characterized by The keyboard scanning circuit according to any one of claims 1-13.

28. A keyboard comprising a keyboard key and a keyboard MCU, characterized in that, The keyboard scanning circuit according to any one of claims 1-13, connected with the keyboard keys and the keyboard MCU.

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