Display substrate and manufacturing method thereof, and display device

Abstract

A display substrate and a preparation method thereof, and a display device. The display substrate includes a first metal layer, a metal oxide layer, and a second metal layer stacked on a base, the metal oxide layer includes a first active layer, the first active layer includes a channel region, a source transition region, and a drain transition region, the source transition region and the drain transition region both include a first region and a second region, the conductivity of the first active layer corresponding to the first region is higher than the conductivity of the first active layer corresponding to the second region, or the oxygen content of the first active layer corresponding to the first region is less than the oxygen content of the first active layer corresponding to the second region, or the thickness of the first active layer corresponding to the first region is less than the thickness of the first active layer corresponding to the second region.

Description

[0001] This application claims the priority of the Chinese patent application filed with the China Patent Office on July 23, 2020, with application number 202010719363.6 and invention name “Display substrate, preparation method thereof, and display device”, the content of which should be understood as being incorporated into this application by reference. Technical Field

[0002] The exemplary embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a display substrate and a method for preparing the same, and a display device. Background Art

[0003] Organic Light Emitting Diode (OLED) display devices have the advantages of ultra-thinness, wide viewing angle, active light emission, high brightness, continuously adjustable light color, low cost, fast response speed, low power consumption, wide operating temperature range and flexible display, and have gradually become the next generation display technology with great development prospects. According to different driving modes, OLED can be divided into passive matrix drive (PM) type and active matrix drive (AM) type. AM OLED is a current-driven device that uses independent thin film transistors (TFT) to control each sub-pixel. Each sub-pixel can be driven to emit light continuously and independently. According to different light emission directions, OLED can be divided into top emission OLED and bottom emission OLED. Bottom emission OLED is the earliest structure used.

[0004] In OLED design, pixel aperture ratio is one of the important parameters and an important factor in improving the resolution of display devices, especially for bottom-emitting OLEDs. In order to ensure the capacity of the storage capacitor, the electrode plate of the storage capacitor needs to have a larger area. With the development of high-resolution (PPI) display technology, the sub-pixel size is getting smaller and smaller, making the driving circuit area occupy a larger and larger proportion of the pixel area, resulting in a significant reduction in the pixel aperture ratio. Summary of the invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] A display substrate comprises a first metal layer, a first insulating layer, a metal oxide layer, a second insulating layer and a second metal layer stacked on a substrate; the metal oxide layer comprises a first active layer, and the second metal layer comprises a first gate electrode, a first source electrode and a first drain electrode; the first active layer comprises a channel region, a source transition region and a drain transition region located on both sides of the channel region, and a source connection region located on a side of the source transition region away from the channel region and a drain connection region located on a side of the drain transition region away from the channel region; the source connection region is connected to the first source electrode, and the drain connection region is connected to the first drain electrode; the source transition region and the drain transition region both comprise a first region away from the channel region and a second region adjacent to the channel region; the conductivity of the first active layer corresponding to the first region is higher than the conductivity of the first active layer corresponding to the second region, or the oxygen content of the first active layer corresponding to the first region is less than the oxygen content of the first active layer corresponding to the second region, or the thickness of the first active layer corresponding to the first region is less than the thickness of the first active layer corresponding to the second region.

[0007] In an exemplary embodiment, the conductivity of the first active layer corresponding to the first region is higher than the conductivity of the first active layer corresponding to the source connection region and the drain connection region, or the oxygen content of the first active layer corresponding to the first region is less than the oxygen content of the first active layer corresponding to the source connection region and the drain connection region, or the thickness of the first active layer corresponding to the first region is less than the thickness of the first active layer corresponding to the source connection region and the drain connection region.

[0008] In an exemplary embodiment, the width of the first region is smaller than the width of the source connection region, or the width of the first region is smaller than the width of the drain connection region.

[0009] In an exemplary embodiment, the width of the first region is smaller than the width of the second region.

[0010] In an exemplary embodiment, the width of the first region is smaller than the width of the channel region.

[0011] In an exemplary embodiment, an orthographic projection of at least a portion of the first region in the source transition region on the substrate does not overlap with an orthographic projection of the first metal layer on the substrate, or an orthographic projection of at least a portion of the first region in the drain transition region on the substrate does not overlap with an orthographic projection of the first metal layer on the substrate.

[0012] In an exemplary embodiment, the first active layer further includes a source outer region located on a side of the source connection region away from the channel region and a drain outer region located on a side of the drain connection region away from the channel region.

[0013] In an exemplary embodiment, the width of the first region is smaller than the width of the source outer region, or the width of the first region is smaller than the width of the drain outer region.

[0014] In an exemplary embodiment, the width of the second region is greater than the width of the source outer region, or the width of the second region is greater than the width of the drain outer region.

[0015] In an exemplary embodiment, the width of the source outer region is smaller than the width of the source connection region, or the width of the drain outer region is smaller than the width of the drain connection region.

[0016] In an exemplary embodiment, the boundary of the orthographic projection of the first gate electrode on the substrate is located within the boundary of the orthographic projection of the second insulating layer on the substrate; the boundary of the orthographic projection of the channel region on the substrate is located within the boundary of the orthographic projection of the second insulating layer on the substrate.

[0017] In an exemplary embodiment, the display substrate includes a plurality of regularly arranged sub-pixels, each sub-pixel includes a pixel driving circuit and an organic electroluminescent diode electrically connected to the pixel driving circuit, the pixel driving circuit includes a storage capacitor, the storage capacitor includes a first electrode plate and a second electrode plate, and an orthographic projection of the first electrode plate on the substrate and an orthographic projection of the second electrode plate on the substrate have an overlapping area.

[0018] In an exemplary embodiment, the pixel driving circuit also includes a first transistor, a second transistor and a third transistor; the gate electrode of the first transistor is coupled to the second electrode of the second transistor, the first electrode of the first transistor is coupled to the first power line, the second electrode of the first transistor is coupled to the first electrode of the organic light-emitting diode, and the second electrode of the organic light-emitting diode is coupled to the second power line; the gate electrode of the second transistor is coupled to the first scan line, and the first electrode of the second transistor is coupled to the data line; the gate electrode of the third transistor is coupled to the second scan line, the first electrode of the third transistor is coupled to the compensation line, and the second electrode of the third transistor is coupled to the second electrode of the first transistor; the first electrode of the storage capacitor is coupled to the gate electrode of the first transistor, and the second electrode of the storage capacitor is coupled to the second electrode of the first transistor.

[0019] In an exemplary embodiment, the display substrate further includes a first conductive layer, the first conductive layer includes a first electrode plate of the storage capacitor, and the metal oxide layer includes a second electrode plate of the storage capacitor.

[0020] In an exemplary embodiment, the material of the first electrode plate includes a transparent conductive material, and the overlapping area is located in a light emitting area of ​​the display substrate.

[0021] In an exemplary embodiment, the first metal layer comprises a first plate of the storage capacitor, and the metal oxide layer comprises a second plate of the storage capacitor.

[0022] In an exemplary embodiment, the second metal layer comprises a first plate of the storage capacitor, and the metal oxide layer comprises a second plate of the storage capacitor.

[0023] In an exemplary embodiment, the first metal layer comprises a first plate of the storage capacitor, and the second metal layer comprises a second plate of the storage capacitor.

[0024] In an exemplary embodiment, the conductivity of the metal oxide layer corresponding to the second electrode plate is higher than the conductivity of the first active layer corresponding to the second region, or the oxygen content of the metal oxide layer corresponding to the second electrode plate is less than the oxygen content of the first active layer corresponding to the second region, or the thickness of the metal oxide layer corresponding to the second electrode plate is less than the thickness of the first active layer corresponding to the second region.

[0025] In an exemplary embodiment, the first metal layer includes a first power line and a first connecting electrode, the first connecting electrode is connected to the first electrode plate, and a transparent conductive film is arranged between the first metal layer and the substrate; the orthographic projection of the first connecting electrode on the substrate and the orthographic projection of the channel region of the first active layer on the substrate have an overlapping area.

[0026] In an exemplary embodiment, the first source electrode and the first drain electrode are arranged on a first insulating layer; the first drain electrode is arranged on a drain connection region of the first active layer and is connected to the first connection electrode through a first via hole; the first end of the first source electrode is connected to the first power line through a second via hole, and the second end of the first source electrode is arranged on a source connection region of the first active layer.

[0027] In an exemplary embodiment, the first source electrode and the first drain electrode are disposed on the second insulating layer; the first drain electrode is connected to the drain connection region of the first active layer through a first active via, and is connected to the first connection electrode through a first via; a first end of the first source electrode is connected to the first power line through a second via, and a second end of the first source electrode is connected to the source connection region of the first active layer through a second active via.

[0028] A display device comprises the above-mentioned display substrate.

[0029] A method for preparing a display substrate, comprising:

[0030] forming a first metal layer and a metal oxide layer in sequence on a substrate, wherein the metal oxide layer includes a first active layer;

[0031] A second insulating layer and a second metal layer are formed in sequence, and the first active layer is formed into a channel region, a source transition region and a drain transition region located on both sides of the channel region, and a source connection region located on the side of the source transition region away from the channel region and a drain connection region located on the side of the drain transition region away from the channel region through two conductor treatments; the second metal layer includes a first gate electrode, a first source electrode and a first drain electrode, the source connection region is connected to the first source electrode, and the drain connection region is connected to the first drain electrode; the source transition region and the drain transition region both include a first region away from the channel region and a second region adjacent to the channel region; the conductivity of the first active layer corresponding to the first region is higher than the conductivity of the first active layer corresponding to the second region, or the oxygen content of the first active layer corresponding to the first region is less than the oxygen content of the first active layer corresponding to the second region, or the thickness of the first active layer corresponding to the first region is less than the thickness of the first active layer corresponding to the second region.

[0032] In an exemplary embodiment, sequentially forming a first metal layer and a metal oxide layer on a substrate includes:

[0033] A transparent first electrode plate and a first metal layer are formed on the substrate, wherein a transparent conductive film is disposed between the first metal layer and the substrate; the first metal layer comprises a first power line and a first connecting electrode, and the first connecting electrode is connected to the first electrode plate;

[0034] forming a first insulating layer covering the first electrode plate and the first metal layer;

[0035] A metal oxide layer is formed on the first insulating layer, the metal oxide layer includes a first active layer and a second electrode plate, an orthographic projection of the second electrode plate on the substrate and an orthographic projection of the first electrode plate on the substrate have an overlapping area, and an orthographic projection of a channel region of the first active layer on the substrate and an orthographic projection of the first connecting electrode on the substrate have an overlapping area.

[0036] In an exemplary embodiment, a second insulating layer and a second metal layer are formed in sequence, and the first active layer is formed into a channel region, a source transition region and a drain transition region located on both sides of the channel region, a source connection region located on a side of the source transition region away from the channel region, and a drain connection region located on a side of the drain transition region away from the channel region through two conductor treatments, including:

[0037] forming a second insulating layer on the first active layer, and forming a first via hole and a second via hole on the first insulating layer; the second insulating layer covers a middle area of ​​the first active layer; the first via hole and the second via hole respectively expose the first connecting electrode and the first power line;

[0038] Performing a first conductorization process on the second electrode plate and the areas on both sides of the first active layer not covered by the second insulating layer to form a conductorized second electrode plate, and forming a source connection area and a drain connection area on both sides of the first active layer respectively;

[0039] A second metal layer is formed, and the photoresist on the second metal layer is retained; the second metal layer includes a first gate electrode, a first source electrode, and a first drain electrode; the first gate electrode is located in the middle area of ​​the first active layer, the first drain electrode is placed on the drain connection area, and is connected to the first connection electrode through the first via hole; the first end of the first source electrode is connected to the first power line through the second via hole, and the second end of the first source electrode is placed on the source connection area;

[0040] Using the second metal layer and the photoresist disposed on the second metal layer as a mask, etching the second insulating layer not covered by the second metal layer;

[0041] The second insulating layer, the second metal layer arranged on the second insulating layer and the photoresist arranged on the second metal layer are used as masks, and the second electrode plate and the first active layer not covered by the second insulating layer are subjected to a second conductorization process to form a channel region of the first active layer and a source transition region and a drain transition region located on both sides of the channel region, wherein the boundary of the orthographic projection of the first gate electrode on the substrate is located within the boundary range of the orthographic projection of the second insulating layer on the substrate; the boundary of the orthographic projection of the channel region on the substrate is located within the boundary range of the orthographic projection of the second insulating layer on the substrate, and the source transition region and the drain transition region both include a first region away from the channel region and a second region adjacent to the channel region; the conductivity of the first active layer corresponding to the first region is higher than the conductivity of the first active layer corresponding to the second region, or the oxygen content of the first active layer corresponding to the first region is less than the oxygen content of the first active layer corresponding to the second region, or the thickness of the first active layer corresponding to the first region is less than the thickness of the first active layer corresponding to the second region.

[0042] In an exemplary embodiment, a second insulating layer and a second metal layer including a first gate electrode are sequentially formed, and the first active layer is subjected to two conductor treatments to form a channel region, a source transition region and a drain transition region located on both sides of the channel region, and a source connection region located on a side of the source transition region away from the channel region and a drain connection region located on a side of the drain transition region away from the channel region, including:

[0043] forming a second insulating layer covering the first active layer, wherein a first via hole, a second via hole, a first active via hole and a second active via hole are formed on the second insulating layer, wherein the first via hole and the second via hole respectively expose the first connecting electrode and the first power line, and the first active via hole and the second active via hole respectively expose partial areas on both sides of the first active layer;

[0044] Performing a first conductorization process on the second electrode plate, the first active via hole, and the first active layer exposed in the second active via hole to form a conductorized second electrode plate and a source connection region and a drain connection region of the first active layer;

[0045] A second metal layer is formed, and the photoresist on the second metal layer is retained; the second metal layer includes a first gate electrode, a first source electrode, and a first drain electrode; the first gate electrode is located in the middle area of ​​the active layer, the first drain electrode is connected to the drain connection area through the second active via hole, and is connected to the first connection electrode through the first via hole; the first end of the first source electrode is connected to the first power line through the second via hole, and the second end of the first source electrode is connected to the source connection area through the first active via hole;

[0046] Using the second metal layer and the photoresist disposed on the second metal layer as a mask, etching the second insulating layer not covered by the second metal layer;

[0047] The second insulating layer, the second metal layer arranged on the second insulating layer and the photoresist arranged on the second metal layer are used as masks, and the second electrode plate and the first active layer not covered by the second insulating layer are subjected to a second conductorization process to form a channel region of the first active layer and a source transition region and a drain transition region located on both sides of the channel region, wherein the boundary of the orthographic projection of the first gate electrode on the substrate is located within the boundary range of the orthographic projection of the second insulating layer on the substrate; the boundary of the orthographic projection of the channel region on the substrate is located within the boundary range of the orthographic projection of the second insulating layer on the substrate, and the source transition region and the drain transition region both include a first region away from the channel region and a second region adjacent to the channel region; the conductivity of the first active layer corresponding to the first region is higher than the conductivity of the first active layer corresponding to the second region, or the oxygen content of the first active layer corresponding to the first region is less than the oxygen content of the first active layer corresponding to the second region, or the thickness of the first active layer corresponding to the first region is less than the thickness of the first active layer corresponding to the second region.

[0048] In an exemplary embodiment, etching the second insulating layer not covered by the second metal layer includes:

[0049] The second insulating layer between the first gate electrode and the first source electrode and the second insulating layer between the first gate electrode and the first drain electrode are removed by self-aligned etching.

[0050] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present disclosure.

[0052] Figure 1 It is a schematic structural diagram of a display unit in an OLED according to an exemplary embodiment of the present disclosure;

[0053] Figure 2 is a schematic diagram of an equivalent circuit of an OLED pixel driving circuit;

[0054] Figure 3 It is a schematic diagram of an exemplary embodiment of the present disclosure after forming a first electrode pattern;

[0055] Figure 4 for Figure 3 Sectional view along the AA direction;

[0056] Figure 5It is a schematic diagram of an exemplary embodiment of the present disclosure after a metal oxide layer pattern is formed;

[0057] Figure 6 for Figure 5 Sectional view along the AA direction;

[0058] Figure 7 It is a schematic diagram of an exemplary embodiment of the present disclosure after forming a second insulating layer pattern;

[0059] Figure 8 for Figure 7 Sectional view along the AA direction;

[0060] Fig. 9 It is a schematic diagram of an exemplary embodiment of the present disclosure after a first conductorization process;

[0061] Fig.10 It is a schematic diagram of an exemplary embodiment of the present disclosure after forming a second metal layer pattern;

[0062] Fig.11 for Fig.10 Sectional view along the AA direction;

[0063] Fig.12 It is a schematic diagram of an exemplary embodiment of the present disclosure after a second etching process;

[0064] Fig.13a , Fig.13b and Fig.13c It is a schematic diagram of an exemplary embodiment of the present disclosure after a second conductorization process;

[0065] Fig.14 It is a schematic diagram of an exemplary embodiment of the present disclosure after a third insulating layer pattern is formed;

[0066] Fig.15 This is a schematic diagram of an exemplary embodiment of the present disclosure after a color filter layer pattern is formed;

[0067] Fig.16 It is a schematic diagram of an exemplary embodiment of the present disclosure after a planar layer pattern is formed;

[0068] Fig.17 It is a schematic diagram of an exemplary embodiment of the present disclosure after an anode pattern is formed;

[0069] Fig.18 It is a schematic diagram of an exemplary embodiment of the present disclosure after forming a pixel definition layer pattern;

[0070] Fig.19 It is a schematic diagram of another exemplary embodiment of the present disclosure after forming a second insulating layer pattern;

[0071] Fig. 20 for Fig.19 Sectional view along the AA direction;

[0072] Fig.21 It is a schematic diagram of another exemplary embodiment of the present disclosure after the first conductorization process;

[0073] Fig. 22 It is a schematic diagram of another exemplary embodiment of the present disclosure after forming a second metal layer pattern;

[0074] Fig.23 for Fig. 22 Sectional view along the AA direction;

[0075] Fig.24 It is a schematic diagram of another exemplary embodiment of the present disclosure after the second etching process;

[0076] Fig.25a , Fig.25b and Fig.25c This is a schematic diagram of another exemplary embodiment of the present disclosure after a second conductorization process.

[0077] Description of reference numerals:

[0078] 10—substrate; 11—first gate electrode; 12—first active layer;

[0079] 13—first source electrode; 14—first drain electrode; 21—second gate electrode;

[0080] 22—second active layer; 23—second source electrode; 24—second drain electrode;

[0081] 31—third gate electrode; 32—third active layer; 33—third source electrode;

[0082] 34—third drain electrode; 41—first insulating layer; 42—second insulating layer;

[0083] 43—third insulating layer; 44—planar layer; 51—first connecting electrode;

[0084] 52—second connecting electrode; 61—first electrode plate; 62—second electrode plate;

[0085] 70—color film layer; 81—anode; 82—pixel definition layer;

[0086] 100—Photoresist. DETAILED DESCRIPTION

[0087] The embodiments herein can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the implementation and content can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined arbitrarily with each other.

[0088] In the drawings, the size of the constituent elements, the thickness of the layer, or the area may be exaggerated for the sake of clarity. Therefore, any implementation of the present disclosure is not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and any implementation of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0089] The ordinal numbers such as "first", "second", and "third" in this article are set to avoid confusion among constituent elements rather than to limit the quantity.

[0090] In this document, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the implementation methods and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements can be appropriately changed according to the direction of the constituent elements being described. Therefore, it is not limited to the words and phrases described in the text and can be appropriately replaced according to the circumstances.

[0091] In this document, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in this disclosure can be understood according to the circumstances.

[0092] In this article, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (or drain electrode terminal, drain connection region, or drain electrode) and a source electrode (or source electrode terminal, source connection region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this article, the channel region refers to the region where the current mainly flows.

[0093] In this article, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" may sometimes be interchanged. Therefore, in this article, the "source electrode" and the "drain electrode" may be interchanged.

[0094] In this article, "electrical connection" includes the situation where the components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. The "element having some electrical function" can be, for example, an electrode or wiring, or a switching element such as a transistor, or other functional elements such as a resistor, inductor or capacitor.

[0095] In this article, "parallel" means that the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes the state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means that the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes the state where the angle is greater than 85° and less than 95°.

[0096] In this document, "film" and "layer" can be interchanged. For example, "conductive layer" can sometimes be replaced by "conductive film". Similarly, "insulating film" can sometimes be replaced by "insulating layer".

[0097] The term "about" as used herein refers to values ​​that are not strictly limited and allow for process and measurement errors.

[0098] With the rapid development of display technology, thin film transistor technology has developed from amorphous silicon (a-Si) thin film transistors to metal oxide (Oxide) thin film transistors. The carrier mobility of the oxide active layer is 20 to 30 times that of the amorphous silicon active layer. It has the characteristics of large mobility, high on-state current, better switching characteristics, and better uniformity. It can greatly improve the characteristics of thin film transistors, increase the response speed of pixels, and achieve faster refresh rates. It can be used in applications that require fast response and large currents.

[0099] There are two types of oxide thin film transistors, namely bottom-gate thin film transistors and top-gate thin film transistors. The structural characteristics of bottom-gate thin film transistors are that the source electrode and the drain electrode cover the two sides of the oxide active layer respectively, and a channel region is formed between the source electrode and the drain electrode. The structural characteristics of top-gate thin film transistors are that the source electrode and the drain electrode are connected to the oxide active layer through vias. Since the top-gate thin film transistor has the characteristics of a short channel, the on-state current (Ion) can be effectively improved, which can significantly improve the display effect and effectively reduce power consumption. Since the overlapping area between the gate electrode and the source and drain electrodes in the top-gate thin film transistor is small, the parasitic capacitance generated is small, the circuit delay is small and the switching speed is high, so the possibility of defects such as gate-drain short circuit (GDS) is low.

[0100] An exemplary embodiment of the present disclosure provides a bottom emission type display substrate including a plurality of regularly arranged display units (sub-pixels). Figure 1 FIG. 1 is a schematic diagram of a display unit in an OLED according to an exemplary embodiment of the present disclosure, wherein the OLED is a bottom emission type. Figure 1 As shown, in a plane parallel to the display substrate, each display unit includes a light-emitting structure area and a driving circuit area, the light-emitting structure area is provided with a light-emitting structure, the light-emitting structure is configured to emit light, the driving circuit area is provided with a pixel driving circuit, the pixel driving circuit is configured to drive the light-emitting structure, and the pixel driving circuit may include multiple thin film transistors and storage capacitors.

[0101] In an exemplary embodiment, the driving circuit area may include a circuit area and a capacitor area, multiple thin film transistors driving the light emitting structure are arranged in the circuit area, the electrode plate of the storage capacitor is arranged in the capacitor area, and the electrode plate of the storage capacitor and the multiple thin film transistors are arranged in parallel.

[0102] In an exemplary embodiment, the storage capacitor is a transparent capacitor structure, and a transparent conductive layer and a conductive metal oxide are used as two electrode plates of the storage capacitor. In this way, the light-emitting structure area and the capacitor area together constitute a light-emitting area, which can ensure the capacity of the storage capacitor and improve the pixel aperture ratio.

[0103] In an exemplary embodiment, the pixel driving circuit may adopt a driving structure such as 3T1C, 4T1C, 5T1C, 6T1C, or 7T1C, which is not limited in the present disclosure.

[0104] Figure 2 FIG. 1 is a schematic diagram of an equivalent circuit of an OLED pixel driving circuit, illustrating a 3T1C driving structure. Figure 2As shown, the pixel driving circuit is electrically connected to the first scan line GN, the second scan line SN, the data line DN, the first power line VDD and the compensation line SE, and the pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitor C ST In the exemplary embodiment, the first transistor T1 is a driving transistor, the second transistor T2 is a switching transistor, and the third transistor T3 is a compensation transistor. In the exemplary embodiment, the gate electrode of the first transistor T1 is connected to the second electrode of the second transistor T2 and the storage capacitor C ST The first electrode of the first transistor T1 is connected to the first power line VDD, and the second electrode of the first transistor T1 is connected to the storage capacitor C ST The second electrode of the OLED and the second electrode of the third transistor T3. The gate electrode of the second transistor T2 is connected to the scan line GN, and the first electrode of the second transistor T2 is connected to the data line DN; the gate electrode of the third transistor T3 is connected to the second scan line SN, and the first electrode of the third transistor T3 is connected to the compensation line SE. The anode of the OLED is connected to the second electrode of the first transistor T1, and the cathode of the OLED is connected to the second power line VSS. The OLED is configured to emit light of corresponding brightness in response to the current of the second electrode of the first transistor T1. In an exemplary embodiment, the third transistor T3 can extract the threshold voltage Vth and mobility of the first transistor T1 in response to the compensation timing to compensate for the threshold voltage Vth, and the storage capacitor C ST It is configured to maintain the voltages of the N1 node and the N2 node within one frame of light emission period.

[0105] In an exemplary embodiment of the present disclosure, a display substrate of a bottom emission type top gate structure includes a first metal layer, a first insulating layer, a metal oxide layer, a second insulating layer and a second metal layer stacked together; the metal oxide layer includes a first active layer, and the second metal layer includes a first gate electrode, a first source electrode and a first drain electrode; the first active layer includes a channel region, a source transition region and a drain transition region located on both sides of the channel region, and a source connection region located on a side of the source transition region away from the channel region and a drain connection region located on a side of the drain transition region away from the channel region; the source connection region is connected to the first source electrode, and the drain connection region is connected to the first drain electrode; the source transition region and the drain transition region both include a first region away from the channel region and a second region adjacent to the channel region; the conductivity of the first active layer corresponding to the first region is higher than the conductivity of the first active layer corresponding to the second region, or the oxygen content of the first active layer corresponding to the first region is less than the oxygen content of the first active layer corresponding to the second region, or the thickness of the first active layer corresponding to the first region is less than the thickness of the first active layer corresponding to the second region.

[0106] In an exemplary embodiment, the conductivity of the first active layer corresponding to the first region is higher than the conductivity of the first active layer corresponding to the source connection region and the drain connection region, or the oxygen content of the first active layer corresponding to the first region is less than the oxygen content of the first active layer corresponding to the source connection region and the drain connection region, or the thickness of the first active layer corresponding to the first region is less than the thickness of the first active layer corresponding to the source connection region and the drain connection region.

[0107] In an exemplary embodiment, the boundary of the orthographic projection of the first gate electrode on the substrate is located within the boundary of the orthographic projection of the second insulating layer on the substrate; the boundary of the orthographic projection of the channel region on the substrate is located within the boundary of the orthographic projection of the second insulating layer on the substrate.

[0108] In an exemplary embodiment, the display substrate further includes a first conductive layer, the first conductive layer includes a first electrode plate disposed on a base, the metal oxide layer includes a second electrode plate that has been subjected to two conductorization treatments, and an orthographic projection of the second electrode plate on the base has an overlapping area with an orthographic projection of the first electrode plate on the base.

[0109] In an exemplary embodiment, the material of the first electrode plate includes a transparent conductive material, and the overlapping area is located in a light emitting area of ​​the display substrate.

[0110] In an exemplary embodiment, the first metal layer includes a first power line and a first connecting electrode, the first connecting electrode is connected to the first electrode plate, and a transparent conductive film is arranged between the first metal layer and the substrate; the orthographic projection of the first connecting electrode on the substrate and the orthographic projection of the channel region of the first active layer on the substrate have an overlapping area.

[0111] In an exemplary embodiment, the first source electrode and the first drain electrode are disposed on the first insulating layer; the first drain electrode is disposed on the drain connection region of the first active layer and is connected to the first connection electrode through a first via hole; the first end of the first source electrode is connected to the first power line through a second via hole, and the second end of the first source electrode is disposed on the source connection region of the first active layer.

[0112] In an exemplary embodiment, the first source electrode and the first drain electrode are disposed on the second insulating layer; the first drain electrode is connected to the drain connection region of the first active layer through a first active via, and is connected to the first connection electrode through a first via; a first end of the first source electrode is connected to the first power line through a second via, and a second end of the first source electrode is connected to the source connection region of the first active layer through a second active via.

[0113] In an exemplary embodiment, a source transition region of the first active layer is located between the first gate electrode and the first source electrode, and a drain transition region of the first active layer is located between the first gate electrode and the first drain electrode.

[0114] In an exemplary embodiment, each sub-pixel includes a light-emitting area and a circuit area, a plurality of transistors in the pixel driving circuit are arranged in the circuit area, and an orthographic projection of a storage capacitor in the pixel driving circuit on the substrate overlaps with the light-emitting area.

[0115] In an exemplary embodiment, the source connection region and the drain connection region of the first active layer are formed by a first conductive process, and the channel region of the first active layer is formed during a self-aligned second conductive process.

[0116] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0117] In an exemplary embodiment, the preparation process of the display substrate may include the following operations: Figures 3 to 18 shown.

[0118] (1) Forming a first electrode plate and a first metal layer pattern. In an exemplary embodiment, forming the first electrode plate and the first metal layer pattern may include: sequentially depositing a first transparent conductive film and a first metal film on a substrate, patterning the first transparent conductive film and the first metal film by a half-tone patterning process, forming a first electrode plate 61 and a first metal layer pattern on the substrate 10, wherein the first metal layer pattern includes at least a first power line VDD, a data line DN, a compensation line SE, a first connection electrode 51 and a second connection electrode 52, wherein the first connection electrode 51 is connected to the first electrode plate 61, as shown in FIG. Figure 3 and Figure 4 As shown, Figure 4 for Figure 3 Cross-section view along the AA direction.

[0119] In an exemplary embodiment, patterning the first transparent conductive film and the first metal film by a halftone patterning process may include: first coating a layer of photoresist on the first metal film, exposing the photoresist by a halftone mask, and forming a photoresist pattern after development, wherein the photoresist pattern includes an unexposed area, a partially exposed area, and a fully exposed area, wherein the unexposed area includes the location of the first power line VDD, the data line DN, the compensation line SE, the first connection electrode 51, and the second connection electrode 52 patterns, and the photoresist in the unexposed area has a first thickness. The partially exposed area includes the location of the first electrode 61, and the photoresist in the partially exposed area has a second thickness, which is less than the first thickness. The other areas are fully exposed areas, and the photoresist in the fully exposed areas is completely removed to expose the surface of the first metal film. Subsequently, a first etching process is used to remove the first transparent conductive film and the first metal film in the fully exposed area. Subsequently, an ashing process is used to remove the photoresist in the partially exposed area, so that the partially exposed area exposes the surface of the first metal film. Subsequently, a second etching process is used to remove the first metal film in the partially exposed area, exposing the first transparent conductive film in the partially exposed area. Finally, the remaining photoresist is stripped off to form the first electrode and the first metal layer pattern on the substrate. After this patterning process, a transparent conductive film is retained under the first metal layer (first power line VDD, data line DN, compensation line SE, first connection electrode 51 and second connection electrode 52).

[0120] In an exemplary embodiment, the first power line VDD, the data line DN and the compensation line SE are parallel to each other and extend in a vertical direction, the first power line VDD is arranged on one side of the sub-pixel, and the data line DN and the compensation line SE are arranged on the other side of the sub-pixel. The first power line VDD is configured to provide a power signal to a first source electrode of the first transistor, the data line DN is configured to provide a data line signal to a second source electrode of the second transistor, and the compensation line SE is configured to provide a compensation signal to a third source electrode of the third transistor.

[0121] In an exemplary embodiment, the first electrode 61 is configured to form a storage capacitor with the second electrode in the metal oxide layer formed subsequently. The first connecting electrode 51 is connected to the first electrode 61. The first connecting electrode 51 is configured to connect the first drain electrode of the first transistor formed subsequently and the third drain electrode of the third transistor on the one hand, so as to realize the connection between the first electrode 61 and the first drain electrode and the third drain electrode, and on the other hand, serves as a shielding layer for the first transistor T1. The second connecting electrode 52 is configured to connect the third gate electrode of the third transistor formed subsequently.

[0122] In an exemplary embodiment, the thickness of the first transparent conductive film is about 40 nm to 150 nm, and the thickness of the first metal film is about 100 nm to 1000 nm.

[0123] In some possible implementations, the first electrode of the first conductive layer can be configured to form a storage capacitor with the subsequently formed second metal layer. Alternatively, the first electrode of the first conductive layer can be configured to form a storage capacitor with the subsequently formed pixel electrode, and the pixel electrode is provided in the same layer as the anode and is formed by the same patterning process.

[0124] In some possible implementations, the first electrode plate can be disposed on the first metal layer, and the first electrode plate of the first metal layer is configured to form a storage capacitor with a subsequently formed second metal layer, or the first electrode plate of the first metal layer is configured to form a storage capacitor with a subsequently formed pixel electrode.

[0125] (2) Forming a metal oxide layer pattern. In an exemplary embodiment, forming the metal oxide layer pattern may include: depositing a first insulating film and a metal oxide film in sequence on the substrate on which the aforementioned pattern is formed, patterning the metal oxide film through a patterning process to form a first insulating layer 41 covering the first electrode 61 and the first metal layer pattern, and forming a first active layer 12, a second active layer 22, a third active layer 32, and a second electrode 62 pattern on the first insulating layer 41, such as Figure 5 and Figure 6 As shown, Figure 6 for Figure 5 Cross-section view along the AA direction.

[0126] In an exemplary embodiment, the first active layer 12 serves as an active layer of the driving TFT (first transistor T1), and the orthographic projection of the first active layer 12 on the substrate overlaps with the orthographic projection of the first connecting electrode 51 on the substrate, the second active layer 22 serves as an active layer of the switching TFT (second transistor T2), the second active layer 22 is connected to the second electrode plate 62, the third active layer 32 serves as an active layer of the compensation TFT (third transistor T3), and the position of the second electrode plate 62 corresponds to the position of the first electrode plate 61, that is, the orthographic projection of the second electrode plate 62 on the substrate overlaps with the orthographic projection of the first electrode plate 61 on the substrate, so that the first electrode plate 61 and the second electrode plate 62 form a storage capacitor of a transparent structure. In some possible exemplary embodiments, the orthographic projection of the second electrode plate 62 on the substrate is located within the orthographic projection range of the first electrode plate 61 on the substrate.

[0127] In an exemplary embodiment, the metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, an oxide containing indium, gallium and zinc, etc. In some possible implementations, the metal oxide layer may be a transparent indium gallium zinc oxide (IGZO) or indium tin zinc oxide (ITZO).

[0128] In an exemplary embodiment, the first insulating film has a thickness of about 200 nm to 1000 nm, and the metal oxide film has a thickness of about 20 nm to 200 nm.

[0129] In some possible implementations, the second electrode in the metal oxide layer can be configured to form a storage capacitor with a subsequently formed second metal layer, or can be configured to form a storage capacitor with a subsequently formed pixel electrode, or can be configured to form a storage capacitor with the first metal layer.

[0130] (3) Forming a second insulating layer pattern. In an exemplary embodiment, forming the second insulating layer pattern may include: depositing a second insulating film on the substrate on which the aforementioned pattern is formed, patterning the second insulating film by a halftone patterning process, forming a second insulating layer 42 pattern and a plurality of via hole patterns opened on the first insulating layer 41, wherein the second insulating layer 42 pattern is located at the positions where the first active layer 12, the second active layer 22, and the third active layer 32 are located, and the plurality of via hole patterns at least include a first via hole K1, a second via hole K2, a third via hole K3, a fourth via hole K4, a fifth via hole K5, and a sixth via hole K6, as shown in FIG. Figure 7 and Figure 8 As shown, Figure 8 for Figure 7 Cross-section view along the AA direction.

[0131] In an exemplary embodiment, patterning the second insulating film by a half-tone patterning process may include: first coating a layer of photoresist on the second insulating film, exposing the photoresist by a half-tone mask, and forming a photoresist pattern after development, wherein the photoresist pattern includes an unexposed area, a partially exposed area, and a fully exposed area, wherein the unexposed area includes the location of the first active layer 12, the second active layer 22, and the third active layer 32, and the photoresist in the unexposed area has a first thickness. The fully exposed area includes the location of the via pattern, and the photoresist in the fully exposed area is completely removed to expose the surface of the second insulating film. The other area is a partially exposed area, and the photoresist in the partially exposed area has a second thickness, which is less than the first thickness. Subsequently, a first etching process is used to remove the second insulating film and the first insulating layer 41 in the fully exposed area to form a plurality of via patterns. Subsequently, an ashing process is used to remove the photoresist in the partially exposed area, so that the partially exposed area exposes the second insulating film. Subsequently, a second etching process is used to remove the second insulating film in the partially exposed area. Finally, the remaining photoresist is stripped off to form a second insulating layer 42 pattern and a plurality of via hole patterns opened on the first insulating layer 41 .

[0132] In an exemplary embodiment, the plurality of via patterns at least include a first via K1, a second via K2, a third via K3, a fourth via K4, a fifth via K5, and a sixth via K6. The first via K1 is located at the position of the first connection electrode 51, exposing the surface of the first connection electrode 51. The first via K1 is configured to connect the first drain electrode of the first transistor and the third drain electrode of the third transistor formed subsequently to the first connection electrode 51, thereby realizing the connection between the first electrode plate 61 and the first drain electrode and the third drain electrode. The second via K2 is located at the position of the first power line VDD, exposing the surface of the first power line VDD, and the second via K2 is configured to connect the first source electrode of the first transistor formed subsequently to the first power line VDD. The third via K3 and the fourth via K4 are respectively located at both ends of the second connection electrode 52, exposing the surface of the second connection electrode 52. The third via K3 and the fourth via K4 are configured to respectively connect the second scan line SN formed subsequently and the third gate electrode of the third transistor, thereby realizing the connection between the second scan line SN and the third gate electrode. The fifth via hole K5 is located at the position where the data line DN is located, exposing the surface of the data line DN, and the fifth via hole K5 is configured to connect the second source electrode of the second transistor formed subsequently, so as to realize the connection between the data line DN and the second source electrode. The sixth via hole K6 is located at the position where the compensation line SE is located, exposing the surface of the compensation line SE, and the sixth via hole K6 is configured to connect the third source electrode of the third transistor formed subsequently, so as to realize the connection between the compensation line SE and the third source electrode.

[0133] In an exemplary embodiment, the second insulating layer 42 located at the position of the second electrode plate 62 is removed to expose the second electrode plate 62 .

[0134] In an exemplary embodiment, the second insulating layer 42 located at the positions of the first active layer 12, the second active layer 22, and the third active layer 32 respectively covers a portion of the first active layer 12, a portion of the second active layer 22, and a portion of the third active layer 32. The second insulating layer 42 located at the position of the first active layer 12 covers the middle region of the first active layer 12, and the covering width is greater than the design width of the channel region of the first active layer 12, and the two side regions not covered by the second insulating layer 42 expose the surface of the first active layer 12. The second insulating layer 42 located at the position of the second active layer 22 covers the middle region of the second active layer 22, and the covering width is greater than the design width of the channel region of the second active layer 22, and the two side regions not covered by the second insulating layer 42 expose the surface of the second active layer 22. The second insulating layer 42 located at the position of the third active layer 32 covers the middle region of the third active layer 32, and the covering width is greater than the design width of the channel region of the third active layer 32, and the two side regions not covered by the second insulating layer 42 expose the surface of the third active layer 32. In this way, when the first conductorization process is performed later, the first active layer 12, the second active layer 22 and the third active layer 32 can all form a wider channel region.

[0135] In an exemplary embodiment, the second insulating film has a thickness of about 100 nm to 500 nm.

[0136] (4) First conductorization process. In an exemplary embodiment, the first conductorization process may include: on the substrate formed with the aforementioned pattern, conducting a conductorization process on the two side regions of the first active layer 12, the second active layer 22, and the third active layer 32 not covered by the second insulating layer 42 and the second electrode 62 to form a conductorized second electrode 62, forming a channel region in the middle region of the first active layer 12, the second active layer 22, and the third active layer 32 covered by the second insulating layer 42, and processing both side regions not covered by the second insulating layer 42 into conductorized regions 12′, and the conductorized regions 12′ serve as the source connection region and the drain connection region of the first active layer 12, the source connection region and the drain connection region of the second active layer 22, and the source connection region and the drain connection region of the third active layer 32, respectively, as shown in FIG. Fig. 9 shown.

[0137] (5) Forming a second metal layer pattern. In an exemplary embodiment, forming the second metal layer pattern may include: depositing a second metal film on a substrate having the aforementioned pattern formed thereon. Coating a layer of photoresist on the second metal film, forming a photoresist pattern by masking, exposing and developing, etching the second metal film by a first etching process to form a second metal layer pattern, and retaining the photoresist 100 on the second metal layer. The second metal layer pattern includes at least a first scan line GN, a second scan line SN, a first gate electrode 11, a second gate electrode 21, a third gate electrode 31, a first source electrode 13, a first drain electrode 14, a second source electrode 23, a second drain electrode 24, a third source electrode 33 and a third drain electrode 34 pattern, as shown in FIG. Fig.10 and Fig.11 As shown, Fig.11 for Fig.10 Cross-section view along the AA direction.

[0138] In an exemplary embodiment, the first scan line GN and the second scan line SN are parallel to each other, extend in the horizontal direction, and are both arranged at the lower side of the sub-pixel. The first scan line GN may be a switch scan line configured to provide an on / off signal for controlling the second transistor to the second gate electrode of the second transistor, the second scan line SN may be a compensation scan line configured to provide an on / off signal for controlling the third transistor to the third gate electrode of the third transistor, and the second scan line SN is connected to the second connection electrode 52 through the fourth via hole K4.

[0139] In an exemplary embodiment, the first gate electrode 11 is an integral structure interconnected with the second drain electrode 24, the second gate electrode 21 is an integral structure interconnected with the first scan line GN, the third gate electrode 31 is connected to the second connection electrode 52 through the third via K3, and since the second connection electrode 52 is connected to the second scan line SN through the fourth via K4, the third gate electrode 31 is connected to the second scan line SN through the second connection electrode 52.

[0140] In the exemplary embodiment, the first end of the first source electrode 13 is connected to the first power line VDD through the second via K2, and the second end is placed on the source connection region of the first active layer 12 after the conductor treatment, forming the first source electrode 13 connected to the first power line VDD. The first end of the first drain electrode 14 is placed on the drain connection region of the first active layer 12 after the conductor treatment, and is connected to the first connection electrode 51 through the first via K1, so as to realize the connection between the first drain electrode 14 and the first electrode plate 61, and the second end of the first drain electrode 14 is placed on the drain connection region of the third active layer 32 after the conductor treatment, forming the first drain electrode 14 and the third drain electrode 34 of an integrated structure.

[0141] In the exemplary embodiment, the first end of the second source electrode 23 is connected to the data line DN through the fifth via K5, and the second end is placed on the source connection region of the second active layer 22 that has been subjected to the conductor treatment, forming the second source electrode 23 connected to the data line DN. The first end of the second drain electrode 24 is placed on the drain connection region of the second active layer 22 that has been subjected to the conductor treatment, and the second end is placed on the channel region of the second active layer 22 that has not been subjected to the conductor treatment, forming the second drain electrode 24 and the first gate electrode 11 of an integrated structure, and realizing the connection between the second drain electrode 24 and the second electrode plate 62.

[0142] In an exemplary embodiment, a first end of the third source electrode 33 is connected to the compensation line SE through a sixth via K6, and a second end is placed on the source connection region of the third active layer 32 after being processed by conductor, forming the third source electrode 33 connected to the compensation line SE. The third drain electrode 34 is placed on the drain connection region of the third active layer 32 after being processed by conductor, and is an integrated structure connected to the first drain electrode 14.

[0143] In an exemplary embodiment, the first gate electrode 11, the first active layer 12, the first source electrode 13 and the first drain electrode 14 constitute a first transistor T1, the second gate electrode 21, the second active layer 22, the second source electrode 23 and the second drain electrode 24 constitute a second transistor T2, the third gate electrode 31, the third active layer 32, the third source electrode 33 and the third drain electrode 34 constitute the second transistor T2, and the first electrode plate 61 and the conductive second electrode plate 62 constitute a storage capacitor of a transparent structure.

[0144] In an exemplary embodiment, the second metal thin film has a thickness of about 100 nm to about 1000 nm.

[0145] In some possible implementations, the second metal layer can form a capacitor plate, can be configured to form a storage capacitor with the first conductive layer, or can be configured to form a storage capacitor with the first metal layer, or can be configured to form a storage capacitor with the metal oxide layer, or can be configured to form a storage capacitor with a subsequently formed pixel electrode.

[0146] (6) Second etching process. In an exemplary embodiment, the second etching process may include: using the second metal layer pattern and the photoresist 100 remaining on the second metal layer as a mask, self-aligningly etching the second insulating layer 42 downward through a second etching process to remove the second insulating layer 42 on the first active layer 12, the second active layer 22, and the third active layer 32 that is not covered by the second metal layer pattern, such as Fig.12As shown. In the exemplary embodiment, since the widths of the first gate electrode 11, the second gate electrode 21 and the third gate electrode 31 are very small, about 6 μm to 10 μm, the width of the second insulating layer 42 that is finally retained is close to the width of the second metal layer, and the width of the second insulating layer 42 on the first active layer 12, the second active layer 22 and the third active layer 32 is close to the design width of the corresponding active layer channel region. In the exemplary embodiment, the boundary of the orthographic projection of the first gate electrode 11 on the substrate is located within the boundary range of the orthographic projection of the second insulating layer 42 on the substrate, and the boundary of the orthographic projection of the active layer channel region on the substrate is located within the boundary range of the orthographic projection of the second insulating layer 42 on the substrate.

[0147] (7) Second conductorization process. In an exemplary embodiment, the second conductorization process may include: using the second insulating layer 42, the second metal layer pattern disposed on the second insulating layer 42, and the photoresist 100 retained on the second metal layer as a mask, performing a second conductorization process on the first active layer 12, the second active layer 22, and the third active layer 32, and performing a second conductorization process on the second electrode plate 62 to form a channel region of the corresponding active layer and the second conductorized second electrode plate 62, and stripping off the remaining photoresist, such as Fig.13a , Fig.13b and Fig.13c As shown, Fig.13b and Fig.13c for Fig.13a The cross-sectional view taken along the AA direction in the middle. Since the second conductorization process uses the second insulating layer 42, the second metal layer pattern and the photoresist 100 as a mask, it is a self-aligned conductorization process, so the final channel width is substantially the same as the width of the first gate electrode 11, the second gate electrode 21 and the third gate electrode 31. The orthographic projection of the channel region of the first active layer 12 on the substrate overlaps with the orthographic projection of the first connecting electrode 51 on the substrate, so that the first connecting electrode 51 blocks the channel region of the first active layer 12. The exemplary embodiment of the present disclosure greatly improves the alignment accuracy between the gate electrode and the underlying channel region through the self-aligned conductorization process, and greatly improves the electrical characteristics of the thin film transistor.

[0148] In an exemplary embodiment, the first active layer is subjected to two conductor processings, so that the first active layer forms three regions: a channel region 12-1 located in the middle, a source transition region 12-2 and a drain transition region 12-3 located on both sides of the channel region 12-1, and a source connection region 12-4 located on the side of the source transition region 12-2 away from the channel region 12-1 and a drain connection region 12-5 located on the side of the drain transition region 12-3 away from the channel region 12-1. The boundary of the orthographic projection of the channel region 12-1 on the substrate substantially overlaps with the boundary of the orthographic projection of the first gate electrode 11 on the substrate, the source connection region 12-4 is connected to the first source electrode 13 and is covered by the first source electrode 13, the drain connection region 12-5 is connected to the first drain electrode 14 and is covered by the first drain electrode 14, the source transition region 12-2 is located between the channel region 12-1 and the source connection region 12-4, that is, the region between the first gate electrode 11 and the first source electrode 13, and the drain transition region 12-3 is located between the channel region 12-1 and the drain connection region 12-5, that is, the region between the first gate electrode 11 and the first drain electrode 14. Similarly, the second active layer and the third active layer will also form three regions. Due to the use of two conductorization processes, the region of the first conductorization process overlaps with the region of the second conductorization process (e.g. Fig.13a , Fig.13b and Fig.13c), so the source transition region 12-2 and the drain transition region 12-3 both include a first region 12A that has been subjected to two conductorization processes and a second region 12B that has been subjected to only the second conductorization process, the first region 12A is far from the channel region 12-1, and the second region 12B is adjacent to the channel region 12-1. In an exemplary embodiment, the first region 12A that has been subjected to two conductorization processes is subjected to two helium (He) plasma processes, the oxygen content in the film layer is further reduced, the oxygen content of the first active layer corresponding to the first region 12A is less than the oxygen content of the first active layer corresponding to the second region 12B, which is beneficial to improving the electrical characteristics of the thin film transistor. In an exemplary embodiment, the first region 12A that has been subjected to two conductorization processes has a lower resistance and a stronger conductivity, the conductivity of the first active layer corresponding to the first region 12A is higher than the conductivity of the first active layer corresponding to the second region 12B, which is beneficial to improving the electrical characteristics of the thin film transistor. In an exemplary embodiment, the oxygen content of the first active layer corresponding to the first region 12A is less than the oxygen content of the first active layer corresponding to the second region 12B, and the conductivity of the first active layer corresponding to the first region 12A is higher than the conductivity of the first active layer corresponding to the second region 12B. Since the source connection region and the drain connection region are only subjected to the first conductorization treatment, the conductivity of the first active layer corresponding to the first region 12A is higher than the conductivity of the first active layer corresponding to the source connection region and the drain connection region, and the oxygen content of the first active layer corresponding to the first region 12A is less than the oxygen content of the first active layer corresponding to the source connection region and the drain connection region. Since the second electrode 62 is subjected to the conductorization treatment twice, the conductivity of the second electrode 62 is improved, which is conducive to improving the driving characteristics of the pixel driving circuit. In an exemplary embodiment, the conductivity of the metal oxide layer corresponding to the second electrode 62 is higher than the conductivity of the first active layer corresponding to the second region 12B, or the oxygen content of the metal oxide layer corresponding to the second electrode 62 is less than the oxygen content of the first active layer corresponding to the second region 12B.

[0149] In example embodiments, the width of the first region 12A may be smaller than the width of the source connection region 12 - 4 , or the width of the first region 12A may be smaller than the width of the drain connection region 12 - 5 .

[0150] In an exemplary embodiment, the width of the first region 12A may be smaller than the width of the second region 12B.

[0151] In example embodiments, the width of the first region 12A may be smaller than the width of the channel region 12 - 1 .

[0152] In an exemplary embodiment, the orthographic projection of at least a portion of the first region 12A in the source transition region 12-2 on the substrate does not overlap with the orthographic projection of the first metal layer on the substrate, or the orthographic projection of at least a portion of the first region 12A in the drain transition region 12-3 on the substrate does not overlap with the orthographic projection of the first metal layer on the substrate.

[0153] During the two conductorization processes of the exemplary embodiment of the present disclosure, the second insulating layer is etched twice. Over-etching during the etching process will etch away part of the thickness of the first active layer 12, so the thickness of the first active layer corresponding to the first region 12A becomes thinner, the thickness of the first active layer corresponding to the first region 12A is less than the thickness of the first active layer corresponding to the second region 12B, the thickness of the first active layer corresponding to the first region 12A is less than the thickness of the first active layer corresponding to the source connection region and the drain connection region, and the thickness of the first active layer corresponding to the first region 12A is less than the thickness of the first active layer corresponding to the channel region, which is beneficial to improving the conductorization effect. In an exemplary embodiment, the thickness of the first active layer 12 corresponding to a part of the first region 12A can be reduced to zero, that is, a hollow structure is formed. In an exemplary embodiment, the thickness of the metal oxide layer corresponding to the second electrode 62 is less than the thickness of the first active layer corresponding to the second region 12B.

[0154] (8) Forming a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include: depositing a third insulating film on the substrate having the aforementioned pattern formed thereon to form a third insulating layer 43 covering the aforementioned structure, such as Fig.14 shown.

[0155] In an exemplary embodiment, the third insulating film has a thickness of about 200 nm to 1000 nm.

[0156] (9) Forming a color filter layer pattern. In an exemplary embodiment, forming a color filter layer pattern may include: on the substrate having the aforementioned pattern formed thereon, sequentially forming a first color unit, a second color unit, and a third color unit by a patterning process to form a color filter layer 70, such as Fig.15 In an exemplary embodiment, the color filter layer 70 is formed in the light emitting area and the capacitor area, the first color unit may be a green unit, the second color unit may be a red unit, and the third color unit may be a blue unit. In some possible implementations, the color filter layer 70 may include other color units, such as white or yellow.

[0157] (10) Forming a planar layer pattern. In an exemplary embodiment, forming the planar layer pattern may include: coating a planar film on the substrate having the aforementioned pattern formed thereon, using the planar film as a photoresist, and after masking, exposure, and development, etching the third insulating layer 43 to form a planar layer 44 covering the aforementioned structure, wherein a seventh via hole K7 is formed on the planar layer 44, and the seventh via hole K7 is located at the position where the first drain electrode 14 is located, and the planar layer 44 and the third insulating layer 43 in the seventh via hole K7 are removed to expose the surface of the first drain electrode 14, such as Fig.16 shown.

[0158] (11) Forming an anode pattern. In an exemplary embodiment, forming the anode pattern may include: depositing a second transparent conductive film on the substrate on which the aforementioned pattern is formed, patterning the second transparent conductive film through a patterning process to form an anode 81 pattern, wherein the anode 81 is connected to the first drain electrode 14 through the seventh via hole K7, as shown in FIG. Fig.17 In an exemplary embodiment, the anode 81 is a transparent anode.

[0159] (12) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer pattern may include: coating a pixel definition film on a substrate formed with the aforementioned pattern, forming a pixel definition layer (Pixel Define Layer) 82 pattern through masking, exposure and development processes, wherein the pixel definition layer 82 defines an opening area exposing the anode 81, such as Fig.18 shown.

[0160] (13) The organic light emitting layer, cathode and encapsulation layer are formed in the same manner as in the related art and will not be described in detail herein. In an exemplary embodiment, the cathode is a reflective cathode.

[0161] In an exemplary embodiment, the organic light-emitting layer may include a first light-emitting sublayer, a first charge generation layer, a second light-emitting sublayer, a second charge generation layer, and a third light-emitting sublayer stacked in sequence. The first light-emitting sublayer is configured to emit a first color light, including a first hole transport layer (HTL), a first light-emitting material layer (EML), and a first electron transport layer (ETL) stacked in sequence. The second light-emitting sublayer is configured to emit a second color light, including a second hole transport layer, a second light-emitting material layer, and a second electron transport layer stacked in sequence. The third light-emitting sublayer is configured to emit a third color light, including a third hole transport layer, a third light-emitting material layer, and a third electron transport layer stacked in sequence. The first charge generation layer is disposed between the first light-emitting sublayer and the second light-emitting sublayer, and is configured to connect the two light-emitting sublayers in series to achieve the transfer of carriers. The second charge generation layer is disposed between the second light-emitting sublayer and the third light-emitting sublayer, and is configured to connect the two light-emitting sublayers in series to achieve the transfer of carriers. Since the organic light-emitting layer includes a first light-emitting material layer emitting a first color light, a second light-emitting material layer emitting a second color light, and a third light-emitting material layer emitting a third color light, the light finally emitted by the organic light-emitting layer is a mixed light. For example, the first light-emitting material layer can be set to be a red light material layer emitting red light, the second light-emitting material layer can be set to be a green light material layer emitting green light, and the third light-emitting material layer can be set to be a blue light material layer emitting blue light, so that the organic light-emitting layer finally emits white light. In an exemplary embodiment, the structure of the organic light-emitting layer can be designed according to actual needs. For example, in each light-emitting sublayer, in order to improve the efficiency of electron and hole injection into the light-emitting material layer, a hole injection layer (HIL) and an electron injection layer (EIL) can be set. For another example, in order to simplify the structure of the organic light-emitting layer, the first electron transport layer, the first charge generation layer and the second hole transport layer can be eliminated, that is, the second light-emitting material layer can be directly set on the first light-emitting material layer.

[0162] In an exemplary embodiment, the first insulating layer, the second insulating layer and the third insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer. The first insulating layer is called a buffer layer, which is configured to improve the water and oxygen resistance of the substrate, the second insulating layer is called a gate insulating (GI) layer, and the third insulating layer is called a passivation (PVX) layer. The first metal film and the second metal film may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multilayer composite structure, such as Ti / Al / Ti, etc. The first transparent conductive film and the second transparent conductive film may be made of indium tin oxide (ITO) or indium zinc oxide (IZO).

[0163] like Figures 3 to 18 As shown, the display substrate formed by the aforementioned preparation process may include:

[0164] Base 10;

[0165] A transparent first electrode plate 61 disposed on the substrate 10;

[0166] A transparent conductive film is disposed on the substrate 10 and a first metal layer is disposed on the transparent conductive film, wherein the first metal layer at least includes a first power line VDD and a first connecting electrode 51, and the first connecting electrode 51 is connected to a first electrode plate 61;

[0167] A first insulating layer 41 covering the first electrode plate 61 and the first metal layer, wherein the first insulating layer 41 is provided with a first via hole K1 and a second via hole K2, wherein the first via hole K1 exposes the first connection electrode 51, and the second via hole K2 exposes the first power line VDD;

[0168] A metal oxide layer is provided on the first insulating layer 41, the metal oxide layer at least includes a first active layer 12 and a second electrode 62 which has been subjected to two conductor treatments, the orthographic projection of the second electrode 62 on the substrate 10 overlaps with the orthographic projection of the first electrode 61 on the substrate 10 to form a transparent storage capacitor; the first active layer 12 includes three regions: a channel region located in the middle, a source transition region and a drain transition region located on both sides of the channel region, and a source connection region located on a side of the source transition region away from the channel region and a drain connection region located on a side of the drain transition region away from the channel region; the orthographic projection of the channel region of the first active layer 12 on the substrate 10 overlaps with the orthographic projection of the first connection electrode 51 on the substrate 10;

[0169] A second insulating layer 42 is arranged on the first active layer 12, and a first gate electrode 11 is arranged on the second insulating layer 42, the boundary of the orthographic projection of the first gate electrode 11 on the substrate is located within the boundary range of the orthographic projection of the second insulating layer 42 on the substrate, and the boundary of the orthographic projection of the channel region of the first active layer 12 on the substrate is located within the boundary range of the orthographic projection of the second insulating layer 42 on the substrate.

[0170] A first source electrode 13 and a first drain electrode 14 are provided on the first insulating layer 41, wherein a first end of the first source electrode 13 is connected to the first power line VDD through a second via hole K2, and a second end of the first source electrode 13 is provided on the source connection region of the first active layer 12; the first drain electrode 14 is provided on the drain connection region of the first active layer 12, and is connected to the first connection electrode 51 through a first via hole K1;

[0171] A third insulating layer 43 covering the aforementioned structure;

[0172] A color filter layer 70 disposed on the third insulating layer 43;

[0173] A planar layer 44 covering the aforementioned structure, wherein a seventh via hole K7 exposing the first drain electrode 14 is disposed on the planar layer 44;

[0174] The anode 81 is disposed on the planar layer 44 , and the anode 81 is connected to the first drain electrode 14 through the seventh via hole K7 .

[0175] In an exemplary embodiment, the display substrate may further include a pixel definition layer, an organic light emitting layer, a cathode, an encapsulation layer, and the like.

[0176] In an exemplary embodiment, the source transition region of the first active layer 12 is located between the first gate electrode 11 and the first source electrode 13, the drain transition region of the first active layer 12 is located between the first gate electrode 11 and the first drain electrode 14, and the second insulating layer 42 of the source transition region and the drain transition region is removed by self-aligned etching.

[0177] In an exemplary embodiment, the source connection region and the drain connection region of the first active layer 12 are formed by a first conductive process, and the channel region of the first active layer 12 is formed during a self-aligned second conductive process.

[0178] A pixel circuit layer of a display substrate with a transparent capacitor structure includes a shielding layer, a transparent conductive layer, a buffer layer, a semiconductor layer, a gate insulating layer, a gate metal layer, an interlayer insulating layer and a source-drain metal layer, which requires 6 patterning processes, with many patterning processes, a complex process flow, high production costs and low production capacity. In the pixel circuit layer of the display substrate provided by the exemplary embodiment of the present disclosure, the first conductive layer and the first metal layer are formed by the same patterning process, and the gate electrode, the source electrode and the drain electrode are arranged in the same layer and formed by the same patterning process. Only 4 patterning processes are required, which minimizes the number of patterning processes. The exemplary method of preparing a display substrate of the present disclosure reduces the number of patterning processes, shortens the process time, reduces the process cost, has good process compatibility, high process feasibility, strong practicality, is very mass-producible, and has good application prospects.

[0179] In a preparation process of a display substrate, a conductorization treatment is performed after forming a second insulating layer and before forming a second metal layer to form a channel region of fixed position and length. However, when the gate electrode pattern is subsequently formed, due to the alignment accuracy limitation of the patterning process, the position of the gate electrode is easy to deviate from the position of the channel region, and the gate electrode is difficult to align directly above the channel region, and the alignment accuracy between the gate electrode and the channel region is low. The deviation in the alignment between the gate electrode and the channel region will reduce the electrical characteristics of the thin film transistor, resulting in an increase in the turn-on voltage and a decrease in the current, which affects the product performance. The exemplary embodiment of the present disclosure proposes a solution of two conductorization treatments. The first conductorization treatment is before forming the second metal layer. A wider channel region is formed by the first conductorization treatment. The second conductorization treatment is after forming the second metal layer. The channel region formed in the self-aligned second conductorization process has a high alignment accuracy with the gate electrode, which greatly improves the alignment accuracy between the gate electrode and the channel region below, and greatly improves the electrical characteristics of the thin film transistor.

[0180] The exemplary embodiment of the present disclosure forms a storage capacitor with a transparent structure by using a first electrode plate and a second electrode plate made of transparent materials, which saves the area occupied by the capacitor and effectively improves the pixel aperture ratio, and is suitable for high PPI display.

[0181] The exemplary embodiment of the present disclosure etches the second insulating layer twice and performs conductor processing twice, so that the resistance of the source connection area and the drain connection area on both sides of the channel area is lower and the conductivity is stronger, which is beneficial to improving the electrical characteristics of the thin film transistor.

[0182] In another exemplary embodiment, the preparation process of the display substrate may include the following operations: Figure 19 to Figure 25c shown.

[0183] (21) Forming a first electrode plate and a first metal layer pattern in the same manner as in the aforementioned process (1).

[0184] (22) Forming a metal oxide layer pattern in the same manner as in the aforementioned process (2).

[0185] (23) Forming a second insulating layer pattern. In an exemplary embodiment, forming the second insulating layer pattern may include: depositing a second insulating film on the substrate on which the aforementioned pattern is formed, patterning the second insulating film through a patterning process to form a second insulating layer 42 covering the first active layer 12, the second active layer 22, and the third active layer 32, wherein a plurality of via patterns are formed on the second insulating layer 42, and the plurality of vias include at least a first via K1, a second via K2, a third via K3, a fourth via K4, a fifth via K5, a sixth via K6, a first active via V1, and a second active via V2, such as Fig.19 and Fig. 20 As shown, Fig. 20 for Fig.10 Cross-section view along the AA direction.

[0186] In an exemplary embodiment, the second insulating layer 42 located at the position of the second electrode plate 62 is removed to expose the second electrode plate 62 .

[0187] In an exemplary embodiment, the first insulating layer 41 and the second insulating layer 42 in the first via K1, the second via K2, the third via K3, the fourth via K4, the fifth via K5 and the sixth via K6 are etched away. The first via K1 is located at the position of the first connection electrode 51, exposing the surface of the first connection electrode 51. The first via K1 is configured to connect the first drain electrode and the third drain electrode formed subsequently to the first connection electrode 51, so as to realize the connection between the first electrode plate 61 and the first drain electrode and the third drain electrode. The second via K2 is located at the position of the first power line VDD, exposing the surface of the first power line VDD, and the second via K2 is configured to connect the first source electrode formed subsequently to the first power line VDD. The third via K3 and the fourth via K4 are respectively located at both ends of the second connection electrode 52, exposing the surface of the second connection electrode 52, and the third via K3 and the fourth via K4 are configured to respectively connect the second scan line SN and the third gate electrode formed subsequently, so as to realize the connection between the second scan line SN and the third gate electrode. The fifth via hole K5 is located at the position where the data line DN is located, exposing the surface of the data line DN, and the fifth via hole K5 is configured to connect the second source electrode formed subsequently, so as to realize the connection between the data line DN and the second source electrode. The sixth via hole K6 is located at the position where the compensation line SE is located, exposing the surface of the compensation line SE, and the sixth via hole K6 is configured to connect the third source electrode formed subsequently, so as to realize the connection between the compensation line SE and the third source electrode.

[0188] In an exemplary embodiment, the second insulating layer 42 in the first active via hole V1 and the second active via hole V2 is etched away, respectively exposing a portion of the surface of the first active layer 12, the second active layer 22, and the third active layer 32 on both sides. The distance between the first active via hole V1 and the second active via hole V2 is greater than the design width of the channel region of the first active layer 12, the second active layer 22, and the third active layer 32. In this way, when the first conductorization process is performed later, the first active layer 12, the second active layer 22, and the third active layer 32 can form a wider channel region.

[0189] (24) First Conductive Processing. In an exemplary embodiment, the first conductive processing may include: on the substrate formed with the aforementioned pattern, conducting a conductive processing on the second electrode plate 62 and the active layer exposed by the first active via hole V1 and the second active via hole V2 to form a conductive second electrode plate 62, forming conductive regions 12′ on both sides of the first active layer 12, the second active layer 22, and the third active layer 32, the conductive regions 12′ serving as the source connection region and the drain connection region of the first active layer 12, the source connection region and the drain connection region of the second active layer 22, and the source connection region and the drain connection region of the third active layer 32, respectively. Fig.21 shown.

[0190] (25) Forming a second metal layer pattern. In an exemplary embodiment, forming the second metal layer pattern may include: depositing a second metal film on a substrate having the aforementioned pattern formed thereon. Coating a layer of photoresist on the second metal film, forming a photoresist pattern by masking, exposing and developing, etching the second metal film by a first etching process to form a second metal layer pattern, and retaining the photoresist 100 on the second metal layer. The second metal layer pattern includes at least a first scan line GN, a second scan line SN, a first gate electrode 11, a second gate electrode 21, a third gate electrode 31, a first source electrode 13, a first drain electrode 14, a second source electrode 23, a second drain electrode 24, a third source electrode 33 and a third drain electrode 34 pattern, as shown in FIG. Fig. 22 and Fig.23 As shown, Fig.23 for Fig. 22 Cross-section view along the AA direction.

[0191] In an exemplary embodiment, the first scan line GN and the second scan line SN are parallel to each other, extend in the horizontal direction, and are both arranged at the lower side of the sub-pixel. The first scan line GN may be a switch scan line configured to provide an on / off signal for controlling the second transistor to the second gate electrode of the second transistor, the second scan line SN may be a compensation scan line configured to provide an on / off signal for controlling the third transistor to the third gate electrode of the third transistor, and the second scan line SN is connected to the second connection electrode 52 through the fourth via hole K4.

[0192] In an exemplary embodiment, the first gate electrode 11 is an integral structure interconnected with the second drain electrode 24, the second gate electrode 21 is an integral structure interconnected with the first scan line GN, the third gate electrode 31 is connected to the second connection electrode 52 through the third via K3, and since the second connection electrode 52 is connected to the second scan line SN through the fourth via K4, the third gate electrode 31 is connected to the second scan line SN through the second connection electrode 52.

[0193] In the exemplary embodiment, the first end of the first source electrode 13 is connected to the first power line VDD through the second via K2, and the second end is connected to the source connection region of the first active layer 12 through the second active via V2, forming the first source electrode 13 connected to the first power line VDD. The first end of the first drain electrode 14 is connected to the drain connection region of the first active layer 12 through the first active via V1, and is connected to the first connection electrode 51 through the first via K1, so as to realize the connection between the first drain electrode 14 and the first electrode plate 61, and the second end is connected to the third active layer 32 through the first active via V1, forming the first drain electrode 14 and the third drain electrode 34 of an integrated structure.

[0194] In the exemplary embodiment, the first end of the second source electrode 23 is connected to the data line DN through the fifth via K5, and the second end is connected to the source connection region of the second active layer 22 through the second active via V2, forming the second source electrode 23 connected to the data line DN. The first end of the second drain electrode 24 is connected to the drain connection region of the second active layer 22 through the first active via V1, and the second end is placed on the channel region of the second active layer 22 that has not been subjected to the conductor treatment, forming the second drain electrode 24 and the first gate electrode 11 of an integrated structure, and realizing the connection between the second drain electrode 24 and the second electrode plate 62.

[0195] In an exemplary embodiment, a first end of the third source electrode 33 is connected to the compensation line SE through a sixth via K6, and a second end is connected to the source connection region of the third active layer 32 through a second active via V2, forming the third source electrode 33 connected to the compensation line SE. The third drain electrode 34 is connected to the drain connection region of the third active layer 32 through a first active via V1, and is an integrated structure connected to the first drain electrode 14.

[0196] In an exemplary embodiment, the first gate electrode 11, the first active layer 12, the first source electrode 13 and the first drain electrode 14 constitute a first transistor T1, the second gate electrode 21, the second active layer 22, the second source electrode 23 and the second drain electrode 24 constitute a second transistor T2, the third gate electrode 31, the third active layer 32, the third source electrode 33 and the third drain electrode 34 constitute the second transistor T2, and the first electrode plate 61 and the conductive second electrode plate 62 constitute a storage capacitor of a transparent structure.

[0197] (26) Second etching process. In an exemplary embodiment, the second etching process may include: using the second metal layer pattern and the photoresist 100 remaining on the second metal layer as a mask, self-aligningly etching the second insulating layer 42 downward through a second etching process to remove the second insulating layer 42 on the first active layer 12, the second active layer 22, and the third active layer 32 that is not covered by the second metal layer pattern, such as Fig.24 shown.

[0198] In an exemplary embodiment, the side surfaces of the first source electrode 13 and the first drain electrode 14 facing the first gate electrode 11 can be partially removed by an appropriate amount of overetching, so that not only the side surfaces of the first source electrode 13 and the first drain electrode 14 facing the first gate electrode 11 are flush, but also the partial conductorized region 12′ in the first active via hole and the partial conductorized region 12′ in the second active via hole are exposed.

[0199] (27) Second conductorization process. In an exemplary embodiment, the second conductorization process may include: using the second insulating layer 42, the second metal layer pattern disposed on the second insulating layer 42, and the photoresist 100 retained on the second metal layer as a mask, performing a second conductorization process on the first active layer 12, the second active layer 22, and the third active layer 32, and performing a second conductorization process on the second electrode plate 62 at the same time, forming channels of the corresponding active layers and the second conductorized second electrode plate 62, and stripping off the remaining photoresist, such as Fig.25a , Fig.25b and Fig.25c As shown, Fig.25b and Fig.25c for Fig.25a The cross-sectional view taken along the AA direction in the middle. Since the second conductorization process uses the second insulating layer 42, the second metal layer pattern and the photoresist 100 as a mask, it is a self-aligned conductorization process, so the width of the channel finally formed is substantially the same as the width of the first gate electrode 11, the second gate electrode 21 and the third gate electrode 31. The orthographic projection of the channel region of the first active layer 12 on the substrate overlaps with the orthographic projection of the first connecting electrode 51 on the substrate, so that the first connecting electrode 51 blocks the channel region of the first active layer 12. The exemplary embodiment of the present disclosure greatly improves the alignment accuracy between the gate electrode and the underlying channel through the self-aligned conductorization process, and greatly improves the electrical characteristics of the thin film transistor.

[0200] In an exemplary embodiment, the first active layer is subjected to two conductor processings, so that the first active layer forms four regions: a channel region 12-1 located in the middle, a source transition region 12-2 and a drain transition region 12-3 located on both sides of the channel region 12-1, a source connection region 12-4 located on the side of the source transition region 12-2 away from the channel region 12-1 and a drain connection region 12-5 located on the side of the drain transition region 12-3 away from the channel region 12-1, and a source outer region 12-6 located on the side of the source connection region 12-4 away from the channel region 12-1 and a drain outer region 12-7 located on the side of the drain connection region 12-5 away from the channel region 12-1. The boundary of the orthographic projection of the channel region 12-1 on the substrate substantially overlaps with the boundary of the orthographic projection of the first gate electrode 11 on the substrate, the source connection region 12-4 is connected to the first source electrode 13, the drain connection region 12-5 is connected to the first drain electrode 14, the source transition region 12-2 is located between the channel region 12-1 and the source connection region 12-4, that is, the region between the first gate electrode 11 and the first source electrode 13, and the drain transition region 12-3 is located between the channel region 12-1 and the drain connection region 12-5, that is, the region between the first gate electrode 11 and the first drain electrode 14. Similarly, the second active layer and the third active layer will also form four regions. Due to the use of two conductorization processes, the region of the first conductorization process overlaps with the region of the second conductorization process (such as Fig.25bAs shown in the black area 12" in the figure, the source transition area 12-2 and the drain transition area 12-3 both include a first area 12A that has been subjected to two conductorization treatments and a second area 12B that has been subjected to only the second conductorization treatment. The first area 12A that has been subjected to two conductorization treatments is subjected to two helium (He) plasma treatments, and the oxygen content in the film layer is further reduced. The oxygen content of the first active layer corresponding to the first area 12A is less than that of the first active layer corresponding to the second area 12B, and the resistance is lower and the conductivity is stronger. The conductivity of the first active layer corresponding to the first area 12A is higher than that of the first active layer corresponding to the second area 12B, which is beneficial to improving the electrical characteristics of the thin film transistor. Since the source connection area and the drain connection area are only subjected to the first conductorization treatment, the oxygen content of the first active layer corresponding to the first area 12A is further reduced. The first region 12A is subjected to the conductorization treatment twice, so that the conductivity of the first active layer corresponding to the first region 12A is higher than the conductivity of the first active layer corresponding to the source connection region and the drain connection region, and the oxygen content of the first active layer corresponding to the first region 12A is less than the oxygen content of the first active layer corresponding to the source connection region and the drain connection region. Since the second electrode plate 62 is subjected to the conductorization treatment twice, the conductivity of the second electrode plate 62 is improved, which is beneficial to improving the driving characteristics of the pixel driving circuit. In an exemplary embodiment, the conductivity of the metal oxide layer corresponding to the second electrode plate 62 is higher than the conductivity of the first active layer corresponding to the second region 12B, or the oxygen content of the metal oxide layer corresponding to the second electrode plate 62 is less than the oxygen content of the first active layer corresponding to the second region 12B.

[0201] In example embodiments, the width of the first region 12A may be smaller than the width of the source connection region 12 - 4 , or the width of the first region 12A may be smaller than the width of the drain connection region 12 - 5 .

[0202] In an exemplary embodiment, the width of the first region 12A may be smaller than the width of the second region 12B.

[0203] In example embodiments, the width of the first region 12A may be smaller than the width of the channel region 12 - 1 .

[0204] In an exemplary embodiment, the orthographic projection of at least a portion of the first region 12A in the source transition region 12-2 on the substrate does not overlap with the orthographic projection of the first metal layer on the substrate, or the orthographic projection of at least a portion of the first region 12A in the drain transition region 12-3 on the substrate does not overlap with the orthographic projection of the first metal layer on the substrate.

[0205] In exemplary embodiments, the width of the first region 12A may be smaller than the width of the source outer region 12 - 6 , or the width of the first region 12A may be smaller than the width of the drain outer region 12 - 7 .

[0206] In example embodiments, the width of the second region 12B may be greater than the width of the source outer region 12 - 6 , or the width of the second region 12B may be greater than the width of the drain outer region 12 - 7 .

[0207] In exemplary embodiments, the width of the source outer region 12 - 6 may be smaller than the width of the source connection region 12 - 4 , or the width of the drain outer region 12 - 7 may be smaller than the width of the drain connection region 12 - 5 .

[0208] During the two conductorization processes of the exemplary embodiment of the present disclosure, the second insulating layer is etched twice. Over-etching during the etching process will etch away part of the thickness of the first active layer 12, so the thickness of the first active layer corresponding to the first region 12A becomes thinner, the thickness of the first active layer corresponding to the first region 12A is less than the thickness of the first active layer corresponding to the second region 12B, the thickness of the first active layer corresponding to the first region 12A is less than the thickness of the first active layer corresponding to the source connection region and the drain connection region, and the thickness of the first active layer corresponding to the first region 12A is less than the thickness of the first active layer corresponding to the channel region, which is beneficial to improving the conductorization effect. In an exemplary embodiment, the thickness of the first active layer 12 corresponding to a part of the first region 12A can be reduced to zero, that is, a hollow structure is formed. In an exemplary embodiment, the thickness of the metal oxide layer corresponding to the second electrode 62 is less than the thickness of the first active layer corresponding to the second region 12B.

[0209] The subsequent patterning of the third insulating layer, color filter layer, planarization layer, anode, pixel definition layer, organic light emitting layer, cathode and encapsulation layer can be the same as the aforementioned processes (8) to (13).

[0210] like Figure 19 to Figure 25c As shown, the display substrate formed by the aforementioned preparation process may include:

[0211] Base 10;

[0212] A transparent first electrode plate 61 disposed on the substrate 10;

[0213] A transparent conductive film is disposed on the substrate 10 and a first metal layer is disposed on the transparent conductive film, wherein the first metal layer at least includes a first power line VDD and a first connecting electrode 51, and the first connecting electrode 51 is connected to a first electrode plate 61;

[0214] A first insulating layer 41 covering the first electrode plate 61 and the first metal layer;

[0215] A metal oxide layer is provided on the first insulating layer 41, the metal oxide layer at least includes a first active layer 12 and a second electrode 62 which has been subjected to two conductor treatments, the orthographic projection of the second electrode 62 on the substrate 10 overlaps with the orthographic projection of the first electrode 61 on the substrate 10 to form a transparent storage capacitor; the first active layer 12 includes three regions: a channel region located in the middle, a source transition region and a drain transition region located on both sides of the channel region, and a source connection region located on a side of the source transition region away from the channel region and a drain connection region located on a side of the drain transition region away from the channel region; the orthographic projection of the channel region of the first active layer 12 on the substrate 10 overlaps with the orthographic projection of the first connection electrode 51 on the substrate 10;

[0216] A second insulating layer 42 is disposed on the first active layer 12, and a first via K1, a second via K2, a first active via V1, and a second active via V2 are disposed on the second insulating layer 42, the first via K1 exposes the first connection electrode 51, the second via K2 exposes the first power line VDD, the first active via V1 exposes the drain connection region of the first active layer 12 that has been subjected to conductor processing, and the second active via V2 exposes the source connection region of the first active layer 12 that has been subjected to conductor processing;

[0217] A first gate electrode 11, a first source electrode 13 and a first drain electrode 14 are arranged on the second insulating layer 42; the boundary of the orthographic projection of the first gate electrode 11 on the substrate is located within the boundary range of the orthographic projection of the second insulating layer 42 on the substrate, and the boundary of the orthographic projection of the channel region of the first active layer 12 on the substrate is located within the boundary range of the orthographic projection of the second insulating layer 42 on the substrate; the first end of the first source electrode 13 is connected to the first power line VDD through the second via K2, and the second end of the first source electrode 13 is connected to the source connection region of the first active layer 12 through the second active via V2; the first drain electrode 14 is connected to the drain connection region of the first active layer 12 through the first active via V1, and is connected to the first connection electrode 51 through the first via K1;

[0218] A third insulating layer 43 covering the aforementioned structure;

[0219] A color filter layer 70 disposed on the third insulating layer 43;

[0220] A planar layer 44 covering the aforementioned structure, wherein a seventh via hole K7 exposing the first drain electrode 14 is disposed on the planar layer 44;

[0221] An anode 81 is disposed on the planar layer 44 , and the anode 81 is connected to the first drain electrode 14 through a seventh via hole K7 .

[0222] In an exemplary embodiment, the display substrate may further include a pixel definition layer, an organic light emitting layer, a cathode, an encapsulation layer, and the like.

[0223] In an exemplary embodiment, the source transition region of the first active layer 12 is located between the first gate electrode 11 and the first source electrode 13, the drain transition region of the first active layer 12 is located between the first gate electrode 11 and the first drain electrode 14, and the second insulating layer 42 of the source transition region and the drain transition region is removed by self-aligned etching.

[0224] In an exemplary embodiment, the source connection region and the drain connection region of the first active layer 12 are formed by a first conductive process, and the channel region of the first active layer 12 is formed during a self-aligned second conductive process.

[0225] The exemplary embodiment of the present disclosure proposes a scheme for forming a pixel circuit layer of a display substrate through four patterning processes. The first conductive layer and the first metal layer are formed through the same patterning process. The gate electrode, the source electrode, and the drain electrode are arranged on the same layer and are formed through the same patterning process. This reduces the number of patterning processes, shortens the process time, and reduces the process cost. It has good process compatibility, high process feasibility, strong practicality, is very mass-producible, and has good application prospects.

[0226] The exemplary embodiment of the present disclosure proposes a solution of two conductorization treatments. The first conductorization treatment is before the second metal layer is formed. A wider channel area is formed through the first conductorization treatment. The second conductorization treatment is after the second metal layer is formed. The channel area formed in the self-aligned second conductorization process has a high alignment accuracy with the gate electrode, which greatly improves the alignment accuracy between the gate electrode and the channel area below, greatly improving the electrical characteristics of the thin film transistor.

[0227] The exemplary embodiment of the present disclosure also provides a method for preparing a display substrate. In an exemplary embodiment, the method for preparing a display substrate may include:

[0228] S1. forming a first metal layer and a metal oxide layer in sequence on a substrate, wherein the metal oxide layer includes a first active layer;

[0229] S2. Form a second insulating layer and a second metal layer in sequence, and form a channel region, a source transition region and a drain transition region located on both sides of the channel region, and a source connection region located on the side of the source transition region away from the channel region and a drain connection region located on the side of the drain transition region away from the channel region through two conductor treatments; the second metal layer includes a first gate electrode, a first source electrode and a first drain electrode, the source connection region is connected to the first source electrode, and the drain connection region is connected to the first drain electrode; the source transition region and the drain transition region both include a first region away from the channel region and a second region adjacent to the channel region; the conductivity of the first active layer corresponding to the first region is higher than the conductivity of the first active layer corresponding to the second region, or the oxygen content of the first active layer corresponding to the first region is less than the oxygen content of the first active layer corresponding to the second region, or the thickness of the first active layer corresponding to the first region is less than the thickness of the first active layer corresponding to the second region.

[0230] In an exemplary embodiment, step S1 may include:

[0231] A transparent first electrode plate and a first metal layer are formed on the substrate, wherein a transparent conductive film is disposed between the first metal layer and the substrate; the first metal layer comprises a first power line and a first connecting electrode, and the first connecting electrode is connected to the first electrode plate;

[0232] forming a first insulating layer covering the first electrode plate and the first metal layer;

[0233] A metal oxide layer is formed on the first insulating layer, the metal oxide layer includes a first active layer and a second electrode plate, an orthographic projection of the second electrode plate on the substrate and an orthographic projection of the first electrode plate on the substrate have an overlapping area, and an orthographic projection of a channel region of the first active layer on the substrate and an orthographic projection of the first connecting electrode on the substrate have an overlapping area.

[0234] In an exemplary embodiment, step S2 may include:

[0235] forming a second insulating layer on the first active layer, and forming a first via hole and a second via hole on the first insulating layer; the second insulating layer covers a middle area of ​​the first active layer; the first via hole and the second via hole respectively expose the first connecting electrode and the first power line;

[0236] Performing a first conductorization process on the second electrode plate and the areas on both sides of the first active layer not covered by the second insulating layer to form a conductorized second electrode plate, and forming a source connection area and a drain connection area on both sides of the first active layer respectively;

[0237] A second metal layer is formed, and the photoresist on the second metal layer is retained; the second metal layer includes a first gate electrode, a first source electrode, and a first drain electrode; the first gate electrode is located in the middle area of ​​the first active layer, the first drain electrode is placed on the drain connection area, and is connected to the first connection electrode through the first via hole; the first end of the first source electrode is connected to the first power line through the second via hole, and the second end of the first source electrode is placed on the source connection area;

[0238] Using the second metal layer and the photoresist disposed on the second metal layer as a mask, etching the second insulating layer not covered by the second metal layer;

[0239] The second insulating layer, the second metal layer arranged on the second insulating layer and the photoresist arranged on the second metal layer are used as masks, and the second electrode plate and the first active layer not covered by the second insulating layer are subjected to a second conductorization process to form a channel region of the first active layer and a source transition region and a drain transition region located on both sides of the channel region, wherein the boundary of the orthographic projection of the first gate electrode on the substrate is located within the boundary range of the orthographic projection of the second insulating layer on the substrate; the boundary of the orthographic projection of the channel region on the substrate is located within the boundary range of the orthographic projection of the second insulating layer on the substrate, and the source transition region and the drain transition region both include a first region away from the channel region and a second region adjacent to the channel region; the conductivity of the first active layer corresponding to the first region is higher than the conductivity of the first active layer corresponding to the second region, or the oxygen content of the first active layer corresponding to the first region is less than the oxygen content of the first active layer corresponding to the second region, or the thickness of the first active layer corresponding to the first region is less than the thickness of the first active layer corresponding to the second region.

[0240] In another exemplary embodiment, step S2 may include:

[0241] forming a second insulating layer covering the first active layer, wherein a first via hole, a second via hole, a first active via hole and a second active via hole are formed on the second insulating layer, wherein the first via hole and the second via hole respectively expose the first connecting electrode and the first power line, and the first active via hole and the second active via hole respectively expose partial areas on both sides of the first active layer;

[0242] Performing a first conductorization process on the second electrode plate, the first active via hole, and the first active layer exposed in the second active via hole to form a conductorized second electrode plate and a source connection region and a drain connection region of the first active layer;

[0243] A second metal layer is formed, and the photoresist on the second metal layer is retained; the second metal layer includes a first gate electrode, a first source electrode, and a first drain electrode; the first gate electrode is located in the middle area of ​​the active layer, the first drain electrode is connected to the drain connection area through the second active via hole, and is connected to the first connection electrode through the first via hole; the first end of the first source electrode is connected to the first power line through the second via hole, and the second end of the first source electrode is connected to the source connection area through the first active via hole;

[0244] Using the second metal layer and the photoresist disposed on the second metal layer as a mask, etching the second insulating layer not covered by the second metal layer;

[0245] The second insulating layer, the second metal layer arranged on the second insulating layer and the photoresist arranged on the second metal layer are used as masks, and the second electrode plate and the first active layer not covered by the second insulating layer are subjected to a second conductorization process to form a channel region of the first active layer and a source transition region and a drain transition region located on both sides of the channel region, wherein the boundary of the orthographic projection of the first gate electrode on the substrate is located within the boundary range of the orthographic projection of the second insulating layer on the substrate; the boundary of the orthographic projection of the channel region on the substrate is located within the boundary range of the orthographic projection of the second insulating layer on the substrate, and the source transition region and the drain transition region both include a first region away from the channel region and a second region adjacent to the channel region; the conductivity of the first active layer corresponding to the first region is higher than the conductivity of the first active layer corresponding to the second region, or the oxygen content of the first active layer corresponding to the first region is less than the oxygen content of the first active layer corresponding to the second region, or the thickness of the first active layer corresponding to the first region is less than the thickness of the first active layer corresponding to the second region.

[0246] In an exemplary embodiment, etching the second insulating layer not covered by the second metal layer includes:

[0247] The second insulating layer between the first gate electrode and the first source electrode and the second insulating layer between the first gate electrode and the first drain electrode are removed by self-aligned etching.

[0248] The exemplary embodiments of the present disclosure provide a display substrate and a method for preparing the same, and a display device. The gate electrode, source electrode, and drain electrode are arranged in the same layer and formed by the same patterning process. Only four patterning processes are required, which minimizes the number of patterning processes. Through two conductorization processes, the alignment accuracy between the gate electrode and the channel region below is greatly improved, and the electrical characteristics of the thin film transistor are greatly improved. The method for preparing the display substrate of the exemplary embodiments of the present disclosure reduces the number of patterning processes, shortens the process time, reduces the process cost, has good process compatibility, high process feasibility, strong practicality, is very mass-producible, and has good application prospects.

[0249] The preparation process of the display substrate has been described in detail in the previous embodiments and will not be repeated here.

[0250] The present disclosure also provides a display device, including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0251] Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any technician in the field to which the present disclosure belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the scope of patent protection of this application shall still be subject to the scope defined in the attached claims.

Claims

1. A display substrate, comprising a first metal layer, a metal oxide layer, a second insulating layer and a second metal layer stacked on a base; the metal oxide layer comprises a first active layer, and the second metal layer comprises a first gate electrode, a first source electrode and a first drain electrode; the first active layer comprises a channel region, a source transition region and a drain transition region located on both sides of the channel region, and a source connection region located on a side of the source transition region away from the channel region and a drain connection region located on a side of the drain transition region away from the channel region; the source connection region is connected to the first source electrode, and the drain connection region is connected to the first drain electrode; the source transition region and the drain transition region both comprise a first region away from the channel region and a second region adjacent to the channel region; the thickness of the first active layer corresponding to the first region is less than the thickness of the first active layer corresponding to the second region.

2. The display substrate according to claim 1, wherein: The conductivity of the first active layer corresponding to the first region is higher than the conductivity of the first active layer corresponding to the source connection region and the drain connection region, or the oxygen content of the first active layer corresponding to the first region is less than the oxygen content of the first active layer corresponding to the source connection region and the drain connection region, or the thickness of the first active layer corresponding to the first region is less than the thickness of the first active layer corresponding to the source connection region and the drain connection region.

3. The display substrate according to claim 1, wherein: The width of the first region is smaller than the width of the source connection region, or the width of the first region is smaller than the width of the drain connection region.

4. The display substrate according to claim 1, wherein: The width of the first region is smaller than the width of the second region.

5. The display substrate according to claim 1, wherein: The width of the first region is smaller than the width of the channel region.

6. The display substrate according to claim 1, wherein: The orthographic projection of at least part of the first region in the source transition region on the substrate does not overlap with the orthographic projection of the first metal layer on the substrate, or the orthographic projection of at least part of the first region in the drain transition region on the substrate does not overlap with the orthographic projection of the first metal layer on the substrate.

7. The display substrate according to claim 1, wherein: The first active layer also includes a source outer region located on a side of the source connection region away from the channel region and a drain outer region located on a side of the drain connection region away from the channel region; the width of the first region is smaller than the width of the source outer region, or the width of the first region is smaller than the width of the drain outer region.

8. The display substrate according to claim 1, wherein: The first active layer also includes a source outer region located on the side of the source connection region away from the channel region and a drain outer region located on the side of the drain connection region away from the channel region; the width of the second region is greater than the width of the source outer region, or the width of the second region is greater than the width of the drain outer region.

9. The display substrate according to claim 1, wherein: The first active layer also includes a source outer region located on a side of the source connection region away from the channel region and a drain outer region located on a side of the drain connection region away from the channel region; the width of the source outer region is smaller than the width of the source connection region, or the width of the drain outer region is smaller than the width of the drain connection region.

10. The display substrate according to claim 1, wherein: The boundary of the orthographic projection of the first gate electrode on the substrate is located within the boundary range of the orthographic projection of the second insulating layer on the substrate; the boundary of the orthographic projection of the channel region on the substrate is located within the boundary range of the orthographic projection of the second insulating layer on the substrate.

11. The display substrate according to claim 1, wherein: The display substrate includes a plurality of regularly arranged sub-pixels, each sub-pixel includes a pixel driving circuit and an organic electroluminescent diode electrically connected to the pixel driving circuit, the pixel driving circuit includes a storage capacitor, the storage capacitor includes a first electrode plate and a second electrode plate, and an orthographic projection of the first electrode plate on the substrate and an orthographic projection of the second electrode plate on the substrate have an overlapping area.

12. The display substrate according to claim 11, wherein: The pixel driving circuit further includes a first transistor, a second transistor and a third transistor; a gate electrode of the first transistor is coupled to a second electrode of the second transistor, a first electrode of the first transistor is coupled to a first power line, a second electrode of the first transistor is coupled to a first electrode of the organic light emitting diode, and a second electrode of the organic light emitting diode is coupled to a second power line; The gate electrode of the second transistor is coupled to the first scan line, and the first electrode of the second transistor is coupled to the data line; the gate electrode of the third transistor is coupled to the second scan line, the first electrode of the third transistor is coupled to the compensation line, and the second electrode of the third transistor is coupled to the second electrode of the first transistor; A first electrode of the storage capacitor is coupled to the gate electrode of the first transistor, and a second electrode of the storage capacitor is coupled to the second electrode of the first transistor.

13. The display substrate according to claim 11, wherein: The display substrate further includes a first conductive layer, the first conductive layer includes a first electrode plate of the storage capacitor, and the metal oxide layer includes a second electrode plate of the storage capacitor.

14. The display substrate according to claim 13, wherein: The material of the first electrode plate includes a transparent conductive material, and the overlapping area is located in the light emitting area of ​​the display substrate.

15. The display substrate according to claim 11, wherein: The first metal layer includes a first plate of the storage capacitor, and the metal oxide layer includes a second plate of the storage capacitor.

16. The display substrate according to claim 11, wherein: The second metal layer includes a first plate of the storage capacitor, and the metal oxide layer includes a second plate of the storage capacitor.

17. The display substrate according to claim 11, wherein: The first metal layer includes a first plate of the storage capacitor, and the second metal layer includes a second plate of the storage capacitor.

18. The display substrate according to any one of claims 13 to 16, wherein: The conductivity of the metal oxide layer corresponding to the second electrode plate is higher than the conductivity of the first active layer corresponding to the second region, or the oxygen content of the metal oxide layer corresponding to the second electrode plate is less than the oxygen content of the first active layer corresponding to the second region, or the thickness of the metal oxide layer corresponding to the second electrode plate is less than the thickness of the first active layer corresponding to the second region.

19. The display substrate according to any one of claims 1 to 17, wherein: The first metal layer includes a first power line and a first connecting electrode, the first connecting electrode is connected to the first electrode plate, and a transparent conductive film is provided between the first metal layer and the substrate; An orthographic projection of the first connecting electrode on the substrate and an orthographic projection of the channel region of the first active layer on the substrate have an overlapping region.

20. The display substrate according to claim 19, wherein: The first source electrode and the first drain electrode are arranged on the first insulating layer; the first drain electrode is arranged on the drain connection area of ​​the first active layer and is connected to the first connection electrode through a first via hole; the first end of the first source electrode is connected to the first power line through a second via hole, and the second end of the first source electrode is arranged on the source connection area of ​​the first active layer.

21. The display substrate according to claim 19, wherein: The first source electrode and the first drain electrode are arranged on the second insulating layer; the first drain electrode is connected to the drain connection area of ​​the first active layer through a first active via, and is connected to the first connection electrode through a first via; the first end of the first source electrode is connected to the first power line through a second via, and the second end of the first source electrode is connected to the source connection area of ​​the first active layer through a second active via.

22. A display device comprising the display substrate according to any one of claims 1 to 21.

23. A method for preparing a display substrate, comprising: forming a first metal layer and a metal oxide layer in sequence on a substrate, wherein the metal oxide layer includes a first active layer; A second insulating layer and a second metal layer are formed in sequence, and through two conductor treatments, the first active layer is formed into a channel region, a source transition region and a drain transition region located on both sides of the channel region, and a source connection region located on the side of the source transition region away from the channel region and a drain connection region located on the side of the drain transition region away from the channel region; the second metal layer includes a first gate electrode, a first source electrode and a first drain electrode, the source connection region is connected to the first source electrode, and the drain connection region is connected to the first drain electrode; the source transition region and the drain transition region both include a first region away from the channel region and a second region adjacent to the channel region; the thickness of the first active layer corresponding to the first region is less than the thickness of the first active layer corresponding to the second region.

24. The method for preparing a display substrate according to claim 23, wherein: A first metal layer and a metal oxide layer are sequentially formed on a substrate, comprising: A transparent first electrode plate and a first metal layer are formed on the substrate, wherein a transparent conductive film is disposed between the first metal layer and the substrate; the first metal layer comprises a first power line and a first connecting electrode, and the first connecting electrode is connected to the first electrode plate; forming a first insulating layer covering the first electrode plate and the first metal layer; A metal oxide layer is formed on the first insulating layer, the metal oxide layer includes a first active layer and a second electrode plate, an orthographic projection of the second electrode plate on the substrate and an orthographic projection of the first electrode plate on the substrate have an overlapping area, and an orthographic projection of a channel region of the first active layer on the substrate and an orthographic projection of the first connecting electrode on the substrate have an overlapping area.

25. The method for preparing a display substrate according to claim 24, wherein: A second insulating layer and a second metal layer are sequentially formed, and the first active layer is formed into a channel region, a source transition region and a drain transition region located on both sides of the channel region, a source connection region located on a side of the source transition region away from the channel region, and a drain connection region located on a side of the drain transition region away from the channel region through two conductor treatments, including: forming a second insulating layer on the first active layer, and forming a first via hole and a second via hole on the first insulating layer; the second insulating layer covers a middle area of ​​the first active layer; the first via hole and the second via hole respectively expose the first connecting electrode and the first power line; Performing a first conductorization process on the second electrode plate and the areas on both sides of the first active layer not covered by the second insulating layer to form a conductorized second electrode plate, and forming a source connection area and a drain connection area on both sides of the first active layer respectively; A second metal layer is formed, and the photoresist on the second metal layer is retained; the second metal layer includes a first gate electrode, a first source electrode, and a first drain electrode; the first gate electrode is located in the middle area of ​​the first active layer, the first drain electrode is placed on the drain connection area, and is connected to the first connection electrode through the first via hole; the first end of the first source electrode is connected to the first power line through the second via hole, and the second end of the first source electrode is placed on the source connection area; Using the second metal layer and the photoresist disposed on the second metal layer as a mask, etching the second insulating layer not covered by the second metal layer; The second insulating layer, the second metal layer arranged on the second insulating layer and the photoresist arranged on the second metal layer are used as masks, and the second electrode plate and the first active layer not covered by the second insulating layer are subjected to a second conductorization process to form a channel region of the first active layer and a source transition region and a drain transition region located on both sides of the channel region, wherein the boundary of the orthographic projection of the first gate electrode on the substrate is located within the boundary range of the orthographic projection of the second insulating layer on the substrate; the boundary of the orthographic projection of the channel region on the substrate is located within the boundary range of the orthographic projection of the second insulating layer on the substrate, and the source transition region and the drain transition region both include a first region away from the channel region and a second region adjacent to the channel region; the conductivity of the first active layer corresponding to the first region is higher than the conductivity of the first active layer corresponding to the second region, or the oxygen content of the first active layer corresponding to the first region is less than the oxygen content of the first active layer corresponding to the second region, or the thickness of the first active layer corresponding to the first region is less than the thickness of the first active layer corresponding to the second region.

26. The method for preparing a display substrate according to claim 24, wherein: A second insulating layer and a second metal layer including a first gate electrode are sequentially formed, and the first active layer is formed into a channel region, a source transition region and a drain transition region located on both sides of the channel region, and a source connection region located on a side of the source transition region away from the channel region and a drain connection region located on a side of the drain transition region away from the channel region through two conductor treatments, including: forming a second insulating layer covering the first active layer, wherein a first via hole, a second via hole, a first active via hole and a second active via hole are formed on the second insulating layer, wherein the first via hole and the second via hole respectively expose the first connecting electrode and the first power line, and the first active via hole and the second active via hole respectively expose partial areas on both sides of the first active layer; Performing a first conductorization process on the second electrode plate, the first active via hole, and the first active layer exposed in the second active via hole to form a conductorized second electrode plate and a source connection region and a drain connection region of the first active layer; A second metal layer is formed, and the photoresist on the second metal layer is retained; the second metal layer includes a first gate electrode, a first source electrode, and a first drain electrode; the first gate electrode is located in the middle area of ​​the active layer, the first drain electrode is connected to the drain connection area through the second active via hole, and is connected to the first connection electrode through the first via hole; the first end of the first source electrode is connected to the first power line through the second via hole, and the second end of the first source electrode is connected to the source connection area through the first active via hole; Using the second metal layer and the photoresist disposed on the second metal layer as a mask, etching the second insulating layer not covered by the second metal layer; The second insulating layer, the second metal layer arranged on the second insulating layer and the photoresist arranged on the second metal layer are used as masks, and the second electrode plate and the first active layer not covered by the second insulating layer are subjected to a second conductorization process to form a channel region of the first active layer and a source transition region and a drain transition region located on both sides of the channel region, wherein the boundary of the orthographic projection of the first gate electrode on the substrate is located within the boundary range of the orthographic projection of the second insulating layer on the substrate; the boundary of the orthographic projection of the channel region on the substrate is located within the boundary range of the orthographic projection of the second insulating layer on the substrate, and the source transition region and the drain transition region both include a first region away from the channel region and a second region adjacent to the channel region; the conductivity of the first active layer corresponding to the first region is higher than the conductivity of the first active layer corresponding to the second region, or the oxygen content of the first active layer corresponding to the first region is less than the oxygen content of the first active layer corresponding to the second region, or the thickness of the first active layer corresponding to the first region is less than the thickness of the first active layer corresponding to the second region.

27. The method for preparing a display substrate according to claim 25 or 26, wherein: Etching the second insulating layer not covered by the second metal layer, comprising: The second insulating layer between the first gate electrode and the first source electrode and the second insulating layer between the first gate electrode and the first drain electrode are removed by self-aligned etching.

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