A cache data structure management method, system, storage medium and device
By allocating and managing cache regions in a RAID system, and optimizing cache line status and operations, cache pollution and performance degradation issues are resolved, thereby improving system performance and disk utilization.
Patent Information
- Application Number
- CN202111432158.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-11-29
- Publication Date
- 2025-12-12
- Estimated Expiration
- 2041-11-29
AI Technical Summary
Existing RAID systems suffer from high cache pollution, which prevents them from maximizing disk performance utilization. In the event of a failure, excessive overhead leads to a decrease in system performance.
The system allocates cache regions in the storage space, establishes multiple cache lines, manages the cache line status through write, read, and disk operations, performs conflict handling and flush operations, and optimizes cache management.
In RAID operations, improve sequential read/write performance, reduce cache pollution, maximize disk performance, reduce overhead during failures, and maintain system performance.
Smart Images
Figure CN114265789B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of computers, in particular to the field of data storage, and more particularly to a cache data structure management method and system, storage medium and device. BACKGROUND
[0002] In the research of the improvement of the performance of the storage system in the field of computers, the input / output bottleneck problem is an important aspect to be solved. In this regard, the disk array technology (RAID) is one of the effective methods to solve this problem. Among the many methods for improving the performance of the disk array, the Cache technology is one of the important methods.
[0003] Cache was first used to solve the problem that the read / write speed of the main memory (SDRAM, DDR, etc.) is slow, which seriously affects the execution efficiency of the CPU. That is, a read / write speed faster Cache is added between the main memory and the CPU to cache part of the content of the main memory, so as to improve the execution efficiency of the CPU.
[0004] In the field of storage, especially in devices using SAS / SCSI interface protocols, access speed has become a bottleneck of storage. In order to achieve the balance between performance and cost, data is usually first cached on DDR, and then written to disk when certain conditions are met. This operation of caching on DDR is called Cache process. In this way, the latency of host access to the disk is greatly reduced.
[0005] At the same time, due to the existence of Cache, when performing RAID (disk array) calculation, if the data is cached in Cache, the interaction with the disk will be greatly reduced, effectively reducing the delay of the system and improving the performance of the system.
[0006] However, in the existing RAID (disk array) system, the existing Cache technology is prone to cause high Cache pollution, insufficient comprehensive judgment of write / read operation types, and insufficient precision in some data storage situations. At the same time, in the RAID system, it is necessary to point out the complex implementation of the disk fault tolerance function, and the RAID controller usually cannot utilize the maximum performance of the disk. In addition, in order to ensure that the RAID system reads data without loss when a disk fails (exits the mode), a large amount of overhead is required, so that the system will cause performance degradation in normal mode and exit mode.
[0007] Therefore, in view of the above shortcomings and problems in the prior art, it is necessary to propose an optimized Cache mode of the RAID system to reduce Cache pollution, maximize disk performance as much as possible, and reduce the overhead when a fault occurs to maintain system performance. SUMMARY
[0008] Therefore, the present application aims to provide an improved cache data structure management method, system, storage medium and device for RAID system, so as to solve the problems of high cache pollution, inability to utilize the maximum performance of the disk, excessive overhead during failure and system performance decline in the prior art.
[0009] To achieve the above object, in one aspect, the present application provides a cache data structure management method, which comprises the following steps:
[0010] allocating a cache area in the storage space based on the number of external hanging disks allowed by the device and establishing a plurality of cache lines;
[0011] in response to a write operation command, parsing the LBA in the write operation command, and based on the LBA and the state of the corresponding cache line, performing a write operation on the corresponding cache line or mounting the cache line as a conflict or falling the data in the cache area to the disk and performing a write operation on the corresponding cache line;
[0012] in response to a read operation command, parsing the LBA in the read operation command, and based on the LBA and the data of the corresponding cache line, reading from the corresponding cache line or falling the data of the corresponding cache line to the hard disk and reading from the hard disk or reading from the hard disk;
[0013] in response to a falling operation command, falling the data in all or part of the cache lines in the cache area to the hard disk.
[0014] In some embodiments of the cache data structure management method according to the present application, the method further comprises:
[0015] in response to the existence of a cache line mounted as a conflict, adding the cache line to the suspension list of the conflict manager for conflict processing.
[0016] In some embodiments of the cache data structure management method according to the present application, the method further comprises:
[0017] in response to a flush operation command, falling the data in all or part of the cache lines in the cache area to the hard disk, and resetting the state of the fallen cache line.
[0018] In some embodiments of the cache data structure management method according to the present application, the response to the write operation command, parsing the LBA in the write operation command, and based on the LBA and the state of the corresponding cache line, performing a write operation on the corresponding cache line or mounting the cache line as a conflict or writing the data in the cache region to the hard disk and performing a write operation on the corresponding cache line further comprises:
[0019] Indexing to the corresponding set based on the LBA;
[0020] Comparing whether there is a repetition of the LBA in each lane of the set in turn;
[0021] In response to the existence of a repetition, judging the state of the corresponding cache line, and in response to the state of the corresponding cache line being IDLE, performing a write operation on the corresponding cache line, and in response to the state of the corresponding cache line being other than IDLE, mounting the cache line as a conflict;
[0022] In response to the absence of a repetition and the existence of an idle cache line in the set, performing a write operation on the idle cache line;
[0023] In response to the absence of a repetition and the occupation of all lanes in the set, writing the data in the cache region to the hard disk and performing a write operation on the corresponding cache line.
[0024] In some embodiments of the cache data structure management method according to the present application, the response to the read operation command, parsing the LBA in the read operation command, and based on the LBA and the data of the corresponding cache line, reading from the corresponding cache line or writing the data of the corresponding cache line to the hard disk and reading from the hard disk or reading from the hard disk further comprises:
[0025] Based on the LBA, searching for the hit of the data to be read in the cache region;
[0026] In response to a full hit, reading the data to be read from the corresponding cache line;
[0027] In response to a partial hit, writing the data of the corresponding cache line to the hard disk and reading the data to be read from the hard disk;
[0028] In response to a miss, reading the data to be read from the hard disk.
[0029] In some embodiments of the cache data structure management method according to the present application, the response to the flush operation command, writing the data in all or part of the cache lines in the cache region to the hard disk, and resetting the state of the written cache line further comprises:
[0030] in response to the flush operation instruction, flushing data in all cache lines in the cache region to the hard disk and resetting states of all cache lines to IDLE;
[0031] in response to the selective flush operation instruction, parsing an address segment in the selective flush operation instruction, flushing data in cache lines of the address segment to the hard disk and resetting states of cache lines of the address segment to IDLE.
[0032] Another aspect of the present application also provides a system for managing cache data structure, comprising:
[0033] an initialization partition module configured to allocate a cache region in the storage space and establish a plurality of cache lines based on a number of external disks allowed by the device;
[0034] a write operation module configured to, in response to a write operation command, parse an LBA in the write operation command, and based on the LBA and a state of a corresponding cache line, perform a write operation on the corresponding cache line or mount the cache line as a conflict or flush data in the cache region and perform a write operation on the corresponding cache line;
[0035] a read operation module configured to, in response to a read operation command, parse an LBA in the read operation command, and based on the LBA and data in a corresponding cache line, read from the corresponding cache line or flush data in the corresponding cache line to the hard disk and read from the hard disk or read from the hard disk;
[0036] a flush operation module configured to, in response to a flush operation command, flush data in all or part of cache lines in the cache region to the hard disk and reset states of the flushed cache lines.
[0037] In some embodiments of the cache data structure management method according to the present application, the system further comprises:
[0038] a conflict processing module configured to, in response to the existence of a cache line mounted as a conflict, add the cache line to a suspension list of the conflict manager for conflict processing; and / or
[0039] a flush operation module configured to, in response to a flush operation command, flush data in all or part of cache lines in the cache region to the hard disk and reset states of the flushed cache lines.
[0040] Still another aspect of the present application provides a computer readable storage medium storing computer program instructions which, when executed, implement any of the above cache data structure management methods according to the present application.
[0041] Still another aspect of the present application provides a computer device comprising a memory and a processor, the memory storing a computer program which, when executed by the processor, implements any of the above cache data structure management methods according to the present application.
[0042] The present application has at least the following beneficial technical effects: based on the method of the present application, there is a significant performance improvement effect in the scenario of sequential read and write when performing RAID operation; the strip management of cache is realized; the post-hardening is facilitated, and the software and hardware function access management is realized. BRIEF DESCRIPTION OF DRAWINGS
[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other embodiments can be obtained from these drawings without creative labor.
[0044] In the drawings:
[0045] Figure 1 A schematic diagram of an embodiment of the cache data structure according to the present application is shown;
[0046] Figure 2 A schematic block diagram of an embodiment of the cache data structure management method according to the present application is shown;
[0047] Figure 3 A schematic diagram of an embodiment of the logical device number index cache device of the cache data structure management method according to the present application is shown;
[0048] Figure 4 A schematic diagram of an embodiment of the logical block address index set of the cache data structure management method according to the present application is shown;
[0049] Figure 5 A flowchart of an embodiment of the write operation processing of the cache data structure management method according to the present application is shown;
[0050] Figure 6 A schematic diagram of an embodiment of the flush-out processing of the cache data structure management method according to the present application is shown;
[0051] Figure 7Fig. 1 shows a schematic diagram of an embodiment of a read operation process of the cache data structure management method according to the present application;
[0052] Figure 8 Fig. 1 shows a schematic diagram of an embodiment of a read operation process of the cache data structure management method according to the present application;
[0053] Figure 9 Fig. 1 shows a schematic diagram of an embodiment of a read operation process of the cache data structure management method according to the present application;
[0054] Figure 10 Fig. 1 shows a schematic diagram of an embodiment of a read operation process of the cache data structure management method according to the present application;
[0055] Figure 11 Fig. 1 shows a schematic diagram of an embodiment of a read operation process of the cache data structure management method according to the present application;
[0056] Figure 12 Fig. 1 shows a schematic diagram of an embodiment of a read operation process of the cache data structure management method according to the present application;
[0057] Figure 13 Fig. 1 shows a schematic diagram of an embodiment of a read operation process of the cache data structure management method according to the present application; DETAILED DESCRIPTION
[0058] To make the objects, technical solutions and advantages of the present application clearer, the embodiments of the present application are further described in detail below with reference to the drawings.
[0059] It should be noted that all the expressions of "first" and "second" in the embodiments of the present application are used to distinguish two same-named non-identical entities or non-identical parameters, and it can be seen that "first" and "second" are only used for the convenience of description, and should not be understood as a limitation on the embodiments of the present application. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, the process, method, system, product or device inherently includes other steps or units.
[0060] Based on the above situation, the application creatively proposes a Cache data structure based on RAID and a management method thereof, mainly solving how to quickly write, read and fall disk when data is managed based on strips, slowing down the software processing flow, and providing the possibility for Cache hardening. The application mainly includes the following two parts: (1) Cache configuration: allocating an area in DDR for use as Cache, the size of the area depends on the number of disks that can be externally connected to the device; and (2) Cache management: mainly including the addition of Cache line, flush of Cache line, collision processing of Cache line, and collection of Cache lines in the same array when falling disk, etc. The Cache data structure according to the application is as shown in Figure 1
[0061] To this end, the first aspect of the application provides a Cache data structure management method 100. Figure 2 A schematic block diagram of an embodiment of the Cache data structure management method according to the application is shown. In the embodiment as shown in Figure 1 The method includes:
[0062] Step S110: allocating a Cache area in the storage space based on the number of externally connected disks allowed by the device and establishing a plurality of Cache lines;
[0063] Step S120: in response to a write operation command, parsing the LBA in the write operation command, and based on the LBA and the state of the corresponding Cache line, performing a write operation on the corresponding Cache line or mounting the Cache line as a conflict or falling the data in the Cache area to disk and performing a write operation on the corresponding Cache line;
[0064] Step S130: in response to a read operation command, parsing the LBA in the read operation command, and based on the LBA and the data of the corresponding Cache line, reading from the corresponding Cache line or falling the data of the corresponding Cache line to the hard disk and reading from the hard disk or reading from the hard disk;
[0065] Step S140: in response to a falling disk operation command, falling the data in all or part of the Cache lines in the Cache area to the hard disk.
[0066] In general, first, in step S110, a cache area is allocated in the storage space based on the number of external hanging disks allowed by the device, and a plurality of cache lines are established. Under the condition that the hardware resource is selected, a block area needs to be divided in the DDR, which is used as cache. This block area cannot be used by other applications or operating systems, and can only be occupied by the cache alone, otherwise, data errors will be caused, and even lost.
[0067] First, several configuration parameters need to be determined, which are derived from the following formula: CACHE_DEV_SIZE = CL_SIZE * CACHE_SET * CACHE_WAY; TOTAL_CACHE_SIZE = CACHE_DEV_SIZE * CACHE_DEV_NUM;
[0068] Among them:
[0069] CL_SIZE, as shown in Figure 1 indicates the minimum effective unit of cache, which occupies a size of 16 bytes; CACHE_SET indicates how many lines, which is generally consistent with the stripe size. If the stripe size of a single device is 1MB, then CACHE_SET can be set to 256, and if the stripe size of a single device is 2MB, then CACHE_SET can be set to 512;
[0070] CACHE_WAY indicates how many stripe backups, if set to 8, it means that a single device can cache up to 8 stripes, and if set to 6, it means that a single device can cache up to 6 stripes.
[0071] Through the first formula, the CACHE_DEV_SIZE occupied by a cache device can be calculated. If the system has a maximum of 32 external disks, then CACHE_DEV_NUM is 32, and the space occupied by the cache TOTAL_CACHE_SIZE is 32 times the space occupied by a single device. If CACHE_DEV_NUM is 64, then the space occupied by the cache TOTAL_CACHE_SIZE is 64 times the space occupied by a single device. That is, the more devices mounted by the system, the more space occupied by the cache.
[0072] On the basis of the cache being opened, write and / or read operations and a series of other management actions such as disk flushing, conflict processing, and flushing out can be performed.
[0073] When the Cache device receives a write operation command, in step S120, the write operation command is first parsed, and then a write operation is performed on the corresponding cache line or the cache line is mounted as a conflict or the data in the cache region is destaged and a write operation is performed on the corresponding cache line according to the information of the LBA (low 8 bits) carried therein and the state of the corresponding cache line.
[0074] When the Cache device receives a read operation command, in step S130, the read operation command is first parsed, and then data is read from the corresponding cache line or the data of the corresponding cache line is destaged to the hard disk and read from the hard disk or read from the hard disk according to the information of the LBA (low 8 bits) carried therein and the data of the corresponding cache line.
[0075] When a destage operation command occurs in the Cache device, step S140 destages the data in all or part of the cache lines in the cache region to the hard disk. The following situations will trigger the Cache destage operation.(1) When a threshold is set, the Cache device will destage when the threshold is reached.(2) When no threshold is set, the Cache device will trigger destage when there is no available CL in a set. Figure 10 A flowchart showing an embodiment of the destage operation processing of the cache data structure management method according to the present application is shown. When destaging, the specific destage strategy is as follows: there is a use_cnt count bit in the CL, which is used to determine hot and cold data, and the initial state is 0; when a new CL is generated, it is set to 128; each time a CL in the set is operated, the use_cnt of the CL that is not hit is decremented by 1, and the hit CL that is in the IDLE state is assigned a value of 128; when destage is to be performed, the CL with the smallest use_cnt is used as the start CL, and then the LBA+1 operation is performed to traverse the entire cache device.
[0076] In some embodiments of the cache data structure management method 100 according to the present application, the method further comprises:
[0077] Step S150: in response to the existence of a cache line mounted as a conflict, the cache line is added to the pending list of the conflict manager for conflict processing.
[0078] The cache line collision is mainly caused by that in the read and write operation initiated by the host, the LBA to be read and written has cache in the cache, but the state of the cache line is not IDLE, but in any of the following states, i.e. destage in process or read in process. In order to ensure the consistency of access, the operation this time is listed as collision. The operation this time needs to be mounted on the suspend list of the collision manager (collisionMgr), and wait for the collision to be solved, and then processed from the suspend list of the collision manager (collisionMgr). Figure 9 A flowchart of an embodiment of the collision processing of the cache data structure management method according to the present application is shown.
[0079] In some embodiments of the cache data structure management method 100 according to the present application, the method further comprises:
[0080] Step S160: in response to the flush operation command, discarding the data in all or part of the cache lines in the cache area to the hard disk, and resetting the state of the discarded cache line.
[0081] The main function of the cache flush operation is to flush the data managed in the cache line out of the cache and perform discarding. After discarding, the state of the corresponding cache line needs to be reset.
[0082] Further, in some embodiments of the cache data structure management method 100 according to the present application, step S160 in response to the flush operation command, discarding the data in all or part of the cache lines in the cache area to the hard disk, and resetting the state of the discarded cache line further comprises:
[0083] Step S161: in response to the flush operation instruction, discarding the data in all cache lines in the cache area to the hard disk, and resetting the state of all cache lines to IDLE;
[0084] Step S162: in response to the selective flush operation instruction, parsing the address segment in the selective flush operation instruction, discarding the data in the cache line of the address segment to the hard disk, and resetting the state of the cache line of the address segment to IDLE.
[0085] The cache flush operation can have two ways of flush.
[0086] The first is flush of the whole Cache, which means all the Cache lines managed by the Cache device are all flushed. After flushing, the state of all CLs is IDLR state. Figure 6 A schematic diagram showing an embodiment of the flush-out processing of the cache data structure management method according to the present application is shown. Specifically, all the data of the CL cache is sorted; the DIP of all CLs is set; after waiting for the completion of the flushing of all the Cache device, the DIP is cleared, and when the Dirty is cleared, the IDLE is set.
[0087] The second is selective flushing, which means flushing the data of a specified address segment. Since the CL stores LBA address information, when flushing, the LBA and the number of LBAs need to be specified. Figure 7 A schematic diagram showing an embodiment of the selective flush-out processing of the cache data structure management method according to the present application is shown. Specifically, the corresponding set is indexed by the LBA low 8 bits; then the hit operation is performed; if there is no hit, the LBA+1 continues to perform the foregoing steps; the DIP is set; the LBA+1 continues to search until it is equal to the flush size; the flushing operation is performed, and the completion is waited for; the Dirty is cleared; and the IDLE is set.
[0088] In some embodiments of the cache data structure management method 100 according to the present application, step S120, in response to the write operation command, parses the LBA in the write operation command, and based on the LBA and the state of the corresponding cache line, performs the write operation on the corresponding cache line or mounts the cache line as a conflict or flushes the data in the cache region and performs the write operation on the corresponding cache line further comprises:
[0089] Step S121: indexing the corresponding set based on the LBA;
[0090] Step S122: comparing whether there is repetition of the LBA in each way of the set in turn;
[0091] Step S123: in response to the existence of repetition, judging the state of the corresponding cache line, and in response to the state of the corresponding cache line being IDLE, performing the write operation on the corresponding cache line, and in response to the state of the corresponding cache line being other than IDLE, mounting the cache line as a conflict;
[0092] Step S124: in response to the non-existence of repetition and the existence of a free cache line in the set, performing the write operation on the free cache line;
[0093] Step S125: in response to the absence of repetition and all ways in the set being occupied, flushing the data in the cache region and performing a write operation on the corresponding cache line.
[0094] In particular, with reference to Figures 3 to 5 The embodiment is further illustrated. Figure 3 A schematic diagram of an embodiment of a logical device number index cache device according to the cache data structure management method of the present application is shown. Figure 4 A schematic diagram of an embodiment of a logical block address index set according to the cache data structure management method of the present application is shown. Figure 5 A flowchart of an embodiment of write operation processing according to the cache data structure management method of the present application is shown. As shown, the cache device is found using the logical device number (LDN), and the low 8 bits of the logical block address (LBA) can be used to index to a specific set. When the cache device receives a write operation command, it first locates the specific set according to the LBA information (low 8 bits) carried in the command. Then it successively compares whether the LBA in each way exists repeatedly. If there is a repeated LBA, the state of the cache line (CL) is determined at this time. If the CL is in the IDLE state, it means that the CL can be replaced, and the write operation is executed. If the CL is in other states, such as destage in process or read in process, it means that there is a conflict. At this time, the operation needs to be suspended and hung to the collision manager (collisionMgr) for processing. Only when the cache has a flush operation returned, the suspend list of the collisionMgr module is searched, and the purpose is to solve the collision.
[0095] If the same LBA is not found in the way in the set, and there is a free CL that can be used, the CL is directly occupied, the write operation is executed on it, and the state of the CL is set to dirty.
[0096] If all the ways in the set are occupied, a flush (destage) operation is generated, and after the flush is completed, the data is inserted into the CL.
[0097] In some embodiments of the cache data structure management method 100 according to the present application, step S130, in response to a read operation command, parses the LBA in the read operation command, and reads data from the corresponding cache line based on the LBA and the data of the corresponding cache line, or writes the data of the corresponding cache line to the hard disk and reads from the hard disk, or reads from the hard disk further comprises:
[0098] Step S131: Based on the LBA, search for the hit of the data to be read in the cache area;
[0099] Step S132: In response to a full hit, read the data to be read from the corresponding cache line;
[0100] Step S133: In response to a partial hit, write the data of the corresponding cache line to the hard disk and read the data to be read from the hard disk;
[0101] Step S134: In response to a miss, read the data to be read from the hard disk.
[0102] Figure 8 A schematic diagram of an embodiment of a read operation processing of a cache data structure management method according to the present application is shown. Specifically, when the host initiates a read operation, first determine whether the data cached in the Cache. This determination process can be divided into two, which are full hit and not full hit.
[0103] Where full hit (full hit) means that the data the host needs to read is in the Cache, which can be directly read from the Cache without reading from the hard disk.
[0104] Non-full hit (not full hit) is divided into two. One is part hit (part hit), that is, part of the data is in the Cache, but part of the data is not in the Cache. At this time, the data in the Cache needs to be written to the hard disk, and then the host directly reads the data from the hard disk. The other is none hit (none hit), which means that the Cache does not cache the data the host needs to read. At this time, the host needs to read from the hard disk.
[0105] According to the foregoing embodiments of the present application, the present application redefines the form of creation and verification of the modular BOM from another dimension, establishes a module-level resource pool and an OD relationship statement library for system calling, directly generates a system modular BOM and verifies it by using a digital process, saves a large amount of time, improves efficiency, and does not need to apply for a corresponding module-level material number for each BOM, nor create a comprehensive BOM table in the form of an Excel table offline, and then convert the comprehensive BOM table into a Loadsheet to edit it in a language recognizable by the system. Moreover, the subsequent changes can also become more simple and convenient. In addition, all data are captured by the system, and many errors can also be avoided. The use of a digital process to capture the module level in the module-level resource pool for visual verification saves time and ensures accuracy.
[0106] The second aspect of the present application also provides a system 200 for managing a cache data structure. Figure 11 A schematic block diagram of an embodiment of the system 200 for managing a cache data structure according to the present application is shown. As shown, the system comprises: Figure 11
[0107] An initialization partitioning module 210 configured to allocate a cache area in a storage space and establish a plurality of cache lines based on the number of external hard drives allowed by the device;
[0108] A write operation module 220 configured to, in response to a write operation command, parse an LBA in the write operation command, and based on the LBA and the state of the corresponding cache line, perform a write operation on the corresponding cache line or mount the cache line as a conflict or fall the data in the cache area to the hard disk and perform a write operation on the corresponding cache line;
[0109] A read operation module 230 configured to, in response to a read operation command, parse an LBA in the read operation command, and based on the LBA and the data of the corresponding cache line, read from the corresponding cache line or fall the data of the corresponding cache line to the hard disk and read from the hard disk or read from the hard disk;
[0110] A fall operation module 240 configured to, in response to a fall operation command, fall the data in all or part of the cache lines in the cache area to the hard disk.
[0111] In addition, in some embodiments of the system 200 for managing a cache data structure according to the present application, the system 200 further comprises:
[0112] a conflict handling module configured to, in response to there being a cache line mounted as a conflict, add the cache line to a suspension list of the conflict manager to be processed for conflict handling; and / or
[0113] a flush operation module configured to, in response to a flush operation command, flush data in all or part of the cache lines in the cache region to the hard disk, and reset the state of the flushed cache lines.
[0114] A third aspect of the embodiment of the present application further provides a computer readable storage medium, Figure 12 A schematic diagram of a computer readable storage medium for implementing the cache data structure management method according to the embodiment of the present application is shown. As shown in Figure 12 The computer readable storage medium 300 stores computer program instructions 310, which can be executed by a processor. The computer program instructions 310, when executed, implement the method of any of the above embodiments.
[0115] It should be understood that, in the case of not conflicting with each other, all the embodiments, features and advantages described above for the cache data structure management method according to the present application are equally applicable to the system and storage medium for cache data structure management according to the present application.
[0116] A fourth aspect of the embodiment of the present application further provides a computer device 400, which comprises a memory 420 and a processor 410, and the memory stores a computer program, which, when executed by the processor, implements the method of any of the above embodiments.
[0117] As shown in Figure 13 A hardware structure schematic diagram of an embodiment of the computer device for implementing the cache data structure management method according to the present application is shown. As shown in Figure 13 For example, the computer device 400 shown in Figure 13 includes a processor 410 and a memory 420, and can further include an input device 430 and an output device 440. The processor 410, the memory 420, the input device 430 and the output device 440 can be connected through a bus or other means, For example, the input device 430 can receive input digital or character information, and generate signal input related to cache data structure management. The output device 440 can include a display device such as a display screen.
[0118] The memory 420, as a non-volatile computer readable storage medium, can be used to store non-volatile software programs, non-volatile computer executable programs and modules, such as program instructions / modules corresponding to the resource monitoring method in the embodiments of the present application. The memory 420 can include a program storage area and a data storage area, wherein the program storage area can store an operating system, at least one application required by a function; and the data storage area can store data created by use of the resource monitoring method, and the like. In addition, the memory 420 can include a high-speed random access memory, and can also include a non-volatile memory, for example, at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state memory device. In some embodiments, the memory 420 can optionally include a memory disposed remotely with respect to the processor 410, and these remote memories can be connected to the local module through a network. Examples of the above network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.
[0119] The processor 410 performs various functional applications and data processing of the server by running the non-volatile software programs, instructions and modules stored in the memory 420, that is, implements the resource monitoring method of the above method embodiments.
[0120] Finally, it should be noted that the computer readable storage medium (for example, the memory) herein can be a volatile memory or a non-volatile memory, or can include both a volatile memory and a non-volatile memory. As an example but not limitation, the non-volatile memory can include a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM) or a flash memory. The volatile memory can include a random access memory (RAM) which can serve as an external cache memory. As an example but not limitation, the RAM can be obtained in various forms, such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct Rambus RAM (DRRAM). The storage device of the disclosed aspect is intended to include but not limited to these and other suitable types of memory.
[0121] Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein can be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present embodiments disclosure.
[0122] The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein can be implemented or performed with a general-purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor, but in the alternative, the processor can be any conventional processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
[0123] The above are exemplary embodiments of the present disclosure, but it should be noted that various changes and modifications can be made without departing from the scope of the present embodiments disclosure defined by the claims. The functions, steps and / or actions of the method claims described herein need not be performed in any particular order. Furthermore, although elements of the present embodiments disclosure can be described or claimed in individual forms, other embodiments can include a plurality of those elements in order to carry out the objectives of the present embodiments disclosure. The above sequences of the present embodiments disclosure are only for description, and do not represent the advantages or disadvantages of the embodiments.
[0124] It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", or "includes" and / or "including" when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The above sequence of the present embodiments disclosure is only for description, and does not represent the advantages or disadvantages of the embodiments.
[0125] Those skilled in the art should understand that the above discussion of any embodiment is only exemplary, and is not intended to mean that the scope of the embodiments disclosed by the present application (including claims) is limited to these examples; under the idea of the embodiments of the present application, the above embodiments or technical features in different embodiments can also be combined, and there are many other changes of different aspects of the embodiments of the present application as above. In order to be brief, they are not provided in details. Therefore, any omission, modification, equivalent replacement, improvement, etc. made in the spirit and principle of the embodiments of the present application shall be included in the protection scope of the embodiments of the present application.
Claims
1. A cache data structure management method characterized by comprising: The method comprises the following steps: allocating a cache area in the storage space and establishing a plurality of cache lines based on the number of external hanging disks allowed by the device; indexing the LBA to the corresponding set; comparing whether there is repetition in each lane of the set in turn; in response to the existence of repetition, judging the state of the corresponding cache line, and in response to the state of the corresponding cache line being IDLE, performing a write operation on the corresponding cache line, in response to the write operation command, parsing the LBA in the write operation command, and based on the LBA and the state of the corresponding cache line, performing a write operation on the corresponding cache line or hanging the cache line as a conflict or falling the data in the cache area to the hard disk and performing a write operation on the corresponding cache line; based on the LBA, retrieving the hit of the data to be read in the cache area; in response to a full hit, reading the data to be read from the corresponding cache line, in response to a read operation command, parsing the LBA in the read operation command, and based on the LBA and the data of the corresponding cache line, reading from the corresponding cache line or falling the data of the corresponding cache line to the hard disk and reading from the hard disk or reading from the hard disk; in response to a fall operation command, falling the data in all or part of the cache lines in the cache area to the hard disk and resetting the state of the fallen cache line. in response to the existence of cache lines hung as conflicts, adding the cache lines to the suspension list of the conflict manager for conflict processing; in response to the fall operation command, falling the data in all or part of the cache lines in the cache area to the hard disk, and resetting the state of the fallen cache line.
2. The method of claim 1, wherein, The response to the write operation command, parsing the LBA in the write operation command, and based on the LBA and the state of the corresponding cache line, performing a write operation on the corresponding cache line or hanging the cache line as a conflict or falling the data in the cache area and performing a write operation on the corresponding cache line further comprises: in response to the state of the corresponding cache line being other than IDLE, hanging the cache line as a conflict; in response to the absence of repetition and the existence of idle cache lines in the set, performing a write operation on the idle cache line; in response to the absence of repetition and the occupation of all lanes in the set, falling the data in the cache area and performing a write operation on the corresponding cache line.
3. The method of claim 1, wherein, The response to the read operation command, parsing the LBA in the read operation command, and based on the LBA and the data of the corresponding cache line, reading from the corresponding cache line or falling the data of the corresponding cache line to the hard disk and reading from the hard disk or reading from the hard disk further comprises: in response to a partial hit, falling the data of the corresponding cache line to the hard disk and reading the data to be read from the hard disk; in response to a miss, reading the data to be read from the hard disk.
4. The method of claim 1, wherein, The flushing operation module is configured to, in response to a flushing operation command, flush data in all or part of cache lines in the cache region to the hard disk, and reset the state of the flushed cache line. In response to a full flushing operation instruction, flush data in all cache lines in the cache region to the hard disk, and reset the state of all cache lines to IDLE. In response to a selective flushing operation instruction, parse the address segment in the selective flushing operation instruction, flush data in the cache line of the address segment to the hard disk, and reset the state of the cache line of the address segment to IDLE.
5. A system for managing a cache data structure, the system comprising: It comprises: An initialization partition module configured to allocate a cache region in the storage space and establish a plurality of cache lines based on the number of external hanging disks allowed by the device; A write operation module configured to index the LBA to the corresponding set based on the LBA, compare whether there is a repetition in each path of the set in turn, in response to the existence of a repetition, judge the state of the corresponding cache line, and in response to the state of the corresponding cache line being IDLE, execute a write operation on the corresponding cache line, in response to a write operation command, parse the LBA in the write operation command, and execute a write operation on the corresponding cache line based on the LBA and the state of the corresponding cache line or hang the cache line as a conflict or flush the data in the cache region and execute a write operation on the corresponding cache line; A read operation module configured to retrieve the hit of the data to be read in the cache region based on the LBA; In response to a full hit, read the data to be read from the corresponding cache line, in response to a read operation command, parse the LBA in the read operation command, and read from the corresponding cache line based on the LBA and the data of the corresponding cache line or flush the data of the corresponding cache line to the hard disk and read from the hard disk or read from the hard disk; A flushing operation module configured to, in response to a flushing operation command, flush data in all or part of cache lines in the cache region to the hard disk, and reset the state of the flushed cache line. The memory stores computer program instructions which, when executed, implement the cache data structure management method of any one of claims 1-4. The memory stores computer program instructions which, when executed, implement the cache data structure management method of any one of claims 1-4. The memory stores computer program instructions which, when executed, implement the cache data structure management method of any one of claims 1-4.
6. A computer-readable storage medium, characterized in that, 7.A computer device, comprising a memory and a processor, and characterized in that,
Citation Information
Patent Citations
Memory controlling device and memory system including same
CN110362507A