Multi-chip system with integrated antenna and method of manufacturing the same

Abstract

The application provides a multi-chip system with an integrated antenna and a manufacturing method thereof, including: a plurality of stacks configured to accommodate one or more of a plurality of chips, an ultra-fine RDL adapter plate, and a plurality of metal support columns, wherein the plurality of stacks are stacked in a thickness direction to form a vertical interconnection structure; and an intermediate RDL layer configured as an interface of the plurality of stacks.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, and in particular to a multi-chip system with integrated antennas and a manufacturing method thereof. BACKGROUND

[0002] Lower cost, more reliable, faster and higher density circuits are the goals of integrated circuit packaging. In the future, integrated circuit packaging will increase the integration density of various electronic components by continuously reducing the minimum feature size.

[0003] At present, advanced packaging methods include wafer level chip scale packaging (WLCSP), fan-out wafer level package (FOWLP), flip chip, package on package (POP), etc.

[0004] Fan-out wafer level package is an embedded chip packaging method of wafer level processing, and is one of the advanced packaging methods with more input / output ports (I / O) and better integration flexibility. Compared with conventional wafer level packaging, fan-out wafer level packaging has its unique advantages: 1. Flexible I / O pitch, not dependent on chip size; 2. Only effective dies are used, product yield is improved; 3. Flexible 3D packaging path, i.e. any array pattern can be formed on the top; 4. Good electrical and thermal performance; 5. Suitable for high frequency applications; 6. Easy to achieve high density wiring in the RDL.

[0005] At present, the fan-out wafer level packaging method of a radio frequency chip generally includes: providing a carrier, forming an adhesive layer on the surface of the carrier; photoetching and electroplating a redistribution layer (RDL) on the adhesive layer; mounting a radio frequency chip on the redistribution layer by chip bonding process; encapsulating the chip in a plastic encapsulation material layer by injection molding process; removing the carrier and the adhesive layer; photoetching and electroplating a under bump metal layer (UBM) on the redistribution layer; performing ball planting and reflow on the UBM to form solder ball bumps; then wafer die bonding and dicing.

[0006] 2.5D system integration technology with integrated antennas meets the needs of integrated multi-chip and high-density packaging. Since fan-out packaging technology is used, there is no need for an organic substrate, so the packaging cost is relatively low, the packaging volume is small, and the wiring density is high.

[0007] But the existing antenna package usually adopts a fan-out package mode, integrates an antenna and a single chip, has low integration, and can only be interconnected with other chips on a system-level PCB, and cannot form a system-level package mode. SUMMARY

[0008] The present application aims to provide a multi-chip system integrated with an antenna and a manufacturing method thereof, to solve the problem that the existing antenna package cannot form a system-level package mode.

[0009] To solve the above technical problems, the present application provides a multi-chip system integrated with an antenna, comprising:

[0010] a plurality of layers configured to accommodate one or more of the following: a plurality of chips, a super-fine RDL adapter plate, and a plurality of metal support columns, wherein a vertical interconnection structure is formed by stacking in the thickness direction between the plurality of layers; and

[0011] an intermediate RDL layer configured to act as an interface of the plurality of layers.

[0012] Optionally, in the multi-chip system integrated with an antenna, comprising:

[0013] a first layer configured to accommodate a plurality of chips, a first super-fine RDL adapter plate, and a plurality of first metal support columns;

[0014] a second layer configured to accommodate a plurality of chips, a second super-fine RDL adapter plate, and a plurality of second metal support columns;

[0015] an intermediate RDL layer configured as an interface of the first layer and the second layer, and attached to a first surface of the first layer and a first surface of the second layer; and

[0016] an outer RDL layer configured to accommodate an antenna, and connected to the first layer and / or the second layer.

[0017] Optionally, in the multi-chip system integrated with an antenna, the outer RDL layer comprises:

[0018] an antenna layer configured to accommodate an antenna, and connected to a second surface of the first layer and / or a second surface of the second layer; and

[0019] a pure RDL layer configured to be connected to the second surface of the first layer and / or the second surface of the second layer;

[0020] wherein the arrangement of the pure RDL layer and the antenna layer is opposite, so that the pure RDL layer and the antenna layer are respectively located on a first surface and a second surface of the multi-chip system integrated with an antenna.

[0021] Optionally, in the multi-chip system integrated with an antenna, further comprising:

[0022] an outer chip layer configured to accommodate a plurality of chips, such that the plurality of chips are connected to the antenna layer and / or the outer side of the pure RDL layer;

[0023] a solder ball layer configured to accommodate solder balls, which are connected to the antenna layer and / or the outer side of the pure RDL layer.

[0024] Optionally, in the integrated antenna multi-chip system, the electrical signals of the first stack and the second stack are connected at least by:

[0025] any two components between the chips of the first stack, the chips of the second stack, the first ultra-fine RDL adapter plate, the first metal support column, the second ultra-fine RDL adapter plate, the second metal support column, the antenna, the chips of the outer chip layer, and the solder balls can form an electrical connection through the intermediate RDL layer and / or the outer RDL layer;

[0026] the first ultra-fine RDL adapter plate can have an electrical connection with any one component in the first stack;

[0027] the second ultra-fine RDL adapter plate can have an electrical connection with any one component in the second stack.

[0028] Optionally, in the integrated antenna multi-chip system, the first ultra-fine RDL adapter plate and the second ultra-fine RDL adapter plate have TSV holes with a diameter of 200 nm to 10.0 μm.

[0029] Optionally, in the integrated antenna multi-chip system, the arrangement of the first ultra-fine RDL adapter plate and the second ultra-fine RDL adapter plate satisfies one or more of the following conditions:

[0030] the first ultra-fine RDL adapter plate and the second ultra-fine RDL adapter plate are vertically interconnected;

[0031] the first ultra-fine RDL adapter plate and the second ultra-fine RDL adapter plate are respectively located at the center positions of the first stack and the second stack;

[0032] a plurality of chips surround the first ultra-fine RDL adapter plate and the second ultra-fine RDL adapter plate.

[0033] Optionally, in the integrated antenna multi-chip system, the arrangement of the first metal support column and the second metal support column satisfies one or more of the following conditions:

[0034] the first metal support column and the second metal support column are vertically interconnected;

[0035] the first metal support column and the second metal support column are arranged around the chips of the first stack and the chips of the second stack;

[0036] The first metal support column and the second metal support column are arranged around the first ultra-fine RDL adapter plate and the second ultra-fine RDL adapter plate.

[0037] The application further provides a manufacturing method of the multi-chip system with the integrated antenna.

[0038] The bonding glue is applied on the carrier wafer, and the antenna layer is prepared on the bonding glue, the antenna layer having the RDL and the antenna array;

[0039] The first metal support column is manufactured on the antenna layer;

[0040] The chip of the first stack is attached on the antenna layer;

[0041] The first ultra-fine RDL adapter plate is attached on the antenna layer;

[0042] The first wafer encapsulation is performed to form the first stack;

[0043] The first surface of the first stack is thinned to expose the first metal support column and the first ultra-fine RDL adapter plate;

[0044] The intermediate RDL layer is prepared on the first surface of the first stack;

[0045] The second metal support column is manufactured on the intermediate RDL layer;

[0046] The chip of the second stack is attached on the intermediate RDL layer;

[0047] The second ultra-fine RDL adapter plate is attached on the intermediate RDL layer;

[0048] The second wafer encapsulation is performed to form the second stack;

[0049] The second surface of the second stack is thinned to expose the second metal support column and the second ultra-fine RDL adapter plate;

[0050] The pure RDL layer is prepared on the second surface of the second stack, the solder ball layer is formed on the pure RDL layer, the carrier wafer attached to the antenna layer is removed, and

[0051] The chip is attached on the antenna layer to form the outer chip layer.

[0052] The application further provides a manufacturing method of the multi-chip system with the integrated antenna.

[0053] The bonding glue is applied on the carrier wafer, and the antenna layer is prepared on the bonding glue, the antenna layer having the RDL and the antenna array;

[0054] The first metal support column is manufactured on the antenna layer;

[0055] attaching a chip of the first stack on the antenna layer;

[0056] attaching a first ultra-fine RDL adapter plate on the antenna layer;

[0057] carrying out first wafer encapsulation to form the first stack;

[0058] thinning the first surface of the first stack to expose the first metal support column and the first ultra-fine RDL adapter plate;

[0059] preparing an intermediate RDL layer on the first surface of the first stack;

[0060] making a second metal support column on the intermediate RDL layer;

[0061] attaching a chip of the second stack on the intermediate RDL layer;

[0062] attaching a second ultra-fine RDL adapter plate on the intermediate RDL layer;

[0063] carrying out second wafer encapsulation to form the second stack;

[0064] thinning the second stack to expose the second metal support column and the second ultra-fine RDL adapter plate;

[0065] preparing an intermediate RDL layer on the second stack;

[0066] making a third metal support column on the intermediate RDL layer;

[0067] attaching a chip of the third stack on the intermediate RDL layer;

[0068] attaching a third ultra-fine RDL adapter plate on the intermediate RDL layer;

[0069] carrying out third wafer encapsulation to form the third stack;

[0070] thinning the third stack to expose the third metal support column and the third ultra-fine RDL adapter plate;

[0071] preparing an antenna layer on the third stack;

[0072] removing the wafer carrier attached to the antenna layer of the first stack; and

[0073] attaching a chip on the antenna layer to form an outer chip layer;

[0074] wherein the first metal support column, the second metal support column and the third metal support column are vertically interconnected.

[0075] In the multi-chip system with integrated antenna and the manufacturing method thereof, the multiple stacked layers along the thickness direction each contain a chip, a super-fine RDL adapter plate and a metal support column, and the intermediate RDL layer is used as the interface of the multiple stacked layers, so that the vertical interconnection structure is formed between the multiple stacked layers, and the vertical high-density interconnection and integration are realized.

[0076] Since the metal interconnection structure includes the super-fine RDL adapter plate, the super-fine RDL interconnection of the vertical interconnection structure is realized, which is used for the high-density interconnection requirement of the chip and can realize the interconnection between the upper and lower chips.

[0077] Since the metal interconnection structure includes the metal support column, the metal support column can be used for electromagnetic shielding of the chip.

[0078] In addition, the multiple stacked layers along the thickness direction each contain the super-fine RDL adapter plate, and especially the vertical interconnection (located at the center of the stacked layer) of the two, so that the adapter plates and the stacked adapter plates are realized, which is beneficial to the shortest interconnection in the signal processing direction of the chip.

[0079] By coating the bonding glue on the carrier wafer and preparing the antenna layer on the bonding glue, the antenna layer has the RDL and the antenna array, the RDL first fan-out packaging process is adopted, the adapter plate, the antenna and the multi-chip are integrated, the problem that the existing antenna packaging can only integrate the antenna and the single chip and cannot form the system-level packaging mode is solved, and the vertical high-density interconnection and integration are realized.

[0080] In summary, the present application has the following advantages:

[0081] 1. The RDL first fan-out packaging process is adopted to integrate the super-fine RDL adapter plate, the antenna and the multi-chip, and the vertical high-density interconnection and integration are realized.

[0082] 2. The super-fine RDL adapter plate can realize the super-fine RDL interconnection, which is used for the high-density interconnection requirement of the chip and can realize the interconnection between the upper and lower chips.

[0083] 3. The multiple super-fine RDL adapter plates are stacked, which is beneficial to the shortest interconnection in the signal processing direction of the chip.

[0084] 4. The metal support column (mega pillar) can be used for electromagnetic shielding of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0085] Figure 1 is a schematic diagram of a multi-chip system with integrated antenna in an embodiment of the present application;

[0086] Figure 2is a manufacturing method of a multi-chip system of an integrated antenna in an embodiment of the present application, a schematic diagram of forming an antenna layer;

[0087] Figure 3 is a manufacturing method of a multi-chip system of an integrated antenna in an embodiment of the present application, a schematic diagram of forming a first metal support column;

[0088] Figure 4 is a manufacturing method of a multi-chip system of an integrated antenna in an embodiment of the present application, a schematic diagram of a first patching;

[0089] Figure 5 is a manufacturing method of a multi-chip system of an integrated antenna in an embodiment of the present application, a schematic diagram of forming a first lamination;

[0090] Figure 6 is a manufacturing method of a multi-chip system of an integrated antenna in an embodiment of the present application, a schematic diagram of forming an intermediate RDL layer;

[0091] Figure 7 is a manufacturing method of a multi-chip system of an integrated antenna in an embodiment of the present application, a schematic diagram of forming a second metal support column;

[0092] Figure 8 is a manufacturing method of a multi-chip system of an integrated antenna in an embodiment of the present application, a schematic diagram of a second patching;

[0093] Figure 9 is a manufacturing method of a multi-chip system of an integrated antenna in an embodiment of the present application, a schematic diagram of forming a second lamination;

[0094] Figure 10 is a manufacturing method of a multi-chip system of an integrated antenna in an embodiment of the present application, a schematic diagram of forming a solder ball;

[0095] Figure 11 is a manufacturing method of a multi-chip system of an integrated antenna in an embodiment of the present application, a schematic diagram of removing a carrier wafer;

[0096] Figure 12 is a manufacturing method of a multi-chip system of an integrated antenna in an embodiment of the present application, a schematic diagram of forming an outer chip layer;

[0097] In the figure: 1-antenna / antenna array; 2-RDL; 3-bonding glue; 4-carrier wafer; 5-first metal support column; 6-outer RDL layer / antenna layer; 7-first ultra-fine RDL adapter plate; 8-chip of the first lamination; 9-first lamination; 10-intermediate RDL layer; 11-second metal support column; 12-chip of the second lamination; 13-second ultra-fine RDL adapter plate; 14-second lamination; 15-outer RDL layer / pure RDL layer; 16-solder ball; 17-chip of the outer chip layer. DETAILED DESCRIPTION

[0098] The application will be further described below with reference to the drawings.

[0099] It should be noted that the components in the various drawings can be shown exaggeratedly for illustration purposes, and are not necessarily true to scale. In the various drawings, the same or functionally similar components are provided with the same reference numerals.

[0100] In the present application, unless otherwise specified, "arranged on", "arranged above", and "arranged over" do not exclude the presence of an intermediate object between the two. In addition, "arranged on or above" only indicates the relative positional relationship between the two components, and in certain cases, such as after reversing the product direction, it can also be converted to "arranged below or below", and vice versa.

[0101] In the present application, each embodiment is only intended to illustrate the scheme of the present application, and should not be understood as limiting.

[0102] In the present application, unless otherwise specified, the quantifier "one" does not exclude the scenario of multiple elements.

[0103] It should also be noted here that in the embodiments of the present application, only a part of the components or assemblies can be shown for clarity and simplicity, but those skilled in the art can understand that under the teaching of the present application, the required components or assemblies can be added according to the specific scene. In addition, unless otherwise stated, the features in different embodiments of the present application can be combined with each other. For example, the corresponding or functionally similar features in the first embodiment can be replaced with the features in the second embodiment, and the resulting embodiment also falls within the scope or range disclosed in the present application.

[0104] It should also be noted here that within the scope of the present application, the phrases "same", "equal", "equal to" and the like do not mean that the two values are absolutely equal, but allow a certain reasonable error, that is, the phrases also cover "substantially the same", "substantially equal", "substantially equal". By analogy, in the present application, the terms "perpendicular to", "parallel to" and the like also cover the meanings of "substantially perpendicular to", "substantially parallel to".

[0105] In addition, the numbering of the steps of each method of the present application does not limit the execution order of the method steps. Unless otherwise specified, each method step can be executed in a different order.

[0106] The integrated antenna multi-chip system and the manufacturing method thereof according to the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present application will be more apparent from the following description. It should be noted that the accompanying drawings are very simplified and are not drawn to scale, and are only used to facilitate and clarify the purpose of illustrating the embodiments of the present application.

[0107] The present application aims to provide an integrated antenna multi-chip system and a manufacturing method thereof to solve the problem that the existing antenna packaging cannot form a system-level packaging mode.

[0108] To achieve the above-mentioned purpose, the present application provides an integrated antenna multi-chip system and a manufacturing method thereof, comprising: a plurality of stacks configured to accommodate one or more of the following: a plurality of chips, a super-fine RDL adapter plate, and a plurality of metal support columns, wherein the plurality of stacks are stacked in the thickness direction to form a vertical interconnection structure; and an intermediate RDL layer configured to serve as an interface of the plurality of stacks.

[0109] An embodiment of the present application provides an integrated antenna multi-chip system, as shown in Figure 1 comprising: a plurality of stacks configured to accommodate one or more of a plurality of chips, a super-fine RDL adapter plate, and a plurality of metal support columns, wherein the plurality of stacks are stacked in the thickness direction to form a vertical interconnection structure; and an intermediate RDL layer 10 configured to serve as an interface of the plurality of stacks.

[0110] In an embodiment of the present application, in the integrated antenna multi-chip system, as shown in Figure 1 comprising: a first stack 9 configured to accommodate a plurality of chips, a first super-fine RDL adapter plate 7, and a plurality of first metal support columns 5; a second stack 14 configured to accommodate a plurality of chips, a second super-fine RDL adapter plate 13, and a plurality of second metal support columns 11; an intermediate RDL layer 10 configured to serve as an interface of the first stack 9 and the second stack 14, and to be attached to a first surface of the first stack 9 and a first surface of the second stack 14; and an outer RDL layer (an antenna layer 6 or a pure RDL layer 15) configured to accommodate an antenna 1 (here, the antenna layer 6 accommodates the antenna), and connected to the first stack 9 and / or the second stack 14.

[0111] In an embodiment of the present application, in the integrated antenna multi-chip system, as shown in Figure 1As shown, the outer RDL layer includes: an antenna layer 6 configured to house an antenna 1, which is connected to the second surface of the first stack 9 and / or the second surface of the second stack 14; and a pure RDL layer 15 configured to be connected to the second surface of the first stack 9 and / or the second surface of the second stack 14; wherein the arrangement of the pure RDL layer 15 and the antenna layer 6 can be reversed, such that the pure RDL layer 15 and the antenna layer 6 are respectively located on the first surface and the second surface of the multi-chip system of the integrated antenna, or both the first surface and the second surface of the multi-chip system of the integrated antenna are antenna layers, or both the first surface and the second surface of the multi-chip system of the integrated antenna are pure RDL layers. Those skilled in the art can derive the relevant technical solutions, all of which are within the protection scope of this invention.

[0112] In one embodiment of the present invention, in the multi-chip system with the integrated antenna, such as Figure 1 As shown, it also includes: an outer chip layer configured to accommodate a plurality of chips 17, such that the plurality of chips 17 can be connected to the outer side of the antenna layer 6 and / or the pure RDL layer 15; and a solder ball layer 16 configured to accommodate solder balls 16, which can be connected to the outer side of the antenna layer 6 and / or the pure RDL layer 15. Figure 1 The chip 17 is not shown connected to the outer side of the pure RDL layer 15, and the solder ball 16 is not shown connected to the outer side of the antenna layer 6, but those skilled in the art can deduce the relevant technical solutions, all of which are within the protection scope of this invention.

[0113] In one embodiment of the present invention, in the multi-chip system of the integrated antenna, the electrical signals of the first stack 9 and the second stack 14 are connected at least in the following ways: any two of the following components—chip 8 of the first stack 9, chip 12 of the second stack 14, first ultra-fine RDL adapter board 7, first metal support pillar 5, second ultra-fine RDL adapter board 13, second metal support pillar 11, antenna 1, chip 17 of the outer chip layer, and solder ball 16—can be electrically connected through the intermediate RDL layer 10 and / or the outer RDL layer (here mainly referring to antenna layer 6 and pure RDL layer 15); the first ultra-fine RDL adapter board 7 can be electrically connected to any one of the components in the first stack 9; the second ultra-fine RDL adapter board 13 can be electrically connected to any one of the components in the second stack 14. Since the metal interconnect structure includes the ultra-fine RDL adapter board, it realizes the ultra-fine RDL interconnect of the vertical interconnect structure, which is used for the high-density interconnection requirements of chips and can realize the interconnection of upper and lower chips.

[0114] In one embodiment of the present invention, in the multi-chip system of the integrated antenna, the first ultra-fine RDL adapter plate 7 and the second ultra-fine RDL adapter plate 13 have TSV holes with a diameter of 200 nm to 10.0 μm. Linewidths and spacings of less than 2 μm, or even submicron, can be achieved on the adapter plates.

[0115] In one embodiment of the present application, in the multi-chip system with integrated antennas, the arrangement of the first ultra-fine RDL adapter 7 and the second ultra-fine RDL adapter 13 satisfies one or more of the following conditions: the first ultra-fine RDL adapter 7 and the second ultra-fine RDL adapter 13 are vertically interconnected; the first ultra-fine RDL adapter 7 and the second ultra-fine RDL adapter 13 are respectively located at the center of the first stack 9 and the second stack 14; a plurality of chips are arranged around the first ultra-fine RDL adapter 7 and the second ultra-fine RDL adapter 13. By stacking a plurality of stacks in the thickness direction, each of which contains an ultra-fine RDL adapter, especially the vertical interconnection of the two (each located at the center of the stack where it is located), the adapter and the stack of adapters are realized, which is conducive to the shortest interconnection of the chip signal handling direction.

[0116] In one embodiment of the present application, in the multi-chip system with integrated antennas, the arrangement of the first metal support column 5 and the second metal support column 11 satisfies one or more of the following conditions: the first metal support column 5 and the second metal support column 11 are vertically interconnected to improve the mechanical stress of the entire structure; the first metal support column 5 and the second metal support column 11 are arranged around the chips 8 of the first stack and the chips 12 of the second stack to improve the EMC and EMI performance of the electrical signal between the chips and improve the reliability; the first metal support column 5 and the second metal support column 11 are arranged around the first ultra-fine RDL adapter 7 and the second ultra-fine RDL adapter 13. Since the metal interconnection structure includes metal support columns, it can be used for electromagnetic shielding of chips and / or adapters.

[0117] Embodiments of the present application also provide a method for manufacturing a multi-chip system with integrated antennas as described above, such as Figures 2-12As shown, the method comprises the following steps: applying the bonding glue 3 on the carrier wafer 4, and preparing the antenna layer 6 on the bonding glue 3, the antenna layer 6 having the RDL 2 and the antenna array 1; making the first metal support column 5 on the antenna layer 6; attaching the chip 8 of the first stack 9 on the antenna layer 6; attaching the first ultra-fine RDL adapter plate 7 on the antenna layer 6; performing the first wafer plastic packaging to form the first stack 9; thinning the first surface of the first stack 9 to expose the first metal support column 5 and the first ultra-fine RDL adapter plate 7; preparing the intermediate RDL layer 10 on the first surface of the first stack 9; making the second metal support column 11 on the intermediate RDL layer 10; attaching the chip 12 of the second stack 14 on the intermediate RDL layer 10; attaching the second ultra-fine RDL adapter plate 13 on the intermediate RDL layer 10; performing the second wafer plastic packaging to form the second stack 14; thinning the second surface of the second stack 14 to expose the second metal support column 11 and the second ultra-fine RDL adapter plate 13; preparing the pure RDL layer 15 on the second surface of the second stack 14, and forming the solder ball 16 layer on the pure RDL layer 15; removing the carrier wafer 4 attached to the antenna layer 6; and attaching the chip on the antenna layer 6 to form the outer chip layer.

[0118] The embodiment of the present application also provides a manufacturing method of the integrated antenna multi-chip system as described above, comprising the following steps: applying the bonding glue 3 on the carrier wafer 4, and preparing the antenna layer 6 on the bonding glue 3, the antenna layer 6 having the RDL 2 and the antenna array 1; making the first metal support column 5 on the antenna layer 6; attaching the chip 8 of the first stack 9 on the antenna layer 6; attaching the first ultra-fine RDL adapter plate 7 on the antenna layer 6; performing the first wafer plastic packaging to form the first stack 9; thinning the first surface of the first stack 9 to expose the first metal support column 5 and the first ultra-fine RDL adapter plate 7; preparing the intermediate RDL layer 10 on the first surface of the first stack 9; making the second metal support column 11 on the intermediate RDL layer 10; attaching the chip 12 of the second stack 14 on the intermediate RDL layer 10; attaching the second ultra-fine RDL adapter plate 13 on the intermediate RDL layer 10; performing the second wafer plastic packaging to form the second stack 14; thinning the second stack 14 to expose the second metal support column 11 and the second ultra-fine RDL adapter plate 13; preparing the intermediate RDL layer 10 on the second stack 14; making the third metal support column on the intermediate RDL layer 10; attaching the chip of the third stack on the intermediate RDL layer 10; attaching the third ultra-fine RDL adapter plate on the intermediate RDL layer 10; performing the third wafer plastic packaging to form the third stack; thinning the third stack to expose the third metal support column and the third ultra-fine RDL adapter plate; preparing the antenna layer 6 on the third stack; removing the carrier wafer 4 attached to the antenna layer 6 connected with the first stack 9; and attaching the chip on the antenna layer 6 to form the outer chip layer; wherein the first metal support column 5, the second metal support column 11 and the third metal support column are vertically interconnected.

[0119] In the multi-chip system integrated with an antenna and the manufacturing method thereof, the multiple stacks stacked along the thickness direction each contain a chip, a super-fine RDL adapter plate and a metal support column, and the vertical interconnection structure is formed between the multiple stacks through the intermediate RDL layer 10 as the interface of the multiple stacks, and the vertical interconnection structure contains a large number of chips and metal interconnection structures, realizing high-density interconnection and integration in the vertical direction.

[0120] Since the metal interconnection structure includes the super-fine RDL adapter plate, the super-fine RDL interconnection of the vertical interconnection structure is realized, which is used for the high-density interconnection requirement of the chip and can realize the interconnection between the upper and lower chips.

[0121] Since the metal interconnection structure includes the metal support column, the metal support column can be used for electromagnetic shielding of the chip.

[0122] In addition, the super-fine RDL adapter plates are contained in the multiple stacks stacked along the thickness direction, and especially the vertical interconnection (located at the center position of the stack) of the two, realizing the stacking of the adapter plates and the adapter plates, which is beneficial to the shortest interconnection in the chip signal processing direction.

[0123] By coating the bonding glue 3 on the carrier wafer 4 and preparing the antenna layer 6 on the bonding glue 3, the antenna layer 6 has RDL and an antenna array, and the RDL first fan-out packaging process is adopted to integrate the adapter plate, the antenna and the multi-chip, which solves the problem that the existing antenna packaging can only integrate the antenna and a single chip and cannot form a system-level packaging mode, and realizes high-density interconnection and integration in the vertical direction.

[0124] In summary, the present application has the following advantages: 1. The RDL first fan-out packaging process is adopted to integrate the super-fine RDL adapter plate, the antenna and the multi-chip, realizing high-density interconnection and integration in the vertical direction; 2. The super-fine RDL adapter plate can realize super-fine RDL interconnection, which is used for the high-density interconnection requirement of the chip and can realize the interconnection between the upper and lower chips; 3. The stacking of multiple super-fine RDL adapter plates is realized, which is beneficial to the shortest interconnection in the chip signal processing direction; 4. The metal support column (mega pillar) can be used for electromagnetic shielding of the chip.

[0125] In summary, the different configurations of the multi-chip system integrated with an antenna and the manufacturing method thereof are described in detail in the above embodiments, of course, the present application includes but is not limited to the configurations listed in the above embodiments, any content transformed on the basis of the configurations provided in the above embodiments belongs to the scope protected by the present application. Those skilled in the art can draw conclusions from the above embodiments.

[0126] The various embodiments described in this specification are implemented in a progressive manner, each embodiment focusing on the differences from other embodiments, and the same or similar parts between embodiments can be mutually referred to. For the system disclosed by the embodiments, since it corresponds to the method disclosed by the embodiments, the description is relatively simple, and the relevant parts can be referred to the method part.

[0127] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any modification or modification made by a person skilled in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A multi-chip system with integrated antennas, characterized by, The application comprises: a plurality of stacks configured to accommodate one or more of the following: a plurality of chips, a super-fine RDL interposer, and a plurality of metal support pillars, wherein the plurality of stacks are stacked along a thickness direction to form a vertical interconnect structure; and an intermediate RDL layer configured to serve as an interface for the plurality of stacks, wherein the plurality of stacks comprises: a first stack configured to accommodate a plurality of chips, a first super-fine RDL interposer, and a plurality of first metal support pillars; a second stack configured to accommodate a plurality of chips, a second super-fine RDL interposer, and a plurality of second metal support pillars; wherein the intermediate RDL layer is configured to serve as an interface for the first stack and the second stack, and is attached to a first face of the first stack and a first face of the second stack; and an outer RDL layer configured to accommodate an antenna, and is connected to the first stack and / or the second stack, wherein the first super-fine RDL interposer and the second super-fine RDL interposer are vertically interconnected; the first super-fine RDL interposer and the second super-fine RDL interposer are respectively located at a center position of the first stack and the second stack; and the plurality of chips are arranged around the first super-fine RDL interposer and the second super-fine RDL interposer.

2. The multiple-chip system of claim 1, wherein the first and second chips are configured to be connected to each other by a wire. The outer RDL layer comprises: an antenna layer configured to accommodate an antenna, and is connected to a second face of the first stack and / or a second face of the second stack; and a pure RDL layer configured to be connected to the second face of the first stack and / or the second face of the second stack; wherein the pure RDL layer is arranged opposite to the antenna layer, such that the pure RDL layer and the antenna layer are respectively located at a first face and a second face of the integrated antenna multi-chip system.

3. The multiple-chip system of claim 2, wherein the first and second antennas are integrated antennas. Further comprising: an outer chip layer configured to accommodate a plurality of chips, such that the plurality of chips are connected to a face of the antenna layer and / or the pure RDL layer which is away from the outer side; and a solder ball layer configured to accommodate solder balls, and is connected to a face of the antenna layer and / or the pure RDL layer which is away from the outer side.

4. The multiple-chip system of claim 3, wherein the first and second antennas are integrated antennas. The electrical signals of the first stack and the second stack are connected at least in the following ways: any two components among the chips of the first stack, the chips of the second stack, the first super-fine RDL interposer, the first metal support pillars, the second super-fine RDL interposer, the second metal support pillars, the antenna, the chips of the outer chip layer, and the solder balls can form an electrical connection through the intermediate RDL layer and / or the outer RDL layer; the first super-fine RDL interposer can have an electrical connection with any component in the first stack; the second super-fine RDL interposer can have an electrical connection with any component in the second stack.

5. The multiple-chip system of claim 1, wherein the first and second antennas are integrated antennas. The first super-fine RDL interposer and the second super-fine RDL interposer have TSV holes with a diameter of 200 nm to 10.0 μm.

6. The multiple-chip system of claim 1, wherein the first and second antennas are integrated antennas. The arrangement of the first metal support pillars and the second metal support pillars satisfies one or more of the following conditions: the first metal support pillars and the second metal support pillars are vertically interconnected; the first metal support pillars and the second metal support pillars are arranged around the chips of the first stack and the chips of the second stack; the first metal support pillars and the second metal support pillars are arranged around the first super-fine RDL interposer and the second super-fine RDL interposer.

7. A method of fabricating an integrated antenna multi-chip system as recited in claim 1, wherein, The application comprises: bonding glue is applied on the carrier wafer, and an antenna layer is prepared on the bonding glue, the antenna layer having an RDL and an antenna array therein; first metal support columns are made on the antenna layer; a chip of the first stack is attached on the antenna layer; a first ultra-fine RDL adapter plate is attached on the antenna layer; first wafer encapsulation is performed to form the first stack; the first surface of the first stack is thinned to expose the first metal support columns and the first ultra-fine RDL adapter plate; an intermediate RDL layer is prepared on the first surface of the first stack; second metal support columns are made on the intermediate RDL layer; a chip of the second stack is attached on the intermediate RDL layer; a second ultra-fine RDL adapter plate is attached on the intermediate RDL layer; second wafer encapsulation is performed to form the second stack; the second surface of the second stack is thinned to expose the second metal support columns and the second ultra-fine RDL adapter plate; a pure RDL layer is prepared on the second surface of the second stack, and a solder ball layer is formed on the pure RDL layer; the carrier wafer attached to the antenna layer is removed; and a chip is attached on the antenna layer to form an outer chip layer. comprising:

8. A method of fabricating an integrated antenna multi-chip system as recited in claim 1, wherein, bonding glue is applied on the carrier wafer, and an antenna layer is prepared on the bonding glue, the antenna layer having an RDL and an antenna array therein; first metal support columns are made on the antenna layer; a chip of the first stack is attached on the antenna layer; a first ultra-fine RDL adapter plate is attached on the antenna layer; first wafer encapsulation is performed to form the first stack; the first surface of the first stack is thinned to expose the first metal support columns and the first ultra-fine RDL adapter plate; an intermediate RDL layer is prepared on the first surface of the first stack; second metal support columns are made on the intermediate RDL layer; a chip of the second stack is attached on the intermediate RDL layer; a second ultra-fine RDL adapter plate is attached on the intermediate RDL layer; second wafer encapsulation is performed to form the second stack; the second surface of the second stack is thinned to expose the second metal support columns and the second ultra-fine RDL adapter plate; an intermediate RDL layer is prepared on the second stack; third metal support columns are made on the intermediate RDL layer; a chip of the third stack is attached on the intermediate RDL layer; a third ultra-fine RDL adapter plate is attached on the intermediate RDL layer; third wafer encapsulation is performed to form the third stack; the third surface of the third stack is thinned to expose the third metal support columns and the third ultra-fine RDL adapter plate; an antenna layer is prepared on the third stack; the carrier wafer attached to the antenna layer connected to the first stack is removed; and a chip is attached on the antenna layer to form an outer chip layer; wherein the first metal support columns, the second metal support columns and the third metal support columns are vertically interconnected. ​ ​

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