Silicon carbide mps diode with buried layer structure and method of manufacturing the same

Abstract

The silicon carbide MPS diode disclosed by the application comprises, from bottom to top, a cathode ohmic contact electrode, a silicon carbide N+ substrate and a silicon carbide N- epitaxial layer; two P+ implantation regions are formed on the top of the silicon carbide N- epitaxial layer, the two P+ implantation regions are in contact with the top of two P+ buried layers I through two P+ buried layers II respectively, the width of the P+ implantation region and the P+ buried layer I is greater than that of the P+ buried layer II; two ohmic contact electrodes are arranged on the top of the two P+ implantation regions, and a Schottky contact electrode is arranged between the two ohmic contact electrodes. The narrow P+ buried layer II is used to connect the P+ implantation region and the P+ buried layer I, the proportion of the PN junction in the epitaxial layer is increased, and the snapback phenomenon of the MPS diode in the forward conduction is eliminated; meanwhile, the transition voltage of the MPS diode from the unipolar working state to the bipolar working state is reduced, so that the diode enters the bipolar working state under a lower forward current, the working temperature of the diode under a large current is reduced, and the diode has a higher surge current resistance.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and more specifically, this invention relates to a silicon carbide MPS diode with a buried layer structure and its fabrication method. Background Technology

[0002] Silicon carbide (SiC), a third-generation wide-bandgap semiconductor material, boasts superior material physics and electrical properties. Compared to silicon (Si), SiC (4H-SiC) exhibits significant advantages such as a wider bandgap (3 times that of Si), higher electron saturation drift velocity (2.5 times that of Si), higher thermal conductivity (3.3 times that of Si), and a higher critical breakdown electric field (10 times that of Si). It can operate at high power density, high frequency, and high temperature, and suffers from lower losses during conduction and switching. This makes it particularly suitable for fabricating high-voltage, high-power, radiation-resistant, and high-temperature reliable semiconductor power devices. SiC unipolar power rectifiers, based on the majority carrier conductivity, feature fast switching speeds and low forward turn-on voltages. Typical examples include the Schottky Barrier Diode (SBD) and the Junction Barrier Schottky Diode (JBS). The SiC JBS diode is an improvement upon the Schottky structure of the SiC SBD diode. By integrating a PN junction with a specific width-to-width ratio into the Schottky structure, it significantly reduces the reverse leakage current of the SBD and improves the device's breakdown voltage, while still retaining the same low conduction loss and fast switching speed characteristics as the SBD. As the earliest commercially available silicon carbide power device, the silicon carbide junction barrier Schottky diode still holds the largest market share.

[0003] Diodes used in switching power supplies must be able to withstand surge currents, which are the peak currents flowing into the power supply device at the moment of power-on. Because the input filter capacitor charges rapidly, this peak current is much larger than the steady-state input current. The repetitive surge current of a typical SiC JBS diode can be 4 to 5 times its steady-state operating current. To improve the reliability of SiC JBS devices in switching power supplies, the diode's surge current resistance needs to be enhanced. Therefore, an ohmic contact is created above the PN junction of the JBS diode, forming an MPS (Merge-PiN-Schottky) diode structure. Using an MPS structure can increase the surge current to 10 to 13 times the steady-state operating current.

[0004] In an MPS diode, when the majority carrier electron current generated at the Schottky electrode diffuses laterally, causing the voltage drop across the PN junction to exceed the built-in potential of the PN junction, the diode enters a bipolar operating state. Therefore, in an unoptimized MPS diode structure, the voltage applied to the PN junction is actually less than the voltage applied to the device itself, requiring an additional voltage to be applied before bipolar mode is activated. If this additional voltage is too large, a snapback phenomenon will be observed in the forward current-voltage characteristics after the diode enters bipolar operation; that is, voltage hysteresis occurs, and the amount of hysteresis is related to the applied additional voltage. This phenomenon can be very harmful when multiple MPS diodes are connected in parallel; a sudden drop in the forward voltage drop of one diode can cause the entire circuit system to collapse. Therefore, eliminating the snapback phenomenon is crucial.

[0005] After forming an MPS diode structure by fabricating the gold-plated contact above the PN junction into an ohmic contact, the surge current capability depends on the current magnitude of the diode in bipolar operation. For MPS diodes, the PN junction conducts under surge current, causing the diode to operate in a bipolar state, resulting in conductivity modulation, reducing the diode's on-resistance and operating temperature, and improving the device's surge current resistance. However, in the normal operating state of a conventional MPS diode, the Schottky junction current dominates. To ensure that the operating current meets requirements under normal operation, the PN junction area is typically a small proportion of the total chip area. This small PN junction area leads to a large PN junction forward voltage, meaning the PN junction may not conduct under surge current, causing premature diode failure. Summary of the Invention

[0006] The present invention provides a silicon carbide MPS diode with a buried layer structure, which aims to improve the above-mentioned problems.

[0007] This invention is achieved by providing a silicon carbide MPS diode with a buried layer structure, the silicon carbide MPS diode comprising:

[0008] The cathode ohmic contact electrode, silicon carbide N+ substrate, and silicon carbide N- epitaxial layer are stacked from bottom to top. Two P+ implantation regions are formed on the top of the silicon carbide N- epitaxial layer. The bottom of the two P+ implantation regions is in contact with the top of the two P+ buried layers II. The bottom of the two P+ buried layers II is in contact with the top of the two P+ buried layers I. The width of the P+ implantation region and the width of the P+ buried layer I are greater than those of the P+ buried layer II.

[0009] Two ohmic contact electrodes are placed on top of the two P+ injection regions, and a Schottky contact electrode is placed between the two ohmic contact electrodes.

[0010] Furthermore, the silicon carbide N-epitaxial layer is composed of silicon carbide N-epitaxial layer I, silicon carbide N-epitaxial layer II and silicon carbide N-epitaxial layer III from bottom to top;

[0011] Among them, silicon carbide N- epitaxial layer I is located on silicon carbide N+ substrate, two P+ buried layers I are located on top of silicon carbide N- epitaxial layer I; two P+ buried layers II are located on silicon carbide N- epitaxial layer II; and two P+ implanted regions are located on silicon carbide N- epitaxial layer III.

[0012] Furthermore, the doping concentrations of silicon carbide N-epitaxial layer I, silicon carbide N-epitaxial layer II, and silicon carbide N-epitaxial layer III are the same.

[0013] Furthermore, the width of the P+ injection zone is equal to the width of P+ buried layer I, while the width of the P+ injection zone is greater than the width of P+ buried layer II.

[0014] Furthermore, the depth of the P+ injection zone is equal to the depth of P+ buried layer I, while the depth of the P+ injection zone is less than the depth of P+ buried layer II.

[0015] Furthermore, the doping concentrations of the P+ implantation region, P+ buried layer I, and P+ buried layer II are equal.

[0016] Furthermore, the P+ buried layer I is located in the middle of the silicon carbide N- epitaxial layer.

[0017] This invention is achieved by providing a method for fabricating a silicon carbide MPS diode with a buried layer structure, the method specifically comprising the following steps:

[0018] Step 1: Epitaxially grow silicon carbide N- epitaxial layer I on silicon carbide N+ substrate, and perform P+ ion implantation on N- epitaxial layer I to form two P+ buried layers I;

[0019] Step 2: A second epitaxial growth of silicon carbide N-epitaxial layer II is performed on N-epitaxial layer I, and P+ ion implantation is performed on silicon carbide N-epitaxial layer II to form two P+ buried layers II;

[0020] Step 3: A second epitaxial growth of silicon carbide N-epitaxial layer III is performed on silicon carbide N-epitaxial layer II, and P+ ion implantation is performed on silicon carbide N-epitaxial layer III to form two P+ implantation regions;

[0021] Step 4: Fabricate two ohmic contact electrodes above the two P+ ion implantation regions respectively, and fabricate ohmic contact electrodes on the back side of the silicon carbide N+ substrate.

[0022] Step 5: Fabricate a Schottky contact electrode between the two ohmic contact electrodes.

[0023] This invention connects the P+ injection region (3) and the P+ buried layer I (7) using a narrow P+ buried layer II (6), increasing the PN junction ratio inside the epitaxial layer and eliminating the snapback phenomenon during forward conduction of the MPS diode. Simultaneously, it reduces the transition voltage of the MPS diode from unipolar to bipolar operating state, allowing the diode to enter the bipolar operating state at a lower forward current, thus lowering the high-current operating temperature and providing higher surge current resistance. Furthermore, the buried layer structure enhances minority carrier injection and conductivity modulation effects in the PN junction of the MPS diode, further reducing the diode's on-resistance and improving its surge current resistance. Attached Figure Description

[0024] Figure 1 A schematic diagram of the silicon carbide MPS diode with a buried layer structure provided by the present invention;

[0025] Figure 2 A flowchart illustrating a method for fabricating a silicon carbide MPS diode with a buried layer structure, provided in an embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of the structure of a conventional MPS diode provided in an embodiment of the present invention;

[0027] Figure 4 A comparison diagram of the forward voltage and current curves when the bipolar mode is enabled, provided in an embodiment of the present invention;

[0028] Figure 5 A comparison graph of the relationship between forward voltage and device temperature provided for embodiments of the present invention;

[0029] Figure 6 A comparison diagram of temperature curves under a sinusoidal current waveform provided in an embodiment of the present invention;

[0030] Figure 7 A comparison of hole concentration distribution curves as a function of device width within the N-epitaxial layer (4 μm depth) provided in an embodiment of the present invention;

[0031] 1. Silicon carbide N+ substrate, 2. Silicon carbide N- epitaxial layer, 3. P+ implantation region, 4. Ohmic contact electrode, 5. Schottky contact electrode, 6. P+ buried layer II, 7. P+ buried layer I, 8. Cathode ohmic contact electrode. Detailed Implementation

[0032] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, so as to help those skilled in the art to have a more complete, accurate and in-depth understanding of the inventive concept and technical solution of the present invention.

[0033] Figure 1This is a schematic diagram of the silicon carbide MPS diode with a buried layer structure provided by the present invention. For ease of explanation, only the parts related to the embodiments of the present invention are shown.

[0034] The silicon carbide MPS diode includes:

[0035] The cathode ohmic contact electrode (8), silicon carbide N+ substrate (1) and silicon carbide N- epitaxial layer (2) are stacked from bottom to top;

[0036] Two P+ implantation regions (3) are formed on the top of the silicon carbide N-epitaxial layer (2). The bottom of the two P+ implantation regions (3) is in contact with the top of the two P+ buried layers II (6). The bottom of the two P+ buried layers II (6) is in contact with the top of the two P+ buried layers I (7). The width of the P+ implantation regions (3) and the width of the P+ buried layers I (7) are greater than those of the P+ buried layers II (6).

[0037] Two ohmic contact electrodes (4) are provided on top of the two P+ injection regions (3), and a Schottky contact electrode (5) is provided between the two ohmic contact electrodes (4).

[0038] The following describes a specific structural parameter of a silicon carbide MPS diode. The structural parameters of a silicon carbide MPS diode include, but are not limited to, the following:

[0039] The silicon carbide N+ substrate (1) has a thickness of 180 micrometers and a doping concentration of 1E20cm. -3 The doping concentration of the silicon carbide N-epitaxial layer (2) is 1E16cm. -3 The thickness is 6 micrometers; the width of the P+ implantation region (3) is 3 micrometers, the width of the P+ buried layer II (6) is 1 micrometer, and the width of the P+ buried layer (7) is greater than 1 micrometer and less than or equal to 3 micrometers; the ohmic contact electrode 4 is made of metallic Ni, and the Schottky contact electrode 5 is made of metallic Ti alloy.

[0040] In addition, the depth (junction depth) of P+ injection area (3), P+ buried layer II (6) and P+ buried layer (7) in this patent refers to the thickness in the stack extension direction, and the width of P+ injection area (3), P+ buried layer II (6) and P+ buried layer (7) refers to the length perpendicular to the stack extension direction.

[0041] In this embodiment of the invention, the silicon carbide N-epitaxial layer is composed of silicon carbide N-epitaxial layer I, silicon carbide N-epitaxial layer II and silicon carbide N-epitaxial layer III from bottom to top. The silicon carbide N-epitaxial layer I is located on the silicon carbide N+ substrate (1), and two P+ buried layers I (7) are located on top of the silicon carbide N-epitaxial layer I; two P+ buried layers II (6) are located in the silicon carbide N-epitaxial layer II; and two P+ implantation regions (3) are located in the silicon carbide N-epitaxial layer III.

[0042] The following describes a specific structural parameter of a silicon carbide MPS diode. The structural parameters of a silicon carbide MPS diode include, but are not limited to, the following:

[0043] The silicon carbide N+ substrate (1) has a thickness of 180 micrometers and a doping concentration of 1E20cm. -3 The doping concentration of silicon carbide N-epitaxial layer I, silicon carbide N-epitaxial layer II, and silicon carbide N-epitaxial layer III is 1E16cm. -3 The thickness is 6 micrometers; the width of the P+ implantation region (3) is 3 micrometers, the width of the P+ buried layer II (6) is 1 micrometer, and the width of the P+ buried layer I (7) is greater than 1 micrometer and less than or equal to 3 micrometers; the ohmic contact electrode 4 is made of metallic Ni, and the Schottky contact electrode 5 is made of metallic Ti alloy.

[0044] In this embodiment of the invention, the width of the P+ injection region (3) is equal to the width of the P+ buried layer I (7), and the width of the P+ injection region (3) is greater than the width of the P+ buried layer II (6).

[0045] The following describes a specific structural parameter of a silicon carbide MPS diode. The structural parameters of a silicon carbide MPS diode include, but are not limited to, the following:

[0046] The silicon carbide N+ substrate (1) has a thickness of 180 micrometers and a doping concentration of 1E20cm. -3 The doping concentration of the silicon carbide N-epitaxial layer (2) is 1E16cm. -3 The thickness is 6 micrometers; the width of the P+ implantation region (3) is 3 micrometers, the width of the P+ buried layer II (6) is 1 micrometer, and the width of the P+ buried layer I (7) is 3 micrometers; the ohmic contact electrode 4 is made of metallic Ni, and the Schottky contact electrode 5 is made of metallic Ti alloy.

[0047] In this embodiment of the invention, the depth of the P+ injection region (3) is equal to the depth of the P+ buried layer I (7), and the depth of the P+ injection region (3) is less than the depth of the P+ buried layer II (6).

[0048] The following describes a specific structural parameter of a silicon carbide MPS diode. The structural parameters of a silicon carbide MPS diode include, but are not limited to, the following:

[0049] The silicon carbide N+ substrate (1) has a thickness of 180 micrometers and a doping concentration of 1E20cm. -3 The doping concentration of the silicon carbide N-epitaxial layer (2) is 1E16cm. -3The thickness is 6 micrometers; the width of the P+ implantation region (3) is 3 micrometers, the junction depth is 0.6 micrometers, the distance between the two P+ implantation regions (3) is 4 micrometers, the width of the P+ buried layer II (6) is 1 micrometer, the junction depth is 2.4 micrometers, the width of the P+ buried layer I (7) is 3 micrometers, the junction depth is 0.6 micrometers, and the distance between the two P+ buried layers I (7) is 4 micrometers; the ohmic contact electrode 4 is made of metallic Ni, and the Schottky contact electrode 5 is made of metallic Ti alloy.

[0050] In this embodiment of the invention, the doping concentrations of the P+ implantation region (3), P+ buried layer I (7), and P+ buried layer II (6) are equal.

[0051] The following describes a specific structural parameter of a silicon carbide MPS diode. The structural parameters of a silicon carbide MPS diode include, but are not limited to, the following:

[0052] The silicon carbide N+ substrate (1) has a thickness of 180 micrometers and a doping concentration of 1E20cm. -3 The doping concentration of the silicon carbide N-epitaxial layer (2) is 1E16cm. -3 The thickness is 6 micrometers; the doping concentration of the P+ implantation region (3) is 5E19cm. -3 The width is 3 micrometers, the junction depth is 0.6 micrometers, the spacing between the two P+ implantation regions (3) is 4 micrometers, and the doping concentration of the P+ buried layer II (6) is 5E19cm. -3 The width is 1 micrometer, the junction depth is 2.4 micrometers, and the doping concentration of the P+ buried layer I(7) is 5E19cm. -3 The width is 3 micrometers, the junction depth is 0.6 micrometers, and the spacing between the two P+ buried layers I (7) is 4 micrometers; the ohmic contact electrode 4 is made of metallic Ni, and the Schottky contact electrode 5 is made of metallic Ti alloy.

[0053] In this embodiment of the invention, the silicon carbide N-epitaxial layer I, silicon carbide N-epitaxial layer II and silicon carbide N-epitaxial layer III have the same doping concentration, and the P+ buried layer I (7) is located in the middle of the silicon carbide N-epitaxial layer.

[0054] Figure 2 A flowchart of a method for fabricating a silicon carbide MPS diode with a buried layer structure provided in this embodiment of the invention is shown. The method specifically includes the following steps:

[0055] Step 1: Epitaxially grow silicon carbide N- epitaxial layer I on silicon carbide N+ substrate (1), the thickness of silicon carbide N- epitaxial layer I is 3μm;

[0056] Step 2: P+ ion implantation was performed on the N-epitaxial layer I, and Al ions were implanted to form two P+ buried layers I (7), with an implantation depth of 0.6 μm;

[0057] Step 3: A second epitaxial growth of silicon carbide N-epitaxial layer II is performed on N-epitaxial layer I. The thickness of silicon carbide N-epitaxial layer I is 2 μm.

[0058] Step 4: P+ ion implantation is performed on silicon carbide N-epitaxial layer II, Al ions are implanted to form two P+ buried layers II (6), with an implantation depth of 2.4 μm;

[0059] Step 5: Secondary epitaxial growth of silicon carbide N-epitaxial layer III on silicon carbide N-epitaxial layer II, the thickness of silicon carbide N-epitaxial layer III is 1 μm;

[0060] Step 6: P+ ion implantation is performed on silicon carbide N-epitaxial layer III, Al ions are implanted to form two P+ implantation regions (3), with an implantation depth of 0.6 μm;

[0061] Step 7: Prepare two ohmic contact electrodes (4) above the two P+ ion implantation regions (3) respectively, and prepare an ohmic contact electrode (8) on the back side of the silicon carbide N+ substrate (1);

[0062] Step 8: Prepare a Schottky contact electrode (5) between the two ohmic contact electrodes (4).

[0063] This invention connects the P+ injection region (3) and the P+ buried layer I (7) using a narrow P+ buried layer II (6), increasing the PN junction ratio inside the epitaxial layer and eliminating the snapback phenomenon during forward conduction of the MPS diode. Simultaneously, it reduces the transition voltage of the MPS diode from unipolar to bipolar operating state, allowing the diode to enter the bipolar operating state at a lower forward current, thus lowering the high-current operating temperature and providing higher surge current resistance. Furthermore, the buried layer structure enhances minority carrier injection and conductivity modulation effects in the PN junction of the MPS diode, further reducing the diode's on-resistance and improving its surge current resistance.

[0064] Build using TCAD software Silvaco, such as Figure 1 , Figure 3 The device structure is such that a forward voltage is applied to the Schottky electrode (5) of the diode, and the relationship curve between the forward voltage and the forward current is obtained, as shown in the figure. Figure 4 As shown. The square legend curve represents a conventional SiCMPS diode (i.e., Figure 3 The forward current curve of the MPS diode (referred to as the ordinary structure) in this patent embodiment is shown in the triangle diagram. Figure 1 (Patent structure) positive current curve.

[0065] from Figure 4 It can be obtained, such as Figure 3The conventional MPS diode shown exhibits a significant hysteresis phenomenon, i.e., a snapback, when the bipolar mode is turned on (4.1V). However, the MPS diode with a buried layer structure in this patent embodiment does not exhibit a snapback phenomenon when the bipolar mode is turned on (3.3V). This effectively demonstrates that the structure of this patent can effectively eliminate the snapback phenomenon of unoptimized MPS diodes.

[0066] from Figure 4 It can be obtained, such as Figure 3 The conventional MPS diode shown has a forward conduction voltage of 1.29V and a PN junction conduction voltage of 4.1V at 10A, with a current of 68A. The MPS diode of this embodiment has a forward conduction voltage of 1.39V and a PN junction conduction voltage of 3.3V at 10A, with a current of 48A. It is evident that the PN junction conduction voltage of the silicon carbide MPS diode with a buried layer structure in this embodiment is reduced by approximately 20% compared to the first conventional MPS diode, and it can enter bipolar operating mode at a lower forward current. Furthermore, the on-state voltage drop of this embodiment only increases by 0.1V at a typical operating current of 10A, meaning the operating on-state voltage drop is not significantly increased due to the buried layer configuration of P+.

[0067] Build using TCAD software Silvaco, such as Figure 1 , Figure 3 The device structure was described, and a forward voltage was applied to the Schottky electrode 5 of the diode. The relationship between the forward voltage and the device temperature was obtained, as shown in the figure. Figure 5 As shown. The square-shaped curve represents the voltage-temperature curve of a conventional SiC MPS diode, while the circular-shaped curve represents the voltage-temperature curve of the MPS diode according to this patent embodiment. From Figure 5 It can be seen that the device temperature of a conventional MPS diode is higher than that of the embodiment of this patent after the bipolar mode is turned on. This indicates that the structure of this patent effectively enhances the minority carrier injection and conductance modulation effects, reduces the on-resistance and temperature of the diode under high current, and effectively enhances the diode's surge current resistance.

[0068] Build using TCAD software Silvaco, such as Figure 1 , Figure 3 The device structure was described. A sinusoidal current waveform with a period of 10ms was applied to the Schottky electrode 5 of the diode to simulate conventional surge current testing conditions, resulting in the temperature change curve of the diode over time. From the temperature curves of the conventional MPS diode and the MPS diode of this embodiment under a sinusoidal current waveform with a period of 10ms and a peak value of 115A, it can be seen that... Figure 6As shown, the square curve represents the temperature curve of a conventional SiC MPS diode at a current of 115A, while the triangular curve represents the temperature curve of the MPS diode in this patent embodiment. It can be seen that the peak temperature of the MPS diode in this embodiment is 583K, while the peak temperature of a conventional MPS diode reaches 654K. At this temperature, the conventional MPS diode has already failed because the temperature exceeds the melting point of the Al leads, while the MPS diode in this patent embodiment has not yet failed. It can be seen that the MPS diode in this patent embodiment has a lower chip temperature under high current and stronger surge current resistance.

[0069] Build using TCAD software Silvaco, such as Figure 1 , Figure 3 The device structure was described. A forward current of 100A was applied to the Schottky electrode 5 of the diode, and the hole concentration distribution curve as a function of device width at the N-epitaxial layer (depth 4μm) of the diode was obtained, as shown in the figure. Figure 7 As shown, the circular curve represents the hole concentration curve of a conventional SiC MPS diode, while the square curve represents the hole concentration curve of the MPS in this patent embodiment. It can be seen that the hole concentration in the epitaxial layer of the MPS diode in this embodiment at 100A is significantly greater than that of a conventional MPS diode. This effectively demonstrates that the structure of this patent enhances minority carrier injection in the PN junction and strengthens the conductivity modulation effect of the MPS, thereby giving the diode a stronger surge current resistance capability.

[0070] The present invention has been described above by way of example with reference to the accompanying drawings. Obviously, the specific implementation of the present invention is not limited to the above-described manner. Any non-substantial improvements made using the inventive concept and technical solution of the present invention, or the direct application of the inventive concept and technical solution of the present invention to other occasions without modification, are all within the protection scope of the present invention.

Claims

1. A silicon carbide MPS diode with a buried layer structure, characterized in that, The silicon carbide MPS diode includes: The cathode ohmic contact electrode, silicon carbide N+ substrate, and silicon carbide N- epitaxial layer are stacked from bottom to top; two P+ implantation regions are formed on the top of the silicon carbide N- epitaxial layer, the bottom of the two P+ implantation regions is in contact with the top of the two P+ buried layers II, and the bottom of the two P+ buried layers II is in contact with the top of the two P+ buried layers I. The width of the P+ implantation region and the width of the P+ buried layer I are greater than those of the P+ buried layer II. Two ohmic contact electrodes are disposed on top of the two P+ injection regions, and a Schottky contact electrode is disposed between the two ohmic contact electrodes; The width of the P+ injection zone is equal to the width of P+ buried layer I, and the width of the P+ injection zone is greater than the width of P+ buried layer II.

2. The silicon carbide MPS diode with a buried layer structure as described in claim 1, characterized in that, The silicon carbide N-epitaxial layer consists of silicon carbide N-epitaxial layer I, silicon carbide N-epitaxial layer II, and silicon carbide N-epitaxial layer III from bottom to top; Among them, silicon carbide N- epitaxial layer I is located on silicon carbide N+ substrate, two P+ buried layers I are located on top of silicon carbide N- epitaxial layer I; two P+ buried layers II are located on silicon carbide N- epitaxial layer II; and two P+ implanted regions are located on silicon carbide N- epitaxial layer III.

3. The silicon carbide MPS diode with a buried layer structure as described in claim 2, characterized in that, The doping concentrations of silicon carbide N-epitaxial layer I, silicon carbide N-epitaxial layer II, and silicon carbide N-epitaxial layer III are the same.

4. The silicon carbide MPS diode with a buried layer structure as described in claim 1 or 2, characterized in that, The depth of the P+ injection zone is equal to the depth of P+ buried layer I, while the depth of the P+ injection zone is less than the depth of P+ buried layer II.

5. The silicon carbide MPS diode with a buried layer structure as described in claim 1 or 2, characterized in that, The doping concentrations of the P+ implantation region, P+ buried layer I, and P+ buried layer II are equal.

6. The silicon carbide MPS diode with a buried layer structure as described in claim 1, characterized in that, The P+ buried layer I is located in the middle of the silicon carbide N- epitaxial layer.

7. A method for fabricating a silicon carbide MPS diode with a buried layer structure as described in any one of claims 1 to 6, characterized in that, The method specifically includes the following steps: Step 1: Epitaxially grow silicon carbide N- epitaxial layer I on silicon carbide N+ substrate, and perform P+ ion implantation on N- epitaxial layer I to form two P+ buried layers I; Step 2: A second epitaxial growth of silicon carbide N-epitaxial layer II is performed on N-epitaxial layer I, and P+ ion implantation is performed on silicon carbide N-epitaxial layer II to form two P+ buried layers II; Step 3: A second epitaxial growth of silicon carbide N-epitaxial layer III is performed on silicon carbide N-epitaxial layer II, and P+ ion implantation is performed on silicon carbide N-epitaxial layer III to form two P+ implantation regions; Step 4: Fabricate two ohmic contact electrodes above the two P+ ion implantation regions respectively, and fabricate ohmic contact electrodes on the back side of the silicon carbide N+ substrate. Step 5: Fabricate a Schottky contact electrode between the two ohmic contact electrodes.

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