A semiconductor structure and a method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the forming method comprising: providing a substrate, the substrate comprising adjacent first and second regions; forming a gate layer on the substrate, part of the gate layer being on the first region and another part of the gate layer also being on the second region; forming a first well region in the first region; forming a second well region in the second region, the second well region having a different conductivity type from the first well region; and doping a first doping ion in the first well region with part of the gate layer as a mask to form a first doping region, the first doping region having the same conductivity type as the first well region, the dopant in the first doping region diffusing to the second region to form a lateral diffusion gradient, so that the channel doping concentration is not uncontrollable, the source end barrier height is increased, the barrier reduction effect is effectively inhibited, the threshold voltage of the device is improved, and the breakdown voltage and other performances of the device are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] LDMOS (Lateral Double-Diffused Metal Oxide Semiconductor Field Effect Transistor) devices in high-voltage power devices are compatible with CMOS device processes due to the characteristic that current flows laterally on the surface of the device. Meanwhile, compared with traditional power devices, LDMOS devices are widely used due to their high breakdown voltage and low on-resistance.

[0003] The contradiction between the withstand voltage and the on-resistance in conventional LDMOS devices is prominent, and researchers have proposed various solutions including surface variable doping technology, light doping technology, and field plates. In addition to the above two performances, LDMOS devices also need to meet other device performance requirements, such as low leakage and stable threshold voltage. The LDMOS devices formed by the prior art are difficult to meet the above performance requirements at the same time, and need to be further improved. SUMMARY

[0004] The technical problem solved by the present application is to provide a semiconductor structure and a forming method thereof, which can improve the performance of the semiconductor structure.

[0005] To solve the above technical problem, the technical solution of the present application provides a semiconductor structure, comprising: a substrate, the substrate comprising adjacent first and second regions; a gate layer on the substrate, part of the gate layer being located on the first region, and another part of the gate layer also being located on the second region; a first well region in the first region; a second well region in the second region, the conductivity type of the second well region being different from that of the first well region; a first doped region having first doped ions in the first well region, the conductivity type of the first doped region being the same as that of the first well region; a source in the first well region on both sides of the gate layer and a drain in the second well region, the conductivity type of the source and the drain being the same as that of the first well region, and the source also being located in the first doped region.

[0006] Optionally, the first doped ions include P-type ions or N-type ions.

[0007] Optionally, the first doped region is also doped with carbon ions or fluorine ions.

[0008] Optionally, the gate layer sidewall surface has a side wall.

[0009] Optionally, the material of the side wall comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride or silicon carbon oxynitride.

[0010] Optionally, further comprising: an isolation structure in the second well region, the isolation structure is between the drain and the gate layer and is partially covered by the gate layer.

[0011] Optionally, the material of the isolation structure comprises silicon oxide.

[0012] Correspondingly, the technical scheme of the present application further provides a forming method of a semiconductor structure, comprising: providing a substrate, the substrate comprises adjacent first and second regions; forming a gate layer on the substrate, part of the gate layer is on the first region and another part of the gate layer is also on the second region; forming a first well region in the first region; forming a second well region in the second region, the second well region has a different conductivity type from the first well region; doping a first doping ion in the first well region to form a first doping region with part of the gate layer as a mask, the first doping region has the same conductivity type as the first well region; forming a source and a drain in the first well region and the second well region respectively on both sides of the gate layer, the source and the drain have the same conductivity type as the first well region, and the source is also in the first doping region.

[0013] Optionally, the first doping ion comprises P-type ion or N-type ion.

[0014] Optionally, the first doping ion further comprises carbon ion or fluorine ion; the carbon ion doping parameter comprises: a concentration range of 2E19 per cubic centimeter to 1E20 per cubic centimeter, an energy range of 5 kiloelectron-volt to 50 kiloelectron-volt, and a depth range of 20 nanometer to 300 nanometer; the fluorine ion doping parameter comprises: a concentration range of 5E19 per cubic centimeter to 5E20 per cubic centimeter, an energy range of 10 kiloelectron-volt to 60 kiloelectron-volt, and a depth range of 20 nanometer to 300 nanometer.

[0015] Optionally, the forming method of the first doping region comprises: forming a first mask layer on the surface of the second region and part of the surface of the gate layer; forming a first doping region with the first mask layer as a mask; after forming the first doping region, the first mask layer is removed.

[0016] Optionally, the material of the first mask layer comprises photoresist.

[0017] Optionally, the gate layer is formed after the first well region and the second well region are formed.

[0018] Optionally, the forming method of the first well region and the second well region comprises: covering the surface of the second region to form a second mask layer; using the second mask layer as a mask, implanting second dopant ions into the first region to form the first well region; removing the second mask layer after forming the first well region; covering the surface of the first region to form a third mask layer; using the third mask layer as a mask, implanting third dopant ions into the second region to form the second well region; removing the third mask layer after forming the second well region.

[0019] Optionally, the materials of the second mask layer and the third mask layer comprise photoresist.

[0020] Optionally, before forming the first well region and the second well region, the gate layer is formed; the forming method of the first well region and the second well region further comprises: the second mask layer also covers part of the gate layer; and the third mask layer also covers part of the gate layer.

[0021] Optionally, the method further comprises: before forming the source and the drain, forming a side wall on the sidewall surface of the gate layer.

[0022] Optionally, the material of the side wall comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride.

[0023] Optionally, the method further comprises: before forming the source and the drain, forming an isolation structure in the second well region, the isolation structure is located between the drain and the gate layer, and is partially covered by the gate layer.

[0024] Optionally, the material of the isolation structure comprises silicon oxide.

[0025] Compared with the prior art, the technical scheme of the embodiment of the present application has the following beneficial effects:

[0026] The structure of the semiconductor device provided by the technical scheme of the present application is that the first doped region is located in the first well region, the conductive type of the first doped region is the same as that of the first well region, the source is located in the first well region, and the drain is located in the second well region, the conductive type of the source and the drain is the same as that of the first well region, and the source is also located in the first doped region, and the first doped region is used to adjust the threshold voltage and the breakdown voltage characteristics of the device.

[0027] Further, the first doped region ions further comprise carbon ions or fluorine ions, due to the blocking effect of the carbon ions or fluorine ions on the dopant ions, the diffusion of the source dopant ions to the channel can be blocked, the concentration of the dopant ions in the channel is kept stable, the threshold voltage of the device is improved, and the breakdown voltage and other performances of the device are improved.

[0028] The method for forming a semiconductor structure in the technical solution of the present application forms a gate layer on the substrate, part of the gate layer is located on the first region, and another part of the gate layer is also located on the second region, forms a first well region in the first region, forms a second well region in the second region, the second well region has a different conductive type from the first well region, and part of the gate layer is used as a mask to dope a first doping ion in the first well region to form a first doping region, the first doping region has the same conductive type as the first well region, and the first doping region is formed by doping with part of the gate layer as a mask, which avoids the case that the doping concentration at the interface between the first region and the second region is difficult to control caused by directly doping in the first region, increases the concentration of the source end and the height of the potential barrier, effectively suppresses the barrier reduction effect, and improves the threshold voltage and the breakdown voltage of the device.

[0029] Further, the first well region and the second well region are formed with part of the gate layer as a mask, the interface between the N well region and the P well region formed by the method is indirectly formed by diffusion of the dopant, unlike the interface directly formed by injecting different conductive type doping ions on both sides of the interface, which does not cause the channel length and the channel dopant concentration to be different from the target value due to misalignment of the doping position, thereby affecting the threshold voltage, the breakdown voltage and other electrical properties of the device, and improving the effectiveness of the device. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figures 1 to 2 is a cross-sectional schematic diagram of a semiconductor structure formation process;

[0031] Figures 3 to 8 is a cross-sectional structure schematic diagram corresponding to each step in the semiconductor structure formation method of an embodiment of the present application;

[0032] Figures 9 to 14 is a cross-sectional structure schematic diagram corresponding to each step in the semiconductor structure formation method of another embodiment of the present application. DETAILED DESCRIPTION

[0033] As described in the background, the performance of the semiconductor structure formed by using the existing lateral double diffusion metal oxide semiconductor field effect transistor needs to be improved. Now a semiconductor structure is described and analyzed.

[0034] Figure 1 is a cross-sectional structure schematic diagram of a semiconductor structure.

[0035] Please refer to Figure 1A substrate 100 is provided, which includes a base 101, a field oxide region 102 is formed in the substrate 100; a first photoresist layer (not shown) is formed on the surface of the field oxide region 102 and part of the surface of the substrate 100, N-type first doping ions are implanted into the substrate 100 to form a body region 103, after the formation of the body region 103, the first photoresist layer is removed; a second photoresist layer (not shown) is formed on the body region 103, P-type second doping ions are implanted into the substrate to form a drift region 104, the drift region 104 is adjacent to the body region 103, and the drift region 104 has the field oxide region 102 therein, after the formation of the drift region 104, the second photoresist layer is removed.

[0036] Please refer to Figure 2 A gate 105 is formed on the surface of the substrate 100, the gate 105 covers part of the body region 103, part of the drift region 104 and part of the field oxide region 102; a source 106 and a drain 107 are formed in the substrate 100 on both sides of the gate 105, the source 106 is located in the body region 103, and the drain 107 is located in the drift region 104 and is adjacent to the field oxide region 102.

[0037] The source and the drain form a channel, and the annealing step in the source and drain forming process will cause the doping ions to diffuse into the channel due to the thermal diffusion effect, which will change the doping ion concentration in the channel, and even cause the power line to pass from the drain to the source, which will reduce the potential barrier height of the source terminal and cause leakage and other problems. In addition, in the above method, during the formation of the body region 103 and the drift region 104, two photoetchings are required, and the N-type doping ions in the body region 103 will be implanted into the drift region 104, or the P-type doping ions in the drift region 104 will be implanted into the body region 103 due to the influence of the photoetching process, such as the overlay error between the two photoetchings. The doping concentration at the interface of the body region 103 and the drift region 104 will be affected, and the channel length of the device will also be non-uniform. The above two cases will make it difficult to predict the characteristics of the LDMOS device, i.e. the controllability of the device performance is poor, which may cause the breakdown voltage to decrease, the device to leak or the on-resistance to increase, etc.

[0038] To solve the technical problem, the application provides a semiconductor structure and a forming method thereof. Different from the method of directly doping a body region in the first region position, a first doping region is formed by doping a first doping ion in the first well region with part of the gate layer as a mask, and the first doping region has the same conductivity type as the first well region, the dopant in the first doping region diffuses to the second region to form a lateral diffusion gradient, which does not cause the uncontrolled channel doping concentration, and at the same time, the concentration of the source end is increased and the barrier height is increased, effectively inhibiting the barrier reduction effect, improving the threshold voltage of the device, and improving the breakdown voltage and other performances of the device.

[0039] To make the above-mentioned purposes, features and benefits of the application more obvious and easy to understand, the specific embodiments of the application will be described in detail below with reference to the drawings.

[0040] Figures 3 to 8 is a schematic diagram of the cross-sectional structure corresponding to each step in the forming method of the semiconductor structure of an embodiment of the application.

[0041] Please refer to Figure 3 , a substrate 200 is provided, which includes adjacent first and second regions A and B.

[0042] The substrate 200 further includes a base 201 and an isolation structure 202 located in the second region B. The isolation structure 202 serves as a field oxide region of an LDMOS device to improve the voltage withstand performance of the LDMOS device. In the embodiment, the forming method of the isolation structure 202 includes etching a groove in the substrate 200 and forming an isolation layer in the groove. The forming process of the isolation layer includes a high-density plasma chemical vapor deposition process, and the material of the isolation layer includes silicon oxide.

[0043] Subsequently, a gate layer is formed on the substrate 200, a first well region is formed in the first region A, a first mask layer is formed to cover the second region B and part of the gate layer, a first doping region is formed with the first mask layer as a mask, the first doping region has a first doping ion, a source is formed in the first doping region, a second well region and a drain are formed in the second region B, and a region in the first well region between the source and the drain and below the gate layer forms a channel.

[0044] Please refer to Figure 4 , a gate layer 203 is formed on the substrate 200, part of the gate layer 203 is located on the first region A, and another part of the gate layer 203 is also located on the second region B.

[0045] The material of the gate layer 203 includes silicon or metal. In this embodiment, the material of the gate layer 203 is polysilicon. In other embodiments, the material of the gate layer includes silicon nitride, silicon carbide, amorphous silicon, polysilicon or monocrystalline silicon, etc.

[0046] The forming method of the gate layer 203 includes: forming a gate material layer on the substrate 200, forming a patterned layer on part of the gate material layer, etching the gate material layer until the surface of the substrate 200 is exposed, and forming the gate layer 203.

[0047] In this embodiment, the gate layer 203 is also partially located on the isolation structure 202.

[0048] Please refer to Figure 5 The first well region 205 is formed in the first area A by using part of the gate layer 203 as a mask.

[0049] The forming method of the first well region 205 includes: forming a second mask layer 204 covering the second area B and part of the surface of the gate layer 203; implanting second doping ions in the first area A by using the second mask layer 204 as a mask, to form the first well region 205; and removing the second mask layer 204 after forming the first well region 205.

[0050] The material of the second mask layer 204 includes photoresist.

[0051] The second doping ions include P-type ions or N-type ions. In this embodiment, the conductivity type of the first well region is P-type, and the second doping ions are boron ions, with a doping concentration of 1E18 per cubic centimeter to 1E19 per cubic centimeter.

[0052] Please refer to Figure 6 The second well region 207 is formed in the second area B by using part of the gate layer 203 as a mask, and the conductivity type of the second well region 207 is different from that of the first well region 205.

[0053] The method of the second well region 207 includes: forming a third mask layer 206 covering the first area A and part of the surface of the gate layer 203; implanting third doping ions in the second area B by using the third mask layer 206 as a mask, to form the second well region 207; and removing the third mask layer 206 after forming the second well region 207.

[0054] The material of the third mask layer 206 includes photoresist.

[0055] The third doping ions include P-type ions or N-type ions. The second well region 207 is used as a drift region of the LDMOS device, has a higher resistance, and can bear a higher voltage. Therefore, the second well region is doped with ions at a lower concentration. In this embodiment, the second well region 207 is of N type, and the third doping ions are phosphorus ions, which have a doping concentration of 1E18 per cubic centimeter to 1E20 per cubic centimeter.

[0056] In this embodiment, the first well region 205 is formed first, and then the second well region 207 is formed. In other embodiments, the second well region is formed first, and then the first well region is formed.

[0057] In this embodiment, the first well region 205 is formed in the first region A and the second well region 207 is formed in the second region B by using part of the gate layer 203 as a mask. In other embodiments, the first well region and the second well region are formed before the gate layer is formed; a second mask layer is formed on the surface of the second region B, and the first well region is formed by using the second mask layer as a mask; a third mask layer is formed on the surface of the first region A, and the second well region is formed by using the third mask layer as a mask.

[0058] Since the first well region and the second well region have different conductive types of doping ions, the first well region and the second well region form a PN junction. In the method of forming the first well region and the second well region by doping ions on the surfaces of the first region A and the second region B, respectively, by using photolithography technology, the position of the PN junction is determined by the positions of the two patterned layers. Since the patterned layers are affected by photolithography technology, in the process of pattern conversion, there may be a problem of misalignment of the doping position, such as partial overlap of the positions of the two patterned layers, or the relative positions of the gate layer and the target position are inconsistent, etc., thereby causing the channel length, channel dopant concentration, etc. of the device formed subsequently to be different from the target value, and further causing the performance of the threshold voltage, breakdown voltage, etc. of the device formed to be unstable. In this embodiment, the first well region and the second well region are formed by using part of the gate layer as a mask, and after the second doping ions and the third doping ions are implanted, the PN junction is formed by diffusion of the concentration downward of the gate layer, and the PN junction is indirectly formed by diffusion of the dopant, and is not directly affected by patterning. The PN junction formed by the first well region and the second well region can accurately control the position of the PN junction by the doping parameters of the second doping ions and the third doping ions, such as ion concentration, ion energy, implantation angle, etc. Therefore, the instability of the device performance caused by misalignment of the doping position is avoided, thereby improving the effectiveness of the device.

[0059] Please refer to Figure 7Part of the gate layer 203 is used as a mask to dope the first doping ions in the first well region 205 to form a first doping region 209, which has the same conductivity type as the first well region 205.

[0060] The first doping ions include P-type ions or N-type ions. The doping parameters of the N-type ions include a concentration range of 5E17 per cubic centimeter to 5E18 per cubic centimeter, an energy range of 30 kiloelectron-volts to 130 kiloelectron-volts, and a depth range of 100 nanometers to 800 nanometers. The doping parameters of the P-type ions include a concentration range of 5E17 per cubic centimeter to 5E18 per cubic centimeter, an energy range of 15 kiloelectron-volts to 80 kiloelectron-volts, and a depth range of 100 nanometers to 800 nanometers. In this embodiment, the first doping region has a P-type conductivity, and the first doping ions are boron ions, which have a concentration of 1E18 per cubic centimeter, an energy of 50 kiloelectron-volts, and a depth of 450 nanometers.

[0061] The first doping region 209 is formed by the following steps: forming a first mask layer 208 on the surface of the second region B and part of the surface of the gate layer 203; using the first mask layer 208 as a mask to form the first doping region 209; and removing the first mask layer 208 after forming the first doping region 209.

[0062] The first doping region 209 increases the concentration near the source and the height of the potential barrier, effectively inhibits the barrier reduction effect, and improves the threshold voltage of the device. Meanwhile, the dopants in the first doping region 209 diffuse into the second well region 207 to form a lateral diffusion gradient. The doping ions in the first doping region 209 have a different conductivity type from the doping ions in the second well region 207. The PN junction formed by the diffusion of the ions in the first doping region 209 and the second well region 207 does not directly depend on the positions of the first mask layer and the second mask layer, and can be accurately controlled by adjusting the doping parameters of the first doping ions and the third doping ions, such as ion concentration, ion energy, and injection angle. Therefore, the first doping region 209 is less affected by the patterned layer (the first mask layer and the second mask layer) formed by the photolithography technology. In addition to improving the threshold voltage of the device, a stable channel doping concentration is obtained, which effectively improves the breakdown voltage and other performances of the device.

[0063] The material of the first mask layer 208 includes a photoresist.

[0064] The first doping ions further include carbon ions or fluorine ions; the carbon ion doping parameters include: a concentration range of 2E19 per cubic centimeter to 1E20 per cubic centimeter, an energy range of 5 kiloelectron-volts to 50 kiloelectron-volts, and a depth range of 20 nanometers to 300 nanometers; and the fluorine ion doping parameters include: a concentration range of 5E19 per cubic centimeter to 5E20 per cubic centimeter, an energy range of 10 kiloelectron-volts to 60 kiloelectron-volts, and a depth range of 20 nanometers to 300 nanometers. In this embodiment, the first doping region is of a P type, the first doping ions are BF2 ions and C ions, the doping concentration of the BF2 ions is 1E20 per cubic centimeter, and the doping concentration of the C ions is 5E19 per cubic centimeter. Due to the blocking effect of the carbon ions or fluorine ions on the dopant ions, the diffusion of the source doping ions to the channel can be blocked, the concentration of the doping ions in the channel is kept stable, and the threshold voltage of the device and the breakdown voltage of the device are improved.

[0065] Please refer to Figure 8 The source 210 and the drain 211 are formed in the first well region 205 and the second well region 207, respectively, on both sides of the gate layer 203, the source 210 and the drain 211 are of the same conductivity type as the first well region 205, and the source 210 is also located in the first doping region 209.

[0066] In this embodiment, the method for forming the source 210 and the drain 211 includes: taking the side wall 212 as a mask, implanting N-type or P-type ions in the substrate 200 through self-alignment, forming the source 210 in the first well region 205, and forming the drain 211 in the second well region 207.

[0067] The doping ions in the source 210 and the drain 211 are N-type or P-type ions. In this embodiment, the source 210 and the drain 211 are of an N type, and the doping ions therein are phosphorus ions.

[0068] In this embodiment, the method for forming the source 210 and the drain 211 includes: taking the side wall 212 as a mask, implanting N-type or P-type ions in the substrate 200 through self-alignment, forming the source 210 in the first well region 205, and forming the drain 211 in the second well region 207.

[0069] The isolation structure 202 is located between the drain 211 and the gate layer 203 and is partially covered by the gate layer 203.

[0070] Correspondingly, the technical scheme of the present application further provides an embodiment of a semiconductor structure formed by the above-mentioned forming method, please continue to refer to Figure 8, including: a substrate 200, the substrate 200 including adjacent first region A and second region B; a gate layer 203 on the substrate 200, part of the gate layer 203 on the first region A, and another part of the gate layer 203 on the second region B; a first well region 205 in the first region A; a second well region 207 in the second region B, the second well region 207 having a different conductivity type from the first well region 205; a first doped region 209 having first doped ions in the first well region 205, the first doped region 209 having the same conductivity type as the first well region 205; a source 210 in the first well region 205 and a drain 211 in the second well region 207 on both sides of the gate layer 203, the source 210 and the drain 211 having the same conductivity type as the first well region 205, the source 210 also in the first doped region 209.

[0071] The first doped ions include P-type ions or N-type ions.

[0072] The first doped region 209 is also doped with carbon ions or fluorine ions.

[0073] The gate layer 203 sidewall surface has a side wall 212.

[0074] The material of the side wall 212 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride.

[0075] The semiconductor structure further includes: an isolation structure 202 in the second well region 207, the isolation structure 202 between the drain 211 and the gate layer 203, and part of the isolation structure 202 covered by the gate layer 203.

[0076] The material of the isolation structure 202 includes silicon oxide.

[0077] Figures 9 to 14 is a corresponding cross-sectional structure schematic diagram of each step in another embodiment of the semiconductor structure forming method of the present application.

[0078] Please refer to Figure 9 , a substrate 300 is provided, the substrate 300 including adjacent first region A and second region B.

[0079] The substrate 300 further comprises a base 301 and an isolation structure 302 located in the second region B. The isolation structure 302 serves as a field oxide region of the LDMOS device to improve the voltage resistance performance of the LDMOS device. In the embodiment, the isolation structure 302 is formed by etching a groove in the substrate 300 and forming an isolation layer in the groove. The isolation layer is formed by a high-density plasma chemical vapor deposition process, and the material of the isolation layer comprises silicon oxide.

[0080] Subsequently, a gate layer is formed on the substrate 300, a first well region is formed in the first region A, a first mask layer is formed to cover the second region B and part of the gate layer, a first doped region is formed by taking the first mask layer as a mask, the first doped region has first doped ions, a source is formed in the first doped region, a second well region and a drain are formed in the second region B, and a channel is formed in the first well region between the source and the drain and below the gate layer.

[0081] Please refer to Figure 10 A first well region 304 is formed in the first region A.

[0082] The first well region 304 is formed by covering the surface of the second region B with a second mask layer 303, doping second doped ions in the first region A to form the first well region 304 by taking the second mask layer 303 as a mask, and removing the second mask layer 304 after forming the first well region 304.

[0083] The material of the second mask layer 303 comprises photoresist.

[0084] The second doped ions comprise P-type ions or N-type ions. In the embodiment, the first well region is of P-type, and the second doped ions are boron ions, and the doping concentration of the boron ions is 1E18 per cubic centimeter to 1E19 per cubic centimeter.

[0085] Please refer to Figure 11 A second well region 306 is formed in the second region B, and the second well region 306 is of a different conductivity type from the first well region 304.

[0086] The second well region 306 is formed by covering the surface of the first region A with a third mask layer 305, doping third doped ions in the second region B to form the second well region 306 by taking the third mask layer 305 as a mask, and removing the third mask layer 305 after forming the second well region 306.

[0087] The material of the third mask layer 305 comprises photoresist.

[0088] The third doping ions include P-type ions or N-type ions. The second well region 306 is used as a drift region of the LDMOS device, has higher resistance, and can bear higher voltage, so the second well region is doped with lower concentration of ions. In this embodiment, the second well region 306 is of N-type, and the third doping ions are phosphorus ions with a doping concentration of 1E18 per cubic centimeter to 1E20 per cubic centimeter.

[0089] In this embodiment, the first well region 304 is formed first, and then the second well region 305 is formed. In other embodiments, the second well region is formed first, and then the first well region is formed.

[0090] Please refer to Figure 12 A gate layer 307 is formed on the substrate 300, part of the gate layer 307 is located on the first region A, and another part of the gate layer 307 is also located on the second region B.

[0091] The material of the gate layer 307 includes silicon or metal. In this embodiment, the material of the gate layer 307 is polysilicon. In other embodiments, the material of the gate layer includes silicon nitride, silicon carbide, amorphous silicon, polysilicon, or single crystal silicon, etc.

[0092] The forming method of the gate layer 307 includes: forming a gate material layer on the substrate 300, forming a patterned layer on part of the gate material layer, and etching the gate material layer with the patterned layer as a mask until the surface of the substrate 300 is exposed, to form the gate layer 307.

[0093] In this embodiment, part of the gate layer 307 is also located on the isolation structure 302.

[0094] Please refer to Figure 13 A first doping region 309 is formed by doping first doping ions in the first well region 304 with part of the gate layer 307 as a mask, and the first doping region 309 is of the same conductivity type as the first well region 304.

[0095] The first doping ions include P-type ions or N-type ions; the doping parameters of N-type ions include: a concentration range of 5E17 per cubic centimeter to 5E18 per cubic centimeter, an energy range of 30 kiloelectron-volt to 130 kiloelectron-volt, and a depth range of 100 nanometer to 800 nanometer; the doping parameters of P-type ions include: a concentration range of 5E17 per cubic centimeter to 5E18 per cubic centimeter, an energy range of 15 kiloelectron-volt to 80 kiloelectron-volt, and a depth range of 100 nanometer to 800 nanometer. In this embodiment, the first doping region is of P-type, and the first doping ions are boron ions, and the doping parameters of the first doping ions include: a concentration of 1E18 per cubic centimeter, an energy of 50 kiloelectron-volt, and a depth of 450 nanometer.

[0096] The first doping region 309 is formed by the following steps: forming a first mask layer 308 on the surface of the second region B and part of the surface of the gate layer 307; forming the first doping region 309 by taking the first mask layer 308 as a mask; and removing the first mask layer 308 after forming the first doping region 309. The first doping region 309 increases the concentration near the source and increases the height of the potential barrier, effectively inhibits the barrier reduction effect, and improves the threshold voltage of the device. Meanwhile, the dopants in the first doping region 309 diffuse to the second well region 306 to form a lateral diffusion gradient, the doping ions in the first doping region 309 and the doping ions in the second well region 306 are of different conductive types, the PN junction formed by the diffusion of the ions in the first doping region 309 and the second well region 306 does not directly depend on the positions of the first mask layer and the second mask layer, and the PN junction can be accurately controlled by adjusting the doping parameters of the first doping ions and the third doping ions, such as ion concentration, ion energy, and injection angle. Therefore, the patterning layer (the first mask layer and the second mask layer) formed by the photolithography technology has less influence, the threshold voltage of the device is improved, the channel doping concentration is stable, and the breakdown voltage and other performances of the device are effectively improved.

[0097] The material of the first mask layer 308 includes photoresist.

[0098] The first doping ions further include carbon ions or fluorine ions; the carbon ion doping parameters include: a concentration range of 2E19 per cubic centimeter to 1E20 per cubic centimeter, an energy range of 5 kiloelectron-volts to 50 kiloelectron-volts, and a depth range of 20 nanometers to 300 nanometers; and the fluorine ion doping parameters include: a concentration range of 5E19 per cubic centimeter to 5E20 per cubic centimeter, an energy range of 10 kiloelectron-volts to 60 kiloelectron-volts, and a depth range of 20 nanometers to 300 nanometers. In this embodiment, the first doping region is of a P type, the first doping ions are BF2 ions and C ions, the doping concentration of the BF2 ions is 1E20 per cubic centimeter, and the doping concentration of the C ions is 5E19 per cubic centimeter. Due to the blocking effect of the carbon ions or fluorine ions on the dopant ions, the diffusion of the source doping ions to the channel can be blocked, the concentration of the doping ions in the channel is kept stable, and the threshold voltage of the device and the breakdown voltage of the device are improved.

[0099] Please refer to Figure 14 The source 311 and the drain 312 are formed in the first well region 304 and the second well region 306, respectively, on both sides of the gate layer 307, the source 311 and the drain 312 are of the same conductivity type as the first well region 304, and the source 311 is also located in the first doping region 309.

[0100] In this embodiment, the method for forming the source 311 and the drain 312 includes: taking the side wall 310 as a mask, implanting N-type or P-type ions in the substrate 300 through self-alignment, forming the source 311 in the first well region 304, and forming the drain 312 in the second well region 306.

[0101] The doping ions in the source 311 and the drain 312 are N-type or P-type ions. In this embodiment, the source 311 and the drain 312 are of an N type, and the doping ions therein are phosphorus ions.

[0102] In this embodiment, the method for forming the source 311 and the drain 312 includes: taking the side wall 310 as a mask, implanting N-type or P-type ions in the substrate 300 through self-alignment, forming the source 311 in the first well region 304, and forming the drain 312 in the second well region 306.

[0103] The isolation structure 302 is located between the drain 312 and the gate layer 307 and is partially covered by the gate layer 307.

[0104] Although the present application is disclosed as above, the present application is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be defined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure is an LDMOS device, comprising: Substrate, the substrate comprising adjacent first and second regions; A gate layer located on the substrate, wherein a portion of the gate layer is located on the first region and another portion of the gate layer is located on the second region; A first well region located within the first region, the first well region having a second doped ion; The second well region is located within the second region. The conductivity type of the second well region is different from that of the first well region. The second well region has a third doped ion. The first well region and the second well region are formed with part of the gate layer as a mask. After the second doped ion and the third doped ion are implanted, they diffuse downwards from the gate layer due to concentration diffusion to form a PN interface. A first doped region containing a first doped ion is located within the first well region. The conductivity type of the first doped region is the same as that of the first well region. The dopant in the first doped region diffuses into the second well region to form a lateral diffusion gradient. The source and drain are located in the first well region on both sides of the gate layer, and the conductivity type of the source and drain is the same as that of the first well region. The source is also located in the first doped region.

2. The semiconductor structure as described in claim 1, characterized in that, The first doped ion includes a P-type ion or an N-type ion.

3. The semiconductor structure as described in claim 1, characterized in that, The first doped region is also doped with carbon ions or fluorine ions.

4. The semiconductor structure as described in claim 1, characterized in that, The sidewall surface of the gate layer has sidewalls.

5. The semiconductor structure as described in claim 4, characterized in that, The sidewall material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, or silicon carbon oxynitride.

6. The semiconductor structure as described in claim 1, characterized in that, Also includes: An isolation structure located within the second well region, the isolation structure being situated between the drain and the gate layer, and partially covered by the gate layer.

7. The semiconductor structure as described in claim 6, characterized in that, The material of the isolation structure includes silicon dioxide.

8. A method for forming a semiconductor structure, characterized in that, The semiconductor structure is an LDMOS device, comprising: A substrate is provided, the substrate comprising an adjacent first region and a second region; A gate layer is formed on the substrate, with a portion of the gate layer located on the first region and another portion of the gate layer located on the second region; A second mask layer is formed by covering the surface of the second region and a portion of the gate layer; Using the second mask layer and part of the gate layer as a mask, second doped ions are doped into the first region to form a first well region. A third mask layer is formed by covering the surface of the first region and part of the gate layer; Using the third mask layer and part of the gate layer as a mask, third doped ions are doped into the second region to form a second well region. The conductivity type of the second well region is different from that of the first well region. Using a portion of the gate layer as a mask, first dopant ions are doped into the first well region to form a first doped region. The conductivity type of the first doped region is the same as that of the first well region, so that the dopant in the first doped region diffuses into the second well region to form a lateral diffusion gradient. A source and a drain are formed in a first well region and a second well region on both sides of the gate layer, respectively. The conductivity type of the source and the drain is the same as that of the first well region. The source is also located in the first doped region.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The first doped ion includes a p-type ion or an n-type ion.

10. The method for forming a semiconductor structure as described in claim 8, characterized in that, The first doped ion further includes carbon ions or fluorine ions; the carbon ion doping parameters include: a concentration range of 2E19 to 1E20 per cubic centimeter, an energy range of 5 kiloelectron volts to 50 kiloelectron volts, and a depth range of 20 nanometers to 300 nanometers; the fluorine ion doping parameters include: a concentration range of 5E19 to 5E20 per cubic centimeter, an energy range of 10 kiloelectron volts to 60 kiloelectron volts, and a depth range of 20 nanometers to 300 nanometers.

11. The method for forming a semiconductor structure as described in claim 8, characterized in that, The method for forming the first doped region includes: forming a first mask layer on the surface of the second region and a portion of the gate layer surface; forming the first doped region using the first mask layer as a mask; and removing the first mask layer after forming the first doped region.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The material of the first mask layer includes photoresist.

13. The method for forming a semiconductor structure as described in claim 8, characterized in that, The method for forming the first well region and the second well region further includes: removing the second mask layer after forming the first well region; and removing the third mask layer after forming the second well region.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The materials of the second and third mask layers include photoresist.

15. The method for forming a semiconductor structure as described in claim 8, characterized in that, Also includes: Before forming the source and drain, a sidewall is formed on the sidewall surface of the gate layer.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The sidewall material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, or silicon carbon oxynitride.

17. The method for forming a semiconductor structure as described in claim 8, characterized in that, Also includes: Before forming the gate, an isolation structure is formed in the second well region, the isolation structure being located between the drain and the gate layer and partially covered by the gate layer.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The material of the isolation structure includes silicon dioxide.

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