Semiconductor packaging

Abstract

A device (2) is formed on the main surface of a semiconductor substrate (1). A passivation film (5) covers the main surface. A metal pattern (6) is formed on the passivation film (5) in a manner surrounding the device (2). A sealing metal layer (7) having a corner (10) when viewed from above is formed on the metal pattern (6). A cover (8) is joined to the metal pattern (6) via the sealing metal layer (7) to vacuum-seal the device (2). A dummy wiring (11) that is softer than the metal pattern (6) and is not electrically connected to the device (2) is formed at least between the outer portion of the corner of the sealing metal layer (7) and the semiconductor substrate (1).

Description

Technical Field

[0001] The present invention relates to semiconductor packaging. Background Art

[0002] There has been proposed a semiconductor package in which a lid is bonded to a semiconductor substrate via a sealing metal layer to vacuum-seal a device formed on a semiconductor substrate (for example, see Patent Document 1).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2010-261806

[0004] The semiconductor substrate is made of Si or the like, and its physical properties such as linear expansion coefficient and Young's modulus are different from those of the sealing metal layer. Therefore, there is a problem that stress may cause the semiconductor substrate to break, thereby reducing heat cycle resistance. Summary of the invention

[0005] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor package capable of improving heat cycle resistance.

[0006] The semiconductor package involved in the present invention is characterized in that it comprises: a semiconductor substrate; a device formed on the main surface of the above-mentioned semiconductor substrate; a passivation film covering the above-mentioned main surface; a metal pattern formed on the above-mentioned passivation film in a manner of surrounding the above-mentioned device; a sealing metal layer formed on the above-mentioned metal pattern and having a corner when viewed from above; a cover joined to the above-mentioned metal pattern via the above-mentioned sealing metal layer to vacuum-seal the above-mentioned device; and a dummy wiring formed at least between the outer part of the above-mentioned corner of the above-mentioned sealing metal layer and the above-mentioned semiconductor substrate, which is softer than the above-mentioned metal pattern and is not electrically connected to the above-mentioned device.

[0007] In the present invention, a soft dummy wiring is formed at least between the outer portion of the corner of the sealing metal layer and the semiconductor substrate. Since the dummy wiring can suppress the stress transmission from the sealing metal layer to the semiconductor substrate, the semiconductor substrate can be prevented from breaking and the heat cycle resistance can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a plan view showing the semiconductor package according to the first embodiment.

[0009] Figure 2 It is along Figure 1 A cross-sectional view of the I-II cut.

[0010] Figure 3 It is along Figure 1 A cross-sectional view of the III-IV cut.

[0011] Figure 4It is a cross-sectional view showing a semiconductor package according to the second embodiment.

[0012] Figure 5 It is a top view showing a semiconductor package according to the third embodiment.

[0013] Figure 6 It is along Figure 5 A cross-sectional view taken along the V-VI line.

[0014] Figure 7 It is a cross-sectional view showing a semiconductor package according to a fourth embodiment.

[0015] Figure 8 It is a top view showing a semiconductor package according to the fifth embodiment.

[0016] Fig. 9 Yes Figure 8 A cross-sectional view obtained by enlarging the outer periphery of the sealing metal layer crossed by the wiring.

[0017] Fig.10 It is a figure which shows the rectangular model used for the simulation of stress.

[0018] Fig.11 It is a graph showing the relationship between the W / H ratio and the stress vector angle.

[0019] Fig.12 Yes Fig.11 The figure is obtained by enlarging the local part of .

[0020] Fig.13 It is a graph showing the relationship between the W / H ratio and the stress ratio.

[0021] Fig.14 Yes Fig.13 The figure is obtained by enlarging the local part of .

[0022] Fig.15 It is a top view showing a semiconductor package according to the sixth embodiment.

[0023] Fig.16 It is a top view showing a semiconductor package according to a seventh embodiment.

[0024] Fig.17 Yes Fig.16 A stereogram obtained by enlarging area A.

[0025] Fig.18 It is a top view showing a semiconductor package according to the eighth embodiment.

[0026] Fig.19 It is along Fig.18 A cross-sectional view of the section VII-VIII. DETAILED DESCRIPTION

[0027] The semiconductor package according to the embodiment will be described with reference to the drawings. The same reference numerals are given to the same or corresponding components, and duplicate descriptions may be omitted.

[0028] Implementation Method 1

[0029] Figure 1 It is a plan view showing the semiconductor package according to the first embodiment. Figure 2 It is along Figure 1 A cross-sectional view of the I-II cut. Figure 3 It is along Figure 1 sectional view cut along III-IV. Device 2, wiring 3 and pad 4 are formed on the main surface of semiconductor substrate 1, for example, made of Si. Device 2 includes, for example, sensors such as imaging elements, circuits, etc. The pad 4 is connected to the device 2 via wiring 3. A passivation film 5 such as SiN is formed on the semiconductor substrate 1 in a manner covering the device 2, wiring 3 and pad 4. An opening is formed in the passivation film 5 above the pad 4 to expose the central portion of the upper surface of the pad 4. The passivation film 5 on the device 2 may also be processed locally or as a whole. For example, in the case where the device 2 includes an imaging element, an internal lens may be realized by performing local processing, or a thin film may be made to increase the transmittance.

[0030] The metal pattern 6 is formed on the passivation film 5 in a manner surrounding the device 2 when viewed from above. The sealing metal layer 7 is formed on the metal pattern 6. A metal pattern 9 is formed on the lower surface of the cover 8 at a position corresponding to the metal pattern 6 on the semiconductor substrate 1 side. The metal pattern 9 of the cover 8 is bonded to the metal pattern 6 on the semiconductor substrate 1 side via the sealing metal layer 7, and the device 2 is vacuum-sealed. For example, the sealing metal layer 7 and the metal pattern 9 of the cover 8 are overlapped on the metal pattern 6, placed in a vacuum heating device to form a vacuum state, and the sealing metal layer 7 is heated and melted to be bonded.

[0031] The hollow portion surrounded by the semiconductor substrate 1, the cover 8 and the sealing metal layer 7 is kept in a vacuum state. However, if the lateral width of the sealing metal layer 7 is reduced, the possibility of vacuum damage caused by the gap generated in the sealing metal layer 7 and the stress generated by the difference between the internal pressure and the external pressure becomes higher. Therefore, it is necessary to keep the lateral width of the sealing metal layer 7 above a certain value. The pad 4 is formed on the outside of the hollow portion and is electrically connected to a wiring substrate (not shown). In addition, in order to maintain the internal vacuum, a gas adsorbent (getter) or the like may also be provided in the hollow portion. In addition, in order to improve the transmittance of infrared rays, an anti-reflection film (AR) may also be provided on the cover 8. In addition, the cover 8 may also be etched to ensure a large vacuum holding volume, thereby reducing the influence of the deterioration of the vacuum degree caused by the release of gas from the surface of the semiconductor substrate 1. In addition, in the case where the device 2 includes a camera element, by providing a concave-convex structure below the detection wavelength on the cover 8, the refractive index of the atmosphere, the cover 8 and the vacuum portion is modulated in stages in appearance, and the transmittance can be improved as a result.

[0032] The metal patterns 6 and 9 are, for example, a stacked body formed by stacking Ti, Cu, Ni, Au, and Pd in ​​any order, and are formed by sputtering or plating. The material or the forming method is not limited thereto and can be appropriately selected. The sealing metal layer 7 is, for example, composed of a solder such as SnAgCu or AuSn. The material of the sealing metal layer 7 is not limited thereto, and a material suitable for bonding with the metal patterns 6 and 9 can be appropriately selected.

[0033] The metal patterns 6, 9 and the sealing metal layer 7 are in a square frame shape when viewed from above in a direction perpendicular to the main surface of the semiconductor substrate 1. Therefore, the sealing metal layer 7 has four corners 10 when viewed from above. A dummy wiring 11 that is not electrically connected to the device 2 is formed between the outer portion of the corner 10 of the sealing metal layer 7 and the semiconductor substrate 1. The wiring 3 and the dummy wiring 11 are made of, for example, AlSi, AlSiCu, etc., and have a lower elastic modulus than the metal patterns 6, 9, that is, they are softer than the metal patterns 6, 9.

[0034] Stress is generated due to the difference in physical properties such as the linear expansion coefficient or Young's modulus between the material of the semiconductor substrate 1 and the material of the sealing metal layer 7. The stress is particularly concentrated on the outer part of the corner 10 of the sealing metal layer 7. As long as the shape of the sealing metal layer 7 is not formed into a completely circular shape, the concentration of stress cannot be eliminated. For example, even if the corners of the square frame shape of the sealing metal layer 7 are removed or rounded, the concentration of stress cannot be completely eliminated. Therefore, in this embodiment, a soft dummy wiring 11 is formed at least between the outer part of the corner 10 of the sealing metal layer 7 and the semiconductor substrate 1. Since the stress transfer from the sealing metal layer 7 to the semiconductor substrate 1 can be suppressed by the dummy wiring 11, the fracture of the semiconductor substrate 1 can be prevented and the heat cycle resistance can be improved. Here, it is possible in principle to suppress stress transfer by thickly stacking soft metals such as Al as metal patterns 6 and 9. However, in this case, the interlayer stress difference between the generated metal patterns 6 and 9 is large, and the possibility of other mode defects such as interlayer peeling or interlayer fracture becomes high, so it is not realistic.

[0035] The wiring 3 bypasses the corner 10 of the sealing metal layer 7 to connect to the pad 4 and the device 2. By arranging the wiring 3 to avoid the corner 10 of the sealing metal layer 7 where stress concentrates, defects caused by disconnection of the wiring 3 can be prevented.

[0036] In addition, when the material of the cover 8 is Si, which is the same as the semiconductor substrate 1, since there is no difference in physical property values ​​such as the linear expansion coefficient between the cover 8 and the semiconductor substrate 1, it is sufficient to consider only the stress caused by the difference in physical property values ​​with the sealing metal layer 7. However, the material of the cover 8 is not limited to Si, and it can also be glass, Ge, etc. In this way, when the material of the semiconductor substrate 1 and the material of the cover 8 are different, since the stress increases due to the difference in physical property values ​​between the two, the stress transmission suppression by the dummy wiring 11 becomes particularly effective.

[0037] Implementation Method 2

[0038] Figure 4 2 is a cross-sectional view showing a semiconductor package according to Embodiment 2. In this embodiment, the dummy wiring 11 is formed on the semiconductor substrate 1 in the same layer as the wiring 3, and the thickness and material of the two are the same. In this case, since the dummy wiring 11 and the wiring 3 can be formed at the same time, there is no need to add a manufacturing process for the formation of the dummy wiring 11. In addition, the thickness of the passivation film 5 is generally set to 0.5 μm to several μm, which is very thin compared to the thickness of the sealing metal layer 7. Therefore, even with the structure of this embodiment, the stress transfer suppression effect of Embodiment 1 can be obtained. Other structures and effects are the same as those of Embodiment 1.

[0039] Implementation 3

[0040] Figure 5 It is a top view showing a semiconductor package according to the third embodiment. Figure 6 It is along Figure 5 The cross-sectional view cut at V-VI of FIG. The stress increases not only at the outer part of the corner 10 of the sealing metal layer 7, but also at the inner part. Therefore, in this embodiment, a dummy wiring 11 is also formed between the inner part of the corner 10 of the sealing metal layer 7 and the semiconductor substrate 1. Since the stress transfer from the sealing metal layer 7 to the semiconductor substrate 1 can be further suppressed by the dummy wiring 11, the heat cycle resistance can be further improved. The other structures and effects are the same as those in the first embodiment.

[0041] Implementation 4

[0042] Figure 7 : is a cross-sectional view of a semiconductor package according to Embodiment 4. If the cover 8 is broken due to stress, the vacuum degree inside the package is deteriorated. Therefore, in this embodiment, a dummy wiring 11 is also formed between the outer portion of the corner 10 of the sealing metal layer 7 and the cover 8. Since the stress transfer from the sealing metal layer 7 to the cover 8 can be suppressed by the dummy wiring 11, the stress resistance of the cover 8 can be enhanced and the reliability of the vacuum degree can be ensured. The other structures and effects are the same as those in Embodiment 1. In addition, a dummy wiring 11 can also be formed between the inner portion of the corner 10 of the sealing metal layer 7 and the cover 8.

[0043] Implementation method 5

[0044] Figure 8 1 is a top view showing a semiconductor package according to Embodiment 5. As in Embodiment 1, a dummy wiring 11 is formed between the sealing metal layer 7 and the semiconductor substrate 1. However, in this embodiment, the dummy wiring 11 is not only provided at the corner 10 of the sealing metal layer 7, but also provided along the outer periphery and the inner periphery. One side of the sealing metal layer 7, which is in a square frame shape when viewed from above, has a portion where the dummy wiring 11 is not provided. At this portion, the wiring 3 crosses the sealing metal layer 7 and connects the device 2 in the package to the external pad 4.

[0045] Fig. 9 Yes Figure 8 FIG. 1 is a cross-sectional view of an enlarged portion of the outer periphery of the sealing metal layer 7 intersected by the wiring. There is a region 12 where the wiring 3 and the dummy wiring 11 do not exist in the outer periphery and inner periphery of the sealing metal layer 7. In this region 12, stress is generated due to the difference in physical property values ​​between the semiconductor substrate 1 and the sealing metal layer 7. On the other hand, the area above the wiring 3 or the dummy wiring 11 becomes a stress relaxation region 13 for relaxing stress.

[0046] When the sealing metal layer 7 is regarded as a component macroscopically, the stress P generated in the sealing metal layer 7 is the vector sum of the stress Ph applied in the thickness direction and the stress Pw applied in the width direction of the sealing metal layer 7. If the width of the region 12 where the wiring 3 and the dummy wiring 11 do not exist is set to W, and the thickness of the sealing metal layer 7 is set to H, then the stress Ph and H are 3 ×W, stress Pw is proportional to W 3 Therefore, by reducing the width W of the region 12 , the stress can be reduced.

[0047] In addition, the semiconductor substrate 1 is a Si wafer with a crystal plane orientation of (100), (110) or (111). In this case, the semiconductor substrate 1 has a crystal structure having a cleavage plane in a direction of 45° to the direction perpendicular to the main surface. Therefore, the semiconductor substrate 1 is easy to break in a direction of 45° to the vertical direction. Therefore, if the stress vector is offset from the 45° direction, the breakage can be reduced. In addition, although the stress in the vertical direction causes surface peeling, since the peeling resistance of the substrate is generally greater than the fracture resistance, the stress in the vertical direction is hardly a problem.

[0048] Here, the effect of the stress relaxation region 13 is quantitatively shown. Fig.10 : is a diagram showing a rectangular model for stress simulation. The left figure shows the case without the wiring 3 as a stress relief layer, and the right figure shows the case with the wiring 3. The width of the region is 150μm, the thickness of the sealing metal layer 7 is 90μm, and the thickness of the wiring 3 is 0.8μm. Since the wiring 3 deforms following the stress of the sealing metal layer 7 and thus the deformation in the sealing metal layer 7 is relieved, the stress in the lateral direction can be reduced.

[0049] The simulation results are shown in the following table: Case 1 shows a case where there is no wiring 3. Case 2 shows a case where there is wiring 3 in the entire width direction. Case 3 shows a case where there is wiring 3 in a range of 20 μm in a width of 150 μm.

[0050] Stress on the upper surface of the passivation film Stress at the upper surface of the substrate CASE1 1143MPa 1143MPa CASE2 886MPa 405MPa CASE3 1125MPa 381MPa

[0051] It is found that in case 2 where the wiring 3 exists, stress is relaxed above and below the wiring 3 compared to case 1 where the wiring 3 does not exist. In case 3, since the stress difference between the upper and lower parts of the wiring 3 is large, there is a possibility that the wiring may be broken due to deformation.

[0052] In case 1 where wiring 3 does not exist, stress Ph1 in the thickness direction is 360 MPa, and stress Pw1 in the width direction is about 1050 MPa. Since the thickness of wiring 3 is very small compared with the width, even in case 2 where wiring 3 exists, stress Ph2 in the thickness direction is about 360 MPa, which is almost the same as case 1. On the other hand, stress Pw2 in the width direction is greatly reduced to 185 MPa. Therefore, in preventing the breakage of semiconductor substrate 1, it is not necessary to consider stress relaxation area 13 where wiring 3 or dummy wiring 11 exists, and it is only necessary to control the W / H ratio of area 12 where wiring 3 and dummy wiring 11 do not exist.

[0053] Fig.11 It is a graph showing the relationship between the W / H ratio and the stress vector angle. Fig.12 Yes Fig.11 The figure is obtained by partially enlarging the part. The stress vector angle represents the angle of the stress vector relative to the main surface of the semiconductor substrate 1. It can be seen that the stress vector angle can be set to 70° or more by W / H≤0.6. That is, the stress vector can be offset from the 45° direction that is easy to break. In addition, in the present embodiment, the example of Si wafers using crystal plane orientations (100), (110) or (111) is used, but substrates such as SiC wafers or GaN wafers with different crystal plane orientations, that is, cleavage planes that are not 45°, can also be used. Even in this case, the same effect can be obtained by offsetting the stress vector angle from the cleavage plane angle. Even in the case of using these substrates, as described above, the peeling resistance of the substrate is greater than the fracture resistance, so the stress in the vertical direction is hardly a problem. Therefore, in order to improve the crack resistance, it is preferred to keep the vector angle above 70°.

[0054] Fig.13 It is a graph showing the relationship between the W / H ratio and the stress ratio. Fig.14 Yes Fig.13 The stress ratio is the magnitude of the stress normalized by taking the case where the W / H ratio is 1 as a reference. It can be seen that by setting W / H ≤ 0.6, the stress can be reduced to near the lower limit.

[0055] Based on the above results, in the present embodiment, the width W of the region 12 where the wiring 3 and the dummy wiring 11 do not exist in the outer periphery and inner periphery of the sealing metal layer 7 is set to be less than 0.6 times the thickness H of the sealing metal layer 7 (W / H≤0.6). Thus, the fracture of the semiconductor substrate 1 can be reduced. In the case where there are multiple regions 12, it is preferred that all of them satisfy W / H≤0.6. However, it is also possible to set the dummy wiring 11 only at the point where the stress is particularly concentrated in a manner that satisfies the above relationship.

[0056] In practice, the thickness H of the sealing metal layer 7 is set to about 40 to 100 μm. It is very difficult to deposit a sealing metal layer 7 having a thickness greater than the above by evaporation, sputtering or drop coating, and the cost becomes high. Therefore, the width W of the region 12 needs to be set to 25 to 60 μm.

[0057] Implementation 6

[0058] Fig.15 1 is a top view showing a semiconductor package according to Embodiment 6. At the outer periphery and inner periphery of the sealing metal layer 7, the wiring 3 extends along the outer periphery or inner periphery of the sealing metal layer 7. Therefore, when the width is measured along the outer periphery or inner periphery of the sealing metal layer 7, the width of the wiring 3 at the outer periphery and inner periphery of the sealing metal layer 7 is greater than the width of the wiring 3 at the central portion of the sealing metal layer 7.

[0059] By expanding the width of the wiring 3 at the outer and inner peripheries of the sealing metal layer 7 where stress is concentrated, the disconnection of the wiring 3 that crosses the sealing metal layer 7 can be prevented. However, it is generally known that when the wiring 3 is arranged too coarsely, the stress difference between the semiconductor substrate 1 or the passivation film 5 causes sliding damage, which damages the reliability of the wiring. Therefore, the width of the wiring 3 is generally set to 100 μm or less. By implementing the countermeasures involved in this embodiment, the width of the wiring 3 at the central part of the sealing metal layer 7 can be reduced. As a result, sliding damage caused by the stress relationship between the wiring 3 and the passivation film 5 can be suppressed.

[0060] Implementation 7

[0061] Fig.16 It is a top view showing a semiconductor package according to a seventh embodiment. Fig.17 Yes Fig.16 The width of the region 12 where the plurality of wirings 3 do not exist has a first width W1 along the outer periphery or inner periphery of the sealing metal layer 7, and a second width W2 in a direction perpendicular to the outer periphery or inner periphery of the sealing metal layer 7. Both the first width W1 and the second width W2 are less than 0.6 times the thickness H of the sealing metal layer 7 (W1, W2 ≤ 0.6 × H). Thus, compared with the case where only the first width W1 is less than 0.6 times the thickness H of the sealing metal layer 7, stress can be relieved.

[0062] Implementation 8

[0063] Fig.18 1 is a plan view showing a semiconductor package according to Embodiment 8. The wiring 3 and the dummy wiring 11 are arranged parallel to each other along the outer periphery of the sealing metal layer 7 at the outer periphery of the sealing metal layer 7 . Fig.19 It is along Fig.18VII-VIII section view of the embodiment of the present invention. The arrow in the figure indicates the tensile stress vector. The stress vector is dispersed by the step difference structure of the wiring 3 and the dummy wiring 11 arranged in parallel, and the stress is relieved. Therefore, the breakage of the semiconductor substrate 1 can be prevented and the heat cycle resistance can be improved. In addition, since the wettability of the sealing metal layer 7 can be improved during heat melting, leakage between the hollow part and the outside can be suppressed. In addition, the sealing metal layer 7 can be prevented from overflowing during heat melting.

[0064] Furthermore, by setting the width of the wiring 3 and the dummy wiring 11 to 100 μm or less, it is possible to suppress sliding damage caused by the stress relationship between the wiring 3 or the dummy wiring 11 and the passivation film 5. Other structures and effects are the same as those of the fifth embodiment.

[0065] Description of Reference Numerals

[0066] 1…semiconductor substrate; 2…device; 3…wiring; 5…passivation film; 6…metal pattern; 7…sealing metal layer; 8…cover; 10…corner; 11…dummy wiring; 12…region.

Claims

1. A semiconductor package, characterized in that: have: Semiconductor substrates; A device formed on a main surface of the semiconductor substrate; a passivation film covering the main surface; A metal pattern is formed on the passivation film in a manner of surrounding the device; a sealing metal layer formed on the metal pattern and having a corner when viewed from above; a cover, bonded to the metal pattern via the sealing metal layer, to vacuum-seal the device; a dummy wiring, formed at least between an outer portion of the corner portion of the sealing metal layer and the semiconductor substrate, being softer than the metal pattern and not electrically connected to the device; as well as A wiring, formed on the main surface of the semiconductor substrate, extending below the sealing metal layer and electrically connected to the device; The dummy wiring does not intersect the wiring in a plan view.

2. The semiconductor package according to claim 1, wherein: The wiring is arranged so as to avoid the corner portion of the sealing metal layer.

3. The semiconductor package according to claim 1 or 2, characterized in that: The material of the semiconductor substrate and the material of the cover are different.

4. The semiconductor package according to claim 2, wherein: The dummy wiring is formed in the same layer as the wiring.

5. The semiconductor package according to claim 1 or 2, characterized in that: The dummy wiring is formed between an inner portion of the corner portion of the sealing metal layer and the semiconductor substrate.

6. The semiconductor package according to claim 1 or 2, characterized in that: The dummy wiring is formed between the outer portion of the corner portion of the sealing metal layer and the cover.

7. A semiconductor package, characterized in that: have: Semiconductor substrates; A device formed on a main surface of the semiconductor substrate; a plurality of wirings formed on the main surface of the semiconductor substrate; a passivation film covering the main surface and the plurality of wirings; A metal pattern is formed on the passivation film in a manner of surrounding the device; A sealing metal layer, disposed on the metal pattern; as well as A cover is bonded to the metal pattern via the sealing metal layer to vacuum seal the device. The plurality of wirings are softer than the metal pattern, The width of a region where the plurality of wirings are not present in the outer periphery and the inner periphery of the sealing metal layer is not more than 0.6 times the thickness of the sealing metal layer.

8. The semiconductor package according to claim 7, wherein: The semiconductor substrate has a crystal structure having a cleavage plane in a direction of 45° with respect to the main surface.

9. The semiconductor package according to claim 7 or 8, characterized in that: The width of the wiring at the outer peripheral portion and the inner peripheral portion of the sealing metal layer is wider than the width of the wiring at the central portion of the sealing metal layer.

10. The semiconductor package according to claim 7 or 8, characterized in that: The width of the region includes a first width along the outer circumference or the inner circumference of the sealing metal layer and a second width in a direction perpendicular to the outer circumference or the inner circumference of the sealing metal layer. Both the first width and the second width are less than or equal to 0.6 times the thickness of the sealing metal layer.

11. A semiconductor package, characterized in that: have: Semiconductor substrates; A device formed on a main surface of the semiconductor substrate; a plurality of wirings formed on the main surface of the semiconductor substrate, including wirings connected to the device and dummy wirings not connected to the device; a passivation film covering the main surface and the plurality of wirings; A metal pattern is formed on the passivation film in a manner of surrounding the device; A sealing metal layer, disposed on the metal pattern; as well as A cover is bonded to the metal pattern via the sealing metal layer to vacuum seal the device. The plurality of wirings are arranged in parallel with each other so as to be separated from each other at the outer periphery of the sealing metal layer and extend along the outer periphery of the sealing metal layer.

12. The semiconductor package according to claim 11, wherein: Each of the plurality of wirings has a width of 100 μm or less.

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