Integrated device having a CMOS structure including a well-less transistor

Abstract

An integrated device includes: a substrate, a first transistor, and a second transistor. The second transistor is configured to be coupled to the first transistor. The first transistor is configured to function as an N-channel metal oxide semiconductor transistor. The first transistor includes a dielectric layer disposed on the substrate; a first source disposed on the dielectric layer; a first drain disposed on the dielectric layer; a first plurality of channels coupled to the first source and the first drain; and a first gate surrounding the plurality of channels. The second transistor is configured to function as a P-channel metal oxide semiconductor transistor. The second transistor includes a dielectric layer; a second source disposed on the dielectric layer; a second drain disposed on the dielectric layer; a second plurality of channels coupled to the second source and the second drain; and a second gate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Non-Provisional Application No. 16 / 817,446 filed in the U.S. Patent and Trademark Office on March 12, 2020, and Provisional Application No. 62 / 890,012 filed in the U.S. Patent and Trademark Office on August 21, 2019, the entire contents of which are incorporated herein by reference as if fully set forth below and for all applicable purposes. Technical Field

[0003] Various features relate to integrated devices, but more particularly to integrated devices having a CMOS structure including well-less transistors. Background Art

[0004] Figure 1 A complementary metal oxide semiconductor (CMOS) structure 100 is shown including a P-type channel metal oxide semiconductor (PMOS) transistor 120 and an N-type channel metal oxide semiconductor (NMOS) transistor 140. The PMOS transistor 120 is formed on an N-type well 102, while the NMOS transistor 140 is formed on a P-type well 104. Both the N-type well 102 and the P-type well 104 are each formed in a substrate 105. Figure 1 As shown, the PMOS transistor 120 and the NMOS transistor 140 are positioned adjacent to each other in a dual well arrangement. The PMOS transistor 120 and the NMOS transistor 140 are separated by a spacer (S). The spacer (S) may represent the spacing between the N-type well 102 and the P-type well 104. An integrated device such as an integrated circuit (IC) may include a plurality of CMOS structures 100, each CMOS structure 100 including a PMOS transistor 120 and an NMOS transistor 140. There is a continuing need to reduce the size and space occupied by CMOS structures in integrated devices. Summary of the invention

[0005] Various features relate to integrated devices, but more particularly to integrated devices having a CMOS structure including well-less transistors.

[0006] One example provides an integrated device including a substrate and a first transistor formed on the substrate. The first transistor includes a dielectric layer disposed on the substrate; a first source disposed on the dielectric layer; a first drain disposed on the dielectric layer; a first plurality of channels coupled to the first source and the first drain, wherein the first plurality of channels are located between the first source and the first drain; and a first gate surrounding the first plurality of channels.

[0007] Another example provides an apparatus, the apparatus comprising a substrate and a first transistor device formed on the substrate. The first transistor device comprises a dielectric layer disposed on the substrate; a first source device disposed on the dielectric layer; a first drain device disposed on the dielectric layer; a first channel device coupled to the first source device and the first drain device, wherein the first channel device is located between the first source device and the first drain device; and a first gate device surrounding the first channel device.

[0008] Another example provides a method for manufacturing an integrated device. The method provides a substrate. The method forms a first transistor on the substrate. Forming the first transistor includes forming a first plurality of channels on the substrate; forming a dielectric layer on the substrate; forming a first source on the dielectric layer; forming a first drain on the dielectric layer; and forming a first gate around the first plurality of channels. The first plurality of channels are coupled to the first source and the first drain. The first plurality of channels are located between the first source and the first drain. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Various features, properties and advantages will become apparent from the detailed description set forth below, taken in conjunction with the accompanying drawings, wherein like reference numerals are correspondingly identified throughout.

[0010] Figure 1 A view of a complementary metal oxide semiconductor (CMOS) structure including a P-channel metal oxide semiconductor (PMOS) transistor and an N-channel metal oxide semiconductor (NMOS) transistor is illustrated.

[0011] Figure 2 A circuit diagram overlaid on a CMOS structure including a PMOS transistor and an NMOS transistor is illustrated.

[0012] Figure 3 An exemplary view of a gate-all-around field effect transistor (FET) formed over a substrate is illustrated.

[0013] Figure 4 A cell of an integrated device including a gate-all-around FET is illustrated.

[0014] Figure 5 An exemplary view of a gate-all-around FET configured as an NMOS transistor is illustrated.

[0015] Figure 6 An exemplary view of a gate-all-around FET configured as a PMOS transistor is illustrated.

[0016] Figure 7 An exemplary energy diagram for a FET is illustrated.

[0017] Figure 8 (including Figure 8A-8G ) illustrates an exemplary sequence for fabricating a wellless gate-all-around FET.

[0018] Fig. 9 An exemplary flow chart of a method for fabricating a well-less gate-all-around FET is illustrated.

[0019] Fig.10 A cross-sectional view of an integrated device including a gate-all-around FET is illustrated.

[0020] Figure 11 (including Figure 11A-11B ) illustrates an exemplary sequence for fabricating an integrated device including a gate-all-around FET.

[0021] Fig.12 An exemplary flow chart of a method for fabricating an integrated device including a gate-all-around FET is illustrated.

[0022] Fig.13 Various electronic devices are illustrated that may integrate the dies, integrated devices, integrated passive devices (IPDs), device packages, packages, integrated circuits, and / or PCBs described herein. DETAILED DESCRIPTION

[0023] In the following description, specific details are given to provide a thorough understanding of various aspects of the present disclosure. However, it will be understood by those of ordinary skill in the art that these aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring various aspects in unnecessary detail. In other cases, well-known circuits, structures, and techniques may not be shown in detail to avoid confusing various aspects of the present disclosure.

[0024] As described above, there is a continuing need to scale complementary metal oxide semiconductor (CMOS) structures so that the CMOS structures are smaller and occupy less space. However, scaling CMOS structures including PMOS transistors and NMOS transistors to smaller sizes has limitations due to well isolation issues and latch-up that may occur with smaller-sized PMOS transistors and NMOS transistors.

[0025] Figure 2An exemplary view of a CMOS structure 200 including an NMOS transistor 202 located next to a PMOS transistor 204 is illustrated. A circuit diagram 210 is overlaid on the CMOS structure 200. The NMOS transistor 202 is formed on a P-type well 220, and the PMOS transistor 204 is formed on an N-type well 240. Both the P-type well 220 and the N-type well 240 are formed in a substrate 201. In some cases, as the spacing between the P-type well 220 and the N-type well 240 decreases, a latch-up may occur between the NMOS transistor 202 and the PMOS transistor 204. Specifically, a latch-up may occur between the power supply (e.g., Vdd) of the PMOS transistor 204 and the ground (e.g., Vss) of the NMOS transistor 202. This may be the case where there is not sufficient isolation between the P-type well 220 and the N-type well 240 in the substrate 201.

[0026] Latch-up is a type of short circuit that can occur in a CMOS structure of an integrated device. Latch-up may occur when an unexpected low impedance path is created between power and ground. During latch-up, when one of the transistors (e.g., an NMOS transistor) is turned on, the other transistor (e.g., a PMOS transistor) may also begin to turn on. In some cases, the two transistors can remain in saturation with each other as long as there is some current flowing through the transistors. Since the PMOS transistors and NMOS transistors in the CMOS structure are formed closer to each other, the possibility of latch-up increases. Therefore, in order to provide any kind of CMOS structure including PMOS transistors and NMOS transistors at a smaller scale, the latch-up problem of the CMOS structure must be solved.

[0027] The present disclosure describes an integrated device that may include a complementary metal oxide semiconductor (CMOS) structure. The CMOS structure may include a substrate, a first transistor formed on the substrate, and a second transistor formed on the substrate. The second transistor may be configured to be electrically coupled to the first transistor. The first transistor may be configured to function as an N-type channel metal oxide semiconductor (NMOS) transistor. The first transistor includes a dielectric layer disposed on the substrate; a first source disposed on the dielectric layer; a first drain disposed on the dielectric layer; a first plurality of channels coupled to the first source and the first drain, the first plurality of channels being located between the first source and the first drain; and a first gate surrounding the plurality of channels. The second transistor may be configured to function as a P-type channel metal oxide semiconductor (PMOS) transistor. The second transistor includes a dielectric layer disposed on the substrate; a second source disposed on the dielectric layer; a second drain disposed on the dielectric layer; a second plurality of channels coupled to the second source and the second drain, the second plurality of channels being located between the second source and the second drain; and a second gate surrounding the second plurality of channels. The second gate and the first gate may be portions of the same gate. In some implementations, neither the first transistor nor the second transistor has a well (e.g., no well). One of the technical advantages of the CMOS structure described in the present disclosure is the ability to more aggressively scale (eg, reduce) the CMOS structure without experiencing latch-up issues.

[0028] Exemplary Wellless Gate-All-Around Field Effect Transistor (FET)

[0029] Figure 3 An example of a transistor 300 formed on a substrate is illustrated. The transistor 300 may be a gate-all-around (GAA) field effect transistor (FET). Specifically, the transistor 300 may be a wellless multi-channel gate-all-around FET. The transistor 300 may be configured as (i) an N-type channel metal oxide semiconductor (NMOS) transistor, or (ii) a P-type channel metal oxide semiconductor (PMOS) transistor. As will be further described below, a complementary metal oxide semiconductor (CMOS) structure may be defined by a first transistor (e.g., 300) configured as an NMOS transistor and a second transistor (e.g., 300) configured as a PMOS transistor. The transistor 300 may be a transistor device. The transistor 300 may be implemented in an integrated device.

[0030] like Figure 3As shown, transistor 300 is formed on substrate 302. Transistor 300 includes source 304, drain 306, gate 308, multiple channels 310, inner spacer 316 and dielectric layer 320. Source 304 can be a source device. Drain 306 can be a drain device. Gate 308 can be a gate device. Multiple channels 310 can be channel devices. In some implementations, substrate 302 can be considered as part of transistor 300. Figure 3 Transistor 300 is also illustrated as not having a well (e.g., N-type well, P-type well). Instead of a well, dielectric layer 320 provides isolation of source 304 and drain 306 from substrate 302. Thus, the presence of dielectric layer 320 with transistor 300 can eliminate the need for transistor 300 to have one or more wells (e.g., N-type well, P-type well).

[0031] Figure 3 A dielectric layer 320 (e.g., an isolation dielectric layer) is illustrated as being disposed (e.g., formed) above a substrate 302. A source 304 is disposed (e.g., formed) above the dielectric layer 320. Similarly, a drain 306 is disposed (e.g., formed) above the dielectric layer 320. A plurality of channels 310 are coupled to the source 304 and the drain 306. The plurality of channels 310 are located between the source 304 and the drain 306. The plurality of channels 310 are configured to allow current to flow between the source 304 and the drain 306 when a voltage (e.g., a threshold voltage) is applied between the gate 308 and the substrate 302. The plurality of channels 310 may include a first channel, a second channel, and a third channel. The first channel, the second channel, and the third channel may be stacked vertically on top of each other with a space (for a gate) between each channel. Different implementations may include different numbers of channels. The gate 308 is located between the source 304 and the drain 306. The gate 308 is formed to surround or encircle the plurality of channels 310. For example, the gate 308 may surround four sides of a channel from the plurality of channels 310. Note that the size and shape of the transistor 300 are exemplary. In addition, the components of the transistor 300 shown may not be to scale.

[0032] As described above, transistor 300 can be configured to operate as an NMOS transistor or a PMOS transistor. To operate as an NMOS transistor, source 304 and drain 306 can each include an N-type dopant (N+). To operate as a PMOS transistor, source 304 and drain 306 can each include a P-type dopant (P+). Examples of how transistor 300 can be configured to operate as an NMOS transistor or a PMOS transistor are described below at least in Figures 5 and 6As will be further described below, a first transistor configured as an NMOS transistor and a second transistor configured as a PMOS transistor can be used to form and define a CMOS structure in an integrated device. Substrate 302 may include one or more shallow trench isolations (STIs). In some implementations, dielectric layer 320 may be located above substrate 302 and / or one or more STIs.

[0033] Figure 4 The diagram shows a cell 400 of an integrated device. The cell 400 may represent a device-level cell of the integrated device. Figure 4 As shown, the unit 400 includes a CMOS structure 401a defined by an NMOS transistor 402a (e.g., a first transistor) and a PMOS transistor 404a (e.g., a second transistor). The NMOS transistor 402a can be a transistor 300, wherein the source and the drain include an N-type dopant (N+). Similarly, the PMOS transistor 404a can be a transistor 300, wherein the source and the drain include a P-type dopant (P+). The NMOS transistor 402a and the PMOS transistor 404a can have separate gates. In some implementations, the NMOS transistor and the PMOS transistor can share a gate. Figure 4 A CMOS structure 401b is illustrated as being defined by an NMOS transistor 402b (e.g., a first transistor) and a PMOS transistor 404b (e.g., a second transistor). The NMOS transistor 402b may be the transistor 300 in which the source and the drain include an N-type dopant (N+). Similarly, the PMOS transistor 404b may be the transistor 300 in which the source and the drain include a P-type dopant (P+). The NMOS transistor 402b and the PMOS transistor 404b share a gate. For example, the gate of the NMOS transistor 402b and the gate of the PMOS transistor 404b may be parts of the same gate. More detailed examples of NMOS transistors and PMOS transistors are described below. Figure 5-Figure 6 As will be further described below, the integrated device may include a plurality of cells 400, each cell having the same or a different arrangement of CMOS structures, NMOS transistors and / or PMOS transistors.

[0034] Figure 5 and Figure 6 The cross-sectional views of NMOS transistors and PMOS transistors are shown in FIG. The cross-sectional views of NMOS transistors and PMOS transistors can be across Figure 3 Cross section AA of transistor 300 .

[0035] Figure 5An exemplary view of a first transistor 500 configured as an NMOS transistor is illustrated. The first transistor 500 may be a first transistor device. The first transistor 500 may be Figure 3 5. A more specific implementation of transistor 300 of the present invention is shown in FIG. 5. A first transistor 500 is formed on a substrate 502. The transistor 500 includes a first source 504, a first drain 506, a first gate 508, a first plurality of channels 510, and a dielectric layer 520. The first source 504 may be a first source device. The first drain 506 may be a first drain device. The first gate 508 may be a first gate device. The first plurality of channels 510 may be a first channel device. In some implementations, the substrate 502 may be considered as part of the first transistor 500. Figure 5 The first transistor 500 is also illustrated as not having a well (e.g., an N-type well, a P-type well). Instead of a well, the dielectric layer 520 provides isolation of the first source 504 and the first drain 506 from the substrate 502. Therefore, the presence of the dielectric layer 520 with the first transistor 500 can eliminate the need for one or more wells (e.g., an N-type well, a P-type well) for the first transistor 500. Different implementations can include different materials for the dielectric layer 520. For example, the dielectric layer 520 can include SiO, SiN, SiC, SiON, and / or combinations thereof.

[0036] Figure 5 A dielectric layer 520 (e.g., an isolation dielectric layer) is illustrated disposed (e.g., formed) over the substrate 502. A first source 504 is disposed (e.g., formed) over the dielectric layer 520. Similarly, a first drain 506 is disposed (e.g., formed) over the dielectric layer 520. The first source 504 and the first drain 506 each include an N-type dopant (N+). The dielectric layer 520 can be similar to the dielectric layer 320.

[0037] The first plurality of channels 510 are coupled to the first source 504 and the first drain 506. The metal component 512 and the high-K dielectric layer 514 can be located above and / or around the first plurality of channels 510. The spacer 516 can be located between the gate 508 and the first source 504. The spacer 516 can be located between the gate 508 and the first drain 506. The metal component 512 can be considered as part of the gate 508. The metal component 512 can include TiN, TaN, TiAl(C), W, and / or a combination thereof. The high-K dielectric layer 514 can include HfO, HfSiO, HfSiON, HfLaO, HfLaSiO, HfLaSiON, HfAlO, HfAlSiO, HfAlSiON, and / or a combination thereof. The spacer 516 can include an outer spacer and / or an inner spacer (e.g., 316, 830). The spacer 516 may include SiO, SiN, SiON, SiC, and / or combinations thereof. However, different implementations may use different materials for the metal component 512, the high-K dielectric layer 514, and / or the spacer 516. The first gate 508 may include the metal component 512. The first gate 508 may include the metal component 512 and the high-K dielectric layer 514.

[0038] The first plurality of channels 510 are located between the first source 504 and the first drain 506. The first plurality of channels 510 are configured to allow current to flow between the first source 504 and the first drain 506 when a voltage is applied between the first gate 508 and the substrate 502. The first plurality of channels 510 may include a first channel, a second channel, and a third channel. The first channel, the second channel, and the third channel may be stacked vertically on each other with space (for the gate) between each channel. Different implementations may include different numbers of channels. The first gate 508 is located between the first source 504 and the first drain 506. The first gate 508 is formed such as to surround or surround the first plurality of channels 510. For example, the first gate 508 may surround four sides of the channel from the first plurality of channels 510.

[0039] The dielectric thickness of the dielectric layer 520 is equal to or less than the first channel thickness of the first channel 510. In some implementations, the dielectric layer 520 has a dielectric thickness in the range of about 7 to 20 nanometers (nm). In some implementations, each channel from the first plurality of channels 510 has a channel thickness of about 5 to 10 nanometers (nm). In some implementations, the vertical space or gap between the channels is about 7 to 20 nanometers (nm).

[0040] Figure 6An exemplary view of a second transistor 600 configured as a PMOS transistor is shown. The second transistor 600 may be a second transistor device. The second transistor 600 may be Figure 3 600. The second transistor 600 may be similar to the first transistor 500. However, some components of the second transistor 600 may be doped differently. The second transistor 600 is formed on a substrate 602. The second transistor 600 includes a second source 604, a second drain 606, a second gate 608, a second plurality of channels 610, and a dielectric layer 620. The second source 604 may be a second source device. The second drain 606 may be a second drain device. The second gate 608 may be a second gate device. The second plurality of channels 610 may be a second channel device. In some implementations, the substrate 602 may be considered as part of the second transistor 600. Figure 6 The second transistor 600 is also illustrated as not having a well (e.g., an N-type well, a P-type well). Instead of a well, the dielectric layer 620 provides isolation of the second source 604 and the second drain 606 from the substrate 602. Therefore, the presence of the dielectric layer 620 with the second transistor 600 can eliminate the need for one or more wells (e.g., an N-type well, a P-type well) of the second transistor 600. Different implementations can include different materials for the dielectric layer 620. For example, the dielectric layer 620 can include SiO, SiN, SiC, SiON, and / or combinations thereof.

[0041] Figure 6 A dielectric layer 620 (e.g., an isolation dielectric layer) is illustrated disposed (e.g., formed) over the substrate 602. A second source 604 is disposed (e.g., formed) over the dielectric layer 620. Similarly, a second drain 606 is disposed (e.g., formed) over the dielectric layer 620. The second source 604 and the second drain 606 each include a P-type dopant (P+). The dielectric layer 620 may be similar to the dielectric layer 320.

[0042] The second plurality of channels 610 are coupled to the second source 604 and the second drain 606. The metal component 612 and the high-K dielectric layer 614 can be located above and / or around the second plurality of channels 610. The spacer 616 can be located between the gate 608 and the first source 604. The spacer 616 can be located between the gate 608 and the first drain 606. The metal component 612 can be considered as a part of the gate 608. The metal component 612 can include TiN, TaN, TiAl (C), W, and / or a combination thereof. The high-K dielectric layer 614 can include HfO, HfSiO, HfSiON, HfLaO, HfLaSiO, HfLaSiON, HfAlO, HfAlSiO, HfAlSiON and / or a combination thereof. The spacer 616 can include an outer spacer and / or an inner spacer (e.g., 316, 830). The spacer 616 may include SiO, SiN, SiON, SiC, and / or combinations thereof. However, different implementations may use different materials for the metal component 612, the high-K dielectric layer 614, and / or the spacer 616. The second gate 608 may include the metal component 612. The second gate 608 may include the metal component 612 and the high-K dielectric layer 614.

[0043] The second plurality of channels 610 are located between the second source 604 and the second drain 606. The second plurality of channels 610 are configured to allow current to flow between the second source 604 and the second drain 606 when a voltage (e.g., a threshold voltage) is applied between the second gate 608 and the substrate 602. The second plurality of channels 610 may include a second channel, a second channel, and a third channel. The second channel, the second channel, and the third channel may be stacked vertically with each other, with space (for the gate) between each channel. Different implementations may include different numbers of channels. The second gate 608 is located between the second source 604 and the second drain 606. The second gate 608 is formed to surround or surround the second plurality of channels 610. For example, the second gate 608 may surround the four sides of the channel from the second plurality of channels 610.

[0044] In some implementations, dielectric layer 620 has a dielectric thickness in the range of about 7 to 20 nanometers (nm). In some implementations, each channel from the second plurality of channels 610 has a channel thickness of about 5 to 10 nanometers (nm). In some implementations, the vertical space or gap between channels is about 7 to 20 nanometers (nm).

[0045] The first transistor 500 and the second transistor 600 can be used in combination to form and define a CMOS structure. In some implementations, the spacing between the NMOS transistor and the PMOS transistor can be about 30-200 nanometers (nm). For example, the spacing between the drain or source of the NMOS transistor and the adjacent drain or source of the PMOS transistor can be about 30-200 nanometers (nm). The spacing between the NMOS transistor and the PMOS transistor sharing the same gate can be about 30-200 nanometers (nm). The size of the transistor and the type of material used can be selected to produce one or more transistors that require as low a threshold voltage as possible to activate (e.g., turn on) the transistor.

[0046] In a field effect transistor (FET), current can flow from the drain to the source via a channel coupled to the drain and source. When a voltage is applied between the gate and the substrate, an electric field is generated that can control the current flowing between the drain and the source. A minimum voltage (or minimum threshold voltage) needs to be applied between the gate and the substrate so that the transistor is "turned on" and a current flowing through the (multiple) channels is introduced. If the minimum voltage (or minimum threshold voltage) is not reached or is not applied between the gate and the substrate, the transistor may be "turned off" and no current flows through the (multiple) channels. The minimum voltage (or minimum threshold voltage) required to make the transistor "turned on" is usually a function or defined by the work function of the transistor channel and the gate. In order to obtain the lowest possible minimum threshold voltage, the work function difference between the channel and the gate should be as small as possible.

[0047] Note that the sizes and shapes of the NMOS transistor 500 and the PMOS transistor 600 are exemplary. Furthermore, the components of the NMOS transistor 500 and / or the PMOS transistor 600 shown may not be to scale. Additionally, the NMOS transistor 500 and / or the PMOS transistor 600 may include other components. In some implementations, at least some portions of the NMOS transistor 500 and / or at least some portions of the PMOS transistor 600 may be located on the substrate and / or one or more STIs.

[0048] Figure 7 An energy diagram for a field effect transistor (FET) is illustrated. Figure 7 The work function for the gate and the work function for the well are illustrated. Additionally, the energy diagram illustrates the various conduction bands, valence bands, and Fermi levels of the various components of the FET (e.g., substrate, gate). C is the conduction band, E V is the valence band, and E Fis the Fermi level. D represents the difference between the work function of the gate and the work function of the dielectric layer. Therefore, when designing a FET (e.g., NMOS transistor, PMOS transistor), the size, shape, and material can be selected to make the difference (D) between the gate and the channel as low as possible.

[0049] Having described a CMOS structure including an NMOS transistor and a PMOS transistor, a sequence for manufacturing the CMOS structure will now be described below.

[0050] Exemplary sequence for fabricating an NMOS transistor or a PMOS transistor

[0051] In some implementations, manufacturing a transistor such as an NMOS transistor or a PMOS transistor includes several processes. FIG. 8A to FIG. 8G ) illustrates an exemplary sequence for providing or manufacturing a transistor. In some implementations, FIG. 8A to FIG. 8G The sequence can be used to provide or make Figure 3 , Figure 4 , Figure 5 , Figure 6 8. The sequence of transistors of the present invention may be used to provide or manufacture a CMOS structure having an NMOS transistor and a PMOS transistor. Additionally, the sequence of transistors may be used to manufacture multiple transistors (e.g., an NMOS transistor, a PMOS transistor) simultaneously. However, for clarity, the sequence of FIG. 8 illustrates the manufacture of one transistor.

[0052] It should be noted that FIG. 8A to FIG. 8G The sequence of one or more stages may be combined to simplify and / or clarify the sequence of providing or manufacturing a transistor. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more processes may be replaced or substituted without departing from the spirit of the present disclosure.

[0053] Stage 1, such as Fig. 8A As shown, a state after providing a substrate 302 is illustrated. Different implementations may provide different materials for the substrate 302. In some implementations, the substrate 302 may include silicon (Si).

[0054] Stage 2 illustrates a state after superlattice formation. In some implementations, superlattice formation includes forming a stacked structure of alternating silicon (Si) layers (e.g., Si layer 803) and silicon germanium (SiGe) layers (e.g., SiGe layer 802) on substrate 302 and creating one or more superlattices 801 from the stacked structure by removing (e.g., etching, dry etching, wet etching) portions of the stacked structure. The process of forming the stacked structure may include using an epitaxial process. The process of manufacturing the superlattice may include manufacturing one or more shallow trench isolations (STIs) (not shown). Superlattice formation may also include a fin reveal process, in which portions of the STI are removed, thereby exposing at least some portions of the superlattice and / or the fins.

[0055] Stage 3, such as Figure 8B , illustrating the state after the pseudo gate and spacer are formed. An oxide layer 810 is formed on the superlattice 801 (e.g., on the top Si layer), and a pseudo gate 820 is formed on the oxide layer 810 and the superlattice 801. Additionally, a spacer 816 is formed on the superlattice 801. More specifically, the spacer 816 is formed on the superlattice 801 and is adjacent to the pseudo gate 820 (and on each side of the pseudo gate 820). Note that the spacer 816 is exemplary. The spacer 816 may include an outer spacer. In some implementations, the spacer 816 includes a spacer 516, a spacer 616, or any spacer described in the present disclosure. A chemical vapor deposition (CVD) process and / or an atomic layer deposition (ALD) process may be used to form a pseudo gate and / or a spacer.

[0056] Stage 4 illustrates the state after cavity etching. After cavity etching, the portion of superlattice 801 not covered by dummy gate 820 and / or spacer 816 is removed. Cavity etching involves removing portions of Si layer (e.g. 803) and SiGe layer (e.g. 802) of superlattice 801.

[0057] Stage 5, such as Figure 8C , which illustrates the state after SiGe recessing. After SiGe recessing, portions of the SiGe layer (eg, 802) under the spacer 816 are removed.

[0058] Stage 6 illustrates the state after the inner spacer formation. After the inner spacer formation, inner spacers 830 are formed in the cavity where the SiGe was previously removed (as shown in stage 5).

[0059] Stage 7, such as Fig.8D As shown in FIG. 7 , a dielectric layer 320 is disposed (eg, formed) on the substrate 302 . A deposition process may be used to form the dielectric layer 320 .

[0060] Stage 8 illustrates the state after source and drain formation. After source and drain formation, the source and drain are formed over dielectric layer 320. For example, first source 304 and first drain 306 are disposed over dielectric layer 320.

[0061] Stage 9, such as Fig. 8E As shown, the state after doping the source and drain is illustrated. The source 304 and the drain 306 can be doped with an N-type dopant (N+) or a P-type dopant (P+). Doping the source 304 and the drain 306 with an N-type dopant (N+) can produce a source 504 and a drain 506. Doping the source 304 and the drain 306 with a P-type dopant (P+) can produce a source 604 and a drain 606. Vapor phase epitaxy can be used to dope the source and drain. However, different implementations can use different processes to dope the source and drain.

[0062] Stage 10 illustrates a state after the interlayer dielectric (ILD) is formed. After the ILD is formed, an oxide layer 840 is formed on the source 304, the drain 306, and the spacer 816. A dielectric layer 850 is further formed on the oxide layer 840. A deposition process may be used to form the oxide layer 840 and / or the dielectric layer 850.

[0063] Stage 11, such as Fig.8F , a state after removing the dummy gate and the dummy dielectric layer is illustrated, wherein the dummy gate 820 and the oxide layer 810 are removed, thereby exposing portions of the top Si layer (eg, 803 ).

[0064] Stage 12 illustrates a state after SiGe removal, where the SiGe layer (eg, 802 ) of the superlattice 801 is removed (eg, etched), leaving a cavity between the Si layer (eg, 803 ) and / or the Si layer and the substrate 302 .

[0065] Stage 13, such as Figure 8G , a state after the high-K dielectric layer is formed is illustrated, wherein the high-K dielectric layer 814 is formed between spacers 816 in the cavity previously occupied by the SiGe layer. The high-K dielectric layer 814 may be the high-K dielectric layer 514 or 614. For clarity, the oxide layer 840 and the dielectric layer 850 are not shown.

[0066] Stage 14 illustrates after metal gate formation. After metal gate formation, metal component 812 is formed between high-K dielectric layer 814. Metal component 812 may be located within a cavity previously occupied by a SiGe layer. Metal component 812 may define gate 308, gate 508, or gate 608. For clarity, oxide layer 840 and dielectric layer 850 are not shown. Note that the high-K dielectric layer (e.g., 814) may be considered to be part of the gate (e.g., 308, 508, 608). Therefore, in some implementations, the gate (e.g., 308, 508, 608) may include metal component 812 and high-K dielectric layer (e.g., 814). Stage 14 may illustrate transistor 300, and depending on the doping of the source and drain, may illustrate NMOS transistor 500 or PMOS transistor 600. In some implementations, additional processes may be performed on the transistor, including a polishing process.

[0067] Exemplary Flowchart of a Method for Fabricating an NMOS Transistor and a PMOS Transistor

[0068] In some implementations, fabricating a transistor includes several processes. Fig. 9 An exemplary flow chart of a method 900 for providing or manufacturing a transistor (e.g., an NMOS transistor and a PMOS transistor) is illustrated. The transistor may be part of a transistor forming a CMOS structure. In some implementations, Fig. 9 The method 900 may be used to provide or manufacture Figure 3 , Figure 4 , Figure 5 , Figure 6 transistors and / or other transistors described in this disclosure.

[0069] It should be noted that Fig. 9 The sequence of the processes may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a transistor. In some implementations, the order of the processes may be changed or modified.

[0070] The method forms (at 905) a stack structure of alternating layers of silicon and silicon germanium (SiGe) on substrate 302. The stack structure can be formed on substrate 302. Different implementations can provide different materials for substrate 302. In some implementations, substrate 302 can include silicon (Si).

[0071] The method forms (at 910) a superlattice (e.g., 801) from the stacked structure. The superlattice can be formed by removing (e.g., etching) portions of the stacked structure. The process of forming the superlattice can include forming shallow trench isolation (STI) around the superlattice and exposing the superlattice by removing portions of the STI. In some implementations, forming the superlattice includes forming the stacked structure as described at 905.

[0072] The method forms (at 915) a dummy gate and spacers, wherein an oxide layer 810 is formed over the superlattice 801 (e.g., over the top Si layer) and a dummy gate 820 is formed over the oxide layer 810 and the superlattice 801. Additionally, spacers 816 are formed over the superlattice 801. More specifically, spacers 816 are formed over the superlattice 801 and proximate to the dummy gate 820 (and on each side thereof). Note that spacers 816 are exemplary. In some implementations, spacers 816 may include spacers 516, spacers 616, or any spacers described in the present disclosure. Figure 8B Stage 3 of FIG. 1 illustrates an example of forming a dummy gate, spacers, and an oxide layer.

[0073] The method performs (at 920) cavity etching, SiGe recess formation, and inner spacer formation. During cavity etching, portions of the superlattice 801 not covered by the dummy gate 820 and / or the spacer 816 are removed. Cavity etching involves removing portions of the Si and SiGe of the superlattice 801. During SiGe recess formation, portions of the SiGe layer under the spacer 816 are removed. During inner spacer formation, inner spacers 830 are formed in the cavities where the SiGe was previously removed. FIG. 8B to FIG. 8C Stages 4-6 of FIG. 1 illustrate examples of cavity formation, SiGe recess formation, and inner spacer formation.

[0074] The method forms (at 925) dielectric layer 320 over substrate 302. Dielectric layer 320 is disposed over substrate 302. Different implementations may use different materials for dielectric layer 320. Fig.8D Stage 7 of FIG. 1 illustrates an example of dielectric formation.

[0075] The method forms (at 930) a source and a drain and performs interlayer dielectric (ILD) formation. Forming the source and the drain may include disposing a source 304 and a drain 306 on the dielectric layer 320. Forming the source and the drain may also include doping the source and the drain. For example, the source 304 and the drain 306 may be doped with an N-type dopant (N+) or a P-type dopant (P+). Doping the source 304 and the drain 306 with an N-type dopant (N+) may produce a source 504 and a drain 506. Doping the source 304 and the drain 306 with a P-type dopant (P+) may produce a source 604 and a drain 606. ILD formation may include forming an oxide layer 840 on the source 304, the drain 306, and the spacer 816. The ILD formation may also include forming a dielectric layer 850 on the oxide layer 840. Fig.8D and Fig. 8E Stages 8-10 of FIG. 1 illustrate examples of source and drain formation, doping, and ILD formation.

[0076] The method performs (at 935) a dummy gate removal, wherein the dummy gate 820 and the oxide layer 810 are removed, thereby exposing portions of the top Si layer (e.g., 803). Additionally, the method may also perform a dummy SiGe removal, wherein the SiGe layer (e.g., 802) of the superlattice 801 is removed, thereby leaving a cavity between the Si layer and / or the Si layer and the substrate 302. One or more etching processes may be used to remove the dummy gate and the SiGe layer(s). Fig.8F Stages 11-12 of FIG. 1 illustrate an example of dummy gate and SiGe removal.

[0077] The method performs (at 940) high-K dielectric layer formation and gate formation. During high-K dielectric layer formation, high-K dielectric layer 814 is formed between spacers 816 in the cavity previously occupied by the SiGe layer. High-K dielectric layer 814 can be high-K dielectric layer 514 or 614. During gate formation, metal component 812 is formed between high-K dielectric layers 814. Metal component 812 can be located in the cavity previously occupied by the SiGe layer. Metal component 812 can define gate 308, gate 508, or gate 608. Figure 8G Stages 13 and 14 illustrate examples of high-K dielectric layer formation and gate formation.

[0078] Exemplary integrated device including a CMOS structure having an NMOS transistor and a PMOS transistor

[0079] Fig.10A cross-sectional view of an integrated device 1000 including at least one CMOS structure having an NMOS transistor and a PMOS transistor is illustrated. The integrated device 1000 includes a substrate 1020, a plurality of device-level cells 1022 (e.g., logic cells), an interconnect portion 1004, and a packaging portion 1006. The plurality of device-level cells 1022 are formed on the substrate 1020. The plurality of device-level cells 1022 may form a device-level layer of the integrated device 1000. In some implementations, the plurality of device-level cells 1022 may include portions of the substrate 1020. In some implementations, the substrate 1020, the device-level layer, and the plurality of device-level cells 1022 may be referred to as a substrate portion 1002 of the integrated device 1000.

[0080] The plurality of device-level cells 1022 may include CMOS structures, NMOS transistors and / or PMOS transistors. The plurality of device-level cells 1022 may include Figure 4 Unit 400 described in. Fig.10 As shown, one of the device-level units includes a CMOS structure 1028, which includes an NMOS transistor 402a and a PMOS transistor 404a. Different implementations may have different numbers and / or arrangements of CMOS structures, NMOS transistors, and / or PMOS transistors. The CMOS structure 1028 may be a CMOS structure 401a. In some implementations, the CMOS structure 1028 may be a CMOS structure 401b, which includes an NMOS transistor 402b and a PMOS transistor 404b (with a shared gate). The NMOS transistor 402a may be an NMOS transistor 500. The PMOS transistor 404a may be a PMOS transistor 600. The NMOS transistor 402a and / or the PMOS transistor 404a may be a wellless transistor.

[0081] The interconnect portion 1004 is formed over the substrate portion 1002. Specifically, the interconnect portion 1004 is formed over the plurality of device-level cells 1022. The interconnect portion 1004 includes a wiring layer. The interconnect portion 1004 includes a plurality of interconnects 1040 (e.g., traces, pads, vias) and at least one dielectric layer 1042. The interconnect portion 1004 can provide interconnections between a plurality of CMOS structures, NMOS transistors, and / or PMOS transistors.

[0082] The package portion 1006 is formed over the interconnect portion 1004. The package portion 1006 includes a passivation layer 1060, an under bump metallization (UBM) layer 1062, and solder interconnects 1064. Note that the size and shape of the integrated device 1000 are exemplary. In addition, the components of the integrated device 1000 shown may not be to scale.

[0083] Exemplary sequence for fabricating integrated devices including CMOS structures

[0084] In some implementations, manufacturing an integrated device including a CMOS structure having NMOS transistors and PMOS transistors includes several processes. Fig.11A -to Fig. 11B ) illustrates an exemplary sequence for providing or manufacturing an integrated device including a CMOS structure having an NMOS transistor and a PMOS transistor. In some implementations, FIG. 11A to FIG. 11B The sequence can be used to provide or make Fig.10 integrated devices and / or other integrated devices described in the present disclosure.

[0085] It should be noted that FIG. 11A to FIG. 11B The sequence of one or more stages may be combined to simplify and / or clarify the sequence for providing or manufacturing an integrated device including a CMOS structure having an NMOS transistor and a PMOS transistor. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more processes may be replaced or substituted without departing from the spirit of the present disclosure.

[0086] Stage 1, such as Fig.11A , a state after providing a substrate 1020 is illustrated. Different implementations may provide different materials for the substrate 1020. In some implementations, the substrate 1020 may include silicon (Si).

[0087] Stage 2 illustrates a state after forming a device level layer on the substrate 1020. The device level layer includes a plurality of device level cells 1022 (e.g., 400). Thus, stage 2 illustrates a state after forming a plurality of device level cells 1022 on the substrate 1020. In some implementations, the device level layer (e.g., the plurality of device level cells 1022) may be manufactured using a front end of line (FEOL) process. One or more cells from the plurality of device level cells may include a CMOS structure having an NMOS transistor and a PMOS transistor as described above. FIG. 8A to FIG. 8G A sequence for fabricating a transistor (eg, NMOS transistor, PMOS transistor) as part of a CMOS structure is illustrated.

[0088] Stage 3 illustrates a state after forming the interconnect portion 1004. The interconnect portion 1004 may include a plurality of interconnects 1040 and at least one dielectric layer 1042. In some implementations, the interconnect portion 1004 may be manufactured using a back end of line (BEOL) process. The interconnect portion 1004 may be configured to electrically couple one or more CMOS structures having NMOS transistors and PMOS transistors.

[0089] Stage 4, such as Fig. 11B , a state after a passivation layer 1060 and an under bump metallization (UBM) layer 1062 are formed over the interconnection portion 1004 is illustrated.

[0090] Stage 5 illustrates a state after the solder interconnect is coupled to the under bump metallization (UBM) layer 1062. Stage 5 may illustrate the integrated device 1000 including a CMOS structure 1028 including an NMOS transistor 402a and a PMOS transistor 404a.

[0091] Exemplary flow chart of a method for fabricating an integrated device including a CMOS structure

[0092] In some implementations, providing an integrated device including a CMOS structure having an NMOS transistor and a PMOS transistor includes several processes. Fig.12 An exemplary flow chart of a method 1200 for providing or manufacturing an integrated device including a CMOS structure having an NMOS transistor and a PMOS transistor is illustrated. In some implementations, Fig.12 The method 1200 may be used to provide or manufacture Fig.10 integrated devices and / or other integrated devices described in the present disclosure.

[0093] It should be noted that Fig.12 The sequence of the processes may combine one or more processes to simplify and / or clarify a method for providing or manufacturing an integrated device including a CMOS structure having an NMOS transistor and a PMOS transistor. In some implementations, the order of the processes may be changed or modified.

[0094] The method provides (at 1205) a substrate (e.g., 1020). Different implementations may provide different materials for the substrate. In some implementations, the substrate may include silicon (Si). The method forms (at 1210) a device-level layer (e.g., a plurality of device-level cells 1022) on the substrate. In some implementations, a front-end-of-line (FEOL) process may be used to manufacture the device-level layer (e.g., a plurality of device-level cells 1022). The device-level layer may include a plurality of device-level cells (e.g., 400). The device-level cell may include one or more active devices (e.g., 1200). As described in the present disclosure, one or more device-level cells may include a CMOS structure having an NMOS transistor and a PMOS transistor. Forming the device-level layer may include forming one or more NMOS transistors (e.g., 402a, 402b, 500) and / or one or more PMOS transistors (e.g., 404a, 404b, 600), wherein a dielectric layer is present between (i) the source and the substrate and (ii) the drain and the substrate. As described above, the NMOS transistor and / or the PMOS transistor may be a gate-all-around (GAA) transistor.

[0095] The method may form (at 1210) a first transistor on a substrate. Forming the first transistor includes forming a first plurality of channels on the substrate, forming a dielectric layer on the substrate, forming a first source on the dielectric layer, forming a first drain on the dielectric layer, and forming a first gate around the first plurality of channels. The first plurality of channels are coupled to the first source and the first drain. The first plurality of channels are located between the first source and the first drain.

[0096] The method may form (at 1210) a second transistor on the substrate. Forming the second transistor includes forming a second plurality of channels on the substrate, forming a dielectric layer on the substrate, forming a second source on the dielectric layer, forming a second drain on the dielectric layer, and forming a second gate around the second plurality of channels. The second plurality of channels are coupled to the second source and the second drain. The second plurality of channels are located between the second source and the second drain.

[0097] The method forms (at 1215) an interconnect 1004 over a device-level layer (e.g., a plurality of device-level cells 1022) and / or a substrate 1020. The interconnect 1004 may include a plurality of interconnects 1040 and at least one dielectric layer 1042. In some implementations, a back-end-of-line (BEOL) process may be used to form the interconnect 1004. The interconnect 1004 may be configured to electrically couple one or more transistors and / or one or more CMOS structures having NMOS transistors and PMOS transistors.

[0098] The method forms (at 1220) package portion 1006 over interconnect portion 1904. Package portion 1006 may include passivation layer 1060 and under bump metallization (UBM) layer 1062. Passivation layer 1060 and under bump metallization (UBM) layer 1062 are formed over interconnect portion 1004.

[0099] The method provides (at 1225 ) a solder interconnect 1064 . In some implementations, the solder interconnect 1064 is coupled to an under bump metallization (UBM) layer 1062 .

[0100] It should also be noted that Fig.12 The method 1200 can be used to manufacture (e.g., simultaneously manufacture) several integrated devices on a wafer. The wafer is then segmented (e.g., cut) into individual integrated devices. These segmented integrated devices can then be coupled to other integrated devices and / or a printed circuit board (PCB).

[0101] Exemplary Electronic Devices

[0102] Fig.13 Various electronic devices that can be integrated with any of the above-mentioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, stacked packages (PoP), system-level packages (SiP), or systems on chips (SoC) are illustrated. For example, a mobile phone device 1302, a laptop computer device 1304, a fixed location terminal device 1306, a wearable device 1308, or a motor vehicle 1310 can include a device 1300 as described herein. For example, the device 1300 can be any device and / or integrated circuit (IC) package described herein. Fig.13 The devices 1302, 1304, 1306, and 1308 and the vehicle 1310 shown in the device 1300 are exemplary only. Other electronic devices may also feature the device 1300, including but not limited to a group of devices (e.g., electronic devices) including: mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, devices supporting global positioning systems (GPS), navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smart phones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in automobiles (e.g., self-driving cars), or any other devices that store or retrieve data or computer instructions, or any combination thereof.

[0103] exist Figure 3-Figure 7 , Figure 8A-8G , Figure 9-10 , Figure 11A-11B and / or Figure 12-13 One or more components, processes, features, and / or functions illustrated in the drawings may be rearranged and / or combined into a single component, process, feature, or function or embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that Figure 3-Figure 7 , Figure 8A-8G , Figure 9-10 , Figure 11A-11B and / or Figure 12-13 and its corresponding description in this disclosure are not limited to die and / or IC. In some implementations, Figure 3-Figure 7 , Figure 8A-8G , Figure 9-10 , Figure 11A-11B and / or Figure 12-13 The invention and its corresponding description may be used to manufacture, create, provide and / or produce a device and / or an integrated device. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device and / or an interposer.

[0104] Note that the drawings in this disclosure may represent actual representations and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, these drawings may not be drawn to scale. In some cases, for the sake of clarity, all components and / or parts may not be shown. In some cases, the position, location, size, and / or shape of the various components and / or components in the figures may be exemplary. In some implementations, the various components and / or parts in the figures may be optional.

[0105] The word "exemplary" is used herein to mean "serving as an example, instance or illustration". Any implementation or aspect described herein as "exemplary" is not necessarily to be interpreted as being more preferred or advantageous than other aspects of the present disclosure. Likewise, the term "aspect" does not require that all aspects of the present disclosure include the features, advantages or modes of operation discussed. The term "coupling" as used herein refers to a direct or indirect coupling between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, objects A and C can still be considered to be coupled to each other, even if they are not in direct physical contact. The term "electrically coupled" can mean that two objects are coupled together directly or indirectly so that an electric current (e.g., signal, power, ground) can propagate between the two objects. Two electrically coupled objects may or may not have an electric current flowing between the two objects. The use of the terms "first", "second", "third" and "fourth" (and / or anything higher than the fourth) is arbitrary. Any component described may be a first component, a second component, a third component or a fourth component. For example, a component referred to as a second component may be a first component, a second component, a third component or a fourth component. The term "encapsulation" means that an object can partially encapsulate or completely encapsulate another object. It should also be noted that the term "above" as used in the context of one component being above another component in this application can be used to refer to a component that is on another component and / or in another component (e.g., on the surface of a component or embedded in a component). Thus, for example, a first component above a second component may mean (1) the first component is above the second component but not directly contacting the second component, (2) the first component is on the second component (e.g., on the surface), and / or (3) the first component is in (e.g., embedded in) the second component. The term etching may include dry etching or wet etching and may involve the use of a mask. Forming or setting a metal may include an electroplating process, a chemical vapor deposition (CVP) process, and / or an atomic layer deposition (ALD) process. In some implementations, forming one or more dielectric layers, Si layers, and / or SiGe layers may include one or more deposition processes. When a transistor does not have a well, this may mean that a portion of the substrate below the source, drain, and / or channel of the transistor does not include a well (P-type well, N-type well). Note that the well is optional. It should also be noted that a transistor including a dielectric layer (for isolation) may still include one or more wells in the substrate.

[0106] In addition, it should be noted that the various disclosures contained herein may be described as processes depicted as flow charts, flow diagrams, structure diagrams, or block diagrams. Although flow charts may describe operations as sequential processes, many operations may be performed in parallel or simultaneously. Additionally, the order of operations may be rearranged. A process terminates when its operations are completed.

[0107] Without departing from the present disclosure, the various features of the present disclosure described herein can be implemented in different systems. It should be noted that the above aspects of the present disclosure are only examples and should not be interpreted as limiting the present disclosure. The description of the various aspects of the present disclosure is intended to be illustrative, rather than limiting the scope of the claims. In this way, the present teaching can be easily applied to other types of equipment, and many alternatives, modifications and variations will be apparent to those skilled in the art.

Claims

1. An integrated device comprising: substrate; as well as A first transistor is formed on the substrate, wherein the first transistor comprises: a dielectric layer disposed on the substrate; a first source electrode disposed on the dielectric layer; a first drain electrode disposed on the dielectric layer; a first plurality of channels coupled to the first source and the first drain, the first plurality of channels being located between the first source and the first drain; and a first gate surrounding the first plurality of channels, a high-K dielectric layer coupled to the first gate, wherein the high-K dielectric layer is made of a material different from that of the dielectric layer, and Wherein a portion of the high-K dielectric layer contacts the substrate and is laterally positioned to the dielectric layer. 2 . The integrated device of claim 1 , wherein the first transistor does not have a well. 3 . The integrated device according to claim 1 , wherein the dielectric layer is an isolation dielectric layer configured to isolate the first source and the first drain from the substrate.

4. The integrated device of claim 1, wherein the dielectric layer has a dielectric thickness in a range of 7 to 20 nanometers (nm). 5 . The integrated device of claim 1 , wherein each channel from the first plurality of channels has a channel thickness of 5 to 10 nanometers (nm).

6. The integrated device according to claim 1, wherein the first plurality of channels includes a first channel coupled to the first source and the first drain, the first channel having a first channel thickness, and The dielectric thickness of the dielectric layer is equal to or less than the first channel thickness of the first channel.

7. The integrated device according to claim 1, further comprising a second transistor formed on the substrate, the second transistor comprising: the dielectric layer disposed on the substrate; a second source electrode disposed on the dielectric layer; a second drain electrode disposed on the dielectric layer; a second plurality of channels coupled to the second source and the second drain, the second plurality of channels being located between the second source and the second drain; as well as A second gate surrounds the second plurality of channels.

8. The integrated device of claim 7, wherein the first gate and the second gate are parts of the same gate.

9. The integrated device of claim 7, wherein neither the first transistor nor the second transistor has a well.

10. The integrated device according to claim 7, wherein the first source and the first drain each include an N-type dopant (N+), and The second source and the second drain each include a P-type dopant (P+).

11. The integrated device of claim 7, wherein the dielectric layer is an isolation dielectric layer configured to (i) isolate the first source and the first drain from the substrate, and (ii) isolate the second source and the second drain from the substrate.

12. The integrated device of claim 1, wherein the integrated device is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a notebook computer, a server, and a device in an automobile.

13. A device comprising: substrate; as well as A first transistor device is formed on the substrate, wherein the first transistor device comprises: a dielectric layer disposed on the substrate; a first source device disposed on the dielectric layer; a first drain device disposed on the dielectric layer; a first channel device coupled to the first source device and the first drain device, the first channel device being located between the first source device and the first drain device; and a first gate means surrounding said first channel means, a high-K dielectric layer coupled to said first gate device, wherein the high-K dielectric layer is made of a material different from that of the dielectric layer, and Wherein a portion of the high-K dielectric layer contacts the substrate and is laterally positioned to the dielectric layer. The apparatus of claim 13 , wherein the first transistor device has no well. 15 . The apparatus of claim 13 , wherein the dielectric layer is an isolation dielectric layer configured to isolate the first source device and the first drain device from the substrate.

16. The apparatus of claim 13, wherein the dielectric layer has a dielectric thickness in a range of 7 to 20 nanometers (nm).

17. The apparatus of claim 13, further comprising a second transistor device formed over the substrate, the second transistor device comprising: the dielectric layer disposed on the substrate; a second source device disposed on the dielectric layer; a second drain arrangement disposed on said dielectric layer; a second channel means coupled to the second source means and the second drain means, the second channel means being located between the second source means and the second drain means; as well as A second gate means surrounds the second channel means.

18. The apparatus of claim 17, wherein the second transistor arrangement is configured to be electrically coupled to the first transistor arrangement to form a complementary metal oxide semiconductor (CMOS) structure.

19. The apparatus of claim 17, wherein neither the first transistor device nor the second transistor device has a well.

20. The apparatus according to claim 17, wherein the first source device and the first drain device each include an N-type dopant (N+), and The second source device and the second drain device each include a P-type dopant (P+).

21. The apparatus of claim 17, wherein the dielectric layer is an isolation dielectric layer configured to (i) isolate the first source device and the first drain device from the substrate, and (ii) isolate the second source device and the second drain device from the substrate.

22. The device of claim 13, wherein the device is incorporated into a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a notebook computer, a server, and a device in an automobile.

23. A method for manufacturing an integrated device, comprising: providing a substrate; as well as forming a first transistor over the substrate, wherein forming the first transistor comprises: forming a first plurality of channels over the substrate; forming a dielectric layer over the substrate; forming a first source electrode on the dielectric layer; forming a first drain electrode on the dielectric layer; forming a high-K dielectric layer coupled to the first gate, wherein the high-K dielectric layer is made of a different material than the dielectric layer, and wherein the portion of the high-K dielectric layer is formed such that the portion of the high-K dielectric layer contacts the substrate and is laterally positioned to the dielectric layer; and forming the first gate around the first plurality of channels, wherein the first plurality of channels are coupled to the first source and the first drain, and The first plurality of channels are located between the first source and the first drain.

24. The method of claim 23, wherein the first transistor is configured to operate as an N-channel metal oxide semiconductor (NMOS) transistor.

25. The method of claim 23, wherein the first transistor is configured to operate as a P-channel metal oxide semiconductor (PMOS) transistor.

26. The method of claim 23, further comprising forming a second transistor over the substrate, wherein forming the second transistor comprises: forming a second plurality of channels over the substrate; forming a second source electrode on the dielectric layer; forming a second drain electrode on the dielectric layer; forming a second gate around the second plurality of channels, wherein the second plurality of channels are coupled to the second source and the second drain, and The second plurality of channels are located between the second source and the second drain.

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