Structure and method of manufacturing resistive memory with vertical predetermined filaments

Abstract

A semiconductor structure including a vertical resistive memory cell and a method of manufacturing the same. The method includes forming a sacrificial layer over a transistor drain contact; forming a first dielectric layer over the sacrificial layer; forming a cell contact hole through the first dielectric layer; forming an access contact hole through the first dielectric layer and exposing the sacrificial layer; removing the sacrificial layer thereby forming a cavity connecting a bottom opening of the cell contact hole and a bottom opening of the access contact hole; forming a second dielectric layer including a seam in the cell contact hole by atomic layer deposition; forming a bottom electrode within the cavity and the bottom electrode is in contact with the drain contact, the second dielectric layer, and the seam; and forming a top electrode over the first dielectric layer and the top electrode is in contact with the second dielectric layer and the seam.

Description

Background Technology

[0001] This invention relates generally to the field of semiconductors, and more specifically to a method for manufacturing resistive memory devices.

[0002] Resistive random access memory (ReRAM) is a type of non-volatile memory that operates based on the resistance difference between its on and off states. Conductive bridged random access memory (CBRAM) is another type of non-volatile memory, also operating based on the resistance difference between its on and off states. High or low resistance is defined by the physical connection of multiple nanometer-sized filaments between the top and bottom electrodes of each memory cell in this type of non-volatile memory.

[0003] The problem with this type of non-volatile memory (e.g., ReRAM or CBRAM) is that it is impossible to predict where and how much filament is formed in each memory cell of such a non-volatile memory. Therefore, cell-to-cell operations in such non-volatile memory can be non-uniform and unpredictable, resulting in rather poor overall performance. Due to the uncertainty in filament formation in each memory cell compared to other memory cells in such a non-volatile memory, the operational reliability of the non-volatile memory is severely affected. Summary of the Invention

[0004] Various embodiments of the present invention include the fabrication of a semiconductor structure comprising at least one resistive memory cell (also referred to as a resistive memory element). Methods and structures, for example, include forming at least one resistive memory cell in a semiconductor structure. The method includes: forming a sacrificial layer on and in contact with an electrical contact of a transistor; forming a first dielectric layer over and in contact with the sacrificial layer; forming a cell contact hole through the first dielectric layer and exposing a first portion of the sacrificial layer; forming an access contact hole through the first dielectric layer and exposing a second portion of the sacrificial layer; removing the remaining portion of the sacrificial layer to form a cavity directly connecting a bottom opening of the cell contact hole and a bottom opening of the access contact hole; forming a second dielectric layer on an inner wall of the first contact hole above the cavity, wherein a seam is formed in the second dielectric layer between the inner walls of the cell contact hole; forming a bottom electrode within a portion of the cavity, the bottom electrode contacting a top surface of the electrical contact and a bottom surface of the second dielectric layer and the bottom surface of the seam; and forming a top electrode over the dielectric layer, the top electrode being in direct contact with the top surface of the second dielectric layer and the top surface of the seam.

[0005] According to various embodiments, the semiconductor structure includes at least one memory cell, which includes a transistor and a resistor. The semiconductor structure includes: a transistor comprising a drain, a gate, and a source; and a vertical memory resistor element having first and second electrical contacts. The first or second electrical contact is electrically connected to the drain of the transistor.

[0006] According to an exemplary embodiment, the vertical memory resistor element includes a vertically oriented seam located near the central region of the length of the vertical memory resistor element from the first electrical contact to the second electrical contact. The vertically oriented seam extends from the first electrical contact to the second electrical contact. According to this exemplary embodiment, the vertically oriented seam includes a conductive filament extending from the first electrical contact to the second electrical contact. Attached Figure Description

[0007] The accompanying drawings are provided to further illustrate various embodiments and explain the various principles and advantages of the invention, wherein like reference numerals denote like or functionally similar elements throughout the various views, and the drawings, together with the following detailed description, are incorporated in and form a part of this specification, wherein:

[0008] Figure 1 This is a cross-sectional side view of an example semiconductor structure at a first point in an example manufacturing process for manufacturing a resistive memory device, according to an embodiment of the present invention.

[0009] Figure 2 At a subsequent point in the exemplary manufacturing process Figure 1 A cross-sectional side view of an exemplary semiconductor structure;

[0010] Figure 3 This is at a subsequent point in the example manufacturing process after the vertical unit contact hole is formed. Figure 2 A cross-sectional side view of an example semiconductor structure;

[0011] Figure 4 This occurs at a subsequent point in the exemplary manufacturing process after the vertical access contact hole has been formed. Figure 3 A cross-sectional side view of an exemplary semiconductor structure;

[0012] Figure 5 yes Figure 4 The diagram shows a top view of the semiconductor structure.

[0013] Figure 6 The removal of the a-Si layer at a later point in the example manufacturing process. Figure 4 A cross-sectional side view of an example semiconductor structure;

[0014] Figure 7This refers to a subsequent point in the example fabrication process after atomic layer deposition of the dielectric material used to fill the vertical cell contact holes and the formation of the seam. Figure 6 A cross-sectional side view of an example semiconductor structure;

[0015] Figure 8 At a subsequent point in the exemplary manufacturing process Figure 7 A cross-sectional side view of an exemplary semiconductor structure;

[0016] Figure 9 This refers to a point after the bottom electrode of the resistive memory cell is formed in the example manufacturing process. Figure 8 A cross-sectional side view of an example semiconductor structure;

[0017] Figure 10 This refers to a point after the top electrode of the resistive memory cell is formed in the example manufacturing process. Figure 9 Example cross-sectional side view of a semiconductor structure; and

[0018] Figure 11 This is an operational flowchart illustrating an example manufacturing process for manufacturing a semiconductor structure including resistive memory cells according to an embodiment of the present invention. Detailed Implementation

[0019] It should be understood that the present invention will be described based on exemplary examples of manufacturing processes for fabricating semiconductor structures including field-effect transistor semiconductor devices and / or other types of transistors. However, other semiconductor architectures, structures, substrate materials, and process features and steps may be modified within the scope of the present invention.

[0020] The inventors have found it highly desirable to have resistive random access memory (ReRAM), including conductive bridged random access memory (CBRAM), in which a single filament is formed at a predetermined location within the resistive memory cell.

[0021] Various embodiments of the present invention include new and novel architectures for semiconductor structures comprising at least one non-volatile memory device. The memory device comprises, for example, multiple resistive memory cells (also referred to herein as resistive memory elements) on the same semiconductor substrate on a wafer. This structure can be used, for example, to create CMOS non-volatile memory devices in integrated circuits.

[0022] It will be understood that when an element, such as a layer, region, or substrate, is referred to as "on" or "above" another element, it may be directly "on" or "above" another element, or there may be intermediate elements present. For an element, such as a layer, region, or substrate, being referred to as "below" or "under" another element, a similar but opposite meaning will be understood. It may be directly "below" or "under" another element, or there may be intermediate elements present. Conversely, when an element is referred to as "directly on" or "directly above" or "directly above" another element, or alternatively as "directly below" or "directly under" another element, no intermediate elements are present. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements present. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate elements are present.

[0023] This embodiment may include a design for an integrated circuit chip, which can be created using a graphical computer programming language and stored in a computer storage medium (such as a disk, magnetic tape, physical hard disk, or virtual hard disk such as in a storage access network). If the designer does not manufacture the chip or the photomask used to manufacture the chip, the designer may transfer the resulting design directly or indirectly to such an entity by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., via the Internet). The stored design is then converted into a suitable format (e.g., GDSII) for manufacturing the photomask, which typically includes multiple copies of the chip design in question to be formed on a wafer. The photomask is used to define areas of the wafer (and / or layers on it) to be etched or otherwise processed.

[0024] The methods described herein can be used as part of a process in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer either as bare dies (i.e., as a single wafer with multiple unpackaged chips) or in a package. In the latter case, the chips are mounted in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other more advanced carrier) or a multi-chip package (such as a ceramic carrier with any one or two surface interconnects or buried interconnects). In either case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (such as a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0025] References to this principle in the specification as "one embodiment" or "embodiment" and other variations thereof mean that a particular feature, structure, characteristic, etc., described in connection with that embodiment is included in at least one embodiment of this principle. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout the specification, as well as any other variations, do not necessarily refer to the same embodiment.

[0026] It should be understood that the different layers and / or regions shown in the accompanying drawings are not drawn to scale, and one or more layers and / or regions of the type commonly used in complementary metal-oxide-semiconductor (CMOS), field-effect transistor (FET), metal-oxide-semiconductor field-effect transistor (MOSFET), and / or other semiconductor devices may not be explicitly shown in a given drawing. This does not mean that layers and / or regions not explicitly shown are omitted from the actual device. Furthermore, some elements may be omitted in a particular view for clarity and / or simplicity when the interpretation is not necessarily focused on the omitted elements. Additionally, the same or similar reference numerals used throughout the drawings are used to denote the same or similar features, elements, or structures; therefore, detailed descriptions of the same or similar features, elements, or structures will not be repeated in each drawing.

[0027] Semiconductor devices and methods of forming thereof according to different embodiments of the present invention can be used in applications, hardware, and / or electronic systems. Suitable electronic hardware and systems for implementing embodiments of the present invention may include, but are not limited to, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., cellular and smartphones), solid-state media storage devices, functional circuits, etc. Systems and hardware comprising semiconductor devices and structures are contemplated embodiments of the present invention. Given the teachings of the exemplary embodiments of the present invention provided herein, those skilled in the art will be able to conceive of other implementations and applications of embodiments of the present invention.

[0028] Various embodiments of the present invention can be implemented in conjunction with semiconductor devices and related semiconductor manufacturing processes, which may utilize CMOS, MOSFET, and / or FET technologies. As a non-limiting example, the semiconductor device may include, but is not limited to, CMOS, MOSFET, and FET devices, and / or semiconductor devices using CMOS, MOSFET, and / or FET technologies.

[0029] As used herein, “vertical” means a direction perpendicular to the substrate in any cross-section and three-dimensional view herein. Current may be described herein as flowing in a vertical direction (e.g., between the bottom electrode in a vertically oriented resistive memory cell and the top electrode in a vertically oriented resistive memory cell above the bottom electrode). As used herein, “horizontal” means a direction parallel to the substrate in any cross-section and three-dimensional view herein.

[0030] As used herein, “thickness”, “thickness”, etc., refer to the dimensions of an element (e.g., layer, trench, hole, etc.) in a cross-sectional view measured from the bottom surface of the element to the top surface or from the left surface of the element to the right surface, and / or the dimensions measured relative to the surface directly adjacent to and in contact with the element (e.g., the surface on which the element is directly disposed).

[0031] Furthermore, the terms "width" or "width value" refer to the distance along a critical dimension from the starting point on the structure to the ending point on the same structure. For example, the width value can be measured horizontally along the critical dimension from the starting point of the perpendicularly contacting metal structure to the ending point on the same perpendicularly contacting metal structure.

[0032] Unless otherwise specified, as used herein, "height" or "height above the substrate" refers to the vertical dimension of an element (e.g., layer, trench, hole, etc.) in a cross-sectional view measured from the top surface of the substrate to the top surface of the element. If the element is directly on the substrate, the thickness of the element may be equal to the height of the element.

[0033] As used herein, the terms "transverse," "transverse side," and "transverse surface" refer to the side surface of an element (e.g., a layer, opening, sidewall spacer, etc.), such as the left or right side surface in the cross-sectional view herein.

[0034] Referring now to the accompanying drawings, the same reference numerals denote the same or similar elements. Figures 1-4 This is a cross-sectional side view of a semiconductor structure 100 shown at a selected point in an example manufacturing process. Figure 4 Line 5-5 shown passes over a portion of the illustrated semiconductor structure 100 and corresponds to Figure 5 The diagram shows a top plan view of the semiconductor structure 100. Figures 6-10 This is a cross-sectional side view of the semiconductor structure 100 shown at a subsequent selected point in the example manufacturing process.

[0035] Figure 1 The example semiconductor structure 100 shown herein will be used in this discussion to illustrate example semiconductor manufacturing processes according to various embodiments of the present invention.

[0036] like Figure 1As shown, according to an example semiconductor manufacturing process, a transistor integration manufacturing process forms a transistor supported on a circuit support substrate 102. Figure 1 As shown, the transistor includes a gate stack inserted into and adjacent to a plurality of corresponding source / drain stacks. The gate stack and the plurality of source / drain stacks are formed in a dielectric layer 108 supported by a circuit support substrate 102. It should be noted that the transistor is a non-limiting example of a type of memory cell selector device used in non-volatile random access memory to select at least one memory cell. However, other types of memory cell selector devices can be used according to different embodiments of the invention. For example, a diode can also be used as a memory cell selector device.

[0037] According to different embodiments, substrate 102 includes at least one material selected from the group consisting of: silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), Si:C (carbon-doped silicon), silicon germanium carbide (SiGeC), carbon-doped silicon germanium (SiGe:C), 11I-V compound semiconductor, or 11-V compound semiconductor, organic semiconductor, layered semiconductor, silicon-on-insulator, SiGe-on-insulator, amorphous material, polycrystalline material, single crystal material, or mixed orientation (HOT) semiconductor material, or a combination of materials in the group.

[0038] Each source / drain stack includes a corresponding epitaxial active region 104, 106 in the substrate 102. Each source / drain stack includes source / drain metals 114, 116 and top metal contacts 118, 120 respectively disposed above the source / drain metals 114, 116.

[0039] The gate stack can be located above the corresponding fin channels in the substrate 102. For example, Figure 1 The fin channel is located in the substrate 102, below the gate stack, and adjacent to and in contact with the two epitaxial active regions 104, 106 of the transistor, forming a path for current to pass horizontally between the two epitaxial active regions 104. Figure 1 The gate stack shown in the example includes a high-K dielectric layer 112 and a gate metal contact 110 disposed on the high-K dielectric layer 112 and in contact with its top surface. Figure 1 The examples shown represent NFET or PFET transistors. It should be noted that the discussion herein provides non-limiting examples for illustrating various aspects of embodiments of the invention. The example transistors discussed herein do not necessarily represent actual circuit layouts. The exemplary transistors are provided merely to illustrate that exemplary process flows according to embodiments of the invention can function for either or both of NFET and PFET circuit elements.

[0040] The target metal contact (also referred to as the target electrical contact) 124 formed in the interlayer dielectric (ILD) layer 122 is electrically connected, according to an example, to a first drain / source metal contact 114 or a second drain / source metal contact 116, or, according to different embodiments, to a combination of the first set of drain / source metal contacts 114 and 118 or a combination of the second set of drain / source metal contacts 116 and 120. According to this example, the target metal contact 124 is electrically connected to... Figure 1 The drain contact 116 of the transistor drain active region 106 shown is (e.g., a second set of drain / source metal contacts 116, 120). In this discussion of the example manufacturing process, the target metal contact 124 may also be referred to as the drain contact 124. However, it should be understood that, according to different embodiments, any combination of the transistor's metal contacts can be electrically coupled to the target metal contact 124.

[0041] Furthermore, as described above, a transistor is one example type of memory selector device that can be used according to different embodiments. Alternatively or additionally, other types of selector devices can be used to select at least one memory cell in a non-volatile memory device. Generally, the selector device contacts are electrically connected to the target metal contacts 124. The selector device can be electrically controlled to select a specific memory cell in the non-volatile memory device.

[0042] Figure 1 Points in an example semiconductor manufacturing process are shown, wherein semiconductor material stacks 102, 108, and 122 are provided, including a substrate 102, a gate stack, and multiple drain / source stacks. Subsequently, as... Figure 1 As shown, an amorphous silicon (a-Si) sacrificial layer 126 has been deposited on the ILD layer 122 located on the dielectric layer 108, followed by a planarization process, such as a chemical and / or mechanical planarization (CMP) step or an etching step, which removes excess material from the top surface of the a-Si sacrificial layer in the semiconductor structure 100, and optionally removes excess material from the top surface of the wafer. The a-Si layer 126 may also be referred to as the sacrificial layer 126 because it will be removed in downstream manufacturing process steps.

[0043] refer to Figure 2 Then, the a-Si layer 126 is patterned into a circle (or rectangle or other shape). A silicon dioxide (SiO2) layer 202, also known as the ILD layer 202 or the first dielectric layer 202, is deposited on the patterned a-Si layer 126 and contacts the top surface of the patterned a-Si layer 126, such as... Figure 2As shown. According to different embodiments, the first dielectric layer 202 comprises at least one dielectric material selected from the group consisting of: silicon nitride (SiN), silicon carbide (SiC), SiCO, silicon oxide, silicon dioxide (SiO2), carbon-doped silicon oxide (SiCOH), one or more silicon-based materials in which some or all of Si are replaced by Ge, carbon-doped oxides, inorganic oxides, inorganic polymers, hybrid polymers, organic polymers such as polyamides or SiLK. TM Other carbon-based materials, organic and inorganic materials such as spin-coated glass and silsesquioxane materials, diamond-like carbon (DLC), also known as amorphous hydrogenated carbon (α-C:H), or any of the aforementioned materials in a porous form, or in a form that becomes porous and / or permeable to non-porous and / or impermeable during processing.

[0044] In the SiO2 layer 202 (also called the ILD layer 202), a vertically oriented cell contact hole 302 (which can also be called a vertical cell contact hole 302, etc.) is formed above the a-Si layer 126 and continuing downward to the bottom surface of the a-Si layer 126, or continuing slightly through the a-Si layer 126. Figure 3 As shown. Vertically oriented cell contact holes 302 can be formed using a vertical etching process (e.g., but not limited to dry etching or reactive ion etching (RIE) using fluoride-based chemicals) or another etching process. According to this example, the vertically oriented cell contact holes 302 expose the drain contact 124 within the vertical cell contact holes 302. However, the cell contact holes 302 are located above the drain contact 124, but not necessarily directly above it (e.g., vertically aligned with the drain contact 124). The cell contact holes 302 may be located at a horizontal position in the a-Si layer 126, close to the horizontal position of the drain contact 124, but not necessarily directly above it.

[0045] Continue this manufacturing process, such as Figure 4As shown, in the SiO2 layer 202 (which may also be referred to as the ILD layer 202 or the first dielectric layer 202, etc.), vertically oriented access contact holes 402 (which may also be referred to herein as vertical access contact holes 402, etc.) are patterned directly above the sacrificial a-Si layer 126 and continuing downwards into or through the bottom surface of the sacrificial a-Si layer 126. The horizontal critical dimension (CD) of the vertically oriented access contact holes 402 can be much larger than the horizontal CD of the vertically oriented unit contact holes 302. The vertically oriented access contact holes 402 can be formed by a vertical etching process, such as, but not limited to, a dry etching process or a reactive ion etching (RIE) process using fluoride-based chemicals, or another etching process.

[0046] A vertically oriented access contact hole 402 creates an access opening into the sacrificial a-Si layer 126, wherein the access opening 402 can have a much larger horizontal CD than the horizontal CD of a vertically oriented unit contact hole 302. For example, the vertically oriented access contact hole 402 can be used to facilitate an etching process to remove the sacrificial a-Si layer 126, thereby forming a void opening or cavity 602 after the removal of the sacrificial a-Si layer 126, such as... Figure 6 As shown. The vertically oriented access contact hole 402 also facilitates the access of the gap opening or cavity 602 in downstream manufacturing process steps. As will be discussed in more detail below, according to different embodiments, the vertically oriented access contact hole 402 facilitates the access of the gap opening or cavity 602 to form a vertical memory cell 802 (see...). Figure 8 , 9 The bottom electrode 902 of 10) and the vertical memory cell 802 are formed in the vertically oriented cell contact hole 302.

[0047] It should be noted that although the formation of the vertically oriented access contact hole 402 and the vertically oriented unit contact hole 302, which are independent of each other, are described above, according to various embodiments, the formation of these two holes 302, 402 can be performed simultaneously or independently of each other.

[0048] Figure 5 A top plan view of the semiconductor structure 100 at this point in an example semiconductor manufacturing process is shown. According to this example, the vertical access contact hole 402 and the vertical cell contact hole 302 are close to each other in the horizontal direction, both directly above the a-Si sacrificial layer 126.

[0049] Continuing with examples of semiconductor manufacturing processes, such as Figure 6As shown, the a-Si sacrificial layer 126 is then completely removed by a selective isotropic etching process. The selective wet etching process can be performed, for example, by an isotropic etching process. Alternatively, etching can be performed by another suitable wet or dry etching process. The selective etching leaves a void space 602 (also referred to as a cavity 602, etc.) in which material from the a-Si sacrificial layer 126 is removed. This cavity 602 connects the bottom opening of the vertically oriented cell contact hole 302 and the bottom opening of the vertically oriented access contact hole 402.

[0050] refer to Figure 7 The example semiconductor manufacturing process continues by performing atomic layer deposition (ALD) of dielectric material 702 on the exposed surfaces in the semiconductor structure 100 (e.g., applying and forming dielectric material 702 on the inner sidewalls of vertical cell contact holes 302). Sequential layers of dielectric material 702 (e.g., each layer approximately 15 nm thick) are progressively and sequentially applied to and formed on the exposed surfaces in the semiconductor structure 100. According to the example, the formed dielectric material 702 fills the vertical cell contact holes 302. See also... Figure 8 .

[0051] In this example, the dielectric material 702 filling the vertical cell contact hole 302 includes the portion adjacent to the vertical memory cell 802 (see, for example, see...). Figure 8 and Figure 10 It shows the fabrication of the vertical memory cell 802, in Figure 10 The vertical seam 704 is located in the central region (horizontally centered relative to the sidewall of the vertically oriented unit contact hole 302) of the top electrode 1004 and bottom electrode 902. As an example, the dielectric material 702 (which may also be referred to as the second dielectric layer 702) may comprise a metal having an oxide. As another example, the second dielectric layer 702 may comprise a metal having a nitride. According to various embodiments, the second dielectric layer 702 comprises at least one dielectric material selected from the group consisting of: metal oxides, metal nitrides, silicon dioxide (SiO2), silicon nitride (SiN), silicon carbonitride oxynitride (SiOCN), carbon-doped silicon nitride (SiCN), or boron-doped silicon carbonitride (SiBCN), or any combination of the above dielectric materials.

[0052] According to this example, the dielectric material 702 is applied as an exposed surface in the void space 602, the exposed surface in the vertical cell contact hole 302 (e.g., on the inner sidewall of the vertical cell contact hole 302), the exposed surface in the vertical access contact hole 402 (e.g., on the inner sidewall of the vertical access contact hole 402), and the exposed surface on the top surface of the semiconductor structure 100 using an ALD process.Figure 7 As shown. According to this example, the thickness of each layer of dielectric material 702 applied by the ALD process can be approximately 15 nm. However, according to various embodiments, other layer thicknesses can be applied. The thin film layers 702 of dielectric material are progressively and sequentially applied to and formed on the exposed surfaces of the semiconductor structure 100. According to the example, after the film layers are applied sequentially on top of each other, the overall thickness of the applied dielectric material film 702 is increased until an overall film thickness of approximately half the diameter of the vertical cell contact hole 302 is reached. This film deposition process adds a layer on top of the film layers of dielectric material 702 until it clamps off any further application of the film layers of dielectric material 702 in the vertical cell contact hole 302. This film deposition process also forms a vertical seam 704 in the dielectric material layer 702 in the vertical cell contact hole 302.

[0053] As a result of the ALD process and / or another thin-film deposition process, a vertical seam 704 is formed in a second dielectric layer 702 within the vertical cell contact hole 302, filling the vertical cell contact hole 302 with progressively applied sequential dielectric material layers 702. According to an example, the vertical seam 704 is formed near the central region of the dielectric material 702 (horizontally centered relative to the sidewalls of the vertically oriented cell contact hole 302), which fills the vertical cell contact hole 302. Also see the vertical memory cell 802, which includes... Figure 8 The vertical seam 704 is shown with its center positioned.

[0054] In this example, the ALD process is used because it reliably forms a uniform seam in the middle of the vertical unit contact hole 302. Although, according to this example, the ALD process is used to apply a thin film layer of the dielectric material 702 as described above and to form the vertical seam 704, other thin film deposition processes may alternatively or additionally be used to apply the thin film layer of the dielectric material 702 and / or to form the vertical seam 704. A possible example deposition process is chemical vapor deposition (CVD). Another possible example deposition process is physical vapor deposition (PVD).

[0055] The ALD process for progressively applying a sequential layer of dielectric material 702 filling the vertical cell contact holes 302 can be, for example, a thermal ALD process. As another example, the ALD process can be a plasma-assisted ALD process. According to various embodiments, the dielectric material layer 702 filling the vertical cell contact holes 302 comprises at least one dielectric material selected from the group consisting of: metal oxides, metal nitrides, silicon dioxide (SiO2), silicon nitride (SiN), carbon-doped silicon oxynitride (SiOCN), carbon-doped silicon nitride (SiCN), boron and carbon-doped silicon nitride (SiBCN), or any combination of the above dielectric materials.

[0056] The vertical seam 704 is formed near the central region of the dielectric material 702 (horizontally centered relative to the sidewall of the vertically oriented cell contact hole 302) by an ALD process, wherein, according to an example, the dielectric material fills the vertical cell contact hole 302. According to different embodiments, the vertical seam 704 may be doped with a conductive material to form a single conductive (e.g., resistive) filament (see [reference needed]) at a known location extending vertically within the top electrode 1004 to the bottom electrode 902 of the vertical memory cell 802. Figure 8 and Figure 10 , Figure 8 and Figure 10 The fabrication of the vertical memory cell 802 is shown. Figure 10 It includes a top electrode 1004 and a bottom electrode 902.

[0057] This single conductive (resistive) filament arrangement can provide significant advantages for non-volatile memories (e.g., resistive random access memory (ReRAM)), including conductive bridged random access memory (CBRAM). In non-volatile memory devices, according to various embodiments, memory cell-to-memory cell operations can be reliably and uniformly fabricated across the memory cells in the non-volatile memory device. This results in superior overall performance of the non-volatile memory device. For each vertical memory cell 802 (see...) Figure 8 and Figure 10 The monofilament arrangement brings determinism to filament formation and device operation in non-volatile memory devices. The reliability of operation of such non-volatile memory devices (e.g., ReRAM memory devices) is significantly improved. This, in turn, significantly increases the commercial viability of this type of resistive non-volatile memory device and the associated semiconductor manufacturing processes.

[0058] Continuing with examples of semiconductor manufacturing processes, such as Figure 8 As shown, optionally, excess dielectric material 702 is removed from the void space 602, from the vertical access contact hole 402, and from the top surface of the semiconductor structure 100, such as... Figure 8As shown. Excess dielectric material 702 can be removed using an isotropic etching process (dry or wet, or a combination of dry and wet etching). The dielectric material 702 filling the vertical cell contact holes 302 will not be removed. Figure 8 As shown, the top and bottom surfaces of the vertical seam 704, located near the central region of the vertical memory cell 802 (horizontally centered relative to the sidewall of the vertically oriented cell contact hole 302), will be exposed at the top and bottom openings of the vertical cell contact hole 302. According to different embodiments, this vertical seam 704 may be doped with the vertical memory cell 802 within the vertical cell contact hole 302 (see [link to documentation]). Figure 8 Conductive material forming a single conductive (e.g., resistive) filament at a known location within the )

[0059] The seam 704 can be doped with a mobile element such as copper (Cu) or silver (Ag) (e.g., a metallic mobile material) to improve the switching characteristics of the filament 704 in the vertical memory cell 802. For example, this doping can involve injecting a metallic mobile material into the seam 704 to aid in the formation of the filament 704. Different methods exist for performing doping on the seam 704. For example, doping can be performed using electrodes 902 or 1004 containing dopant.

[0060] As another example, doping can also be done in Figure 9 After that and Figure 10 This was carried out in the manufacturing process of previous examples. (Refer to...) Figure 10 After the dielectric plug material 1002 is formed, the dopant material can be deposited and driven into the seam 704 by thermal annealing. After the dopant is driven into the seam 704, the dopant on the surface is removed, leaving only the dopant in the seam 704.

[0061] The following text will refer to Figure 10 The top electrode 1004 of the vertical memory cell 802 discussed (see...) Figure 10 The top electrode 1004 is formed directly on and in contact with the top surface of the vertical memory cell 802 and the top surface of the vertical seam (and filament) 704. According to different embodiments, the top electrode 1004 may also be a dopant for doping movable elements (e.g., movable metallic materials) into the vertical seam (and filament) 704. For example, according to some embodiments, after a metal such as copper (Cu) is deposited on and in contact with the top surface of the vertical seam (and filament) 704 to form the top electrode 1004 of the vertical memory cell 802, copper atoms can diffuse downwards and migrate from the top electrode 1004 into the vertical seam (and filament) 704.

[0062] like Figure 9As shown, conductive material 902 can be deposited in the vertically oriented access contact 402 to fill the vertical memory cell 802 (see Figure 1). Figure 8 The gap space 602 below the vertical memory cell 802 contacts the bottom surface of the vertical memory cell 802 and the vertical seam 704, thereby forming the bottom electrode 902 of the vertical memory cell 802. The bottom electrode 902 of the vertical memory cell 802 is formed directly on and in contact with the top surface of the target metal contact 124 (e.g., the drain contact 124 of a transistor). Figure 9 As shown, conductive material 902 can partially (or completely) fill the vertical access contact hole 402, and excess conductive material 902 can be deposited directly on and in contact with the top surface of the semiconductor structure 100. The deposition of conductive material 902 can be achieved through a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process, or through another conductive material deposition process, or any combination of processes, which allows conductive material 902 to fill the void space 602 below the vertical memory cell 802 (see...). Figure 8 This forms the bottom electrode 902 of the vertical storage cell 802.

[0063] Continuing with examples of semiconductor manufacturing processes, such as Figure 10 As shown, conductive material 902 is removed from the vertical access contact hole 402 and from the top surface of the semiconductor structure 100. As an example, a dry etching process (such as a reactive ion etching (RIE) process using fluoride-based chemicals) can vertically etch the conductive material 902 from the vertical access contact hole 402. A dry etching process, or alternatively combined with a suitable wet etching process, can be used to remove the conductive material 902 from the top surface of the semiconductor structure 100. The gap filler of the dielectric material in the vertical access contact hole 402 forms a dielectric material plug 1002 filling the vertical access contact hole 402. The bottom electrode 902 maintains electrical contact with the bottom surface of the vertical memory cell 802, the bottom surface of the vertical seam 704, and the top surface of the target metal contact 124 (e.g., the drain contact 124 of a transistor).

[0064] like Figure 10 As shown, the example semiconductor manufacturing process then performs the deposition of a conductive material, optionally followed by patterning, which forms a top electrode 1004 above the dielectric layer 702 and above and in direct contact with the top surface of the vertical seam 704 (see [link to documentation]). Figure 8 The vertical memory cell 802 shown. According to the example manufacturing process, the top electrode 1004 contacts the top surface of the vertical seam (and filament) 704 near the central region of the vertical memory cell 802 (horizontally centered relative to the sidewall of the vertically oriented cell contact hole 302).

[0065] The top electrode 1004 of the vertical memory cell 802, which is formed directly on the top surface of the vertical joint (and filament) 704 and contacts the top surface of the vertical joint (and filament) 704 (see [reference]). Figure 10 It can also act as a dopant for adding movable elements (e.g., movable metallic materials) to the vertical seam (and filament) 704. For example, according to some embodiments, after a conductive material (such as, but not limited to, copper (Cu) or silver (Ag) or another metal) is deposited on the top surface of the vertical seam (and filament) 704 to form a top electrode 1004, conductive material atoms (e.g., copper atoms) can diffuse downwards and migrate from the top electrode 1004 into the vertical seam (and filament) 704, thereby doping the vertical seam (and filament) 704 with conductive material atoms (e.g., with copper atoms).

[0066] Independent of using the top electrode 1004 (and / or bottom electrode 902) as a dopant, conductive material may be used as a dopant for doping the vertical seam (and filament) 704, depending on the doping process. The conductive material may be added as a dopant for doping the vertical seam (and filament) 704 via a separate doping process as part of the overall semiconductor manufacturing process, as discussed above. By way of example and not limitation, the conductive material used for doping the vertical seam (and filament) 704 may include mobile elements (e.g., metallic mobile materials), or non-stoichiometric compounds obtained by adding reactive elements, or combinations thereof. A non-stoichiometric compound refers to a compound comprising amounts of reactants that are not in a simple integral ratio or a ratio expected from an ideal chemical formula or equation. For example, TiO2 is stoichiometric titanium dioxide. However, TiOx (where x is less than or greater than 2) should be understood to represent non-stoichiometric titanium oxide.

[0067] As another example, the vertical seam 704 may be doped with a conductive material selected from the group consisting of: metal oxides, non-conductive metal nitrides, copper (Cu), titanium (Ti), aluminum (Al), hafnium (Hf), or lanthanum (La). Seam 704 may therefore contain a material selected from the group consisting of: metal oxides, non-conductive metal nitrides, copper (Cu), titanium (Ti), aluminum (Al), hafnium (Hf), or lanthanum (La). As another example, seam 704 may be doped with at least one of a mobile element or a non-stoichiometric compound by adding a reactive element.

[0068] According to various embodiments, the second dielectric layer 702, formed in the vertically oriented cell contact holes 302 by an ALD process to generate the vertical memory resistive element 802, comprises at least one material selected from the group consisting of: metal oxides, non-conductive metal nitrides, silicon oxide, silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride, silicon carbonitride (SiOCN), carbon-doped silicon nitride (SiCN), or silicon boron carbonitride (SiBCN), or any combination of the above materials. The formed second dielectric layer 702 may also contain a material selected from the group consisting of: metal oxides, non-conductive metal nitrides, aluminum (Al), hafnium (Hf), zirconium (Zr), titanium (Ti), silicon (Si), germanium (Ge), copper (Cu), or lanthanum (La).

[0069] According to different embodiments, the top electrode 1004 or the bottom electrode 902 (see...) Figure 10 At least one of the following includes a conductive material selected from the group consisting of copper (Cu), cobalt (Co), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), hafnium (Hf), zirconium (Zr), nickel (Ni), platinum (Pt), tin (Sn), silver (Ag), gold (Au), conductive metal compound materials, or conductive metal alloys comprising at least one of the aforementioned conductive materials. According to different embodiments, the vertical seam 704 may include a single conductive filament 704 extending from the top electrode 1004 to the bottom electrode 902.

[0070] Figure 11 An exemplary method 1100 for manufacturing a semiconductor structure including vertical memory cells electrically connected to transistor devices on a substrate is shown. Various embodiments of the invention may include, but are not necessarily all, of the method steps shown in the examples.

[0071] The example manufacturing method proceeds to step 1102 and immediately continues to step 1104 to receive a semiconductor substrate material stack, which includes a substrate 102 supporting a gate stack for transistors and a first source / drain stack and a second source / drain stack for transistors. The gate stack is adjacent to and between the first and second source / drain stacks in a dielectric layer 108. The gate stack includes a gate metal contact 110. The first source / drain stack includes drain metal contacts 116 and 120. The second source / drain stack includes source metal contacts 114 and 118. An ILD layer 122 is directly above the dielectric layer 108. A target metal contact 124 is located in the ILD layer 122.

[0072] In step 1106, the semiconductor manufacturing method continues by depositing an a-Si layer 126 directly on and in contact with the top surface of the ILD layer 122. The a-Si layer is patterned to form the a-Si layer 126 directly on and in contact with the top surface of the target metal contact 124 of the transistor. According to an example, the target metal contact 124 includes at least one of drain metal contacts 116, 120 or source metal contacts 114, 118, and is electrically coupled to them. A first dielectric layer 202 is deposited on the a-Si layer 126. Vertical etching patterning is performed through the first dielectric layer 202 and into the vertical cell contact vias 302 and 402 of the a-Si layer 126. According to an example, the vertical cell contact vias 302 and 402 are horizontally close to each other directly above the a-Si layer 126.

[0073] In step 1108, the semiconductor manufacturing process continues by removing the a-Si layer 126. Then, an ALD (Alternating Deposition) of the dielectric material 702 is performed to fill the vertical cell contact holes 302 and form a vertical seam 704 near the central region of the memory cell 802 formed in the vertical cell contact holes 302. The ALD process also applies the dielectric material 702 to other exposed surfaces in the dielectric structure 100. The semiconductor manufacturing process then continues by performing isotropic etching to remove excess dielectric material 702 from the semiconductor structure 100, thereby exposing the seam 704 and leaving a void space 602 (where the a-Si layer 126 is removed). The semiconductor manufacturing process performs doping of a movable metal material into the seam 704. Then, a conductive material 902 is deposited in the void space 602, followed by isotropic etching, thereby forming the bottom electrode 902 of the memory cell 802. The bottom electrode 902 is electrically connected to the top surface of the target metal contact 124 and the bottom surface of the memory cell 802 and the bottom surface of the seam 704.

[0074] In step 1110, a dielectric plug 1002 is generated by performing dielectric material gap-filling deposition in the vertical access contact hole 402, and the semiconductor manufacturing method continues. The method then performs deposition of a conductive material layer 1004 on the top surface of the memory cell 802 and the top surface of the seam 704, and contacts the top surface of the memory cell 802 and the top surface of the seam 704, and then patterns it to form the top electrode 1004 of the memory cell 802.

[0075] Then exit the manufacturing method in step 1112.

[0076] The design of resistive nonvolatile memory devices (e.g., ReRAM memory devices) according to various embodiments includes a plurality of vertical memory cells 802, wherein each memory cell 802 includes a single vertical conductive seam 704. This can significantly improve the reliability of the operation of the nonvolatile memory device. Cell-to-cell operation can be reliably and uniformly fabricated across the memory cells in the nonvolatile memory device, resulting in superior overall performance of the nonvolatile memory device. The monofilament arrangement for each vertical memory cell 802 brings determinism to filament formation and device operation in the nonvolatile memory device. According to various embodiments, this can also reduce manufacturing process defects and lower the manufacturing cost of semiconductor products. This, in turn, significantly increases the commercial viability of this type of resistive nonvolatile memory device and the associated semiconductor manufacturing processes.

[0077] While specific embodiments of the invention have been disclosed, those skilled in the art will understand that changes can be made to these specific embodiments without departing from the scope of the invention. Therefore, the scope of the invention is not limited to the specific embodiments, and the appended claims are intended to cover any and all such applications, modifications, and embodiments within the scope of the invention.

[0078] It should be noted that some features of the present invention may be used in one embodiment without using other features of the invention. Therefore, the foregoing description should be considered merely as illustrative of the principles, teachings, examples, and exemplary embodiments of the invention, and not as limiting the invention.

[0079] Furthermore, these embodiments are merely examples of the many advantageous uses of the innovative teachings herein. In general, the statements made in this application's specification do not necessarily limit any of the claimed inventions. Moreover, some statements may apply to certain inventive features but not others.

Claims

1. A method of fabricating a semiconductor structure comprising at least one resistive memory cell, the method comprising: forming a dielectric layer on inner sidewalls of a cell contact hole over a cavity in the semiconductor structure, wherein a seam is formed in the dielectric layer between the inner sidewalls of the cell contact hole; forming a bottom electrode within a portion of the cavity, the bottom electrode in contact with a top surface of a target electrical contact and with a bottom surface of the dielectric layer and a bottom surface of the seam; and forming a top electrode over the dielectric layer and in direct contact with a top surface of the dielectric layer and a top surface of the seam.

2. The method of claim 1, further comprising: forming a sacrificial layer on and in contact with the target electrical contact; forming a second dielectric layer over and in contact with the sacrificial layer; forming the cell contact hole through the second dielectric layer and exposing a first portion of the sacrificial layer; forming an access contact hole through the second dielectric layer and exposing a second portion of the sacrificial layer; and removing a remaining portion of the sacrificial layer, thereby forming the cavity directly connecting a bottom opening of the cell contact hole and a bottom opening of the access contact hole. forming the dielectric layer by atomic layer deposition of a dielectric material on the inner sidewalls of the cell contact hole located over the cavity, and wherein the seam in the dielectric layer is formed by atomic layer deposition of the dielectric material. the seam is formed vertically oriented and located near a central region of the dielectric layer between the inner sidewalls of the cell contact hole over the cavity.

3. The method of claim 1, wherein, the dielectric layer comprises at least one material selected from the group consisting of:

4. The method of claim 1, wherein, a metal oxide, a non-conductive metal nitride, silicon oxide, silicon dioxide (Si02), silicon nitride (SiN), silicon oxynitride, silicon carbon oxynitride (SiOCN), carbon doped silicon nitride (SiCN), or silicon boron carbon nitride (SiBCN), or any combination of the above.

5. The method of claim 1, wherein, the dielectric layer comprises at least one material selected from the group consisting of: a metal oxide, a non-conductive metal nitride, aluminum (Al), hafnium (Hf), zirconium (Zr), titanium (Ti), silicon (Si), germanium (Ge), copper (Cu), or lanthanum (La).

6. The method of claim 1, wherein, 7. The method of claim 1, further comprising: doping the seam with at least one of a metal element and a non-stoichiometric compound by adding an active element.

8. The method of claim 1, further comprising: doping the seam with a conductive material selected from a group of conductive materials consisting of copper (Cu), titanium (Ti), aluminum (Al), hafnium (Hf), or lanthanum (La). the seam comprises a conductive filament extending from the top electrode to the bottom electrode. the top electrode, the dielectric layer, the seam comprising a conductive filament, the bottom electrode, and the target electrical contact collectively form a resistive memory cell in a semiconductor structure fabricated according to the method.

9. The method of claim 1, wherein, the seam comprises a conductive filament extending from the top electrode to the bottom electrode.

10. The method of claim 1, wherein, the top electrode, the dielectric layer, the seam comprising a conductive filament, the bottom electrode, and the target electrical contact collectively form a resistive memory cell in a semiconductor structure fabricated according to the method.

11. The method of claim 1, wherein, At least one of the top electrode or the bottom electrode includes a conductive material selected from a group of conductive materials consisting of: copper (Cu), cobalt (Co), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), hafnium (Hf), zirconium (Zr), nickel (Ni), platinum (Pt), tin (Sn), silver (Ag), gold (Au), a conductive metal compound material, or a conductive metal alloy including at least one of the foregoing conductive materials.

12. A semiconductor structure comprising at least one memory cell comprised of a transistor and a resistor, the semiconductor structure comprising: a target metal contact; and a vertical memory resistive element having a first electrical contact and a second electrical contact, and including a vertically oriented junction extending from the first electrical contact to the second electrical contact, one of the first and second electrical contacts being electrically connected to the target metal contact, wherein the vertical memory resistive element includes a dielectric material formed within and filling a vertical cell contact hole in a dielectric layer of the semiconductor structure, the vertically oriented junction being surrounded by and in direct contact with the dielectric material forming the vertical memory resistive element, and the vertically oriented junction includes at least one conductive material selected from a group of conductive materials consisting of: a doped metal element and a doped non-stoichiometric compound including a reactive element.

13. The semiconductor structure of claim 12, wherein the vertically oriented junction is located near a central region of a length of the vertical memory resistive element extending from the first electrical contact to the second electrical contact, and wherein the target metal contact is electrically connected to a memory cell selector device.

14. The semiconductor structure of claim 12, wherein, The vertically oriented junction includes at least one material selected from a group of materials consisting of: a metal oxide, a non-conductive metal nitride, copper (Cu), titanium (Ti), aluminum (Al), hafnium (Hf), or lanthanum (La).

15. The semiconductor structure of claim 12, wherein, The vertical memory resistive element includes at least one material selected from a group of materials consisting of: a metal oxide, a non-conductive metal nitride, aluminum (Al), hafnium (Hf), zirconium (Zr), titanium (Ti), silicon (Si), germanium (Ge), copper (Cu), or lanthanum (La).

16. The semiconductor structure of claim 12, wherein, The vertical memory resistive element includes at least one material selected from a group of materials consisting of: a metal oxide, a metal nitride, silicon dioxide (SiO2), silicon nitride (SiN), silicon oxycarbonitride (SiOCN), carbon-doped silicon nitride (SiCN), or boron-doped silicon carbonitride (SiBCN), or any combination of the foregoing materials.

17. The semiconductor structure of claim 12, wherein, The vertically oriented junction includes a single conductive filament extending from the first electrical contact to the second electrical contact.

18. A method of fabricating a semiconductor structure including at least one resistive memory cell, the method comprising: A semiconductor material stack is provided, the semiconductor material stack comprising: a substrate; a gate stack comprising a gate metal contact; a first source-drain stack comprising a first source / drain metal contact; and a second source-drain stack comprising a second source / drain metal contact, the substrate supporting the gate stack and the first and second source-drain stacks; performing deposition of an amorphous silicon (a-Si) layer directly on and in contact with a top surface of a target metal contact, the target metal contact being electrically connected to at least one of: the first source / drain metal contact, or the second source / drain metal contact; performing deposition of an interlayer dielectric (ILD) layer directly on and in contact with a top surface of the a-Si layer; performing vertical direction etching in the ILD layer from its top surface down to at least a bottom surface thereof, forming a vertical cell contact hole in the ILD layer, thereby exposing the a-Si layer in the vertical cell contact hole; performing vertical direction etching in the ILD layer from its top surface down to at least a bottom surface thereof, forming a vertical access contact hole in the ILD layer, and exposing the a-Si layer in the vertical access contact hole, the vertical access contact hole being positioned horizontally proximate to the vertical cell contact hole; performing isotropic etching to remove the a-Si layer, thereby leaving a void space; performing atomic layer deposition of a dielectric material, filling the vertical cell contact hole in the ILD layer and forming a vertical seam in a vicinity of a center of a vertical memory cell formed in the vertical cell contact hole; performing deposition of a conductive material in the vertical access contact hole, the conductive material filling the vertical access contact hole and the void space, thereby forming a bottom electrode of the vertical memory cell on a top surface of the target metal contact, the bottom electrode directly contacting the top surface of the target metal contact and contacting a bottom surface of the vertical memory cell and the vertical seam; and performing deposition of a conductive material on and in contact with a top surface of the vertical memory cell and the vertical seam, thereby forming a top electrode of the vertical memory cell.

19. The method of claim 18, further comprising: doping the vertical seam with a conductive material selected from a group of conductive materials consisting of copper (Cu), titanium (Ti), aluminum (Al), hafnium (Hf), or lanthanum (La).

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