Display substrate and manufacturing method thereof, and display device

Abstract

A display substrate, a method for manufacturing the same, and a display device. The display substrate comprises a display area including an opening and first and second display areas located on either side of the opening. The peripheral area includes an opening peripheral area at least partially located within the opening. The display substrate further comprises a first routing line and a second routing line disposed on the same layer; the first routing line and the second routing line sequentially extend through the first display area, the opening peripheral area, and the second display area. Within the opening peripheral area, the first routing line includes a first bend, and the second routing line includes a second bend; the first and second bends are arranged side by side along a first direction. This routing arrangement of the display substrate can reduce routing space, enabling a narrow-frame design.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate, a method for manufacturing the same, and a display device. Background Art

[0002] Currently, display screens of display devices are developing towards larger and full-screen displays. Typically, display devices (such as mobile phones and tablets) include a camera (or imaging device), which is typically located on a side outside the display area of ​​the display screen. However, since the camera requires a specific location for installation, this is not conducive to the full-screen, narrow-frame design of the display screen. For example, the camera can be integrated with the display area of ​​the display screen, with a reserved space for the camera in the display area to maximize the display area of ​​the display screen. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a display substrate, which includes a display area and a peripheral area at least partially surrounding the display area; wherein the display area includes an opening and a first display area and a second display area located on opposite sides of the opening, the first display area, the opening and the second display area are arranged in sequence along a first direction, and the peripheral area includes an opening peripheral area at least partially located in the opening; the display substrate also includes a first routing line and a second routing line arranged in the same layer, the first routing line and the second routing line are configured to transmit electrical signals for the display area; the first routing line and the second routing line sequentially pass through the first display area, the opening peripheral area and the second display area; in the opening peripheral area, the first routing line includes a first bending portion, the second routing line includes a second bending portion, and the first bending portion and the second bending portion are arranged side by side along the first direction.

[0004] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first bending portion includes at least one S-shaped bending portion; or the second bending portion includes at least one S-shaped bending portion; or the first bending portion and the second bending portion both include at least one S-shaped bending portion.

[0005] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first display area and the second display area include multiple rows of sub-pixels separated by the opening, the first wiring provides a scanning signal for a first row of sub-pixels arranged along the first direction in the first display area and the second display area, and the second wiring provides a scanning signal for a second row of sub-pixels arranged along the first direction in the first display area and the second display area.

[0006] For example, in the display substrate provided in at least one embodiment of the present disclosure, the opening peripheral area also includes a semiconductor pattern and a conductive pattern; the semiconductor pattern is located on the base substrate, the first routing line and the second routing line are located on the side of the semiconductor pattern away from the base substrate, and the conductive pattern is located on the side of the first routing line and the second routing line away from the semiconductor pattern; in a direction perpendicular to the base substrate, the first routing line is insulated from at least one of the semiconductor pattern and the conductive pattern so as to form a capacitor, and the second routing line is insulated from at least one of the semiconductor pattern and the conductive pattern so as to form a capacitor.

[0007] For example, in the display substrate provided in at least one embodiment of the present disclosure, in a direction perpendicular to the base substrate, the first bent portion of the first trace is insulated from at least one of the semiconductor pattern and the conductive pattern to form a capacitor, and the second bent portion of the second trace is insulated from at least one of the semiconductor pattern and the conductive pattern to form a capacitor.

[0008] For example, the display substrate provided by at least one embodiment of the present disclosure also includes a third routing line arranged on the same layer as the first routing line and the second routing line, and the third routing line sequentially passes through the first display area, the opening peripheral area and the second display area, and the third routing line extends along the first direction to provide a scanning signal for the third row of sub-pixels arranged along the first direction in the first display area and the second display area, and the third routing line is insulated from at least one of the semiconductor pattern and the conductive pattern to form a capacitor.

[0009] For example, in the display substrate provided by at least one embodiment of the present disclosure, the number of sub-pixels included in the third row of sub-pixels is greater than the number of sub-pixels included in the first row of sub-pixels; or the number of sub-pixels included in the third row of sub-pixels is greater than the number of sub-pixels included in the second row of sub-pixels; or the number of sub-pixels included in the third row of sub-pixels is greater than the number of sub-pixels included in the first row of sub-pixels and also greater than the number of sub-pixels included in the second row of sub-pixels.

[0010] For example, in the display substrate provided in at least one embodiment of the present disclosure, the display area also includes a third display area, and two opposite edges of the third display area in a second direction perpendicular to the first direction are respectively aligned with an edge of the first display area in the second direction away from the opening and an edge of the second display area in the second direction away from the opening, and the third display area includes sub-pixels arranged in multiple rows and columns, and also includes multiple fourth lines extending along the first direction for providing scanning signals to each row of sub-pixels in the multiple rows and columns.

[0011] For example, in the display substrate provided by at least one embodiment of the present disclosure, the number of sub-pixels included in each row of sub-pixels in the multiple rows and columns of sub-pixels is greater than the number of sub-pixels included in the first row of sub-pixels, the number of sub-pixels included in the second row of sub-pixels, and the number of sub-pixels included in the third row of sub-pixels.

[0012] For example, in the display substrate provided in at least one embodiment of the present disclosure, the semiconductor pattern includes multiple semiconductor traces extending along a second direction, the second direction is perpendicular to the first direction, and the conductive pattern is continuously arranged on the side of the first trace and the second trace away from the semiconductor pattern.

[0013] For example, the display substrate provided in at least one embodiment of the present disclosure further includes a first insulating layer and a second insulating layer; wherein, the first insulating layer is located on a side of the semiconductor pattern away from the base substrate, the first routing and the second routing are located on a side of the first insulating layer away from the semiconductor pattern, the second insulating layer is located on a side of the first routing and the second routing away from the first insulating layer, and the conductive pattern is located on a side of the second insulating layer away from the first routing and the second routing; the first insulating layer and the second insulating layer have vias therein, and the semiconductor pattern and the conductive pattern are electrically connected through the vias in the first insulating layer and the second insulating layer.

[0014] For example, in the display substrate provided by at least one embodiment of the present disclosure, the display area includes a plurality of sub-pixels, the sub-pixels include pixel circuits, the pixel circuits include thin film transistors and storage capacitors, the thin film transistors include an active layer, a gate and a source and drain, and the storage capacitors include a first capacitor plate and a second capacitor plate; the gate is arranged on the same layer as the first capacitor plate, and the first routing and the second routing are arranged on the same layer as the second capacitor plate.

[0015] For example, in the display substrate provided in at least one embodiment of the present disclosure, the semiconductor pattern is provided in the same layer as the active layer, and the conductive pattern is provided in the same layer as the source and drain.

[0016] For example, in the display substrate provided in at least one embodiment of the present disclosure, the area surrounding the opening also includes a power pattern electrically connected to the conductive pattern, and the power pattern is configured to provide an electrical signal to the conductive pattern. The display area also includes a first power line electrically connected to the pixel circuit, and the power pattern and the first power line are arranged on the same layer.

[0017] For example, in the display substrate provided by at least one embodiment of the present disclosure, the area surrounding the opening also includes a power supply pattern electrically connected to the conductive pattern, and the power supply pattern is configured to provide an electrical signal to the conductive pattern. The sub-pixel also includes a light-emitting element, and the light-emitting element includes a cathode, an anode, and a light-emitting layer between the cathode and the anode. At least one of the cathode and the anode is electrically connected to the pixel circuit, and the power supply pattern is arranged on the same layer as the anode.

[0018] At least one embodiment of the present disclosure provides a display device including any of the above-mentioned display substrates.

[0019] At least one embodiment of the present disclosure provides a method for preparing a display substrate, the method comprising forming a display area and a peripheral area at least partially surrounding the display area; wherein an opening and a first display area and a second display area are formed in the display area on opposite sides of the opening, the first display area, the opening and the second display area are arranged in sequence along a first direction, and the peripheral area includes an opening peripheral area at least partially located in the opening; the display substrate further comprises a first routing line and a second routing line formed in the same layer, the first routing line and the second routing line being configured to transmit electrical signals for the display area; the first routing line and the second routing line sequentially pass through the first display area, the opening peripheral area and the second display area; in the opening peripheral area, the first routing line includes a first bending portion, the second routing line includes a second bending portion, and the first bending portion and the second bending portion are arranged side by side along the first direction.

[0020] For example, in the preparation method of the display substrate provided in at least one embodiment of the present disclosure, the first bending portion is formed to include at least one S-shaped bending portion; or the second bending portion is formed to include at least one S-shaped bending portion; or the first bending portion and the second bending portion are both formed to include at least one S-shaped bending portion.

[0021] For example, in the preparation method of the display substrate provided in at least one embodiment of the present disclosure, forming the opening peripheral area also includes forming a semiconductor pattern and a conductive pattern; the semiconductor pattern is formed on a base substrate, the first routing line and the second routing line are formed on a side of the semiconductor pattern away from the base substrate, and the conductive pattern is formed on a side of the first routing line and the second routing line away from the semiconductor pattern; in a direction perpendicular to the base substrate, the first bent portion of the first routing line is insulated from at least one of the semiconductor pattern and the conductive pattern so as to form a capacitor, and the second bent portion of the second routing line is insulated from at least one of the semiconductor pattern and the conductive pattern so as to form a capacitor.

[0022] For example, in the preparation method of the display substrate provided in at least one embodiment of the present disclosure, forming the display area includes forming a pixel circuit, the pixel circuit includes a thin film transistor and a storage capacitor, the thin film transistor includes an active layer, a gate and a source and drain, and the storage capacitor includes a first capacitor plate and a second capacitor plate; the gate is formed on the same layer as the first capacitor plate, the first wiring and the second wiring are formed on the same layer as the second capacitor plate, the semiconductor pattern is formed on the same layer as the active layer, and the conductive pattern is formed on the same layer as the source and drain. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0024] Figure 1A is a planar schematic diagram of a display substrate;

[0025] Figure 1B for Figure 1A A partial enlarged view of the display substrate;

[0026] Figure 2A A schematic plan view of a display substrate provided in some embodiments of the present disclosure;

[0027] Figure 2B for Figure 2A A partial enlarged view of the display substrate;

[0028] Figure 2C for Figure 2A Another partial enlarged view of the display substrate;

[0029] Figure 3 A schematic plan view of an opening peripheral area of ​​a display substrate provided in at least one embodiment of the present disclosure;

[0030] Figure 4 A schematic plan view of the arrangement of sub-pixels near an opening peripheral area of ​​a display substrate provided by at least one embodiment of the present disclosure;

[0031] Figure 5A for Figure 2A A schematic cross-sectional view of the opening peripheral area of ​​the display substrate along line AA';

[0032] Figure 5B for Figure 2A Another schematic cross-sectional view of the opening peripheral area of ​​the display substrate along line AA';

[0033] Figure 5CAnother schematic cross-sectional view of the opening peripheral region of the display substrate along line AA' in FIG2 ;

[0034] Figure 5D Another schematic cross-sectional view of the opening peripheral region of the display substrate along line AA' in FIG2 ;

[0035] Figure 5E 2 is a schematic cross-sectional view of the display area of ​​the display substrate along line AA';

[0036] Figure 6 for Figure 2A A schematic cross-sectional view of the display area and the opening peripheral area of ​​the display substrate along line AA';

[0037] Figure 7 A schematic plan view of another display substrate provided for at least one embodiment of the present disclosure;

[0038] Figure 8 An equivalent circuit diagram of a pixel circuit in a display substrate provided by at least one embodiment of the present disclosure;

[0039] Figures 9A-9E A schematic diagram of various layers of a pixel circuit in a display substrate provided in some embodiments of the present disclosure;

[0040] Figure 10 A schematic diagram of a conductive layer of a pixel circuit in a display substrate provided in some embodiments of the present disclosure;

[0041] Figure 11A Another schematic diagram of a second conductive layer of a pixel circuit in a display substrate provided by some embodiments of the present disclosure;

[0042] Figure 11B Another schematic diagram of a third conductive layer of a pixel circuit in a display substrate provided in some embodiments of the present disclosure; and

[0043] Figure 11C Another schematic diagram of a fourth conductive layer of a pixel circuit in a display substrate provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0044] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0045] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0046] Figure 1A FIG. 1 is a schematic plan view of a display substrate. Figure 1A As shown, the display substrate 10 includes a display area 101 and a peripheral area 102 surrounding the display area 101. The display area 101 is designed to be an irregular shape, for example, having a notch 103 on at least one side. The display substrate 10 can arrange devices such as cameras and distance sensors in the area of ​​the notch 103, thereby helping to achieve a narrow-frame design of the display substrate 10.

[0047] like Figure 1AAs shown, the display area 101 includes a first sub-display area 1011 and a second sub-display area 1012 located on the left and right sides of the notch 103. The first sub-display area 1011 and the second sub-display area 1012 are located at the same horizontal position relative to the bottom edge of the display area 101 (the lower edge in the figure), and are driven, for example, by one or more scanning signal lines (gate lines) extending horizontally to the left and right in the figure. Due to the presence of the notch 103, the number of sub-pixels in the same row of sub-pixels in the first sub-display area 1011 and the second sub-display area 1012 is less than the number of sub-pixels in a row of sub-pixels in other parts of the display area 101 (e.g., the middle part in the figure) excluding the first sub-display area 1011 and the second sub-display area 1012. Therefore, in the display substrate 10, the number of sub-pixels connected to the horizontally extending signal lines used to provide electrical signals (e.g., scan signals) to the same row of sub-pixels in the first sub-display area 1011 and the second sub-display area 1012 is different from the number of sub-pixels connected to the signal lines used to provide electrical signals (e.g., scan signals) to a row of sub-pixels in other parts of the display area 101 except the first sub-display area 1011 and the second sub-display area 1012. Furthermore, when the recess 103 is an irregular shape (e.g., a trapezoid), the number of sub-pixels in different rows of sub-pixels in the first sub-display area 1011 and the second sub-display area 1012 may also be different. Therefore, in the display substrate 10, the different numbers of sub-pixels in different rows of sub-pixels result in different loads on the signal lines connecting the different rows of sub-pixels, and thus different signal transmission speeds of these signal lines, which affects the display effect of the display substrate.

[0048] For example, load compensation can be performed on these signal lines with different loads to make the loads of these signal lines substantially the same. For example, a certain number of compensation units with capacitor structures can be provided for these signal lines to make the loads of the signal lines reach an ideal value.

[0049] like Figure 1B As shown, in order not to affect the display effect of the display area 101, the compensation unit with a capacitive structure that provides load compensation for the wiring 1031 and the wiring 1032 is usually arranged in the peripheral area between the first display area 1011 and the second display area 1012. In order to achieve a narrow frame design of the display substrate, the size of the peripheral area needs to be as small as possible. At this time, if the wiring 1031 and the wiring 1032 are arranged in a linear shape, the arrangement space of the compensation unit is small, so the number of compensation units provided may not be enough to meet the demand. To this end, the wiring 1031 and the wiring 1032 can be bent in the above-mentioned peripheral area to increase the extension length of the wiring 1031 and the wiring 1032, thereby increasing the arrangement space of the compensation unit.

[0050] For example, the trace 1031 and the trace 1032 can be arranged as Figure 1B The bending arrangement is performed in the manner shown, and compensation units are provided on the bending portions of the traces 1031 and 1032. For example, Figure 1B In the example shown, each rectangular box on the trace 1031 and the trace 1032 represents a compensation unit. Figure 1B As shown, providing two rows of compensation units for routing 1031 and routing 1032 respectively can meet the compensation requirements. In this case, there will be an extra row of routing parts without compensation units, such as Figure 1B Due to process limitations and routing reliability, adjacent routing lines must be separated by a certain distance D, which is difficult to reduce. Therefore, the presence of routing lines 1031A and 1032B reduces space utilization and is not conducive to narrow-frame designs.

[0051] At least one embodiment of the present disclosure provides a display substrate, a method for manufacturing the same, and a display device. The display substrate includes a display area and a peripheral area at least partially surrounding the display area. The display area includes an opening and a first display area and a second display area located on opposite sides of the opening, the first display area, the opening, and the second display area being arranged sequentially along a first direction. The peripheral area includes an opening peripheral area at least partially located within the opening. The display substrate also includes a first routing line and a second routing line disposed on the same layer, the first routing line and the second routing line being configured to transmit electrical signals for the display area. The first routing line and the second routing line sequentially extend through the first display area, the opening peripheral area, and the second display area. In the opening peripheral area, the first routing line includes a first bend portion, and the second routing line includes a second bend portion, the first bend portion and the second bend portion being arranged side by side along the first direction. This routing arrangement of the display substrate can reduce the space occupied by the routing lines in the opening peripheral area, thereby facilitating a narrow-frame, large-screen design for the display substrate.

[0052] The display substrate and its preparation method, and the display device of some embodiments of the present disclosure are described below through several specific embodiments.

[0053] At least one embodiment of the present disclosure provides a display substrate. Figure 2A shows a schematic plan view of the display substrate, Figure 2B FIG. 1 shows a partial enlarged view of the display substrate. Figure 2A and Figure 2BAs shown, the display substrate 20 includes a display area 201 and a peripheral area 202 that at least partially surrounds the display area 201. The display area 201 includes sub-pixels arranged in an array and various wirings for the sub-pixels to achieve a display function; the peripheral area 202 includes wirings and contact pads that are electrically connected to the sub-pixels. The wirings in the peripheral area are electrically connected to wirings in the display area (e.g., gate lines, data lines, etc.) to provide electrical signals (e.g., scan signals, data signals, etc.) to the sub-pixels.

[0054] For example, the display area 201 includes an opening 201A and a first display area 2011 and a second display area 2012 located on opposite sides of the opening 201A (shown as the left and right sides in the figure). The first display area 2011, the opening 201A and the second display area 2012 are arranged in sequence along the first direction R1 (the horizontal direction in the figure), and the peripheral area 202 includes an opening peripheral area 203 that is at least partially located in the opening 201A. For example, the opening peripheral area 203 is located between the first display area 2011 and the second display area 2012.

[0055] For example, the display substrate 20 further includes a plurality of traces 230 ( Figure 2A The plurality of wirings 230 sequentially pass through the first display area 2011, the opening peripheral area 203 and the second display area 2012, thereby electrically connecting the sub-pixels in the first display area 2011 and the second display area 2012 on opposite sides of the opening 201A, for example, providing electrical signals for the plurality of sub-pixels in the display area 201 and the opening peripheral area 203 that are at the same horizontal position, and the electrical signals may be any form of electrical signals such as scanning signals, light-emitting control signals or reset signals, that is, the electrical signals may be one or more of scanning signals, light-emitting control signals, reset signals, etc., for the pixel driving circuit in the display area 201.

[0056] For example, in some embodiments, Figure 2B As shown, the multiple traces 230 include a first trace 2301 and a second trace 2302. The first trace 2301 and the second trace 2302 sequentially pass through the first display area 2011, the opening peripheral area 203, and the second display area 2013 in a non-linear manner. In the opening peripheral area 203, the first trace 2301 includes a first curved portion 2311, and the second trace 2302 includes a second curved portion 2312. The first curved portion 2311 and the second curved portion 2312 are arranged side by side along the first direction R1. In this case, different portions of a straight line extending along the first direction R1 will simultaneously pass through the first curved portion 2311 and the second curved portion 2312.

[0057] Therefore, relative to Figure 1B As for the wiring arrangement in the embodiment, the above wiring method can reduce the wiring arrangement space of each wiring 230 while obtaining sufficient load compensation, thereby helping to achieve a narrow frame and large screen design of the display substrate 20.

[0058] For example, in some embodiments, the first bend portion 2311 includes at least one S-shaped bend portion; or, the second bend portion 2312 includes at least one S-shaped bend portion; or, both the first bend portion 2311 and the second bend portion 2312 include at least one S-shaped bend portion. For example, the number of S-shaped bend portions included in the first bend portion 2311 and the second bend portion 2312 can be determined based on the size of the load that needs to be compensated by the first trace 2301 and the first trace 2301. For example, when the load compensation that can be set within the space provided by one S-shaped bend portion is insufficient to meet the compensation requirements, the first bend portion 2311 and the second bend portion 2312 can include multiple S-shaped bend portions to increase the space for arranging the load.

[0059] For example, in some embodiments, the first display area 2011 and the second display area 2012 include multiple rows of sub-pixels separated by the opening 201A, and the multiple rows of sub-pixels in the first sub-display area 2011 and the multiple rows of sub-pixels in the second sub-display area 2012 correspond to each other one-to-one. For example, the sub-pixels in the nth row (n is a positive integer) of the first sub-display area 2011 correspond to the sub-pixels in the nth row of the second sub-display area 2012. From the perspective of display effect, they are located in the same row and are therefore considered as the same row of sub-pixels in the display area 201. For example, the first wiring 2301 provides an electrical signal, such as a scan signal, to the first row of sub-pixels arranged along the first direction R1 in the first display area 2011 and the second display area 2012, and the second wiring 2302 provides an electrical signal, such as a scan signal, to the second row of sub-pixels arranged along the first direction R1 in the first display area 2011 and the second display area 2012. At this time, the first wiring 2301 and the second wiring 2302 are scanning signal lines (ie, gate lines) that provide scanning signals to sub-pixels in different rows in the display area.

[0060] For example, in some embodiments, Figure 3 and Figure 5A As shown, the opening peripheral area 203 also includes a semiconductor pattern 220 and a conductive pattern 240. The semiconductor pattern 220 and the conductive pattern 240 can be respectively spaced and insulated from the first routing 2301 and the second routing 2302 to form a capacitor, thereby forming a compensation unit with a certain capacitance structure to provide load compensation for the first routing 2301 and the second routing 2302.

[0061] For example, Figure 3 and Figure 5AAs shown, the semiconductor pattern 220 is located on the base substrate 210, the first trace 2301 and the second trace 2302 are located on a side of the semiconductor pattern 220 away from the base substrate 210, and the conductive pattern 240 is located on a side of the first trace 2301 and the second trace 2302 away from the semiconductor pattern 220. In a direction perpendicular to the base substrate 210, the first trace 2301 is insulated from at least one of the semiconductor pattern 220 and the conductive pattern 240 to form a capacitor, and the second trace 2302 is insulated from at least one of the semiconductor pattern 220 and the conductive pattern 240 to form a capacitor.

[0062] For example, in some embodiments, the first trace 2301 may be insulated from both the semiconductor pattern 220 and the conductive pattern 240 to form a capacitor, or the first trace 2301 may be insulated from one of the semiconductor pattern 220 and the conductive pattern 240 to form a capacitor, or a portion of the first trace 2301 may be insulated from one of the semiconductor pattern 220 and the conductive pattern 240 to form a capacitor, while another portion of the first trace 2301 may be insulated from both the semiconductor pattern 220 and the conductive pattern 240 to form a capacitor. Similarly, in some embodiments, the second trace 2302 may be insulated from both the semiconductor pattern 220 and the conductive pattern 240 to form a capacitor, or the second trace 2302 may be insulated from one of the semiconductor pattern 220 and the conductive pattern 240 to form a capacitor, or a portion of the second trace 2302 may be insulated from one of the semiconductor pattern 220 and the conductive pattern 240 to form a capacitor, while another portion of the second trace 2302 may be insulated from both the semiconductor pattern 220 and the conductive pattern 240 to form a capacitor. Therefore, the first trace 2301 and the second trace 2302 can perform load compensation through different capacitive structures formed with the semiconductor pattern 220 and the conductive pattern 240 .

[0063] For example, in some embodiments, in a direction perpendicular to the substrate 210, the first bent portion 2311 of the first trace 2301 is insulated from at least one of the semiconductor pattern 220 and the conductive pattern 240 to form a capacitor. For example, the first bent portion 2311 of the first trace 2301 may be insulated from both the semiconductor pattern 220 and the conductive pattern 240 to form a capacitor. Alternatively, the first bent portion 2311 of the first trace 2301 may be insulated from one of the semiconductor pattern 220 and the conductive pattern 240 to form a capacitor. Alternatively, a portion of the first bent portion 2311 of the first trace 2301 may be insulated from one of the semiconductor pattern 220 and the conductive pattern 240 to form a capacitor, while another portion of the first bent portion 2311 of the first trace 2301 may be insulated from both the semiconductor pattern 220 and the conductive pattern 240 to form a capacitor. Thus, the first trace 2301 can fully utilize the compensation space provided by the first bent portion 2311 to fully compensate for the load of the first trace 2301.

[0064] For example, in a direction perpendicular to the substrate 210, the second bent portion 2312 of the second trace 2302 is insulated from at least one of the semiconductor pattern 220 and the conductive pattern 240 to form a capacitor. For example, the second bent portion 2312 of the second trace 2302 can be insulated from both the semiconductor pattern 220 and the conductive pattern 240 to form a capacitor. Alternatively, the second bent portion 2312 of the second trace 2302 can be insulated from one of the semiconductor pattern 220 and the conductive pattern 240 to form a capacitor. Alternatively, a portion of the second bent portion 2312 of the second trace 2302 can be insulated from one of the semiconductor pattern 220 and the conductive pattern 240 to form a capacitor, while another portion of the second bent portion 2312 of the second trace 2302 can be insulated from both the semiconductor pattern 220 and the conductive pattern 240 to form a capacitor. Thus, the second trace 2302 can fully utilize the compensation space provided by the second bent portion 2312 to fully compensate for the load of the second trace 2302.

[0065] It can be seen that the first bending portion 2311 and the second bending portion 2312 of the above-mentioned bending arrangement can provide more load compensation space for the first line 2301 and the second line 2302 respectively, thereby providing sufficient load compensation for the first line 2301 and the second line 2302 in a smaller setting space.

[0066] For example, in some embodiments, Figure 3As shown, the semiconductor pattern 220 includes a plurality of semiconductor traces 221 extending along a second direction R2, and the second direction R2 intersects with the first direction R1, for example, perpendicularly; the conductive pattern 220 may also include a plurality of conductive traces extending along the second direction R2, so that the portion where the trace 230 overlaps with the conductive trace forms a capacitor; or, in some embodiments, as Figure 3 As shown, the conductive pattern 220 can also be continuously arranged on the side of at least one trace 230 away from the semiconductor pattern 220, that is, the conductive pattern 220 is arranged in the form of a whole block rather than separate traces on the side of at least one trace 230 away from the semiconductor pattern 220, thereby increasing the overlapping area between the conductive pattern 220 and the trace 230, and further increasing the capacitance of the capacitor formed by the conductive pattern 220 and the trace 230.

[0067] For example, in some embodiments, the line width of the trace 230 may be approximately 3 microns to 5 microns, such as 4 microns, and the line width of the semiconductor trace 221 may be approximately 20 microns to 30 microns, such as 25 microns.

[0068] For example, "about" in the embodiments of the present disclosure means within a range of 5% above and below the numerical value.

[0069] For example, Figure 3 and Figure 5A As shown, in some embodiments, in a direction perpendicular to the substrate 210, the portion of the trace 230 that overlaps with both the semiconductor trace 221 and the conductive pattern 240 constitutes a first compensation unit 230A, while the portion of the trace 230 that does not overlap with the semiconductor pattern 220 but only overlaps with the conductive pattern 240 constitutes a second compensation unit 230B. Thus, by arranging and combining the two different compensation units, the load compensation effect of each trace 230 can be more diversified, thereby making the compensation effect more precise and further improving the load consistency of each trace 230.

[0070] For example, in other embodiments, Figure 5BAs shown, in a direction perpendicular to the base substrate 210, the second portion 232 of the trace 230 does not overlap with the conductive pattern 240, so that the second portion 232 is only insulated from the semiconductor pattern 220 to provide a second capacitor structure, namely, the second compensation unit 230B. At this time, during the manufacturing process of this display substrate, the conductive pattern 240 located above the second portion 232 of the trace 230 is etched, while the conductive pattern 240 above the first portion 231 of the trace 230 is retained, so that the second portion 232 is only insulated from the semiconductor pattern 220 to provide the second capacitor structure, namely, the second compensation unit 230B, while the first portion 231 is insulated from both the semiconductor pattern 220 and the conductive pattern 240 to provide the first capacitor structure, namely, the first compensation unit 230A. For example, the etched portion of the conductive pattern 240 is filled with an insulating material.

[0071] For example, in an embodiment of the present disclosure, an insulation arrangement between two structures may refer to a space between the two structures, thereby isolating the two structures, for example, an insulating material may be provided between the two structures. For example, in some embodiments, in a direction perpendicular to the display substrate, at least a portion of the trace 230 overlaps with the semiconductor pattern 220, with an insulating layer therebetween, to form a capacitor structure, and at least a portion of the trace 230 overlaps with the conductive pattern 240, with an insulating layer therebetween, to form a capacitor structure.

[0072] It should be noted that in the embodiment of the present disclosure, a first compensation unit 230A is defined by the overlapped portion of the trace 230 and the semiconductor trace 221 when spaced apart. In this case, the spacing between adjacent semiconductor traces 221 defines the spacing between adjacent first compensation units 230A. Similarly, a second compensation unit 230B is defined and the spacing between adjacent second compensation units 230B is defined based on the area of ​​the overlapped portion of the trace 230 and the semiconductor trace 221 when spaced apart in the first compensation unit 230A and the spacing between adjacent first compensation units 230A. In this case, because the conductive pattern 220 is continuously arranged, the compensation effect of the capacitance formed by the trace 230 and the conductive pattern 240 in each compensation unit is superimposed on the compensation effect of the capacitance formed by the trace 230 and the conductive pattern 240 between adjacent compensation units. In this case, the difference between the compensation effects of the first compensation unit 230A and the second compensation unit 230B is the compensation effect of the capacitance formed by the trace 230 and the semiconductor trace 221 in each first compensation unit 230A. In addition, in other embodiments of the present disclosure, the first compensation unit 230A and the second compensation unit 230B may be divided in other ways, as long as different compensation units with different compensation effects can be formed.

[0073] For example, in some embodiments, the number of sub-pixels included in the first row of sub-pixels is the same as the number of sub-pixels included in the second row of sub-pixels. At this time, the loads of the first routing 2301 and the second routing 2302 are basically the same. Therefore, the number of first compensation units 230A included in the first routing 2301 can be the same as the number of first compensation units 230A included in the second routing 2302, and the number of second compensation units 230B included in the first routing 2301 can also be the same as the number of second compensation units 230B included in the second routing 2302, thereby providing basically the same load compensation for the first routing 2301 and the second routing 2302, so that the loads of the first routing 2301 and the second routing 2302 remain basically the same and achieve an ideal load.

[0074] For example, in other embodiments, the number of sub-pixels included in the first row of sub-pixels is different from the number of sub-pixels included in the second row of sub-pixels. In this case, the number of first compensation units 230A included in the first routing 2301 is different from the number of first compensation units 230A included in the second routing 2302, or the number of second compensation units 230B included in the first routing 2031 is different from the number of second compensation units 230B included in the second routing 2302, or the number of first compensation units 230A included in the first routing 2301 and the number of second compensation units 230B included in the first routing 2301 are respectively different from the number of first compensation units 230A included in the second routing 2302 and the number of second compensation units 230B included in the second routing 2302. Therefore, by providing different compensation units for the first routing 2301 and the second routing 2302, the loads of the first routing 2301 and the second routing 2302 are basically the same, and an ideal load is achieved.

[0075] For example, in some embodiments, Figure 2C As shown, in the display substrate 20, the plurality of traces 230 further include a third trace 2303 disposed on the same layer as the first trace 2301 and the second trace 2302. The third trace 2303 sequentially passes through the first display area 2011, the opening peripheral area 203, and the second display area 2012. The third trace 2303 extends along the first direction R1, for example, extending substantially linearly in the opening peripheral area 203, and is used to provide scan signals to the third row of sub-pixels arranged along the first direction R1 in the first display area 2011 and the second display area 2012.

[0076] For example, the third trace 2303 is insulated from at least one of the semiconductor pattern 220 and the conductive pattern 240 to form a capacitor. For example, the third trace 2303 can be insulated from both the semiconductor pattern 220 and the conductive pattern 240 to form a capacitor, or the third trace 2303 can be insulated from one of the semiconductor pattern 220 and the conductive pattern 240 to form a capacitor, or a portion of the third trace 2303 can be insulated from one of the semiconductor pattern 220 and the conductive pattern 240 to form a capacitor, while another portion of the third trace 2303 can be insulated from both the semiconductor pattern 220 and the conductive pattern 240 to form a capacitor. Thus, the third trace 2303 can perform load compensation by forming different types of capacitor structures with the semiconductor pattern 220 and the conductive pattern 240.

[0077] For example, in some embodiments, the number of sub-pixels included in the third row of sub-pixels is greater than the number of sub-pixels included in the first row of sub-pixels; or the number of sub-pixels included in the third row of sub-pixels is greater than the number of sub-pixels included in the second row of sub-pixels; or the number of sub-pixels included in the third row of sub-pixels is greater than the number of sub-pixels included in the first row of sub-pixels and greater than the number of sub-pixels included in the second row of sub-pixels. Since the number of sub-pixels included in the third row of sub-pixels is greater than that in the first row of sub-pixels and the second row of sub-pixels, less load compensation is required for the third trace 2303. In this case, the third trace 2303 can be fully compensated by using fewer capacitor structures. Therefore, the third trace 2303 can be substantially linear and pass through the opening peripheral area 203 without any bend in the opening peripheral area 203.

[0078] For example, in some embodiments, Figure 2A As shown, the display area 201 also includes a third display area 2013. Two edges 2013A and 2013B of the third display area 2013 that are opposite to each other in a second direction R2 that is perpendicular to the first direction R1 are aligned with an edge 2011A of the first display area 2011 in the second direction R2 and away from the opening 201A, and an edge 2012A of the second display area 201 in the second direction R2 and away from the opening 201A. The third display area 201 includes sub-pixels arranged in multiple rows and columns, and also includes multiple fourth traces 2304 (one fourth trace 2304 is shown in the figure as an example) that provide electrical signals (e.g., scan signals) to each row of sub-pixels in the multiple rows and columns and extend along the first direction R1. Figure 2AAs shown, the first sub-display area 2011, the opening 201A, the second sub-display area 2012, and the third sub-display area 2013 collectively form a rectangular area. For example, in other embodiments, the first sub-display area 2011, the opening 201A, the second sub-display area 2012, and the third sub-display area 2013 may collectively have other shapes, such as regular shapes such as circles and squares, or other irregular shapes, and the embodiments of the present disclosure are not specifically limited to this.

[0079] For example, in some embodiments, the number of sub-pixels included in each row of sub-pixels in the multiple rows and columns of sub-pixels is substantially the same. In this case, the number of sub-pixels electrically connected to each of the multiple fourth routing lines 2304 is substantially the same, and therefore the multiple fourth routing lines 2304 have substantially the same load. For example, the number of sub-pixels included in each row of sub-pixels in the multiple rows and columns of sub-pixels is greater than the number of sub-pixels included in the first row of sub-pixels, greater than the number of sub-pixels included in the second row of sub-pixels, and greater than the number of sub-pixels included in the third row of sub-pixels. For example, after load compensation, the load of each routing line 230 is substantially the same as the load of the multiple fourth routing lines 2304, and thus the signal transmission speed of each routing line 230 is substantially the same as that of each fourth routing line 2304, thereby maintaining the display consistency of the display area 201 and improving the display effect of the display substrate 20.

[0080] For example, during the design process of the display substrate 20, the load of the plurality of routing lines 230 can be designed with the load of the fourth routing line 2304 as a reference load, so that the load of each signal line providing scan signals to the display area 201 is the same. For example, a certain number of first compensation units 230A and second compensation units 230B can be provided for each routing line 230, so that the load of each routing line 230 is substantially the same as the load of the plurality of fourth routing lines 2304. For example, when the first routing line 2301 and the second routing line 2302 electrically connect to different numbers of sub-pixels, different numbers of first compensation units 230A and second compensation units 230B can be provided for the first routing line 2301 and the second routing line 2302, so that the load of the first routing line 2301 and the second routing line 2302 is substantially the same as the load of the fourth routing line 2304.

[0081] For example, Figure 4 Six rows of sub-pixels near the opening periphery are shown. For example, in some examples, Figure 4 As shown in the figure, assuming that the sixth row of sub-pixels is a full row of sub-pixels, its total load is M, and the sub-pixels in the first to fifth rows are sub-pixels on both sides of the opening, which are not full rows of sub-pixels, and the number of sub-pixels gradually increases from the first to the fifth rows. In this case, by providing compensation units for the first to fifth rows of sub-pixels, the load of each row of sub-pixels is made closer to or substantially equal to M. For example, the total capacitance of the compensation units provided for the first to fifth rows of sub-pixels is gradually reduced.

[0082] For example, in some examples, due to the limited space provided for the compensation unit, for example, from the first row to the fifth row, the lengths of the compensation space are A, B, C, D, and E, respectively. After compensation, the total load of each row of sub-pixels from the first row to the fifth row is difficult to reach M. At this time, the total load of the sub-pixels from the first row to the fifth row can be gradually increased, that is, a load gradient compensation scheme is adopted.

[0083] For example, after compensation, the total loads of the sub-pixels in the first to fifth rows are V / 100×M, U / 100×M, T / 100×M, S / 100×M and R / 100×M, respectively, where R>S>T>U>V, R≤100, and R, S, T, U, and V are the fractions of the loads of the sub-pixels in the first to fifth rows when M is 100.

[0084] Taking the fifth row of sub-pixels as an example, by placing X first compensation units and Y second compensation units in a space of length E, the total load of the fifth row of sub-pixels can be made R / 100×M. Assuming that the total capacitance of the first compensation units is P and the total capacitance of the second compensation units is Q, then X×P+Y×Q+the total load of the fifth row before compensation (i.e., the total load of the sub-pixels on the left and right sides of the space E) = R / 100×M.

[0085] The capacitance formula (C = εS / d) shows that the capacitance of a capacitor depends on the facing area and distance between the two capacitor substrates. Therefore, by designing the widths of trace 230 and semiconductor trace 221, the distance between trace 230 and semiconductor trace 221, and the distance between trace 230 and conductive pattern 240, the required total capacitance P of the first compensation unit and the total capacitance Q of the second compensation unit can be calculated.

[0086] In some examples, due to process or other requirements, the total load of the sub-pixels in the fifth row needs to be reduced to R1 / 100×M. In this case, only the fabrication process of the semiconductor pattern 220 or the conductive pattern 240 can be changed, for example, by changing the mask used to fabricate the semiconductor pattern 220 or the conductive pattern 240, replacing the original first compensation unit with a second compensation unit, or vice versa. The compensation provided to the sub-pixels in the fifth row is then changed to R1 / 100×M. Assuming the number of first compensation units after the change is X1 and the number of second compensation units is Y1, then X1×P+Y1×Q+the total load of the fifth row before compensation (i.e., the total load of the sub-pixels on the left and right sides of the E space) = R1 / 100×M. If, during the compensation unit change, W first compensation units are replaced by second compensation units, then Y1=Y+W and X1=XW. If, during the compensation unit change, H second compensation units are replaced by first compensation units, then Y1=YH and X1=X+H.

[0087] Therefore, in the preparation process of the display substrate provided in the embodiment of the present disclosure, by changing the preparation process of a functional layer, such as changing the mask for making the semiconductor pattern 220 or the conductive pattern 240, the compensation amount provided for a row of pixel units can be changed, and the required compensation amount can be obtained by designing the size and number of the first compensation unit and the second compensation unit.

[0088] For example, in some embodiments, Figure 5A As shown, the display substrate 20 further includes a first insulating layer 250 and a second insulating layer 260. The first insulating layer 250 is located on a side of the semiconductor pattern 220 away from the base substrate 210. The first trace 2301 and the second trace 2302 are located on a side of the first insulating layer 250 away from the semiconductor pattern 220. The second insulating layer 260 is located on a side of the first trace 2301 and the second trace 2302 away from the first insulating layer 250. The conductive pattern 240 is located on a side of the second insulating layer 260 away from the first trace 2301 and the second trace 2302. Thus, the first insulating layer 250 insulates the semiconductor pattern 220 from the trace 230, and the second insulating layer 260 insulates the trace 230 from the conductive pattern 240, thereby forming compensation units with different capacitance structures.

[0089] For example, the first insulating layer 250 and the second insulating layer 260 have via holes, and the semiconductor pattern 220 and the conductive pattern 240 are electrically connected through the via holes 261 in the first insulating layer 250 and the second insulating layer 260. Thus, the semiconductor pattern 220 and the conductive pattern 240 may have the same voltage level.

[0090] For example, in some embodiments, Figure 5CAs shown, the display substrate 20 may further include a first barrier wall 281 and a second barrier wall 282 located on both sides of the opening peripheral area 203. For example, in a direction perpendicular to the base substrate 210, i.e., in the vertical direction in the figure, a plurality of vias 261 overlap with the first barrier wall 281 and / or the second barrier wall 282. At this time, a portion of the semiconductor pattern 220 located between the first barrier wall 281 and the second barrier wall 282 may be etched, so that the second portion of the trace 230 is only insulated from the conductive pattern 240 at the position where the semiconductor pattern 220 is etched, to form a second compensation unit 230B having a second capacitor structure. For example, in Figure 5C In the embodiment, multiple vias 261 are located only below the first barrier wall 281 and / or the second barrier wall 282. In this case, there are no vias 261 between the first barrier wall 281 and the second barrier wall 282. This eliminates or reduces the surface undulation of the conductive pattern 240 between the first barrier wall 281 and the second barrier wall 282 caused by the presence of the vias, thereby maintaining a uniform and flat surface. Furthermore, the surfaces of the insulating layers and encapsulation layers covering the conductive pattern 240 remain uniform and flat, thereby avoiding or reducing potential cracks in the encapsulation layer surface, further improving the uniformity and consistency of the encapsulation layer, and ultimately enhancing the encapsulation effect of the encapsulation layer on the display substrate.

[0091] For example, in some other embodiments, the semiconductor pattern 220 and the conductive pattern 240 may not be electrically connected through a via, but may be independently provided, so as to have different electrical levels.

[0092] For example, in some embodiments, the display substrate 10 further includes a power wiring pattern 270 electrically connected to the conductive pattern 240 . The power wiring pattern 270 is configured to provide an electrical signal to the conductive pattern 240 . The electrical signal can be a fixed electrical signal in any form rather than a pulse signal.

[0093] For example, in some embodiments, functional structures such as the semiconductor pattern 220 , at least one trace 230 , and the conductive pattern 240 in the opening peripheral area 203 may be provided on the same layer as some functional structures in the display area 201 to simplify the preparation of the display substrate.

[0094] In some embodiments, as Figure 5A and Figure 5B As shown, the side of the conductive pattern 240 away from the substrate 210 is provided with an insulating layer 113, a first planarization layer 112, a pixel defining layer 170, a first inorganic encapsulation layer 291, an organic encapsulation layer 292, and a second inorganic encapsulation layer 293. For example, these functional layers all extend from the display area, and are thus provided on the same layer and integrally connected with the corresponding functional layers in the display area.

[0095] For example, in other embodiments, Figure 5D As shown, an insulating layer 113, a first planarization layer 113, a second planarization layer 114, a pixel defining layer 170, a first inorganic encapsulation layer 291, an organic encapsulation layer 292, and a second inorganic encapsulation layer 293 are provided on the side of the conductive pattern 240 away from the substrate 210. Compared with the above embodiment, Figure 5D The peripheral area 203 in the embodiment has an additional second planarization layer 114. At this time, a partial cross-sectional view of the display area is shown as follows: Figure 5E As shown, Figure 6 The display area shown is different from Figure 5E In the display area shown, the anode 181 of the light emitting element 180 is electrically connected to the drain 123 of the thin film transistor TFT through the switching electrode 171. At this time, the switching electrode 171 is covered with the second planarization layer 114, and the second planarization layer 114 extends to the opening peripheral area 203, thereby forming Figure 5D The structure shown.

[0096] For example, in other embodiments, the display region of the display substrate may not have the insulating layer 113 and the second planarization layer 114 .

[0097] It should be noted that, in the embodiments of the present disclosure, "same-layer arrangement" means that two functional layers or structural layers are in the same layer and are formed of the same material in the hierarchical structure of the display substrate, that is, in the preparation process, the two functional layers or structural layers can be formed by the same material layer, and the required patterns and structures can be formed by the same composition process. For example, the material layer can be formed first and then formed by the material layer through a composition process.

[0098] For example, the display substrate 20 may be an organic light-emitting diode (OLED) display substrate, a quantum dot light-emitting diode (QLED) display substrate, or a liquid crystal display substrate. For example, in the case of an organic light-emitting diode display substrate, the display area of ​​the display substrate 201 includes a plurality of sub-pixels arranged in an array, each of which includes a light-emitting element (organic light-emitting diode) and a pixel circuit that provides a driving signal to the light-emitting element.

[0099] For example, Figure 6As shown, each subpixel in the display area 201 of the display substrate 20 includes a pixel circuit, which includes a thin-film transistor (TFT) and a storage capacitor (Cst). The thin-film transistor (TFT) includes an active layer 120, a gate electrode 121, and source and drain electrodes 122 / 123; the storage capacitor (Cst) includes a first capacitor plate CE1 and a second capacitor plate CE2. For example, the semiconductor pattern 220 can be provided on the same layer as the active layer 120; the gate electrode 121 can be provided on the same layer as the first capacitor plate CE1; the at least one trace 230 can be provided on the same layer as the second capacitor plate CE2; and the conductive pattern 240 can be provided on the same layer as the source and drain electrodes 122 and 123. This simplifies the manufacturing process of the display substrate 20.

[0100] For example, in other embodiments, the conductive pattern may be arranged on the same layer as the gate and the first capacitor electrode; or, a portion of the conductive pattern may be arranged on the same layer as the second capacitor electrode, and another portion of the conductive pattern may be arranged on the same layer as the gate and the first capacitor electrode, that is, the conductive pattern includes two parts formed alternately. The embodiments of the present disclosure do not limit the specific form of the conductive pattern.

[0101] For example, Figure 6 As shown, the display area 201 also includes a first gate insulating layer 151 between the active layer 120 and the gate electrode 121, a second gate insulating layer 152 on the gate electrode 121, and an interlayer insulating layer 160. The second gate insulating layer 152 is located between the first capacitor plate CE1 and the second capacitor plate CE2, so that the first capacitor plate CE1, the second gate insulating layer 152, and the second capacitor plate CE2 constitute a storage capacitor Cst. The interlayer insulating layer 160 covers the second capacitor plate CE2. For example, the first insulating layer 250 in the opening peripheral area 203 is provided in the same layer as the first gate insulating layer 151 and the second gate insulating layer 152 in the display area 201, and the second insulating layer 260 in the opening peripheral area 203 is provided in the same layer as the interlayer insulating layer 160 in the display area 201. This can simplify the preparation process of the display substrate 20.

[0102] For example, in some embodiments, Figure 6As shown, each sub-pixel of the display area 201 of the display substrate 20 also includes a light-emitting element 180, and the light-emitting element 180 includes a cathode 183, an anode 181, and a light-emitting layer 182 between the cathode 183 and the anode 181. At least one of the cathode 183 and the anode 181 is electrically connected to the pixel circuit. For example, the power wiring pattern 270 in the opening peripheral area 203 can be arranged in the same layer as the cathode 183 in the display area 201. For example, in some examples, the cathode 183 is a whole-surface structure arranged on the display substrate 20, which is a common electrode for multiple sub-pixels. In this case, the power wiring pattern 270 can be a portion of the cathode 183 extending to the opening peripheral area 203, that is, the power wiring pattern 270 and the cathode 183 are a continuously arranged integral structure. In this case, as Figure 5C As shown, the power trace pattern 270 at least partially covers the side of the conductive pattern 240 away from the base substrate 210 and contacts the conductive pattern 240, thereby achieving electrical connection. Figure 5C Alternatively, in some examples, the power trace pattern 270 is electrically connected to the conductive pattern 240 through a via. Thus, the power trace pattern 270 can transmit the same electrical signal as the cathode 183 to the conductive pattern 240.

[0103] For example, in some embodiments, the power trace pattern 270 in the opening peripheral region 203 can be provided on the same layer and insulated from the anode 181 in the display region 201. The power trace pattern 270 overlaps with the VSS power line in the opening peripheral region. The power trace pattern 270 at least partially covers the side of the conductive pattern 240 away from the base substrate 210 and contacts the conductive pattern 240, thereby achieving an electrical connection and transmitting the same electrical signal as the cathode 183 to the conductive pattern 240. In some embodiments, the power trace pattern 270 further overlaps with the cathode 183 to provide a VSS power signal to the cathode.

[0104] In some embodiments, the power routing pattern 270 covers part of the compensation structure (the first compensation structure and / or the second compensation structure), for example, there is a power routing pattern 270 above the compensation structure near the first barrier wall 281 and the second barrier wall 282, and there is no power routing pattern 270 above the compensation structure near the display area 201.

[0105] For example, in some other embodiments, the display area 201 further includes a first power line electrically connected to the pixel circuit (described in detail later), and the power line pattern 270 can be provided on the same layer as the first power line. For example, the first power line is used to provide a VDD power signal. Figure 3As shown, the power routing pattern 270, the first power line VDD, and the conductive pattern 240 are arranged in the same layer and are integrally connected. For example, the first power line VDD can provide a power signal to the sub-pixels P in the third sub-display area 2013; alternatively, in some examples, the power routing pattern 270 serves as a connecting electrode to electrically connect the first power line to the conductive pattern 240 through a via. The embodiments of the present disclosure do not limit the specific structure of the power routing pattern 270, as long as the power routing pattern 270 can electrically connect the first power line to the conductive pattern 240. As a result, the power routing pattern 270 can transmit the same electrical signal to the conductive pattern 240 as the first power line.

[0106] For example, in some embodiments, the display substrate 20 further includes other functional structures. For example, the opening peripheral region 203 of the display substrate 20 further includes a first barrier wall 281 and a second barrier wall 282. The first barrier wall 281 and the second barrier wall 282 can prevent cracks that may be formed when the opening 201A is formed from extending to the display region 201, thereby protecting the display region 201. For example, the display region 201 further includes an insulating layer 113 (e.g., a passivation layer) and a first planarization layer 112 covering the pixel circuit, as shown in FIG. Figure 6 As shown; for example, in other embodiments, as Figure 5E As shown, the display area 201 may further include a switching electrode 171 and a second planarization layer 114. Figure 5E and Figure 6 As shown, the display area 201 further includes a pixel defining layer 170 for defining a plurality of sub-pixels and spacers (not shown) on the pixel defining layer 170. For example, the first barrier wall 281 and the second barrier wall 282 may include a multi-layer structure, for example, Figure 5C The first barrier wall 281 shown in FIG. 1 includes a three-layer structure. In this case, the first barrier wall 281 can be provided on the same layer as the planarization layer 112 / 114 , the pixel definition layer 170 , and the spacer. Figure 5C The second barrier wall 282 shown in FIG. 1 includes a double-layer structure. In this case, the second barrier wall 282 can be provided on the same layer as any two of the planarization layer 112 / 114 , the pixel defining layer 170 , and the spacer. This simplifies the manufacturing process of the display substrate.

[0107] like Figure 5EAs shown, in some embodiments, the anode 181 is electrically connected to the drain 123 through a transfer electrode, and an insulating layer 113 (for example, a passivation layer, formed of materials such as silicon oxide, silicon nitride or silicon oxynitride) is also included above the source and drain. A first planarization layer 112 is arranged above the insulating layer, a transfer electrode 171 is arranged above the first planarization layer 112, and a second planarization layer 114 is arranged above the transfer electrode 171. The transfer electrode 171 is electrically connected to the anode 181 through a via hole penetrating the second planarization layer 114, and is electrically connected to the drain 123 through a via hole penetrating the first planarization layer 112 and the insulating layer 113.

[0108] For example, the opening peripheral region 203 of the display substrate 20 further includes encapsulation layers 291, 292, and 293. The display region 201 further includes an encapsulation layer 190, which includes multiple encapsulation sublayers 191 / 192 / 193. For example, the first encapsulation layer 291 is disposed on the same layer as the first encapsulation sublayer 191 in the encapsulation layer 190, the second encapsulation layer 292 is disposed on the same layer as the second encapsulation sublayer 192 in the encapsulation layer 190, and the third encapsulation layer 293 is disposed on the same layer as the third encapsulation sublayer 193 in the encapsulation layer 190. For example, both the first encapsulation layer 291 and the third encapsulation layer 293 may include an inorganic encapsulation material, such as silicon oxide, silicon nitride, or silicon oxynitride, and the second encapsulation layer 292 may include an organic material, such as a resin material. The multi-layer encapsulation structure of the display region 201 and the opening peripheral region 203 can achieve a better encapsulation effect, preventing impurities such as moisture and oxygen from penetrating into the interior of the display substrate 20.

[0109] For example, in the embodiments of the present disclosure, the base substrate 210 may be a glass substrate, a quartz substrate, a metal substrate, or a resin substrate. For example, the material of the base substrate 210 may include an organic material, such as a resin material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. For example, the base substrate 210 may be a flexible substrate or a non-flexible substrate, which is not limited in the embodiments of the present disclosure.

[0110] For example, the materials of the first gate insulating layer 151, the second gate insulating layer 152, the interlayer insulating layer 160, the planarizing layer 112, the pixel defining layer 170, and the spacers may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, or may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin. The embodiments of the present disclosure do not specifically limit the materials of the first gate insulating layer 151, the second gate insulating layer 152, the interlayer insulating layer 160, the planarizing layer 112, the pixel defining layer 170, and the spacers. For example, the materials of the first gate insulating layer 151, the second gate insulating layer 152, the interlayer insulating layer 160, the planarizing layer 112, the pixel defining layer 170, and the spacers may be the same or partially the same as each other, or may be different from each other, and the embodiments of the present disclosure do not limit this.

[0111] For example, the materials of the semiconductor pattern 220 and the active layer 120 may include semiconductor materials such as polysilicon or oxide semiconductors (e.g., indium gallium zinc oxide). For example, portions of the semiconductor pattern 220 and the active layer 120 may be made conductive by a conductive treatment such as doping to provide higher conductivity. In this case, the semiconductor pattern 220 is a conductive semiconductor pattern.

[0112] For example, the second capacitor plate CE2 and the at least one trace 230 may be made of metal or alloy materials, such as molybdenum, aluminum, and titanium. The gate 121 and the first capacitor plate CE1 may also be made of metal or alloy materials, such as molybdenum, aluminum, and titanium.

[0113] For example, the materials of the source / drain 133 / 123 and the conductive pattern 240 may include metal materials or alloy materials, such as a metal single layer or multilayer structure formed by molybdenum, aluminum and titanium, etc. For example, the multilayer structure is a multi-metal layer stack, such as a three-layer metal stack of titanium, aluminum and titanium (Al / Ti / Al), etc.

[0114] For example, the material of the anode 181 may include at least one conductive oxide material, including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc., or may also include a metal with high reflectivity as a reflective layer, such as silver (Ag). The material of the cathode 183 may include a metal material such as lithium (Li), aluminum (Al), magnesium (Mg), silver (Ag), etc.

[0115] For example, when the display substrate 20 is an organic light-emitting diode (OLED) display substrate, the light-emitting layer 182 may include a small molecule organic material or a polymer molecule organic material, and may be a fluorescent material or a phosphorescent material, and may emit red, green, blue, or white light. Furthermore, depending on actual needs, in different examples, the light-emitting layer 182 may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.

[0116] For example, in the case where the display substrate 20 is a quantum dot light-emitting diode (QLED) display substrate, the light-emitting layer 182 may include quantum dot materials, such as silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots and indium arsenide quantum dots, etc., and the particle size of the quantum dots is 2-20 nm.

[0117] For example, in other embodiments of the present disclosure, Figure 7 As shown, the opening 201A in the display substrate 20 can also be circular (as shown in the figure), teardrop-shaped, triangular or other shapes. In this case, the display area 201, the peripheral area 202 and the opening peripheral area 203 are arranged as shown in FIG. Figure 7 As shown, the embodiment of the present disclosure does not limit the specific shape of the opening 201A.

[0118] At least one embodiment of the present disclosure provides a display device comprising any of the aforementioned display substrates. The display device may be, for example, an organic light-emitting diode display device, a quantum dot light-emitting diode display device, a liquid crystal display panel, an electronic paper display device, or other types of devices having a display function, and the embodiments of the present disclosure are not limited thereto.

[0119] The structure, function, and technical effects of the display device provided by the embodiment of the present disclosure can refer to the corresponding description of the display substrate provided by the above embodiment of the present disclosure, and will not be repeated here.

[0120] For example, the display device provided in the embodiments of the present disclosure may be any product or component with a display function, such as a display panel, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc., and the embodiments of the present disclosure are not limited thereto.

[0121] At least one embodiment of the present disclosure provides a method for manufacturing a display substrate, the method comprising forming a display area 201 and a peripheral area at least partially surrounding the display area 201. The display area 201 includes an opening 201A, and a first display area 201 and a second display area 201 formed on opposite sides of the opening 201A. The first display area 201, the opening 201A, and the second display area 201 are arranged sequentially along a first direction R1. The peripheral area includes an opening peripheral area 203 at least partially located within the opening 201A. The display substrate also includes a first routing line 2301 and a second routing line 2302 formed in the same layer. The first routing line 2301 and the second routing line 2302 are configured to transmit electrical signals for the display area 201. The first routing line 2301 and the second routing line 2302 sequentially pass through the first display area 201, the opening peripheral area 203, and the second display area 201. In the opening peripheral area 203, the first routing line 2301 includes a first bending portion 2311, and the second routing line 2302 includes a second bending portion 2312. The first bending portion 2311 and the second bending portion are arranged side by side along the first direction R1.

[0122] For example, in some embodiments, the first bending portion 2311 is formed to include at least one S-shaped bending portion; or the second bending portion 2312 is formed to include at least one S-shaped bending portion; or the first bending portion 2311 and the second bending portion 2312 are both formed to include at least one S-shaped bending portion.

[0123] For example, in some embodiments, forming the opening peripheral area 203 also includes forming a semiconductor pattern 220 and a conductive pattern 240; the semiconductor pattern 220 is formed on the base substrate 210, the first trace 2301 and the second trace 2302 are formed on the side of the semiconductor pattern 220 away from the base substrate 210, and the conductive pattern 240 is formed on the side of the first trace 2301 and the second trace 2302 away from the semiconductor pattern 220; in a direction perpendicular to the base substrate 210, the first bent portion 2311 of the first trace 2301 is insulated from at least one of the semiconductor pattern 220 and the conductive pattern 240 to form a capacitor, and the second bent portion 2312 of the second trace 2302 is insulated from at least one of the semiconductor pattern 220 and the conductive pattern 240 to form a capacitor.

[0124] For example, in some embodiments, forming the display area 201 includes forming a pixel circuit, the pixel circuit includes a thin film transistor TFT and a storage capacitor Cst, the thin film transistor TFT includes an active layer, a gate and a source and drain, the storage capacitor Cst includes a first capacitor plate CE1 and a second capacitor plate CE2; the gate is formed on the same layer as the first capacitor plate CE1, the first wiring 2301 and the second wiring 2302 are formed on the same layer as the second capacitor plate CE2, the semiconductor pattern 220 is formed on the same layer as the active layer, and the conductive pattern 240 is formed on the same layer as the source and drain.

[0125] The display substrate and its manufacturing method are described below in conjunction with the pixel circuit and layout in the display substrate.

[0126] Figure 8 An equivalent circuit diagram of a pixel circuit in a display substrate provided by at least one embodiment of the present disclosure, Figures 9A-9E A schematic diagram of various layers of a pixel circuit in a display substrate provided in some embodiments of the present disclosure.

[0127] In some embodiments, as Figure 8 As shown, the pixel circuit includes multiple thin-film transistors T1, T2, T3, T4, T5, T6, and T7, multiple signal lines connected to the multiple thin-film transistors T1, T2, T3, T4, T5, T6, and T7, and a storage capacitor Cst. The multiple signal lines include a gate line GL (i.e., a scanning signal line), an emission control line EM, an initialization line RL, a data line DAT, and a first power line VDD. The gate line GL may include a first gate line GLn and a second gate line GLn-1. For example, the first gate line GLn can be used to transmit a gate scanning signal, and the second gate line GLn-1 can be used to transmit a reset signal. The emission control line EM can be used to transmit an emission control signal. Thus, the pixel circuit is a 7T1C pixel circuit.

[0128] It should be noted that the embodiments of the present disclosure include but are not limited to this. The pixel circuit may also adopt other types of circuit structures, such as a 7T2C structure or a 9T2C structure, etc., and the embodiments of the present disclosure are not limited to this.

[0129] For example, the first gate lines GLn of the pixel circuits corresponding to the sub-pixels in each row on the left and right sides of the opening of the display area 201 can be electrically connected via the wiring 230 to transmit gate scanning signals, thereby achieving a compensation effect of the gate scanning signals.

[0130] For example, Figure 8As shown, the first gate G1 of the first thin film transistor T1 is electrically connected to the third drain D3 of the third thin film transistor T3 and the fourth drain D4 of the fourth thin film transistor T4. The first source S1 of the first thin film transistor T1 is electrically connected to the second drain D2 of the second thin film transistor T2 and the fifth drain D5 of the fifth thin film transistor T5. The first drain D1 of the first thin film transistor T1 is electrically connected to the third source S3 of the third thin film transistor T3 and the sixth source S6 of the sixth thin film transistor T6.

[0131] For example, Figure 8 As shown, the second gate G2 of the second thin film transistor T2 is configured to be electrically connected to the first gate line GLn to receive a gate scan signal, the second source S2 of the second thin film transistor T2 is configured to be electrically connected to the data line DAT to receive a data signal, and the second drain D2 of the second thin film transistor T2 is electrically connected to the first source S1 of the first thin film transistor T1.

[0132] For example, Figure 8 As shown, the third gate G3 of the third thin film transistor T3 is configured to be electrically connected to the first gate line GLn, the third source S3 of the third thin film transistor T3 is electrically connected to the first drain electrode D1 of the first thin film transistor T1, and the third drain D3 of the third thin film transistor T3 is electrically connected to the first gate G1 of the first thin film transistor T1.

[0133] For example, Figure 8 As shown, the fourth gate G4 of the fourth thin film transistor T4 is configured to be electrically connected to the second gate line GLn-1 to receive a reset signal, the fourth source S4 of the fourth thin film transistor T4 is configured to be electrically connected to the initialization line RL to receive an initialization signal, and the fourth drain D4 of the fourth thin film transistor T4 is electrically connected to the first gate G1 of the first thin film transistor T1.

[0134] For example, Figure 8 As shown, the fifth gate G5 of the fifth thin film transistor T5 is configured to be electrically connected to the light emitting control line EM to receive the light emitting control signal, the fifth source S5 of the fifth thin film transistor T5 is configured to be electrically connected to the first power line VDD to receive the first power signal, and the fifth drain D5 of the fifth thin film transistor T5 is electrically connected to the first source S1 of the first thin film transistor T1.

[0135] For example, Figure 8 As shown, the sixth gate G6 of the sixth thin film transistor T6 is configured to be electrically connected to the light emitting control line EM to receive a light emitting control signal, the sixth source S6 of the sixth thin film transistor T6 is electrically connected to the first drain D1 of the first thin film transistor T1, and the sixth drain D6 of the sixth thin film transistor T6 is electrically connected to the first display electrode (e.g., anode) of the light emitting element 180.

[0136] For example, Figure 8 As shown, the seventh gate electrode G7 of the seventh thin-film transistor T7 is configured to be electrically connected to the second gate line GLn-1 to receive a reset signal, the seventh source electrode S7 of the seventh thin-film transistor T7 is electrically connected to the first display electrode (e.g., the anode 181) of the light-emitting element 180, and the seventh drain electrode D7 of the seventh thin-film transistor T7 is configured to be electrically connected to the initialization line RL to receive an initialization signal. For example, the seventh drain electrode D7 of the seventh thin-film transistor T7 can be electrically connected to the initialization line RL by being connected to the fourth source electrode S4 of the fourth thin-film transistor T4.

[0137] For example, Figure 8 As shown, the storage capacitor Cst includes a first capacitor electrode CE1 and a second capacitor electrode CE2. The second capacitor electrode CE2 is electrically connected to the first power line VDD, and the first capacitor electrode CE1 is electrically connected to the first gate G1 of the first thin film transistor T1 and the third drain D3 of the third thin film transistor T3.

[0138] For example, Figure 8 As shown, the second display electrode (eg, cathode 183) of the light emitting element 180 is electrically connected to the second power line VSS.

[0139] It should be noted that one of the first power line VDD and the second power line VSS is a power line providing a high voltage, and the other is a power line providing a low voltage. Figure 8 In the embodiment shown, the first power line VDD provides a constant first voltage, which is a positive voltage, and the second power line VSS provides a constant second voltage, which can be a negative voltage, etc. For example, in some examples, the second voltage can be a ground voltage.

[0140] It should be noted that the reset signal and the initialization signal may be the same signal.

[0141] For example, the cathode 183 of the display substrate 20 can be configured to receive a second voltage provided by the second power line VSS. When the power trace pattern 270 is provided on the same layer as the cathode 183 and is electrically connected thereto, the second voltage is applied to the power trace pattern 270, the conductive pattern 240, and the semiconductor pattern 220 electrically connected thereto. This allows a capacitor to be formed between the trace 230 electrically connected to the first gate line GLn and transmitting the gate scan signal and the semiconductor trace 221 in the semiconductor pattern 220, thereby achieving a compensation effect. Alternatively, when the power trace pattern 270 is provided on the same layer as the first power line VDD and is electrically connected thereto, the first voltage is applied to the power trace pattern 270, the conductive pattern 240, and the semiconductor pattern 220 electrically connected thereto. This allows a capacitor to be formed between the trace 230 electrically connected to the first gate line GLn and transmitting the gate scan signal and the semiconductor trace 221 in the semiconductor pattern 220, thereby achieving a compensation effect.

[0142] It should be noted that, according to the characteristics of transistors, transistors can be divided into N-type transistors and P-type transistors. For the sake of clarity, the embodiments of the present disclosure use P-type transistors (e.g., P-type TFTs) as an example to describe the technical solutions of the present disclosure in detail. That is, in the description of the present disclosure, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can all be P-type transistors. However, the transistors of the embodiments of the present disclosure are not limited to P-type transistors. Those skilled in the art can also use N-type transistors (e.g., N-type TFTs) to implement the functions of one or more transistors in the embodiments of the present disclosure according to actual needs.

[0143] It should be noted that the transistors used in the embodiments of the present disclosure may be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. The thin-film transistors may include oxide semiconductor thin-film transistors, amorphous silicon thin-film transistors, or polycrystalline silicon thin-film transistors. The source and drain of the transistor may be structurally symmetrical, so the source and drain may be physically identical. The source and drain of all or some of the transistors in the embodiments of the present disclosure may be interchangeable as needed.

[0144] In some embodiments, as Figure 9A As shown, the pixel circuit includes the above-mentioned thin film transistors T1, T2, T3, T4, T5, T6 and T7, a storage capacitor Cst, a first gate line GLn connected to the plurality of thin film transistors T1, T2, T3, T4, T5, T6 and T7, a second gate line GLn-1, a light emitting control line EM, an initialization line RL, a data line DAT and a first power line VDD. Figure 8 and Figures 9A-9EThe structure of the pixel circuit will be described.

[0145] For example, Figure 9A Schematic diagram of the stacking position relationship of the semiconductor layer, the first conductive layer, the second conductive layer and the third conductive layer of the pixel circuit.

[0146] Figure 9B The semiconductor layer of the pixel circuit is shown. For example, Figure 8 The semiconductor layer shown in B includes Figure 6 The active layer 120 shown in FIG. 1 is, for example, the active layer of the sixth thin film transistor T6. Figure 8 As shown in Figure B, the semiconductor layer can be formed using a semiconductor material layer through a patterning process. The semiconductor layer can be used to form the active layers of the first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3, the fourth thin-film transistor T4, the fifth thin-film transistor T5, the sixth thin-film transistor T6, and the seventh thin-film transistor T7. Each active layer may include a source region, a drain region, and a channel region between the source and drain regions. For example, the semiconductor layer can be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the source and drain regions can be regions doped with n-type impurities or p-type impurities.

[0147] For example, the semiconductor layer of the pixel circuit can be formed in the same layer as the semiconductor pattern 220 in the opening peripheral region 203. That is, the semiconductor layer of the pixel circuit and the semiconductor pattern in the opening peripheral region 203 can be formed using the same semiconductor material layer and the same patterning process. In this case, the semiconductor pattern 220 in the opening peripheral region 203 is formed only at the location where the first portion 231 of the trace 230 will later be formed, while the semiconductor material corresponding to the location where the second portion 232 of the trace 230 will be formed is etched, so that the semiconductor pattern 220 does not overlap with the second portion 232 of the trace 230 to be formed later.

[0148] In the display substrate provided in some embodiments of the present disclosure, an insulating layer is formed on the above-mentioned semiconductor layer, and the insulating layer includes Figure 6 The first gate insulating layer 151 and a portion of the first insulating layer 250 shown in FIG. Figures 9A-9E Not shown in the figure.

[0149] Figure 9C The first conductive layer of the pixel circuit is shown. Figure 9C As shown, the first conductive layer of the pixel circuit is arranged on the above insulating layer, so as to Figure 9BThe semiconductor layer shown is insulated. The first conductive layer may include a first capacitor electrode CE1 of the storage capacitor Cst, a first gate line GLn, a second gate line GLn-1, a light emitting control line EM, and gates of the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7 (for example, the first gate G1, the second gate G2, the third gate G3, the fourth gate G4, the fifth gate G5, the sixth gate G6, and the seventh gate G7 mentioned above). Figure 9C As shown, the gates of the second thin-film transistor T2, the fourth thin-film transistor T4, the fifth thin-film transistor T5, the sixth thin-film transistor T6, and the seventh thin-film transistor T7 are the portions where the first gate line GLn and the second gate line GLn-1 overlap with the semiconductor layer. The third thin-film transistor T3 may be a dual-gate thin-film transistor, one gate of which may be the portion where the first gate line GLn overlaps with the semiconductor layer, and the other gate of which may be a protrusion from the first gate line GLn. The gate of the first thin-film transistor T1 may be the first capacitor electrode CE1. The fourth thin-film transistor T4 may be a dual-gate thin-film transistor, with both gates being the portions where the second gate line GLn-1 overlaps with the semiconductor layer.

[0150] In the display substrate provided in some embodiments of the present disclosure, another insulating layer is formed on the first conductive layer, and the insulating layer includes Figure 6 The second gate insulating layer 152 and another portion of the first insulating layer 250 are shown in FIG. Figures 9A-9E Not shown in the figure.

[0151] Figure 9D The second conductive layer of the pixel circuit is shown. Figure 9D As shown, the second conductive layer of the pixel circuit includes a second capacitor electrode CE2 of the storage capacitor Cst and an initialization line RL. The second capacitor electrode CE2 at least partially overlaps with the first capacitor electrode CE1 to form the storage capacitor Cst.

[0152] For example, Figure 10 The second capacitor electrode CE2 shown in D has a notch. In some embodiments, the second capacitor electrode CE2 may not have the notch. The embodiments of the present disclosure do not limit the specific structure of the second capacitor electrode CE2.

[0153] For example, the wiring 230 in the opening peripheral area 203 is formed in the same layer as the second conductive layer of the pixel circuit, that is, the wiring 230 in the opening peripheral area 203 and the second conductive layer of the pixel circuit are formed through the same conductive material layer and through the same composition process, that is, the wiring 230 and the second capacitor electrode CE2 and the initialization line RL are formed through the same conductive material layer and the same composition process.

[0154] For example, the trace 230 in the opening peripheral area 203 includes a first trace 2301 and a second trace 2302, wherein the first trace 2301 and the second trace 2302 are configured to transmit electrical signals for the display area 201; the first trace 2301 includes a first bend 2311, and the second trace 2302 includes a second bend 2312, wherein the first bend 2311 and the second bend are arranged side by side along the first direction R1. For example, in some embodiments, the first bend 2311 is formed to include at least one S-shaped bend; or the second bend 2312 is formed to include at least one S-shaped bend; or both the first bend 2311 and the second bend 2312 are formed to include at least one S-shaped bend (as shown in the figure, the first bend 2311 and the second bend 2312 each include one S-shaped bend).

[0155] For example, in some embodiments, the second conductive layer may further include a first light shielding portion 791 and a second light shielding portion 792. The orthographic projection of the first light shielding portion 791 on the base substrate 210 covers the active layer of the second thin-film transistor T2, the drain electrode of the third thin-film transistor T3, and the drain electrode of the fourth thin-film transistor T4, thereby preventing external light from affecting the active layers of the second thin-film transistor T2, the third thin-film transistor T3, and the fourth thin-film transistor T4. The orthographic projection of the second light shielding portion 792 on the base substrate 210 covers the active layer between the two gate electrodes of the third thin-film transistor T3, thereby preventing external light from affecting the active layer of the third thin-film transistor T3. The first light shielding portion 791 may be integrally formed with the second light shielding portion 792 of an adjacent pixel circuit and electrically connected to the first power line VDD via a via extending through the insulating layer.

[0156] In the display substrate provided in some embodiments of the present disclosure, another insulating layer is formed on the second conductive layer, and the insulating layer includes Figure 6 The interlayer insulating layer 160 and the second insulating layer 260 shown in FIG. Figures 9A-9E Not shown in the figure.

[0157] Figure 9E The third conductive layer of the pixel circuit is shown. Figure 9E As shown, the third conductive layer of the pixel circuit includes a data line DAT and a first power line VDD. Figure 9A and Figure 9EAs shown, the data line DAT is connected to the source region of the second thin film transistor T2 in the semiconductor layer through at least one via (e.g., via VH1) in the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer. The first power line VDD is connected to the source region of the corresponding fifth thin film transistor T5 in the semiconductor layer through at least one via (e.g., via VH2) in the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer. The first power line VDD is connected to the second capacitor electrode CE2 in the second conductive layer through at least one via (e.g., via VH3) in the interlayer insulating layer.

[0158] For example, in some embodiments (corresponding to the example of FIG. 5 ), the conductive pattern 240 and the power trace pattern 270 in the opening peripheral region 203 are formed in the same layer as the third conductive layer of the pixel circuit, i.e., they are formed using the same conductive material layer and through the same patterning process. For example, the conductive pattern 240 and the power trace pattern 270 in the opening peripheral region 203 are formed in the same layer as the first power line VDD and are electrically connected thereto, so that the conductive pattern 240 and the power trace pattern 270 transmit the same electrical signal as the first power line VDD. For example, when the semiconductor pattern 220 is electrically connected to the conductive pattern 240, the semiconductor pattern 220, the conductive pattern 240, the power trace pattern 270, and the first power line VDD all transmit the same electrical signal.

[0159] For example, the third conductive layer further includes a first connection portion CP1, a second connection portion CP2, and a third connection portion CP3. One end of the first connection portion CP1 is connected to the drain region of the corresponding third thin film transistor T3 in the semiconductor layer through at least one via (e.g., via VH4) in the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer. The other end of the first connection portion CP1 is connected to the gate of the first thin film transistor T1 in the first conductive layer through at least one via (e.g., via VH5) in the second gate insulating layer and the interlayer insulating layer. One end of the second connection portion CP2 is connected to the initialization line RL through a via (e.g., via VH6) in the interlayer insulating layer. The other end of the second connection portion CP2 is connected to the source region of the seventh thin film transistor T7 and the source region of the fourth thin film transistor T4 in the semiconductor layer through at least one via (e.g., via VH7) in the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer. The third connection portion CP3 is connected to the drain region of the sixth thin film transistor T6 in the semiconductor layer through at least one via hole (eg, via hole VH8 ) in the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer.

[0160] For example, in some embodiments, the pixel circuit of the display substrate may further include a fourth conductive layer. Figure 10 F shows the fourth conductive layer of the pixel circuit. Figure 10As shown in FIG. 5 , the fourth conductive layer includes a second power line VDD2 and a third power line VDD3. The second power line VDD2 extends vertically in the figure, and the third power line VDD3 intersects the second power line VDD2. For example, the second power line VDD2 and the third power line VDD3 are electrically connected to each other or form an integrated structure.

[0161] For example, in some embodiments, the second power line VDD2 and the third power line VDD3 are electrically connected to the first power line VDD through vias, thereby forming a mesh-like power line structure. This structure helps reduce resistance on the power lines, thereby reducing voltage drops on the power lines, and helps evenly deliver the power voltage to each sub-pixel of the display substrate.

[0162] For example, in some embodiments, the fourth conductive layer further includes a fourth connection portion CP4 insulated from the second power line VDD2 and the third power line VDD3, and the fourth connection electrode 234 is used to electrically connect the drain D6 of the sixth transistor T6 to the light-emitting element 180. For example, the fourth connection electrode 234 is implemented as the transfer electrode 171 in the above embodiment, and is used to electrically connect the anode of the light-emitting element to the drain of the thin film transistor.

[0163] In the display substrate provided in some embodiments of the present disclosure, a protective layer is formed on the fourth conductive layer, and the protective layer includes Figure 6 The planarization layer 112 shown in FIG. Figures 9A-9E For example, a sublayer of the first barrier wall 281 in the opening peripheral region 203 is formed in the same layer as the protective layer, that is, a sublayer of the first barrier wall 281 in the opening peripheral region 203 and the protective layer are formed using the same insulating material layer and through the same patterning process.

[0164] For example, the wiring 230 may be connected to the first gate line GLn in the first conductive layer through at least one via hole in the second gate insulating layer.

[0165] In some embodiments, as Figure 6 As shown, forming the display substrate further includes forming a buffer layer 111 on the base substrate 210. The buffer layer 111 serves as a transition layer to prevent harmful substances in the base substrate 210 from invading the interior of the display substrate 20 and to increase the adhesion of the film layers in the display substrate 20 to the base substrate 210. For example, the material of the buffer layer 111 may include a single layer or a multilayer structure formed of insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0166] For example, pixel defining layers, spacers, barrier walls, light-emitting elements, encapsulation layers and other structures may be formed on the protective layer of the display substrate. The formation methods of these structures may refer to relevant technologies, and the implementation of the present disclosure does not limit this.

[0167] For example, in some embodiments, the above-mentioned conductive layers may also adopt other layouts. Figure 11A FIG. 2 shows another schematic plan view of the second conductive layer. Figure 11A As shown, in this example, the second conductive layer includes a second capacitor electrode CE2 of the storage capacitor Cst, a reset signal line Init1 , a second power signal line VDD2 , and a light shielding portion S. The second power signal line VDD2 and the second capacitor electrode CE2 are integrally formed.

[0168] For example, Figure 11B FIG. 2 shows another schematic plan view of the third conductive layer. Figure 11B As shown, the third conductive layer includes a data line Vd, a first power signal line VDD1, and a shield line PB. The data line Vd, the first power signal line VDD1, and the shield line PB all extend in the same direction, such as the vertical direction in the figure. For example, the third conductive layer may further include a first connecting portion CP1, a second connecting portion CP2, and a third connecting portion CP3 for electrically connecting different traces or electrodes.

[0169] For example, Figure 11C FIG. 1 shows another schematic plan view of the fourth conductive layer. Figure 11C As shown, the fourth conductive layer includes a fourth connection portion CP4 and a third power signal line VDD3 that is distributed vertically and horizontally in the figure. For example, in some examples, the third power signal line VDD3 can be connected in parallel with the first power signal line VDD1 to form a mesh power structure, which is beneficial for reducing the resistance of the power signal line.

[0170] In addition, the embodiments of the present disclosure do not specifically limit the materials of each structural or functional layer. Examples of the materials of these structural or functional layers can be found in the above embodiments and will not be repeated here.

[0171] There are a few points to note:

[0172] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0173] (2) For the sake of clarity, the thickness of layers or regions in the drawings used to describe the embodiments of the present disclosure are exaggerated or reduced, i.e., these drawings are not drawn to scale. It is understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or intervening elements may be present.

[0174] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0175] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate comprising a display area and a peripheral area at least partially surrounding the display area; in, The display area includes an opening and a first display area and a second display area located on opposite sides of the opening, the first display area, the opening and the second display area are arranged sequentially along a first direction, and the peripheral area includes an opening peripheral area at least partially located in the opening; The display substrate further includes a first routing line and a second routing line provided in the same layer, the first routing line and the second routing line being configured to transmit electrical signals for the display area; the first routing line and the second routing line sequentially passing through the first display area, the opening peripheral area, and the second display area; In the area surrounding the opening, the first wiring includes a first bending portion, the second wiring includes a second bending portion, and the first bending portion and the second bending portion are arranged side by side along the first direction; The first bending portion and the second bending portion each include at least one S-shaped bending portion, and the at least one S-shaped bending portion of the first bending portion is centrally symmetrical with the at least one S-shaped bending portion of the second bending portion.

2. The display substrate according to claim 1, wherein The first display area and the second display area include a plurality of rows of sub-pixels separated by the opening, The first wiring provides a scanning signal for the first row of sub-pixels arranged along the first direction in the first display area and the second display area. The second wiring provides a scanning signal to the second row of sub-pixels arranged along the first direction in the first display area and the second display area.

3. The display substrate according to claim 2, wherein: The opening peripheral area further includes a semiconductor pattern and a conductive pattern; The semiconductor pattern is located on the substrate, the first trace and the second trace are located on a side of the semiconductor pattern away from the substrate, and the conductive pattern is located on a side of the first trace and the second trace away from the semiconductor pattern; In a direction perpendicular to the substrate, the first trace is insulated from at least one of the semiconductor pattern and the conductive pattern to form a capacitor, and the second trace is insulated from at least one of the semiconductor pattern and the conductive pattern to form a capacitor.

4. The display substrate according to claim 3, wherein: In a direction perpendicular to the substrate, the first bent portion of the first trace is insulated from at least one of the semiconductor pattern and the conductive pattern to form a capacitor, and the second bent portion of the second trace is insulated from at least one of the semiconductor pattern and the conductive pattern to form a capacitor.

5. The display substrate according to claim 3, further comprising a third wiring provided on the same layer as the first wiring and the second wiring, in, The third wiring sequentially passes through the first display area, the opening peripheral area and the second display area. The third wiring extends along the first direction to provide a scanning signal for the third row of sub-pixels arranged along the first direction in the first display area and the second display area. The third wiring is insulated from at least one of the semiconductor pattern and the conductive pattern to form a capacitor. The display substrate according to claim 5 , wherein: The number of sub-pixels included in the third row of sub-pixels is greater than the number of sub-pixels included in the first row of sub-pixels; or The number of sub-pixels included in the third row of sub-pixels is greater than the number of sub-pixels included in the second row of sub-pixels; or The number of sub-pixels included in the third row of sub-pixels is greater than the number of sub-pixels included in the first row of sub-pixels, and is also greater than the number of sub-pixels included in the second row of sub-pixels.

7. The display substrate according to claim 5, wherein: The display area further includes a third display area, wherein two opposite edges of the third display area in a second direction perpendicular to the first direction are respectively aligned with an edge of the first display area in the second direction away from the opening and an edge of the second display area in the second direction away from the opening. The third display area includes sub-pixels arranged in multiple rows and columns, and also includes multiple fourth wirings extending along the first direction and providing scanning signals to each row of sub-pixels in the multiple rows and columns.

8. The display substrate according to claim 7, wherein: The number of sub-pixels included in each row of the multiple rows and columns of sub-pixels is greater than the number of sub-pixels included in the first row of sub-pixels, the number of sub-pixels included in the second row of sub-pixels, and the number of sub-pixels included in the third row of sub-pixels.

9. The display substrate according to claim 3, wherein: The semiconductor pattern includes a plurality of semiconductor traces extending along a second direction, wherein the second direction is perpendicular to the first direction, and the conductive pattern is continuously arranged on a side of the first trace and the second trace away from the semiconductor pattern.

10. The display substrate according to claim 3, further comprising a first insulating layer and a second insulating layer; in, The first insulating layer is located on a side of the semiconductor pattern away from the substrate, and the first trace and the second trace are located on a side of the first insulating layer away from the semiconductor pattern. The second insulating layer is located on a side of the first trace and the second trace away from the first insulating layer, and the conductive pattern is located on a side of the second insulating layer away from the first trace and the second trace; The first insulating layer and the second insulating layer have via holes therein, and the semiconductor pattern and the conductive pattern are electrically connected through the via holes in the first insulating layer and the second insulating layer.

11. The display substrate according to claim 3, wherein: The display area includes a plurality of sub-pixels, each of which includes a pixel circuit. The pixel circuit includes a thin film transistor and a storage capacitor, the thin film transistor includes an active layer, a gate and a source and drain electrode, and the storage capacitor includes a first capacitor plate and a second capacitor plate; The gate is provided on the same layer as the first capacitor plate, and the first wiring and the second wiring are provided on the same layer as the second capacitor plate.

12. The display substrate according to claim 11, wherein: The semiconductor pattern is disposed in the same layer as the active layer, and the conductive pattern is disposed in the same layer as the source and drain electrodes.

13. The display substrate according to claim 11, wherein: The opening peripheral area further includes a power pattern electrically connected to the conductive pattern, the power pattern being configured to provide an electrical signal to the conductive pattern, and the display area further includes a first power line electrically connected to the pixel circuit. The power pattern and the first power line are arranged on the same layer.

14. The display substrate according to claim 11, wherein: The opening peripheral area further includes a power pattern electrically connected to the conductive pattern, and the power pattern is configured to provide an electrical signal to the conductive pattern. The sub-pixel further includes a light-emitting element, the light-emitting element including a cathode, an anode, and a light-emitting layer between the cathode and the anode, at least one of the cathode and the anode being electrically connected to the pixel circuit. The power supply pattern is arranged on the same layer as the anode.

15. A display device comprising the display substrate according to any one of claims 1 to 14.

16. A method for preparing a display substrate, comprising forming a display area and a peripheral area at least partially surrounding the display area; in, The display area includes an opening and a first display area and a second display area formed on opposite sides of the opening, the first display area, the opening, and the second display area are arranged sequentially along a first direction, and the peripheral area includes an opening peripheral area at least partially located in the opening; The display substrate further includes a first routing line and a second routing line formed in the same layer, the first routing line and the second routing line being configured to transmit electrical signals for the display area; the first routing line and the second routing line sequentially pass through the first display area, the opening peripheral area, and the second display area; In the area surrounding the opening, the first wiring includes a first bending portion, the second wiring includes a second bending portion, and the first bending portion and the second bending portion are arranged side by side along the first direction; The first bending portion and the second bending portion each include at least one S-shaped bending portion, and the at least one S-shaped bending portion of the first bending portion is centrally symmetrical with the at least one S-shaped bending portion of the second bending portion.

17. The method for preparing a display substrate according to claim 16, wherein: Forming the opening peripheral area further includes forming a semiconductor pattern and a conductive pattern; The semiconductor pattern is formed on a substrate, the first routing line and the second routing line are formed on a side of the semiconductor pattern away from the substrate, and the conductive pattern is formed on a side of the first routing line and the second routing line away from the semiconductor pattern; In a direction perpendicular to the substrate, the first bent portion of the first trace is insulated from at least one of the semiconductor pattern and the conductive pattern to form a capacitor, and the second bent portion of the second trace is insulated from at least one of the semiconductor pattern and the conductive pattern to form a capacitor.

18. The method for preparing a display substrate according to claim 17, wherein: Forming the display area includes forming a pixel circuit, the pixel circuit includes a thin film transistor and a storage capacitor, the thin film transistor includes an active layer, a gate and a source and drain, and the storage capacitor includes a first capacitor plate and a second capacitor plate; The gate is formed in the same layer as the first capacitor plate, the first wiring and the second wiring are formed in the same layer as the second capacitor plate, the semiconductor pattern is formed in the same layer as the active layer, and the conductive pattern is formed in the same layer as the source and drain.

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