Chip and data processing device and method

Abstract

The present invention discloses a chip and a data processing device and method, wherein the device comprises: a first memory for storing application data, a second memory for storing program data; a first memory controller connected to the first memory, a second memory controller connected to the second memory; a DMA controller for receiving communication data when receiving a first instruction; a CPU processor for controlling the first memory controller to start application data erasure when receiving a second instruction, and controlling the second memory controller to read program data in the second memory after starting application data erasure or after the DMA controller receives communication data, and when application data erasure and communication data exist at the same time, first using the read program data to process communication data, and after the communication data processing is completed, waiting for the application data erasure to be completed. The data processing device can improve the memory erasure life and data processing efficiency.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a chip and a data processing device and method. Background Art

[0002] With the development of the chip industry and the increase in market demand, the application fields and scenarios of chips have also become diversified to meet the different needs of users.

[0003] In order to implement different functions on the chip, users usually choose erasable memory (such as EEPROM (Electrically Erasable Programmable read only memory), Flash (flash memory), etc.) chips, download the user program to the memory and execute the program. If a new function needs to be implemented, the program currently stored in the memory is erased and a new user program is downloaded to implement it.

[0004] In the chip application process, there is usually a need for multiple communication interfaces in parallel. For memory chips, the most common need is the parallel operation of memory erase and interface communication. Taking two parallel communication interfaces as an example, when the user is erasing memory application data (such as amount data and file data, etc.) through communication interface 1, the data of communication interface 2 can still be received and processed normally.

[0005] To meet the needs of parallel memory erasing and interface communication, there are usually two solutions: 1. After the CPU starts memory erasing, the CPU is suspended, and the storage controller continuously detects the interface abort request signal. When the request signal is valid, the storage controller resets the current erasing operation and sets the abort mark. The CPU recovers and immediately responds to the interrupt generated by the communication interface. After the interrupt response is completed, the CPU returns to the memory erasing function. The software determines that the abort mark is set, then restarts the memory erasing and completes it; 2. Two storage controllers are connected to the same cache device, and the cache device establishes and maintains a mapping table between cache partitions and storage controllers. The cache partition where the storage controller reads and writes data is located according to the mapping table, data reading and writing are performed in the located partition, and the results are returned to the storage controller that issued the read and write commands.

[0006] However, for the above two solutions, although Solution 1 solves the problem of responding to the communication interface when the memory is erased, it still has the problem of repeated memory erasure and low execution efficiency, which is manifested as: after processing the communication interface interruption, the memory erasure must be restarted, which reduces the memory erasure life and execution efficiency. Although Solution 2 uses two storage controllers to operate the same cache device, it does not store the application data and interface communication program in different partitions, and does not realize the function of two storage controllers working in parallel, which cannot meet the requirements of application data erasure and communication interface working in parallel. Summary of the invention

[0007] The present invention aims to solve one of the technical problems in the related art at least to a certain extent. To this end, one object of the present invention is to provide a data processing device to increase the erase and write life of a memory and improve data processing efficiency.

[0008] The second objective of the present invention is to provide a chip.

[0009] The third objective of the present invention is to provide a data processing method.

[0010] To achieve the above-mentioned purpose, an embodiment of the first aspect of the present invention proposes a data processing device, comprising: a first memory and a second memory, the first memory being used to store application data, and the second memory being used to store program data; a first storage controller and a second storage controller, the first storage controller being connected to the first memory, and the second storage controller being connected to the second memory; a DMA controller, the DMA controller being used to receive communication data upon receiving a first instruction; a CPU processor, the CPU processor being used to control the first storage controller to start erasing application data upon receiving a second instruction, and to control the second storage controller to read program data in the second memory after starting erasing application data or after the DMA controller receives the communication data, and to first use the read program data to process the communication data when both application data erasing and the communication data exist, and after the communication data processing is completed, wait for the application data erasing to be completed.

[0011] In order to achieve the above-mentioned object, a second embodiment of the present invention proposes a chip, characterized in that it includes the data processing device of the above-mentioned embodiment.

[0012] To achieve the above-mentioned purpose, the third aspect of the present invention proposes a data processing method for the above-mentioned data processing device, the method comprising: when receiving a first instruction, receiving communication data through the DMA controller; when receiving a second instruction, controlling the first storage controller through the CPU processor to start application data erasure; after starting application data erasure or the DMA controller receives the communication data, controlling the second storage controller through the CPU processor to read program data in the second memory; when application data erasure and the communication data exist at the same time, first using the read program data to process the communication data, and after the communication data processing is completed, waiting for the application data erasure to be completed.

[0013] The chip, data processing device, and method of the embodiment of the present invention do not have to repeatedly erase and write the memory. The memory erase and write is only started once in the entire process, which improves the erase and write life of the memory. The dual storage controller can realize independent and parallel operation of the corresponding two independent memories, and there is no situation where the dual storage controller accesses the memory beyond the boundary or reads and writes data incorrectly. By adding the DMA function, the dual storage controller control and DMA receive data independently and in parallel, which can significantly improve the efficiency of application data erasing, DMA communication data reception, CPU reading and executing communication programs, and CPU responding to DMA interrupts and processing received communication data while working in parallel.

[0014] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a structural block diagram of a data processing device according to an embodiment of the present invention;

[0016] Figure 2 is a structural block diagram of a data processing device according to a specific embodiment of the present invention;

[0017] Figure 3 is a work flow chart of a data processing device according to an embodiment of the present invention;

[0018] Figure 4 is a structural block diagram of a chip according to an embodiment of the present invention;

[0019] Figure 5 is a flow chart of a data processing method according to an embodiment of the present invention;

[0020] Figure 6 is a flow chart of a data processing method according to another embodiment of the present invention.

[0021] Reference numerals:

[0022] 100. Chip;

[0023] 10. Data processing device;

[0024] 1. First memory, 2. Second memory, 3. First memory controller, 4. Second memory controller, 5. DMA controller, 6. CPU processor;

[0025] 51. DMA mover, 52. RAM memory. DETAILED DESCRIPTION

[0026] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0027] Please refer to the following Figure 1-6 The chip, data processing device and method according to the embodiments of the present invention are described.

[0028] Figure 1 It is a structural block diagram of a data processing device according to an embodiment of the present invention.

[0029] like Figure 1 As shown, the data processing device 10 includes: a first memory 1, a second memory 2, a first memory controller 3, a second memory controller 4, a DMA (Direct Memory Access) controller 5 and a CPU (Central Processing Unit) processor 6.

[0030] In this embodiment, the first memory 1 is used to store application data, and the second memory 2 is used to store program data. The first memory 1 and the second memory 2 may be two independent storage areas of the same size in the chip; the application data may include at least one of telecommunication application data, account information data, and power consumption data, and the program data may include at least one of transaction program data, control program data, and power distribution communication program.

[0031] See also Figure 1 The first storage controller 3 is connected to the first storage 1 and is used to independently control the first storage 1. The second storage controller 4 is connected to the second storage 2 and is used to independently control the second storage 2. The first storage controller 3 and the second storage controller 4 are both hardware controllers, which are used to control the corresponding storage to perform operations such as erasing / writing / reading / executing programs.

[0032] It should be noted that the functions of the first memory 1 and the second memory 2 are interchangeable, and the functions of the first storage controller 3 and the second storage controller 4 are interchangeable, that is, the first memory 1 can store program data, and the second memory 2 can store application data. At this time, the first storage controller 3 still controls the first memory 1, and the second storage controller 4 still controls the second memory 2. The number of the first memory 1, the second memory 2, the first storage controller 3, and the second storage controller 4 can be one or more, which can be set according to needs.

[0033] The DMA controller 5 is used to receive communication data when receiving the first instruction.

[0034] Specifically, the DMA controller 5 can be connected to the first communication interface of the chip, such as the SPI interface (Serial Peripheral Interface). When an external terminal or user controls the chip, a first instruction can be sent through the first communication interface, such as a contactless transaction instruction between a mobile phone and a bus or subway fare collection machine, a remote control instruction of a vehicle, etc. The first instruction can be hardware-triggered to start the DMA controller 5 to receive communication data corresponding to the first instruction, such as transaction data, remote control data, etc.

[0035] Optionally, the first communication interface may also be a contactless interface (such as a radio frequency interface, a wireless communication interface, etc.), a CAN interface, etc.

[0036] As an example, Figure 2 As shown, the DMA controller 5 may include a DMA mover 51 and a RAM (Random Access Memory) memory 52. ​​The DMA mover 51 is connected to the RAM memory 52. ​​The DMA mover 51 is used to receive communication data when receiving a first instruction and move the received communication data to the RAM memory 52.

[0037] In some embodiments of the present invention, the DMA mover 51 may also be used to generate a DMA interrupt flag after the communication data is moved, such as setting the DMA interrupt flag, and the setting information may be stored in the RAM memory 52. ​​The CPU processor may determine that the DMA controller has finished receiving the communication data according to the DMA interrupt flag (such as the setting information read from the RAM memory 52), so as to start processing the communication data and ensure timely response of the communication data.

[0038] Optionally, the RAM memory 52 may be a memory inherent in the chip and integrated with the DMA mover 51 , or a buffer allocated by the CPU processor 6 , or a storage area in the second memory 2 .

[0039] like Figure 3As shown, the CPU processor 6 is used to control the first storage controller 3 to start the application data erasure when receiving the second instruction, and after starting the application data erasure or the DMA controller 5 receives the communication data, control the second storage controller 4 to read the program data in the second memory 2, and when there is application data erasure and communication data at the same time, first use the read program data to process the communication data, and after the communication data processing is completed, wait for the application data erasure to be completed. Among them, if the CPU processor 6 determines that the communication data reception is completed according to the DMA interrupt flag, it can also clear the DMA interrupt flag after using the program data to process the communication data, so as to make an accurate judgment next time; after the CPU processor 6 processes the DMA interrupt, it will wait for the first storage controller 3 to complete the application data erasure, see Figure 3 .

[0040] Specifically, the CPU processor 6 can be connected to the second communication interface of the chip, such as the 7816 interface. When the user or the external terminal controls the chip, a second instruction can be sent through the second communication interface, such as an instruction to make or receive a call, an instruction to send a text message, an instruction to update account information, etc. The second instruction can trigger the CPU processor 6 to control the first storage controller 3 to start the application program erasing.

[0041] As an example, see Figure 3 After starting the program erasing, the CPU processor 6 can directly control the second storage controller 4 to read the program data in the second memory 2. After reading the program data, if it is determined that the DMA controller 5 has finished receiving the communication data, the communication data is processed using the read program data. After the communication data processing is completed, wait for the application data erasing to be completed.

[0042] In this example, after reading the program, if it cannot be determined that the DMA controller 5 has finished receiving the communication data, the CPU processor 6 directly waits for the application data to be erased and written.

[0043] As another example, the CPU processor 6 may first determine that the DMA controller 5 has finished receiving the communication data, and then control the second storage controller 4 to read the program data in the second memory 2. After reading the program data, if the second instruction is received, the CPU processor 6 is first triggered to control the first storage controller 3 to start the application program erasing, and then the communication data is processed using the read program data. After the communication data processing is completed, the application data erasing is waited for completion.

[0044] In this example, after reading the program data, if the second instruction is not received, the CPU processor 6 directly processes the communication data using the read program data.

[0045] In some embodiments, the CPU processor 6 may be connected to the first storage controller 3 and the second storage controller 4 respectively through a bus. In this way, the expandability of the chip and the versatility of each component in the chip may be improved.

[0046] In some embodiments, the CPU processor 6 may also control the second storage controller 4 to store the communication data received by the DMA controller 5 and the processed communication data into the second memory 2 for subsequent viewing.

[0047] The data processing device of the embodiment of the present invention does not have repeated memory erasure and writing, and the memory erasure and writing is only started once in the whole process, which improves the memory erasure and writing life; it can realize independent and parallel operation of the dual storage controllers on the corresponding two independent memories, and there is no situation where the dual storage controllers access the memory beyond the boundary or read and write data erroneously. By adding the DMA function, the dual storage controller control and DMA receiving data can work independently and in parallel, which can significantly improve the efficiency of application data erasure, DMA communication data reception, CPU reading and executing communication programs, and CPU responding to DMA interrupts and processing received communication data while working in parallel.

[0048] The working principle of the data processing device of the present invention is described below through four specific embodiments:

[0049] Specific embodiment 1: When the mobile phone is making a call or sending and receiving text messages, it can conduct a contactless transaction on a bus or subway. The specific implementation process is as follows: telecommunication application data is stored in the first memory 1 of the chip, and contactless transaction program data is stored in the second memory 2 of the chip. When the second communication interface of the chip, such as the 7816 interface, is communicating with the baseband chip, that is, when the user is making a call or sending and receiving text messages, the chip interprets the telecommunication application data of the first memory 1, and the CPU processor 6 controls the first storage controller 3 to start erasing the telecommunication application data. At the same time, the mobile phone conducts a contactless transaction on a bus or subway, and the chip receives the terminal data through the contactless interface (i.e., the first communication interface) and the DMA controller 5. After the CPU processor 6 starts erasing the telecommunication application data, the CPU processor 6 controls the second storage controller 4 to read and execute the program data of the second memory 2. The CPU processor 6 can immediately respond to the terminal data received by the contactless interface. The CPU processor 6 processes the terminal data and completes the contactless transaction. After that, the CPU processor 6 waits for the first storage controller 3 to complete erasing the telecommunication application data, that is, the mobile phone completes making a call or sending and receiving text messages.

[0050] Since a lot of data needs to be updated when making and receiving calls, such as call records, call charges and remaining call charges, etc., it takes a long time to erase and write telecommunication application data. Therefore, compared with using dual storage controller technology alone, the execution efficiency of the parallel processing solution for making and receiving calls and contactless transactions of the present invention is improved by nearly 30%; compared with using DMA technology alone, the execution efficiency of the parallel processing solution for making and receiving calls and contactless transactions of the present invention is improved by nearly 40%.

[0051] Specific embodiment 2: Applied in the field of vehicle networking and vehicle-mounted terminals, the specific implementation process is: a vehicle-mounted T-BOX is installed on the car, and the T-BOX is integrated with an eSIM application and a SE application. The eSIM application is connected to the baseband chip through the 7816 interface and completes telephone communication. The SE application is connected to the vehicle-mounted T-BOX through the CAN interface and completes vehicle remote control. The vehicle control operation program is stored in the second memory 2 of the chip, and the telecommunications application data is stored in the first memory 1 of the chip. When the driver sends a control command through the mobile phone APP (Applicaton), the car remote service background will send a request instruction to the vehicle T-BOX. The T-BOX sends the control command to the SE application through the CAN (Controller Area Network) interface and the DMA controller 5. The SE application interprets it as remote control of vehicle startup and other operations. The second storage controller 4 of the chip reads and executes the vehicle startup and other operation programs stored in the second memory 2. At the same time, the mobile phone is connected to the call, the eSIM application is connected to the baseband chip through the 7816 interface and starts a call. The eSIM application interprets it as erasing the telecommunications application data of the first memory 1. The first storage controller 3 of the chip starts erasing the telecommunications application data. After waiting for the vehicle to start, the chip waits for the telecommunications application data to be erased, that is, the phone call is completed.

[0052] Since the reading and execution time of operating programs such as vehicle startup is relatively long, and the time for erasing telecommunication application data is also relatively long, the execution efficiency of the remote control vehicle startup and telecommunication call parallel processing solution of the present invention is improved by nearly 25% compared with the use of dual storage controller technology alone; compared with the use of DMA technology alone, the execution efficiency of the remote control vehicle startup and telecommunication call parallel processing solution of the present invention is improved by nearly 35%.

[0053] Specific embodiment 3: Multi-application Java card scenario, a Java card supports multiple applications, and it is common to support social security and financial applications at the same time. The specific implementation process is: social security account information and the like are stored in the first memory 1 of the chip, and the financial transaction process program data is stored in the second memory 2 of the chip. When a user uses a multi-application Java card in a medical institution to update the social security account information, the chip interprets it as erasing the social security account information data of the first memory 1, and the CPU processor 6 controls the first storage controller 3 to start erasing the social security account information data. At the same time, the mobile phone APP uses the bound multi-application Java card to perform financial transactions, and the chip receives the transaction information through the payment background (DMA controller 5). After the CPU processor 6 starts erasing the social security account information data, the CPU processor 6 controls the second storage controller 4 to read and execute the financial transaction process program of the second memory 2. After the CPU processor 6 processes the financial transaction, it waits for the first storage controller 3 to complete the update of the social security account information.

[0054] Since the reading and execution time of social security account information update and financial transaction program is comparable, the execution efficiency of the social security account information update and financial transaction parallel processing scheme of the present invention is improved by nearly 20% compared with the use of dual storage controller technology alone; compared with the use of DMA technology alone, the execution efficiency of the social security account information update and financial transaction parallel processing scheme of the present invention is improved by nearly 30%.

[0055] Specific embodiment 4: applied in the intelligent fusion terminal chip, supporting the access and parallel processing of the power distribution and power consumption dual systems, the specific implementation process is: the fusion terminal power distribution communicates with the main station through wireless, the power consumption communicates with the electric meter through interfaces such as SPI, the power consumption data is stored in the first memory 1 of the chip, and the power distribution communication program is stored in the second memory 2 of the chip. When the user is using electricity or charging the electric meter, the CPU processor 6 of the chip parses the power consumption data of the first memory 1, and the CPU processor 6 controls the first storage controller 3 to start the erasure of the power consumption data. At the same time, the fusion terminal communicates with the main station through wireless power distribution, and the chip receives the communication data of the main station through the wireless interface and the DMA controller 5. After the CPU processor 6 starts the erasure of the power consumption data, the CPU processor 6 controls the second storage controller 4 to read and execute the second storage 2 program, and the CPU processor 6 can immediately respond to the wireless communication data of the main station. After the CPU processor 6 processes the communication data of the main station, the CPU waits for the first storage controller 3 to complete the erasure of the power consumption data, that is, the communication with the electric meter is completed.

[0056] Since the time for updating the meter data is relatively short and the time for wireless data communication with the main station is relatively long, the execution efficiency of the parallel processing scheme for updating the meter data and the main station wireless communication data of the present invention is improved by nearly 20% compared with the use of the dual storage controller technology alone; compared with the use of the DMA technology alone, the execution efficiency of the parallel processing scheme for updating the meter data and the main station wireless communication data of the present invention is improved by nearly 20%.

[0057] Based on the above data processing device, the present invention proposes a chip.

[0058] In an embodiment of the present invention, Figure 4 As shown, the chip 100 includes the data processing device 10 of the above embodiment.

[0059] Figure 5 It is a flow chart of a data processing method according to an embodiment of the present invention.

[0060] In an embodiment of the present invention, the data processing method is used in the data processing device of the above embodiment. Figure 5 As shown, the data processing method includes:

[0061] S1, when receiving the first instruction, receiving communication data through the DMA controller.

[0062] S2, when receiving the second instruction, controlling the first storage controller through the CPU processor to start erasing the application data.

[0063] The application data includes at least one of telecommunication application data, account information data, and electricity usage data; the program data includes at least one of transaction program data, control program data, and power distribution communication program.

[0064] S3, after starting application data erasure or the DMA controller finishes receiving communication data, the CPU processor controls the second storage controller to read the program data in the second memory.

[0065] In some embodiments, after the DMA controller finishes receiving the communication data, it may also generate a DMA interrupt flag, wherein the CPU processor determines that the DMA controller has finished receiving the communication data according to the DMA interrupt flag.

[0066] S4, when there are both application data erasing and communication data, first use the read program data to process the communication data, and after the communication data processing is completed, wait for the application data erasing to be completed.

[0067] In some embodiments, if the CPU processor determines that the DMA controller has finished receiving the communication data according to the DMA interrupt flag, the DMA interrupt flag is cleared by the CPU processor after the communication data is processed using the program data.

[0068] In some embodiments, Figure 6 As shown, the processing method may also include:

[0069] S5, controlling the second storage controller through the CPU processor to store the communication data received by the DMA controller and the processed communication data into the second memory.

[0070] The data processing method of the embodiment of the present invention does not have to repeatedly erase and write the memory. The memory erase and write is only started once in the whole process, which improves the erase and write life of the memory. The dual storage controller can realize independent and parallel operation of the corresponding two independent memories, and there is no situation where the dual storage controller accesses the memory beyond the boundary or reads and writes data incorrectly. By adding the DMA function, the dual storage controller control and DMA receive data independently and in parallel, which can significantly improve the efficiency of application data erasing, DMA communication data reception, CPU reading and executing communication programs, and CPU responding to DMA interrupts and processing received communication data while working in parallel.

[0071] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0072] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0073] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0074] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0075] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0076] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0077] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0078] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A data processing device, characterized in that: include: a first memory and a second memory, the first memory being used to store application data, and the second memory being used to store program data; a first storage controller and a second storage controller, the first storage controller being connected to the first storage, and the second storage controller being connected to the second storage; A DMA controller, wherein the DMA controller is used to receive communication data when receiving a first instruction; A CPU processor, wherein the CPU processor is used to control the first storage controller to start erasing application data when receiving a second instruction, and control the second storage controller to read program data in the second memory after starting erasing application data or the DMA controller finishes receiving the communication data, and when erasing application data and the communication data exist at the same time, first use the read program data to process the communication data, and after the communication data processing is completed, wait for the completion of erasing the application data.

2. The data processing device according to claim 1, characterized in that: The DMA controller includes a DMA mover and a RAM memory, the DMA mover is connected to the RAM memory, and the DMA mover is used to receive communication data when receiving the first instruction, and move the received communication data to the RAM memory.

3. The data processing device according to claim 2, characterized in that: The DMA mover is also used to generate a DMA interrupt flag after the communication data is moved; The CPU processor is specifically used to determine that the DMA controller has finished receiving the communication data according to the DMA interrupt flag, and clear the DMA interrupt flag after processing the communication data using the program data.

4. The data processing device according to claim 1, characterized in that The CPU processor is also used for: The second storage controller is controlled to store the communication data received by the DMA controller and the processed communication data into the second memory.

5. The data processing device according to claim 1, characterized in that: The DMA controller receives the first instruction through a first communication interface, and the CPU processor receives the second instruction through a second communication interface.

6. The data processing device according to claim 5, characterized in that: The first communication interface includes at least one of a contactless interface, an SPI interface, and a CAN interface, and the second communication interface includes a 7816 interface.

7. The data processing device according to claim 1, characterized in that The application data includes at least one of telecommunication application data, account information data, and power usage data; the program data includes at least one of transaction program data, control program data, and power distribution communication program.

8. The data processing device according to any one of claims 1 to 7, characterized in that: The CPU processor is connected to the first storage controller and the second storage controller respectively through a bus.

9. A chip, characterized in that: The method comprises a data processing device as claimed in any one of claims 1 to 8.

10. A data processing method, characterized in that: Used in a data processing device according to any one of claims 1 to 8, the method comprising: When receiving the first instruction, receiving communication data through the DMA controller; When receiving the second instruction, controlling the first storage controller through the CPU processor to start erasing application data; After the application data is started to be erased or the DMA controller finishes receiving the communication data, the CPU processor controls the second storage controller to read the program data in the second memory; When the application data and the communication data are being erased at the same time, the communication data is first processed using the read program data, and after the communication data processing is completed, the application data is waited to be erased and written.

11. The data processing method according to claim 10, characterized in that: After the DMA controller finishes receiving the communication data, the DMA controller generates a DMA interrupt flag, wherein the CPU processor determines that the DMA controller has finished receiving the communication data according to the DMA interrupt flag.

12. The data processing method according to claim 11, characterized in that: The method further comprises: After the communication data is processed by the program data, the DMA interrupt flag is cleared by the CPU processor.

13. The data processing method according to claim 10, characterized in that: The method further comprises: The second storage controller is controlled by the CPU processor to store the communication data received by the DMA controller and the processed communication data into the second memory.

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