Data information processing device and method

Abstract

The present invention provides a data information processing device and method. The device comprises: a first interface module for sending a first control signal and data information to a control module; the control module for receiving the first control signal and the data information and generating a first instruction or a second instruction based on the first control signal; the control module for generating a third instruction based on the second control signal; a cache module for receiving the first instruction or the second instruction, writing the data information based on the first instruction, and reading the data information based on the second instruction; and a second interface module for outputting the data information read by the cache module based on the third instruction. The present invention utilizes the processing device to implement storage and access of gain values ​​used for shading correction, thereby saving storage space and improving the efficiency of gain value reading.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit integration technology, and in particular to a data information processing device and method. Background Art

[0002] When processing images captured using CCD / CMOS image sensors, the optical characteristics of the lens often lead to uneven brightness and color in the captured image. This uneven brightness is primarily due to the strong reflection and refraction of incident light at the lens edges. This causes the intensity of the light passing through the lens to gradually decrease from the center to the corners, resulting in a halo effect. This phenomenon manifests as a bright center and dark edges in the image. Color unevenness is primarily due to the different refractive indices of different wavelengths of incident light, causing them to fall on different locations on the photosensitive device. This manifests as color deviation in the image, with the deviation increasing with distance from the image center. Lens shading can negatively impact the image signal processing process, primarily causing: 1) localized deviations in image brightness and color, resulting in degraded image quality; and 2) inaccurate white balance adjustment, hindering the debugging of other algorithms. Therefore, eliminating lens shading is essential, a process known as lens shading correction.

[0003] To address the aforementioned lens shading effect, the image pixels are typically divided into several regions along the rows and columns. Each region's four vertices are assigned a gain value. Bilinear interpolation is then used to correct the pixels within the region, ensuring that the brightness of the pixels at the edges of the image is consistent with the brightness at the center. The gain values ​​are determined through testing and then stored within the chip for automatic retrieval and use later.

[0004] However, the current method of storing the gain value occupies a large amount of storage space, resulting in a waste of storage space.

[0005] Therefore, the present invention proposes a data information processing device and method to solve the above problems. Summary of the Invention

[0006] The embodiment of the present invention provides a data information processing device and method, and the storage and access of the gain value mentioned in the background technology are realized by the processing device, which can save storage space and improve the efficiency of reading the gain value.

[0007] In a first aspect, the present invention provides a data information processing device, comprising: a control module, a first interface module, a cache module, and a second interface module; the first interface module is connected to the control module and is used to send a first control signal and data information to the control module; the control module is connected to the first interface module on one side and to the second interface module on the other side; the control module is used to receive the first control signal and the data information, and generate a first instruction or a second instruction according to the first control signal; the control module is also used to receive a second control signal sent by the second interface module, and generate a third instruction according to the two control signals; the cache module is connected to the control module, is used to receive the first instruction or the second instruction, and write the data information according to the first instruction, and read the data information according to the second instruction; the first interface module is also used to receive the data information; the second interface module is used to receive the third instruction, and output the data information read by the cache module according to the third instruction.

[0008] Its beneficial effect is that: the present invention sends the first control signal to the control module through the first interface module, so that the control module generates the first instruction or the second instruction according to the first control signal, wherein the cache module performs reading or writing according to the first instruction and the second instruction, and the second interface module outputs the data information read by the cache module according to the third instruction, so that the reading and writing work of the cache module and the external output of the read data are controlled by different instructions, so the reading and writing work of the cache module and the external output of the read data are independent of each other and are not affected by their respective working clocks, thereby improving the working efficiency of the cache module for data storage and data output. If the device provided by the present invention is used to process the gain value mentioned in the background technology, not only storage space is saved, but also the processing efficiency of the gain value is improved.

[0009] Optionally, the device further includes a clock module, and the control module is connected to the clock module to obtain a clock signal; the operating clock of the first interface module is a first operating clock, and the operating clock of the second interface module is a second operating clock; the control module switches the operating clock of the cache module to the first operating clock or the second operating clock according to the clock signal. This has the beneficial effect of enabling the first interface module and the second interface module to operate at different clocks, thereby enabling the read and write operations of the cache module and the external output of read data to be controlled by different clocks through the control module. The cache module's work task at a certain moment is determined based on actual conditions, and the control module switches to the corresponding work clock based on the work task.

[0010] Optionally, the first control signal includes at least one of a read / write operation signal, a read / write address signal, and a read / write data signal; and the second control signal includes at least one of a read operation signal, a read address signal, and a read data signal. This advantageously enables the control module to implement different specific functions through different control signals to meet actual needs.

[0011] Optionally, the first instruction includes at least one of a write operation instruction, a write address instruction, and a write data instruction; and the second instruction includes at least one of a first read operation instruction, a first read address instruction, and a first read data instruction. This advantageously enables the cache module to implement different functions through different instructions to meet specific needs.

[0012] Optionally, the third instruction includes at least one of a second read operation instruction, a second read address instruction, and a second read data instruction. The beneficial effect is that different instructions enable the second interface module to implement different functions to meet specific needs.

[0013] In a second aspect, the present invention provides a method for processing data information, comprising: providing a first interface module, a control module, a second interface module and a cache module; the first interface module sends a first control signal and data information to the control module; the control module receives the first control signal and the data information, and generates a first instruction or a second instruction based on the first control signal; the control module also receives a second control signal sent by the second interface module, and generates a third instruction based on the two control signals; the cache module receives the first instruction or the second instruction, and writes the data information according to the first instruction, and also reads the data information according to the second instruction; the first interface module receives the data information; the second interface module receives the third instruction, and outputs the data information read by the cache module according to the third instruction.

[0014] Its beneficial effect is that: the present invention sends the first control signal to the control module through the first interface module, so that the control module generates the first instruction or the second instruction according to the first control signal, wherein the cache module performs reading or writing according to the first instruction and the second instruction, and the second interface module outputs the data information read by the cache module according to the third instruction, so that the reading and writing work of the cache module and the external output of the read data are controlled by different instructions, so the reading and writing work of the cache module and the external output of the read data are independent of each other and are not affected by their respective working clocks, thereby improving the working efficiency of the cache module for data storage and data output. If the method provided by the present invention is used to process the gain value mentioned in the background technology, not only storage space is saved, but also the processing efficiency of the gain value is improved.

[0015] Optionally, the method further includes: the first interface module operating at a first operating clock, the second interface module operating at a second operating clock; and the control module switching the cache module operating at the first operating clock or the second operating clock based on the clock signal. This advantageously allows the first and second interface modules to operate at different clocks, thereby enabling the cache module's read and write operations and external output of read data to be controlled by different clocks via the control module. The control module then determines the cache module's work task at a given moment based on actual conditions, and switches to the corresponding work clock based on the work task.

[0016] Optionally, the first control signal includes at least one of a read / write operation signal, a read / write address signal, and a read / write data signal; and the second control signal includes at least one of a read operation signal, a read address signal, and a read data signal. This advantageously enables the control module to implement different specific functions through different control signals to meet actual needs.

[0017] Optionally, the first instruction includes at least one of a write operation instruction, a write address instruction, and a write data instruction; and the second instruction includes at least one of a first read operation instruction, a first read address instruction, and a first read data instruction. This advantageously enables the cache module to implement different functions through different instructions to meet specific needs.

[0018] Optionally, the third instruction includes at least one of a second read operation instruction, a second read address instruction, and a second read data instruction. The beneficial effect is that different instructions enable the second interface module to implement different functions to meet specific needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of a data information processing device provided in an embodiment of the present application;

[0020] Figure 2 A schematic diagram of another data information processing device provided in an embodiment of the present application;

[0021] Figure 3 A flow chart of a method for processing data information provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application. Among them, in the description of the embodiments of the present application, the terms used in the following embodiments are only for the purpose of describing specific embodiments, and are not intended to be used as limitations on the present application. As used in the specification and claims of the present application, the singular expressions "a", "the", "above", "the" and "this" are intended to also include expressions such as "one or more", unless there is a clear contrary indication in the context. It should also be understood that in the following embodiments of the present application, "at least one", "one or more" refer to one or more (including two). The term "and / or" is used to describe the association relationship of associated objects, indicating that three relationships can exist; for example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0023] References to "one embodiment" or "some embodiments" etc. described in this specification mean that the specific features, structures or characteristics described in conjunction with the embodiment are included in one or more embodiments of the present application. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. appearing in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in another way. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in another way. The term "connected" includes direct and indirect connections, unless otherwise stated. "First" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0024] In the embodiments of this application, words such as "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplarily" or "for example" is intended to present the relevant concepts in a concrete manner.

[0025] This embodiment proposes a cache module, namely an SRAM module, applicable to the entire inventive content of the present invention. The SRAM module includes a storage array and row and column circuits (used to control operations such as read, write, and refresh; the storage array and row and column circuits are not shown in the accompanying drawings). The storage array is also composed of multiple storage cells arranged in rows and columns. The storage array is composed of SRAM cells, which are composed of complementary metal oxide semiconductor field effect transistors, including access transistors, which are used to control access to the storage cells during read and write operations. Of course, the cache module 202 can also be composed of any number and combination of dynamic random access memories (DRAMs), flash memories, and first-in-first-out (FIFO) queues.

[0026] The present application provides a data information processing device, such as Figure 1 As shown, the apparatus includes: a control module 101, a first interface module 102, a cache module 103, and a second interface module 104. For example, the first interface module 102 may be an Advanced Peripheral Bus (APB), and the cache module 103 may be a Static Random-Access Memory (SRAM).

[0027] The first interface module 102 is connected to the control module 101 and is used to send control signals and data information to the control module 101. The control module 101 is connected to the first interface module 102 on one side and to the second interface module 104 on the other side. The control module 101 is used to receive the first control signal and the data information and generate a first instruction or a second instruction based on the first control signal. The control module 101 is also used to receive a second control signal from the second interface module 104 and generate a third instruction based on the second control signal. The cache module 103 is connected to the control module 101 and is used to receive the first instruction or the second instruction, write the data information according to the first instruction, and read the data information according to the second instruction. The first interface module 102 is also used to receive the data information. The second interface module 104 is used to receive the third instruction and output the data information read by the cache module 103 according to the third instruction.

[0028] For example, the data information may be a gain value used for image shading correction. The first interface module 102 sends the gain value and a first control signal for the gain value to the control module 101. The first and second instructions are used to control the specific operations of the cache module 103; the third instruction is used to control the specific operations of the second interface module 104. The cache module 103 writes the gain value to a certain address in accordance with the first instruction and stores it in the corresponding location of the cache module 103. The cache module 103 also reads the gain value and its address information in accordance with the second instruction. The second interface module 104 is configured to read the gain value in accordance with the read data instruction and to read the address information of the gain value in accordance with the address information instruction.

[0029] In a possible embodiment, the device further includes a clock module 201, such as Figure 2 As shown, the control module 101 is connected to the clock module 201 to obtain a clock signal; the working clock of the first interface module 102 is a first working clock, and the working clock of the second interface module 104 is a second working clock; the control module 101 switches the working clock of the cache module 103 to the second working clock according to the clock signal.

[0030] For example, the first interface module 102 can use the second instruction to cause the cache module 103 to read the data information stored therein to verify whether the data information is stored correctly, and the first interface module 102 can perform a self-test operation when the processing device is idle. When the operating clocks of the first interface module 102 and the second interface module 104 are inconsistent, the read and write operations of the cache module 103 and the external output of the read data can be controlled by different clocks through the control module 101. Based on the actual situation, the working task of the cache module 103 at a certain moment is determined, and the control module 101 switches to the corresponding working clock according to the working task.

[0031] In another possible embodiment, the first control signal includes: at least one of a read / write operation signal, a read / write address signal, and a read / write data signal; the second control signal includes: at least one of a read operation signal, a read address signal, and a read data signal.

[0032] Exemplarily, the read / write operation signal is used to cause the control module 101 to generate the first read operation instruction or write operation instruction; the read / write address signal is used to cause the control module 101 to generate the first read address instruction or write address instruction; and the read / write data signal is used to cause the control module 101 to generate the first read data instruction or write data instruction. The read operation signal is used to cause the control module 101 to generate a second read operation instruction; the read address signal is used to cause the control module 101 to generate a second read address instruction; and the read data signal is used to cause the control module 101 to generate a second read data instruction. Different control signals enable the control module 101 to implement different specific functions to meet actual needs. In the optimal embodiment of the present invention, the first control signal simultaneously includes three signals: a read / write operation signal, a read / write address signal, and a read / write data signal; and the second control signal simultaneously includes three signals: a read operation signal, a read address signal, and a read data signal.

[0033] In another possible embodiment, the first instruction includes at least one of a write operation instruction, a write address instruction, and a write data instruction, and the second instruction includes at least one of a first read operation instruction, a first read address instruction, and a first read data instruction.

[0034] In this embodiment, the read and write operation instructions are used to control the cache module 103 to read or write the accessed storage unit. The read and write address instructions are used to control the cache module 103 to read or write the address of the accessed storage unit. The read and write data instructions are used to control the cache module 103 to read or write the data of the accessed storage unit. In the most preferred embodiment of the present invention, the first instructions include a write operation instruction, a write address instruction, and a write data instruction; and the second instructions include a first read operation instruction, a first read address instruction, and a first read data instruction.

[0035] In another possible embodiment, the third instruction includes at least one of a second read operation instruction, a second read address instruction, and a second read data instruction.

[0036] Illustratively, the second read operation instruction is used to control the cache module 103 to perform a read operation on the accessed storage unit. The second read address instruction is used to output the address read by the cache module 103. The second read data instruction is used to output the data read by the cache module 103. In a preferred embodiment of the present invention, the third instruction includes three instructions: a second read operation instruction, a second read address instruction, and a second read data instruction.

[0037] The embodiment of the present application provides a method for processing data information. Before processing, a first interface module, a control module, a second interface module and a cache module are required. The steps are as follows: Figure 3 The specific steps are as follows:

[0038] S301: The first interface module sends a first control signal and data information to the control module.

[0039] Exemplarily, the data information may be a gain value used to perform image shading correction, and the control signal may be a signal for controlling processing of the gain value.

[0040] S302, the control module receives the first control signal and the data information, and generates a first instruction or a second instruction according to the first control signal; the control module also receives a second control signal sent by the second interface module, and generates a third instruction according to the second control signal.

[0041] Exemplarily, the first instruction and the second instruction are instructions for controlling specific work contents of the cache module, and the third instruction is an instruction for controlling specific work contents of the second interface module.

[0042] S303, the cache module receives the first instruction or the second instruction, writes the data information according to the first instruction, and reads the data information according to the second instruction; the first interface module receives the data information.

[0043] Exemplarily, the cache module writes the gain value of a certain address information according to the first instruction and stores it in a corresponding position of the cache module. The cache module also reads the gain value and its address information according to the second instruction.

[0044] S304: The second interface module receives the third instruction and outputs the data information read by the cache module according to the third instruction.

[0045] Exemplarily, when the third instruction is a second read data instruction and a second read address information instruction, the second interface module is used to read the gain value according to the second read data instruction, and is also used to read the address information of the gain value according to the second read address information instruction.

[0046] In a possible embodiment, the working clock of the first interface module is a first working clock, and the working clock of the second interface module is a second working clock; the control module switches the working clock of the cache module to the first working clock or the second working clock according to the clock signal.

[0047] Exemplarily, when the working clocks of the first interface module and the second interface module are inconsistent, the reading and writing work of the cache module and the external output work of the read data can be controlled by different clocks through the control module, and according to actual conditions, the working task of the cache module at a certain moment is determined, and the control module switches to the corresponding working clock according to the working task.

[0048] In another possible embodiment, the first control signal includes: at least one of a read / write operation signal, a read / write address signal, and a read / write data signal; the second control signal includes: at least one of a read operation signal, a read address signal, and a read data signal.

[0049] Exemplarily, the read / write operation signal is used to cause the control module to generate the first read operation instruction or write operation instruction; the read / write address signal is used to cause the control module to generate the first read address instruction or write address instruction; and the read / write data signal is used to cause the control module to generate the first read data instruction or write data instruction. The read operation signal is used to cause the control module to generate a second read operation instruction; the read address signal is used to cause the control module to generate a second read address instruction; and the read data signal is used to cause the control module to generate a second read data instruction. Through different control signals, the control module can implement different specific functions to meet actual needs. The optimal implementation method of the present invention is that the first control signal simultaneously includes three signals: a read / write operation signal, a read / write address signal, and a read / write data signal; and the second control signal simultaneously includes three signals: a read operation signal, a read address signal, and a read data signal.

[0050] In another possible embodiment, the first instruction includes at least one of a write operation instruction, a write address instruction, and a write data instruction, and the second instruction includes at least one of a first read operation instruction, a first read address instruction, and a first read data instruction.

[0051] In this embodiment, the read and write operation instructions are used to control the cache module's read or write operations on the accessed storage unit. The read and write address instructions are used to control the cache module's read or write operations on the address of the accessed storage unit. The read and write data instructions are used to control the cache module's read or write operations on the data of the accessed storage unit. The optimal implementation of the present invention is that the first instruction includes three instructions: a write operation instruction, a write address instruction, and a write data instruction; and the second instruction includes three instructions: a first read operation instruction, a first read address instruction, and a first read data instruction.

[0052] In another possible embodiment, the third instruction includes at least one of a second read operation instruction, a second read address instruction, and a second read data instruction.

[0053] Exemplarily, the second read operation instruction is used to control the cache module 103 to perform a read operation on the accessed storage unit. The second read address instruction is used to output the address read by the cache module. The read data instruction is used to output the data read by the cache module. In a preferred embodiment of the present invention, the third instruction includes four instructions: a second read operation instruction, a second read address instruction, and a second read data instruction.

[0054] The above description is merely a specific implementation of the embodiments of the present application, but the scope of protection of the embodiments of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the embodiments of the present application shall be included in the scope of protection of the embodiments of the present application. Therefore, the scope of protection of the embodiments of the present application shall be based on the scope of protection of the claims.

Claims

1. A data information processing device, characterized in that: include: A control module, a first interface module, a storage module, a second interface module and a cache module; The first interface module is connected to the control module and is used to send a first control signal and data information to the control module; The control module is connected to the first interface module on one side and to the second interface module on the other side; the control module is used to receive the first control signal and the data information, and generate a first instruction or a second instruction according to the first control signal; the control module is also used to receive a second control signal sent by the second interface module, and generate a third instruction according to the second control signal; The cache module is connected to the control module and is used to receive the first instruction or the second instruction, write the data information according to the first instruction, and read the data information according to the second instruction; the first interface module is also used to receive the data information; The second interface module is configured to receive the third instruction and output the data information read by the cache module according to the third instruction.

2. The device according to claim 1, characterized in that It also includes a clock module, and the control module is connected to the clock module to obtain a clock signal; The working clock of the first interface module is a first working clock, and the working clock of the second interface module is a second working clock; The control module switches the working clock of the cache module to the first working clock or the second working clock according to the clock signal.

3. The device according to claim 1, characterized in that The first control signal includes at least one of a read / write operation signal, a read / write address signal, and a read / write data signal; the second control signal includes at least one of a read operation signal, a read address signal, and a read data signal.

4. The device according to claim 1, characterized in that The first instruction includes at least one of a write operation instruction, a write address instruction, and a write data instruction; the second instruction includes at least one of a first read operation instruction, a first read address instruction, and a first read data instruction.

5. The device according to claim 1, characterized in that The third instruction includes at least one of a second read operation instruction, a second read address instruction, and a second read data instruction.

6. A method for processing data information, characterized in that: include: Providing a first interface module, a control module, a second interface module and a cache module; The first interface module sends a first control signal and data information to the control module; The control module receives the first control signal and the data information, and generates a first instruction or a second instruction according to the first control signal; the control module also receives a second control signal sent by the second interface module, and generates a third instruction according to the second control signal; The cache module receives the first instruction or the second instruction, writes the data information according to the first instruction, and reads the data information according to the second instruction; The first interface module receives the data information; The second interface module receives the third instruction and outputs the data information read by the cache module according to the third instruction.

7. The method according to claim 6, characterized in that Also includes: Providing a clock module, the control module is connected to the clock module to obtain a clock signal; The working clock of the first interface module is a first working clock, and the working clock of the second interface module is a second working clock; The control module switches the working clock of the cache module to the first working clock or the second working clock according to the clock signal.

8. The method according to claim 6, characterized in that The first control signal includes at least one of a read / write operation signal, a read / write address signal, and a read / write data signal; the second control signal includes at least one of a read operation signal, a read address signal, and a read data signal.

9. The method according to claim 6, characterized in that The first instruction includes at least one of a write operation instruction, a write address instruction, and a write data instruction; the second instruction includes at least one of a first read operation instruction, a first read address instruction, and a first read data instruction.

10. The method according to claim 6, characterized in that The third instruction includes at least one of a second read operation instruction, a second read address instruction, and a second read data instruction.

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