Data acquisition, reporting method, system, chip, CPU and storage medium

Abstract

The embodiment of the present application provides a data collection and reporting method, system, business chip, CPU and storage medium, a shared memory which can be accessed by the business chip and the CPU is arranged outside the business chip and the CPU, the shared memory comprises a plurality of shared memory segments, the business chip can write the collected reporting data into the idle memory segment of the shared memory, the CPU can read the data in the occupied memory segment by directly accessing the shared memory, thereby obtaining the reporting data from the business chip, and the occupied memory segment is changed into the idle memory segment again, so that the business chip can write data. Moreover, since the access speed of the CPU to the shared memory is greater than the access speed of the CPU to the business chip, the data collection speed of the CPU can be improved by the data collection scheme provided in the embodiment of the present application, thereby reducing the resource occupation of the CPU in data collection and improving the processing performance of the CPU to other transactions.

Description

Technical Field

[0001] The embodiments of the present invention relate to, but are not limited to, the field of communications. Specifically, they relate to, but are not limited to, a data acquisition and reporting method, system, service chip, CPU, and storage medium. Background Technology

[0002] As the service density on the service board continues to increase, the amount of performance alarm data collected on the service board is also growing. In related technologies, the CPU of the service board accesses the service chip on the service board through PCIe (Peripheral Component Interconnect Express) interface, Local Bus (Local Bus, CPU bus) interface, etc., to obtain the performance alarm data collected by the service chip, thereby realizing data collection. However, because the CPU access speed to the service chip is quite slow, even if the CPU only performs data collection once per second, more than half of the processing resources will be occupied, thus affecting the CPU's processing performance in other aspects. Summary of the Invention

[0003] The data acquisition and reporting method, system, business chip, CPU, and storage medium provided in this invention mainly solve the technical problem that the relevant data acquisition schemes consume a lot of CPU processing resources, affecting the CPU's performance in processing other tasks.

[0004] To address the aforementioned technical problems, embodiments of the present invention provide a data collection and reporting method, comprising:

[0005] The business chip collects data and obtains the reported data.

[0006] The service chip writes the reported data to the idle memory segment of the shared memory. The shared memory is accessible to both the service chip and the CPU, and the CPU's access speed to the shared memory is greater than the CPU's access speed to the service chip. The shared memory includes multiple memory segments, and the idle memory segment is the memory segment that is in an idle state.

[0007] This invention also provides a data acquisition method, comprising:

[0008] The CPU reads the reported data from the occupied memory segment of the shared memory. The reported data in the occupied memory segment is written by the application chip. The CPU's access speed to the shared memory is greater than the CPU's access speed to the application chip. The shared memory includes multiple memory segments, and the occupied memory segment is the memory segment that is in an occupied state.

[0009] The CPU sets the occupied memory segment to an idle memory segment.

[0010] This invention also provides a service chip, which includes a microcontroller and a chip memory communicatively connected to the microcontroller.

[0011] The microcontroller is used to execute one or more programs stored in the chip memory to implement the steps of the above data acquisition and reporting method.

[0012] This invention also provides a CPU for executing one or more programs to implement the steps of the above-described data acquisition method.

[0013] This invention also provides a data acquisition system, characterized in that it includes shared memory, the aforementioned service chip, and the aforementioned CPU; the shared memory is accessed by both the service chip and the CPU, and the CPU's access speed to the shared memory is greater than its access speed to the service chip; the shared memory includes multiple memory segments.

[0014] This invention also provides a storage medium storing at least one of a data acquisition and reporting program and a data acquisition program. The data acquisition and reporting program can be executed by one or more processors to implement the steps of the above-described data acquisition and reporting method; the data acquisition program can be executed by one or more processors to implement the steps of the above-described data acquisition method.

[0015] According to the data acquisition and reporting method, system, service chip, CPU, and storage medium provided in the embodiments of the present invention, the service chip acquires data to obtain reporting data, and then writes the reporting data to an idle memory segment of shared memory. The CPU reads the reporting data from the occupied memory segment of shared memory, and after reading, the CPU sets the occupied memory segment as an idle memory segment. By setting a shared memory that can be accessed by both the service chip and the CPU, and the shared memory includes multiple shared memory segments, the service chip can write the acquired reporting data to the idle memory segment of the shared memory. The CPU can directly access the shared memory, read the data in the occupied memory segment to obtain the reporting data from the service chip, and then set the occupied memory segment back to an idle memory segment for the service chip to write data. Moreover, since the CPU's access speed to this shared memory is greater than the CPU's access speed to the service chip, the data acquisition scheme provided in the embodiments of the present invention can improve the CPU's data acquisition speed, thereby reducing the CPU's resource consumption in data acquisition and improving the CPU's processing performance for other tasks.

[0016] Other features and corresponding beneficial effects of the present invention will be described in the latter part of the specification, and it should be understood that at least some of the beneficial effects will become obvious from the description in the specification. Attached Figure Description

[0017] Figure 1 This is a flowchart of a data acquisition method shown in Embodiment 1 of the present invention;

[0018] Figure 2 This is a flowchart illustrating how a service chip writes reporting data into an idle memory segment of shared memory, as shown in Embodiment 1 of the present invention.

[0019] Figure 3 This is a flowchart illustrating a CPU reading data from shared memory, as shown in Embodiment 1 of the present invention.

[0020] Figure 4 This is a flowchart illustrating how a business chip writes data to a chip memory, as shown in Embodiment 2 of the present invention.

[0021] Figure 5 This is a flowchart illustrating how a service chip writes data to shared memory, as shown in Embodiment 2 of the present invention.

[0022] Figure 6 This is a flowchart illustrating a CPU reading data from shared memory, as shown in Embodiment 2 of the present invention.

[0023] Figure 7 This is a schematic diagram of a hardware structure of a service chip provided in Embodiment 3 of the present invention;

[0024] Figure 8 This is a schematic diagram of a data acquisition system provided in Embodiment 3 of the present invention;

[0025] Figure 9 This is a schematic diagram of a functional unit in the data acquisition system provided in Embodiment 3 of the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the embodiments of this invention will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0027] Example 1:

[0028] The rapid development of technologies such as 5G, IoT, cloud computing, and big video has placed higher demands on the transmission bandwidth of core services. Traffic at core nodes is growing rapidly, with the switching capacity of some core nodes already evolving towards 100T+ (i.e., exceeding 100T). Although traffic is experiencing explosive growth, the number of subrack slots in OTN (Optical Transport Network) equipment is limited. Therefore, to meet the demands of high-volume services, it is necessary to continuously increase the bandwidth per slot, leading to a rapid increase in service density per slot. Currently, the bandwidth per slot has evolved from 100G, 200G, and 400G, continuously moving towards 1T, 1.2T, and even 2.4T.

[0029] The increase in single-slot bandwidth leads to a surge in the amount of performance alarm data collected per slot. For example, with a single-slot bandwidth of 100G, the amount of performance alarm data to be collected is 6KB, but when the single-slot bandwidth is upgraded to 2.4T, the amount of performance alarm data to be collected becomes 150KB. In the relevant data acquisition scheme, after the service chip on the service board generates raw performance alarm data, the service board CPU needs to access the service chip through the PCIe interface or Locbus interface to obtain the raw performance alarm data. Subsequently, the CPU processes the collected data and reports it to the main control board. Because the CPU's access to the service chip is inefficient, a single data acquisition by the CPU takes a long time. During this period, most of the CPU's processing resources are occupied, inevitably affecting the CPU's performance in processing other tasks.

[0030] To address the aforementioned issues, this embodiment provides a data acquisition scheme. Please refer to [link / reference]. Figure 1 The following is an optional flowchart of a data acquisition scheme:

[0031] S102: The business chip collects data and obtains the reported data.

[0032] It is understood that the service chip can be located on the service board to process the services on the service board. In this embodiment, the service chip and the CPU can be located on the same board or on different boards. For example, in some examples, the service chip is on the service board (line card), while the CPU is on the main control board (main card). In other examples, the service chip and the CPU are both located on the same service board.

[0033] The service chip itself generates raw performance alarm data. Therefore, in some examples of this embodiment, the service chip can directly use this raw data as reported data. Considering that if the raw data is directly reported to the CPU, the CPU would need to process this raw data after data acquisition, for example, processing the raw performance alarm data according to the OTN standard G.798 protocol before obtaining data that can be reported or used, in other examples of this embodiment, the service chip can perform secondary processing on the raw data to obtain the reported data. For example, the service chip can process the raw data according to alarm filtering rules to obtain the reported data. In this example, after receiving the reported data from the service chip, the CPU does not need to perform secondary processing and can directly report the reported data to the main control board, or directly perform control and management based on the reported data.

[0034] S104: The service chip writes the reported data to an idle memory segment of the shared memory.

[0035] After receiving reported data, the application chip can write the data to an idle memory segment of shared memory for the CPU to access. Shared memory refers to memory that can be shared by the application chip and the CPU, allowing joint access from both. Shared memory includes multiple memory segments, which can be divided into idle and occupied segments based on their occupancy status. An idle memory segment is one that is currently unused. It's worth noting that in some examples, an idle memory segment means it's currently free, i.e., no data has been written to it. However, in other examples, an idle memory segment may store reported data, but this data has already been read by the CPU and can now be cleared or overwritten. An occupied memory segment is the memory segment currently occupied by reported data that has been written to it but not yet read by the CPU; it is the memory segment occupied by valid reported data. After receiving reported data, the application chip can write it to an idle memory segment.

[0036] In some examples of this embodiment, the service chip can be configured according to... Figure 2 The flowchart shown illustrates writing reported data to an idle memory segment of shared memory:

[0037] S202: Indicator table for service chip access to shared memory.

[0038] In this embodiment, an indicator table can be set for the shared memory. This indicator table is used to indicate the address information, status, etc. of each memory segment. For example, in some examples, the indicator table includes multiple indicator rows, each of which uniquely corresponds to a memory segment in the shared memory. That is, the indicator row is only used to indicate the information of that memory segment and has no relation to other memory segments. In some examples, a memory segment can correspond to two or more indicator rows at the same time. For example, in one example, a memory segment 'a' corresponds to three indicator rows in the indicator table. The first indicator row records the address information of memory segment 'a', the second indicator row records the status information of memory segment 'a', that is, whether memory segment 'a' is in an idle state or an occupied state, and the third indicator row is used to indicate the data length in memory segment 'a'. It can be seen that in these examples, the correspondence between memory segments and indicator rows is a "one-to-many" relationship. In some examples, there is a one-to-one correspondence between memory segments and instruction rows. That is, a memory segment has one and only one instruction row in the instruction table. This instruction row records the address information and status information of the memory segment. In other examples, the address information recorded in the instruction row is the starting address information of the memory segment. At the same time, the instruction row also records the length of the stored data in the memory segment. Of course, in some other examples of this embodiment, the instruction row may not need to record the data length, because the size of each memory segment is the same. For the application chip, knowing the size of the memory segment means knowing how much data it cannot write to a memory segment. For the CPU, knowing the size of a memory segment means knowing where it has read all the reported data in the occupied memory segment when reading the reported data.

[0039] It should be understood that if the instruction row only records the start address information of a memory segment, then the storage space within that memory segment should be contiguous. Normally, the storage space within a memory segment is contiguous, and the storage spaces of adjacent memory segments may or may not be contiguous. However, in some examples of this embodiment, the storage space within a memory segment is not contiguous. For example, a memory segment may be further divided into two sub-segments, and the storage space between the first and second sub-segments is not contiguous. Therefore, when recording the address information of this memory segment, the instruction table cannot record only a single start address.

[0040] In some examples of this embodiment, the shared memory instruction table can be directly stored in a fixed location in the shared memory. This storage location is known in advance by both the service chip and the CPU. Therefore, the service chip can access the instruction table according to this storage location. In other examples, the shared memory instruction table can also be stored in a storage space outside the shared memory. Similarly, the service chip and the CPU know the storage location of the instruction table in advance.

[0041] S204: The service chip searches the instruction table for the first target instruction row whose status is idle.

[0042] When the service chip needs to write reported data into shared memory, it can access the indicator table corresponding to the shared memory and look up the indicator row whose status is idle as the target indicator row. It can be understood that when the service chip queries the indicator table of shared memory, it is to find the indicator row whose status is idle. The CPU also queries the indicator table, but the CPU is to find the indicator row whose status is occupied. In order to distinguish the target row found by the service chip querying the indicator table from the target row found by the CPU querying the indicator table, in this embodiment, the target row found by the service chip querying the indicator table is called the first indicator row, and the target row found by the CPU querying the indicator table is called the second indicator row. The first indicator row is the indicator row corresponding to the idle memory segment, and the second indicator row is the indicator row corresponding to the occupied memory segment.

[0043] In some examples, the application chip can query the first target indicator row from the first row of the indicator table, row by row. Alternatively, in other examples, the application chip can query from the row following its most recently selected first target indicator row each time, until the last row of the indicator table, and then start querying again from the first row. For example, assuming the application chip's most recently selected first target indicator row is row 12, in this query process, the application chip can directly query the status of the record in row 13. If the record's status is idle, it is used as the first target indicator row for this query; if the record's status is occupied, it continues querying row 14. Of course, these two query methods are not the only methods. In other examples, the application chip can randomly start traversing from any position and in any order to search for the first target indicator row, as long as an idle memory segment can be found.

[0044] S206: The service chip obtains the address information recorded in the first target indication line.

[0045] After the business chip finds the first target instruction row in the instruction table, it can directly obtain the address information recorded in the first target instruction row. This address information is the address information of the idle memory segment that the business chip needs to find. For example, in some examples, the business chip can obtain the starting address information of the idle memory segment; in other examples, the business chip can obtain the starting and ending address information of the idle memory segment.

[0046] S208: The service chip writes the reported data into the idle memory segment according to the address information, and changes the status to occupied status in the first target indication line.

[0047] After obtaining the address information of an idle memory segment, the application chip can write the reported data into the idle memory segment according to that address information. To ensure the CPU is aware that data has been written to this memory segment and can read the written data promptly, and to prevent the application chip from continuing to write data to the memory segment before the CPU reads the data from it, the application chip will change the status in the first target indicator line to "occupied." It's understandable that the application chip can modify the status of the memory segment after writing data to it, or it can immediately modify the status of an indicator line to "occupied" after selecting it as the first target indicator line. Since the application chip will definitely write data to the memory segment corresponding to that line after selecting it as the first target indicator line, directly modifying the status in the first target indicator line avoids the application chip needing to access the indicator table twice during a single data write, reducing the burden on the application chip.

[0048] In the above example, the service chip immediately writes the reported data into the shared memory after receiving it. However, in other examples of this embodiment, after receiving the reported data, the service chip can first store the reported data in its internal chip memory. Then, once the amount of data in the chip memory meets the requirements, or when the reporting time arrives, the reported data in the chip memory is written into the shared memory. This reduces the number of times the service chip accesses the shared memory and the shared memory indicator table, thus reducing the data reporting burden on the service chip.

[0049] In some examples of this embodiment, the service chip is equipped with RAM (Random Access Memory), which can be used as chip memory.

[0050] Understandably, the business chip acquires data very quickly. Therefore, if the business chip directly writes the acquired data to shared memory, it will quickly fill up the idle memory segments of shared memory. However, if the CPU needs to maintain the same data read speed as the business chip's data write speed, the processing resource consumption will be relatively high. But if a chip memory is set up as a "transfer station" for reported data, since chip memory is usually not very large, the amount of reported data that the business chip can store is relatively limited. When the amount of data already stored in the chip memory reaches the storage threshold, the business chip cannot continue to write data and must pause data acquisition. This serves to control the business chip's ability to start data acquisition tasks. Therefore, for the business chip, when writing reported data to the chip memory, it needs to first determine whether the existing data storage in the chip memory has reached the storage threshold. Only if the result is no, can the business chip continue to write reported data; otherwise, the business chip will pause data acquisition. In some examples, the storage threshold is the maximum storage capacity of the chip memory.

[0051] Optionally, the service chip can periodically or non-periodically write reported data from the chip memory to the shared memory. For example, in some examples of this embodiment, the service chip retrieves reported data from the chip memory and writes it to the shared memory according to the data reporting cycle. The size of the data reporting cycle can be set according to the processing capability of the service chip. In some examples of this embodiment, the CPU also periodically reads data from the shared memory. For example, the CPU reads data according to the data acquisition cycle. Optionally, the data acquisition cycle is n times the data reporting cycle, where n is greater than or equal to 1. In some examples, the data reporting cycle is equal to the data acquisition cycle; for every data write operation by the service chip to the shared memory, the CPU will also perform a data read operation. In other examples of this embodiment, the data acquisition cycle is longer than the data reporting cycle. This allows the CPU to perform a data read operation only after the service chip has performed two or more data write operations. This allows the storage space of the shared memory to be used to increase the CPU's processing time, reducing the CPU's processing burden.

[0052] It should be understood that after the business chip writes the reported data from the chip memory to the shared memory, it should clear the reported data from the chip memory in order to free up the chip memory to write new reported data.

[0053] S106: The CPU reads the reported data from the occupied memory segment of shared memory.

[0054] The CPU can read reported data from occupied memory segments in shared memory. This read data can be used for management and control, or further reported to the main control board. When reading reported data, the CPU first needs to locate the occupied memory segment in shared memory. In some examples of this embodiment, the CPU can directly traverse each memory segment in shared memory to find the segment with reported data. In other examples, the CPU can determine the occupied memory segment based on shared memory indication information. For example, in some examples of this embodiment, the CPU reads reported data according to the shared memory indication table: the CPU searches the indication table for the second target indication line whose status is occupied, and then reads the data according to the address information recorded in the second target indication line.

[0055] S108: The CPU sets the occupied memory segment to an idle memory segment.

[0056] Of course, to achieve cyclical use of shared memory, after the CPU reads data from the occupied memory segment, the occupied memory segment should be set as an idle memory segment. In some examples of this embodiment, the CPU can directly clear the data in the occupied memory segment where data reading has been completed, so that the application chip can directly write data to these idle memory segments later. In this case, since no corresponding indication information is set for the memory segment, the application chip needs to access each memory segment separately to determine whether the memory segment is an idle memory segment. In other examples, since the CPU and the application chip manage shared memory based on an indication table, the application chip can write data in an overwrite manner. Therefore, the CPU does not need to clear the reported data in the occupied memory segment. In this case, in order to let the application chip know that these memory segments are in an idle state, the CPU can change the recorded status from occupied state to idle state in the second target indication line. Of course, in some examples, the CPU can both clear the reported data in the occupied memory segment and modify the status in the second target indication line.

[0057] Figure 3 This diagram illustrates a process where the CPU reads data from shared memory. The following section combines... Figure 3 The illustrated process describes the CPU-side process:

[0058] S302: Indicator table for CPU access to shared memory.

[0059] The CPU knows the storage location of the instruction table in advance, so it can access the instruction table at that address each time it needs to. In this embodiment, the instruction table can be stored in a fixed location in shared memory.

[0060] S304: The CPU searches the instruction table for the second target instruction line whose status is occupied.

[0061] The CPU can search for the second target indicator line from the first line of the indicator table, line by line. Alternatively, in some examples, the CPU can start searching from the line following its most recently selected second target indicator line each time, until it reaches the last line of the indicator table, and then start searching again from the first line. For example, assuming the CPU's most recently selected first target indicator line is the 4th line of the indicator table, then in this search process, the CPU can start searching from the 5th line. If the recorded status is occupied, it will be used as the second target indicator line for this search; if the recorded status is idle, it will continue searching to the 6th line. Of course, these two search methods are not the only ones. In other examples, the CPU can randomly start searching for the second target indicator line from any position and in any order, as long as it can find the occupied memory segment.

[0062] S306: The CPU obtains the address information recorded in the second target instruction line.

[0063] In some examples of this embodiment, the address information recorded in the second target indication line is the start address information of the corresponding memory segment. In other examples of this embodiment, the address information recorded in the second target indication line is the start and end address information of the corresponding memory segment.

[0064] Optionally, the second target indication line may also record at least one of several, such as the size of the memory segment and the length of the reported data already stored in the memory segment.

[0065] S308: The CPU reads the reported data from the occupied memory segment of shared memory according to the address information.

[0066] After the CPU obtains the address information, it can read data according to that address. For example, if the CPU obtains start and end address information, it can start reading data from that start address. The end address can be determined based on the size of the memory segment. For instance, if all memory segments are the same size and the CPU knows their sizes, it can combine the obtained start address information with its pre-known memory segment sizes to determine the start and end positions of the read operation. In other examples, although the sizes of the memory segments are different, the size of the corresponding memory segment is recorded in the second target instruction table. Therefore, the CPU can also determine the start address and size of the memory segment by querying the instruction table, and thus determine the start and end positions of the read operation. In still other examples, the instruction table records the length of data already stored in each memory segment. In this case, the CPU can accurately determine the start and end positions of the read operation, avoiding reading from spaces where no data has been written. This improves the efficiency of CPU data reading, reduces CPU resource consumption in data acquisition, and enhances CPU processing performance.

[0067] S310: The CPU clears the occupied memory segment and changes the status to idle in the second target indication line.

[0068] After reading data, the CPU can clear the reported data in the occupied memory segment, making the occupied memory segment idle. Furthermore, to inform the application chips that these memory segments are now idle, the CPU will also modify the recorded status in the second target instruction line to idle. It is understandable that the CPU can modify the information recorded in the second target instruction line either after clearing the occupied memory segment or simultaneously with clearing it.

[0069] In the above example, the CPU and the application chip manage shared memory based on an instruction table. However, in other examples of this embodiment, shared memory management can be implemented without an instruction table. For example, in shared memory, all address spaces are contiguous, and the size of each memory segment is consistent. In this case, the CPU and the application chip only need to know the starting address of the shared memory to find each memory segment. In these examples, an instruction information storage space can be set at a fixed location in the memory segment, such as the beginning of the memory segment. This instruction information storage space records the current state of the memory segment. In some examples, the instruction information storage space can also record the length of the reported data already stored in the memory segment. However, it is clear that managing shared memory based on an instruction table avoids the problem of the CPU and application chip needing to traverse the shared memory when reading and writing data, which is beneficial to significantly improving the data reading and writing efficiency of the CPU and application chip and reducing the processing burden of the CPU and application chip.

[0070] In some examples of this embodiment, the CPU can access shared memory using DMA (Direct Memory Access). It is understood that the speed of the CPU accessing shared memory using DMA is significantly faster than the speed of the CPU accessing the service chip. Therefore, the time spent by the CPU to access shared memory to read reported data is much shorter than the time spent accessing the service chip to obtain reported data. This reduces the processing resource consumption of the CPU during the reported data acquisition process, allowing the CPU to use the same processing resources as the original single reported data acquisition to achieve multiple reported data acquisitions, meeting the acquisition requirement of "100ms*N", that is, reducing the time consumption of a single data acquisition to the level of hundreds of milliseconds.

[0071] It is understandable that shared memory can reside on the same board as the CPU or the service chip. For example, in some examples of this embodiment, the shared memory, CPU, and service chip are all on the same board, and this board is a service board. In other examples, the CPU and the service chip are on different boards. In this case, the shared memory and the service chip can be on the same board. For example, if the service chip is on the service board, the shared memory can be a part of the service board's memory, while the CPU is located on the main control board. Alternatively, the shared memory and CPU can be placed on the same board, while the service chip is on another board. For example, if the service chip is on the service board, the shared memory and CPU are both on the main control board, with the CPU being the CPU of the main control board and the shared memory being a part of the main control board's memory. In some even more examples, the service chip, shared memory, and CPU are all on different boards. For example, the CPU is the CPU of the main control board, the service chip is on the service board, and the shared memory is on another service board. In this case, service chips on two or more service boards can share a single shared memory.

[0072] The data acquisition method provided in this embodiment of the invention sets up shared memory, allowing the business chip to store the data to be reported to the CPU in the shared memory. The CPU acquires data by accessing the shared memory. Since the speed of the CPU accessing the shared memory is higher than that of accessing the business chip, the efficiency of the CPU in data acquisition is improved, the CPU avoids long-term occupation of processing resources during the data acquisition process, and the CPU's performance in processing other tasks is improved.

[0073] Moreover, after acquiring the raw data, the business chip can process the raw data before reporting it to the shared memory, avoiding the process of the CPU performing secondary processing on the data after acquisition. By transferring the processing process that originally required the CPU to the business chip, the processing burden on the CPU is reduced, further reducing the CPU processing resource occupation during the data acquisition process and improving CPU performance.

[0074] In addition, the CPU can read reported data from shared memory in a cycle that is several times longer than the business chip can write data to shared memory. This can exchange storage space for CPU processing time, further reducing the CPU's processing burden.

[0075] Example 2:

[0076] To enable those skilled in the art to better understand the advantages and details of the aforementioned data acquisition scheme, this embodiment will continue to illustrate the scheme with examples:

[0077] In this embodiment, the data acquisition process is divided into the following stages:

[0078] Phase 1: The business chip writes data to the chip memory;

[0079] Phase Two: The business chip writes data to the shared memory;

[0080] Phase 3: The CPU reads data from shared memory.

[0081] Please see below. Figure 4 The following is a flowchart of stage one:

[0082] S402: The business chip determines whether the chip memory is full.

[0083] If the judgment result is yes, the service chip executes S404; otherwise, it executes S406.

[0084] S404: Preset waiting time for the service chip.

[0085] In this embodiment, the preset duration can be set based on the data reporting cycle of the service chip. Therefore, at any time, if the monthly chip determines that its memory is full, it will wait for at most one data reporting cycle before its memory is cleared. Thus, in some examples, the preset duration can be one-quarter, one-half, or equal to the data reporting cycle. In other examples, the preset duration can be set to be longer than the data reporting cycle. However, generally, the preset duration should not exceed the data acquisition cycle for CPU data reading, as this may prevent the CPU from reading the reported data from shared memory.

[0086] S406: The business chip collects raw data.

[0087] The raw data collected by the business chip is the raw performance alarm data.

[0088] S408: The service chip processes the raw data according to the alarm filtering rules to obtain the reported data.

[0089] In this embodiment, after the service chip collects the raw data, it processes the raw data according to the alarm filtering rules. This can transfer the data processing process that was originally completed by the CPU to each service chip, reduce the processing burden of the CPU, and improve the data collection efficiency of the CPU.

[0090] Please see below. Figure 5 A flowchart of stage two is shown below:

[0091] S502: The service chip determines whether the timing result of the write timer has reached a data reporting cycle.

[0092] If the judgment result is yes, the service chip executes S504; otherwise, the service chip continues to execute S502.

[0093] S504: The service chip queries the shared memory instruction table to determine the first target instruction line.

[0094] In this embodiment, the service chip can query the indicator table stored in the shared memory. For example, it can search row by row from the first row of the indicator table and find the first indicator row with an idle record as the first target indicator row.

[0095] S506: The service chip obtains the address information from the first target instruction line.

[0096] In some examples, the address information of the record in the first target indication line is the starting address information of the memory segment, and the intra-segment storage space of each memory segment in the shared memory is contiguous.

[0097] S508: The service chip writes the data in the chip memory into the corresponding memory segment according to the obtained address information.

[0098] After the service chip obtains the address information of the idle memory segment, it can write the reported data into the idle memory segment according to the address information.

[0099] S510: The service chip modifies the status information recorded in the first target instruction line, records the data length in the memory segment, and clears the chip memory.

[0100] To ensure the CPU is aware that data has been written to a memory segment and can read it promptly, and to prevent application chips (including this chip and others) from continuing to write data to the memory segment before the CPU reads it, the application chip will change the status in the first target indication line to "occupied." Simultaneously, to inform the CPU of the amount of reported data in the corresponding memory segment, the application chip will also record the length of the reported data already stored in the memory segment in the first target indication line.

[0101] Since the reported data in the chip memory has already been written to the shared memory, the chip memory can be cleared after the write operation is completed, allowing the business chip to continue data acquisition in subsequent processes.

[0102] S512: Service chip restart write timer.

[0103] After the service chip writes data to the shared memory once, it will restart the write timer. When the write timer reaches another data reporting cycle, the service chip will retrieve data from the chip memory and write it to the shared memory again.

[0104] The following is combined with Figure 6 The illustrated process describes the aforementioned Phase Three:

[0105] S602: The CPU determines whether the timer result has reached a data acquisition cycle.

[0106] If the judgment result is yes, the CPU executes S604; otherwise, the CPU continues to execute S602.

[0107] S604: The CPU queries the shared memory instruction table to determine the second target instruction line.

[0108] In this embodiment, the CPU can query the indicator table stored in the shared memory. For example, it can search row by row from the first row of the indicator table to find all the indicator rows whose record status is occupied as the second target indicator rows.

[0109] S606: The CPU obtains the address information and data length from the second target instruction line.

[0110] After the CPU finds the second target indication line, it can obtain the address information and data length in the second target indication line. In this embodiment, the address information obtained by the CPU is the starting address information of the occupied memory segment.

[0111] S608: The CPU reads the reported data from the occupied memory segment of shared memory according to the address information.

[0112] The CPU determines the starting address of the memory segment to be occupied according to the starting address information in the second instruction line, and reads the reported data according to the data length in the second instruction line.

[0113] S610: The CPU clears the occupied memory segment and changes the status to idle in the second target indication line.

[0114] After the CPU finishes reading the data from the occupied memory segment, it clears the reported data stored in the occupied memory segment and modifies the status in the second target indication line. In addition, the CPU can also modify the data length in the second target indication line to 0.

[0115] It should be understood that there is no strict temporal relationship between the three stages above, from stage one to stage three. For example, when stage one is being executed, stage three may also be being executed at the same time. Moreover, stage two is not necessarily executed after stage one, nor is stage three necessarily executed immediately after stage two. In many cases, stage two is executed once after stage one has been executed multiple times, and stage three is executed once after stage two has been executed multiple times.

[0116] The data acquisition method provided in this embodiment reduces the data acquisition burden on the CPU, improves data acquisition efficiency, and helps enhance the CPU's performance in handling tasks other than data acquisition.

[0117] Example 3:

[0118] This embodiment provides a storage medium that includes volatile or non-volatile, removable or non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, computer program modules, or other data). Storage media include, but are not limited to, RAM (Random Access Memory), ROM (Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), flash memory or other memory technologies, CD-ROM (Compact Disc Read-Only Memory), DVD or other optical disc storage, magnetic cartridges, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible by a computer.

[0119] The storage medium may store one or more computer programs that can be read, compiled and executed by one or more processors. In this embodiment, the storage medium may store at least one of a data acquisition and reporting program and a data acquisition program. The data acquisition and reporting program may be executed by one or more processors (or controllers) to implement the business chip-side process of any data acquisition scheme described in the foregoing embodiments; while the data acquisition program may be executed by one or more processors (or controllers) to implement the CPU-side process of any data acquisition scheme described in the foregoing embodiments.

[0120] This embodiment also provides a computer program product, including a computer-readable device on which the computer program as shown above is stored. In this embodiment, the computer-readable device may include the computer-readable storage medium as shown above.

[0121] For example, the computer program product includes business chips, such as... Figure 7 As shown: The service chip 70 includes a microcontroller 71 and a chip memory 72 communicatively connected to the microcontroller 71. The chip memory 72 can be the aforementioned storage medium storing the data acquisition and reporting program. The microcontroller 71 can read the data acquisition and reporting program stored in the chip memory 72 to implement the data acquisition and reporting method on the service chip side of the aforementioned data acquisition scheme.

[0122] The microcontroller 71 acquires data and reports it, then writes the reported data to an idle memory segment of the shared memory. This shared memory is accessed by both the service chip 70 and the CPU, and the CPU's access speed to the shared memory is greater than its access speed to the service chip. The shared memory includes multiple memory segments, and the idle memory segment is the memory segment that is in an idle state.

[0123] Optionally, when the microcontroller 71 writes the reported data to an idle memory segment of the shared memory, it can first store the reported data in its internal chip memory 72. Then, the microcontroller 71 periodically writes the reported data from the chip memory 72 to the idle memory segment of the shared memory according to the data reporting cycle and clears the reported data in the chip memory. The data reporting cycle is shorter than the cycle in which the CPU reads the reported data from the shared memory.

[0124] In some examples of this embodiment, before storing the reported data in the internal chip memory, the microcontroller 71 will first determine that the amount of data already stored in the chip memory 72 is less than the storage threshold.

[0125] In some examples of this embodiment, when the microcontroller 71 acquires data to obtain the reported data, it can first acquire raw data, which is performance alarm data. Then, the microcontroller 71 processes the raw data according to alarm filtering rules to obtain the reported data.

[0126] In some examples of this embodiment, when the microcontroller 71 writes the reported data to an idle memory segment of the shared memory, it first accesses the indicator table corresponding to the shared memory. The indicator table includes multiple indicator rows, and each indicator row corresponds one-to-one with a memory segment in the shared memory segment. The indicator rows record the status and address information of the memory segment. The microcontroller 71 searches for the first target indicator row in the indicator table, which is recorded as having an idle status. Then, it obtains the address information recorded in the first target indicator row, writes the reported data to the idle memory segment according to the address information, and modifies the status to occupied status in the first target indicator row.

[0127] In other examples of this embodiment, the computer program product includes a CPU that can execute a data acquisition program to implement the CPU-side process in the aforementioned data acquisition scheme:

[0128] The CPU reads the reported data from the occupied memory segment of the shared memory and sets the occupied memory segment as an idle memory segment. The reported data in the occupied memory segment is written by the application chip, and the CPU's access speed to the shared memory is greater than the CPU's access speed to the application chip. The shared memory includes multiple memory segments, and the occupied memory segment is the memory segment that is in an occupied state.

[0129] Optionally, when the CPU reads reported data from the occupied memory segment of shared memory, it can first access the indicator table corresponding to the shared memory. The indicator table includes multiple indicator rows, and each indicator row corresponds one-to-one with a memory segment in the shared memory segment. The indicator rows record the status and address information of the memory segment. Then, the CPU searches for a second target indicator row in the indicator table whose status is "occupied," obtains the address information recorded in the second target indicator row, and then reads the reported data from the occupied memory segment of shared memory according to the address information. After the CPU finishes reading, it can change the status to "idle" in the second target indicator row. In some examples of this embodiment, the CPU can also clear the reported data in the occupied memory segment.

[0130] In some examples of this embodiment, the address information is the starting address information, and the instruction line also records the data length in the memory segment; when the CPU reads the reported data from the occupied memory segment of the shared memory according to the address information, it can determine the starting address of the occupied memory segment according to the starting address information in the second instruction line, and read the reported data according to the data length in the second instruction line.

[0131] Optionally, the CPU can read the reported data from the occupied memory segment of the shared memory according to the data acquisition cycle, and then periodically read the reported data from the occupied memory segment of the shared memory according to the data acquisition cycle. The data acquisition cycle is longer than the cycle in which the service chip writes the reported data to the shared memory.

[0132] In some examples of this embodiment, the CPU reads the reported data from the occupied memory segment of shared memory via Direct Memory Access (DMA).

[0133] This embodiment also provides a data acquisition system; please refer to [link / reference]. Figure 8 A schematic diagram of a data acquisition system is shown below:

[0134] The data acquisition system 8 includes shared memory 80, CPU 81, and the aforementioned service chip 82. CPU 81 can be the aforementioned CPU, and service chip 82 can be the aforementioned service chip 70. Shared memory 80 can be accessed by both service chip 82 and CPU 81, and the CPU 81's access speed to shared memory 80 is greater than its access speed to service chip 82. Shared memory 80 includes multiple memory segments.

[0135] In some examples of this embodiment, the shared memory 80 also stores an indicator table, which includes multiple indicator rows. Each indicator row uniquely corresponds to a memory segment in the shared memory 80. In some examples, the indicator row and the memory segment are uniquely associated, meaning that a memory segment has exactly one indicator row in the indicator table. The indicator row for a memory segment records at least the current state of the memory segment and its address information. In other examples of this embodiment, the indicator row also records the memory segment and the length of the data storing the reported data.

[0136] For details on how the shared memory 80, CPU 81, and business chip 82 work together to implement the data acquisition scheme, please refer to the description of the aforementioned embodiments, which will not be repeated here.

[0137] The data acquisition system 8 can be deployed in various communication systems. For example, in one instance, the data acquisition system 8 is located in an OTN system.

[0138] It is understood that shared memory 80 can reside on the same board as CPU 81 or service chip 82. For example, in some examples of this embodiment, shared memory 80, CPU 81, and service chip 82 are all on the same board, and this board is a service board. In other examples, CPU 81 and service chip 82 are on different boards. In this case, shared memory 80 and service chip 82 can be on the same board. For example, if service chip 82 is on the service board, then shared memory 80 can be a part of the service board's memory, while CPU 81 is located on the main control board. Alternatively, shared memory 80 and CPU 81 can be placed on the same board, while service chip 82 is located on another board. For example, if service chip 82 is on the service board, then shared memory 80 and CPU 81 are both on the main control board, with CPU 81 being the CPU 81 of the main control board, and shared memory 80 being a part of the main control board's memory. In some examples, the service chip 82, shared memory 80, and CPU 81 are all located on different boards. For example, CPU 81 is the CPU 81 on the main control board, service chip 82 is located on the service board, and shared memory 80 is located on another service board. In this case, service chips 82 can share a shared memory 80 on two or more service boards.

[0139] Figure 9 The diagram illustrates a functional unit of the aforementioned data acquisition system 8: the service chip 82 includes a data acquisition unit 8201, a chip RAM 8202, and a timed reporting unit 8203; the CPU 81 includes a reading unit 8101 and a timer unit 8102; the shared memory 80 includes an indicator table 8001 and a memory unit 8002, and the memory unit 8002 includes multiple memory segments.

[0140] The raw performance alarm data generated by the service chip 82 is input into the data acquisition unit 8201. The data acquisition unit 8201 performs secondary processing on the raw data from the service chip 82 according to the protocol. The processed report data is stored in the chip RAM 8202 inside the service chip 82. The chip RAM 8202 can store data according to a user-configured storage threshold. If the amount of data already stored in the chip RAM 8202 is less than the storage threshold, the processed report data can be stored normally in the chip RAM 8202. Otherwise, the chip RAM 8202 will generate flow control back pressure to the data acquisition unit 8201, preventing the data acquisition unit 8201 from continuing to store data. When the timer of the timed reporting unit 8203 expires, the timed reporting unit 8203 attempts to write the report data from the chip RAM 8202 into the shared memory 80.

[0141] The shared memory 80 can be shared and accessed by the service chip 82 and the CPU 81. The instruction table 8001 is divided into M rows, each row is a description of a contiguous memory segment, that is, a description of a memory segment: including whether the memory segment is occupied, the starting address information of the memory segment, and the length of the reported data stored in the memory segment.

[0142] Before attempting to write the reported data from the chip RAM 8202 to the memory unit 8002, the timed reporting unit 8203 first checks the datavlid row in the indicator table 8001 (a value of "1" in the datavlid row indicates that the memory segment corresponding to the indicator row is occupied, and a value of "0" indicates that the memory segment corresponding to the indicator row is idle). It finds the first indicator row with an idle status. If no such row is found, no data dump is performed. If an indicator row with an idle status exists, the starting address information of that row is obtained, and the reported data from the chip RAM 8202 is stored in the memory segment corresponding to that row. After the dump is complete, if the chip RAM 8202 has reached the storage threshold and flow control has been generated before the data transfer, the flow control backpressure flag is canceled.

[0143] When the timing of the timing unit 8102 arrives, the reading unit 8101 attempts to obtain the reported data from the memory unit 8002. The process for the reading unit 8101 to obtain the reported data is as follows: The reading unit 8101 first accesses the indicator table 8001, finds all indicator rows whose records are in an occupied state based on the value in the dataValid row, and then reads the reported data in the memory segment pointed to by these indicator rows. After reading, the value of dataValid in the corresponding indicator row is changed from "1" to "0".

[0144] In one example, to further reduce the burden on CPU 81, the data reporting cycle of the reading unit 8101 can be set to 1 second, and the data acquisition cycle of the timing unit 8102 can be set to 5 seconds. In this way, 5 sets of reported data are stored in the shared memory 80, and after the 5-second data acquisition cycle is reached, the CPU 81 performs a unified read. The combination of the two cycles reduces the CPU burden.

[0145] The data acquisition system provided in this embodiment establishes a shared memory, accessible to both the service chip and the CPU, outside of the service chip and CPU. This shared memory includes multiple shared memory segments. The service chip can write acquired reporting data into idle segments of the shared memory. The CPU can directly access the shared memory to read data from occupied memory segments, thereby obtaining the reporting data from the service chip. After reading, the CPU clears the reported data from the occupied memory segments, making them idle again for the service chip to write data to. Furthermore, since the CPU's access speed to this shared memory is greater than its access speed to the service chip, the data acquisition scheme provided in this embodiment can improve the CPU's data acquisition speed, thereby reducing CPU resource consumption in data acquisition and improving the CPU's performance in processing other tasks.

[0146] Therefore, those skilled in the art should understand that all or some of the steps, systems, and devices disclosed above, as well as the functional modules / units, can be implemented as software (which can be implemented using computer program code executable by a computing device), firmware, hardware, and suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as integrated circuits, such as application-specific integrated circuits (ASICs).

[0147] Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, computer program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium. Therefore, this invention is not limited to any particular combination of hardware and software.

[0148] The above description, in conjunction with specific implementation methods, provides a further detailed explanation of the embodiments of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A data collection reporting method, comprising: a business chip collecting data to obtain reporting data; the business chip writing the reporting data into an idle memory segment of a shared memory, the shared memory being accessed by the business chip and a CPU, and the CPU having a higher access speed to the shared memory than to the business chip, the shared memory including a plurality of memory segments, an idle memory segment being in an idle state, and an occupied memory segment being in an occupied state, a memory segment being in the occupied state after being written with reporting data by the business chip, and being in the idle state after the reporting data is read by the CPU; the business chip writing the reporting data into an idle memory segment of a shared memory, comprising: the business chip storing the reporting data in an internal chip memory; the business chip periodically writing the reporting data in the chip memory into the idle memory segment of the shared memory according to a data reporting period, the data reporting period being shorter than a period for the CPU to read reporting data from the shared memory; the business chip emptying the reporting data in the chip memory.

2. The data collection reporting method of claim 1, wherein, Before the business chip storing the reporting data in an internal chip memory, further comprising: the business chip determining that an amount of data already stored in the chip memory is less than a storage threshold.

3. The data collection reporting method of any of claims 1-2, wherein, the business chip collecting data to obtain reporting data, comprising: the business chip collecting raw data, the raw data being performance alarm data; the business chip processing the raw data according to an alarm filtering rule to obtain reporting data.

4. The data collection reporting method of any of claims 1-2, wherein, the business chip writing the reporting data into an idle memory segment of a shared memory, comprising: the business chip accessing an indication table corresponding to the shared memory, the indication table including a plurality of indication rows, each indication row corresponding to a memory segment in the shared memory segment, and the indication row recording a state and address information of the memory segment; the business chip finding a first target indication row with an idle state recorded in the indication table; the business chip obtaining the address information recorded in the first target indication row; the business chip writing the reporting data into the idle memory segment according to the address information, and modifying the state in the first target indication row to an occupied state. 5.A data collection method, comprising: a CPU reading reporting data from an occupied memory segment of a shared memory, the reporting data in the occupied memory segment being written by a business chip, and the CPU having a higher access speed to the shared memory than to the business chip, the shared memory including a plurality of memory segments, an idle memory segment being in an idle state, and an occupied memory segment being in an occupied state, a memory segment being in the occupied state after being written with reporting data by the business chip, and being in the idle state after the reporting data is read by the CPU; the CPU setting the occupied memory segment as an idle memory segment; the CPU reading reporting data from an occupied memory segment of a shared memory, comprising: The CPU reads the reported data from the occupied memory segment of the shared memory according to the address information; The CPU periodically reads the reported data from the occupied memory segment of the shared memory according to a data acquisition period, and the data acquisition period is greater than a period in which the service chip writes the reported data into the shared memory.

6. The data collection method of claim 5, wherein, The CPU reads the reported data from the occupied memory segment of the shared memory according to the address information; The CPU accesses an indication table corresponding to the shared memory, the indication table includes a plurality of indication rows, and each indication row corresponds to a memory segment in the shared memory segment, and the indication row records the state and address information of the memory segment; The CPU finds a second target indication row with an occupied state recorded in the indication table; The CPU acquires the address information recorded in the second target indication row; The CPU reads the reported data from the occupied memory segment of the shared memory according to the address information; The CPU sets the occupied memory segment as an idle memory segment includes: The CPU modifies the state in the second target indication row to an idle state.

7. The data collection method of claim 6, wherein, The CPU sets the occupied memory segment as an idle memory segment further includes: The CPU clears the reported data in the occupied memory segment.

8. The data collection method of claim 6, wherein, The address information is start address information, and the indication row further records the data length in the memory segment; The CPU reads the reported data from the occupied memory segment of the shared memory according to the address information includes: The CPU determines the start address of the occupied memory segment according to the start address information in the second indication row, and reads the reported data according to the data length in the second indication row.

9. The data acquisition method of any of claims 5-8, wherein, The CPU reads the reported data from the occupied memory segment of the shared memory includes: The CPU reads the reported data from the occupied memory segment of the shared memory by a direct memory access (DMA) mode.

10. A service chip, the service chip comprising a microcontroller and a chip memory in communication connection with the microcontroller; The microcontroller is configured to execute one or more programs stored in the chip memory to implement the steps of the data acquisition and reporting method according to any one of claims 1 to 4.

11. A CPU, the CPU being configured to execute one or more programs to implement the steps of the data acquisition method according to any one of claims 5 to 9.

12. A data acquisition system characterized by, The shared memory, the service chip according to claim 10, and the CPU according to claim 11; the shared memory is accessed by the service chip and the CPU, and the access speed of the CPU to the shared memory is greater than the access speed of the CPU to the service chip, and the shared memory includes a plurality of memory segments.

13. A storage medium, characterized by The storage medium stores at least one of a data acquisition and reporting program and a data acquisition program, the data acquisition and reporting program being executable by one or more processors to implement the steps of the data acquisition and reporting method according to any one of claims 1 to 4, and the data acquisition program being executable by one or more processors to implement the steps of the data acquisition method according to any one of claims 5 to 9.

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