Cache synthesis prefetching method, device, processor and electronic device

Abstract

A cache synthetic prefetching method, apparatus, processor, and electronic device are disclosed. The cache synthetic prefetching method is used to prefetch a first cache and a second cache, where the first cache is closer to the processor core than the second cache. The method includes: obtaining utilization information of a prefetching information source; and determining a prefetching method for the first cache and the second cache based on the utilization information of the prefetching information source, wherein the prefetching methods for the first cache and the second cache are different. This cache synthetic prefetching method can effectively reduce cache contamination in target caches (e.g., the first cache and the second cache), thereby improving overall CPU performance.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a cache synthesis prefetching method, apparatus, processor, and electronic device. Background Art

[0002] In existing CPU (central processing unit) architectures, program instructions and data can be stored in DRAM (Dynamic Random Access Memory). The CPU core (also known as the processor core) operates at a much higher frequency than DRAM. Therefore, fetching instructions and data from memory requires hundreds of clock cycles, often causing the core to idle, unable to continue executing related instructions and resulting in performance loss. Therefore, modern high-performance CPU architectures incorporate a multi-level cache hierarchy to store recently accessed data. While each level of cache stores recently accessed data, the core still has to wait for tens or even hundreds of clock cycles when reading data that has never been accessed or has been evicted due to cache size limitations, resulting in performance loss. Currently, data prefetching is commonly used to improve the performance of modern high-performance CPU architectures. Instruction or data prefetching analyzes past instruction or data access patterns to pre-fetch upcoming instructions or data, thereby reducing the number of clock cycles the core must wait and improving the overall performance of the CPU architecture. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a cache synthesis prefetching method for prefetching a first cache and a second cache, wherein the first cache is closer to a processor core than the second cache. The method includes: obtaining utilization information of a prefetching information source; and determining a prefetching method for the first cache and the second cache based on the utilization information of the prefetching information source, wherein the prefetching method for the first cache and the second cache are different.

[0004] For example, in the method provided in some embodiments of the present disclosure, the prefetching method for the first cache and the second cache is determined based on the utilization information of the prefetching information source, including: prefetching the first cache using a first mode; prefetching or not prefetching the second cache using a second mode, wherein the prefetching accuracy of the first mode is higher than the prefetching accuracy of the second mode.

[0005] For example, in the methods provided by some embodiments of the present disclosure, the prefetch coverage of the first mode is less than the prefetch coverage of the second mode.

[0006] For example, the method provided by some embodiments of the present disclosure also includes: providing a first prefetch trigger mode, wherein the first prefetch trigger mode represents prefetch accuracy information, and determining the prefetch method for the first cache and the second cache based on the utilization information of the prefetch information source, including: in response to the utilization information being greater than or equal to a first threshold, determining whether the first prefetch trigger mode is saturated; and in response to the first prefetch trigger mode being unsaturated, using the first mode to prefetch one of the first cache and the second cache, and not prefetching the other cache of the first cache and the second cache; in response to the first prefetch trigger mode being saturated, not prefetching either the first cache or the second cache.

[0007] For example, the method provided by some embodiments of the present disclosure further includes: providing a second prefetch trigger mode, wherein the second prefetch trigger mode represents prefetch coverage information, and determining the prefetch method for the first cache and the second cache based on the utilization information of the prefetch information source, and further includes: in response to the utilization information being less than a first threshold and greater than or equal to a second threshold, determining whether the second prefetch trigger mode is saturated, and in response to the second prefetch trigger mode being saturated, using the first mode to prefetch one of the first cache and the second cache, and not prefetching the other of the first cache and the second cache, or in response to the second prefetch trigger mode being unsaturated, using the first mode to prefetch the first cache, and using the second mode to prefetch the second cache, wherein the second threshold is less than the first threshold, and the prefetch accuracy of the first mode is higher than the prefetch accuracy of the second mode.

[0008] For example, in the method provided in some embodiments of the present disclosure, the prefetching method for the first cache and the second cache is determined based on the utilization information of the prefetching information source, and also includes: in response to the utilization information being less than the second threshold, prefetching the first cache using the first mode and prefetching the second cache using the second mode.

[0009] For example, in the method provided in some embodiments of the present disclosure, prefetching is performed on one of the first cache and the second cache using the first mode, and prefetching is not performed on the other of the first cache and the second cache, including: prefetching is performed on the first cache using the first mode and prefetching is not performed on the second cache.

[0010] For example, in the methods provided in some embodiments of the present disclosure, the first mode is generated by the first prefetch trigger mode; and the second mode is generated by the first prefetch trigger mode and the second prefetch trigger mode together.

[0011] For example, in the method provided in some embodiments of the present disclosure, the first prefetch trigger mode and the second prefetch trigger mode have the same number of bits, each bit is 1 or 0, and the second prefetch trigger mode includes all bits of the first prefetch trigger mode that are 1.

[0012] For example, in the method provided in some embodiments of the present disclosure, the first prefetch trigger mode is represented as an accuracy bias bit mode AP, the second prefetch trigger mode is represented as a coverage bias bit mode CP, and the first prefetch trigger mode and the second prefetch trigger mode are jointly used to generate a second mode, including: obtaining a third prefetch trigger mode from (~AP) & CP, and generating the second mode from the third prefetch trigger mode.

[0013] For example, in the methods provided in some embodiments of the present disclosure, the first cache is a first-level cache and the second cache is a second-level cache; or the first-level cache is a second-level cache and the second cache is a third-level cache.

[0014] For example, in the methods provided in some embodiments of the present disclosure, the pre-fetch information source is a memory, and the utilization information is a memory access bandwidth for the memory.

[0015] At least one embodiment of the present disclosure also provides a cache synthetic prefetch device, which is arranged to be at the same level as a first cache or a second cache, and the first cache is closer to the processor core than the second cache, wherein the cache synthetic prefetch device includes: a utilization monitoring module, configured to obtain utilization information of a prefetch storage source, and a prefetch mode selection module, configured to determine the prefetch mode for the first cache and the second cache based on the utilization information of the prefetch storage source, wherein the prefetch mode for the first cache and the second cache is different.

[0016] For example, in the device provided in some embodiments of the present disclosure, the prefetching mode selection module includes: a first mode selection unit, configured to use the first mode to prefetch the first cache, and a second mode selection unit, configured to use the second mode to prefetch or not prefetch the second cache, wherein the prefetching accuracy of the first mode is higher than the prefetching accuracy of the second mode.

[0017] For example, the device provided in some embodiments of the present disclosure also includes: a prefetch prediction module, configured to provide a first prefetch trigger mode, wherein the first prefetch trigger mode represents prefetch accuracy information, and the first mode selection unit is further configured to: in response to the utilization information being greater than or equal to a first threshold, determine whether the first prefetch trigger mode is saturated, and in response to the first prefetch trigger mode being unsaturated, use the first mode to prefetch one of the first cache and the second cache, and do not prefetch the other of the first cache and the second cache; in response to the first prefetch trigger mode being saturated, do not prefetch either the first cache or the second cache.

[0018] For example, in the device provided in some embodiments of the present disclosure, the prefetch prediction unit is further configured to provide a second prefetch trigger mode, wherein the second prefetch trigger mode represents prefetch coverage information, and the first mode selection unit is further configured to: in response to the utilization information being less than a first threshold and greater than or equal to a second threshold, determine whether the second prefetch trigger mode is saturated, and in response to the second prefetch trigger mode being saturated, adopt the first mode to prefetch one of the first cache and the second cache, and not prefetch the other of the first cache and the second cache, or in response to the second prefetch trigger mode being unsaturated, adopt the first mode to prefetch the first cache, and the second mode selection unit is further configured to: in response to the utilization information being less than the first threshold and greater than or equal to the second threshold, determine whether the second prefetch trigger mode is saturated, and in response to the second prefetch trigger mode being saturated, adopt the second mode to prefetch the second cache, wherein the second threshold is less than the first threshold, and the prefetch accuracy of the first mode is higher than the prefetch accuracy of the second mode.

[0019] For example, in the device provided in some embodiments of the present disclosure, the first mode selection unit is further configured to: in response to the utilization information being less than the second threshold, pre-fetch the first cache using the first mode; the second mode selection unit is further configured to: in response to the utilization information being less than the second threshold, pre-fetch the second cache using the second mode.

[0020] For example, in the apparatus provided by some embodiments of the present disclosure, the first mode selection unit is further configured to: perform prefetching on the first cache using the first mode and not perform prefetching on the second cache.

[0021] For example, in the device provided by some embodiments of the present disclosure, the prefetch prediction module is further configured to: obtain a third prefetch trigger mode from the first prefetch trigger mode and the second prefetch trigger mode, so that the third prefetch trigger mode generates the second mode.

[0022] At least one embodiment of the present disclosure further provides a processor, comprising the cache synthesis prefetching device provided by any of the above embodiments.

[0023] At least one embodiment of the present disclosure further provides an electronic device including the processor as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0025] Figure 1 A schematic diagram of the architecture of a multi-core processor is shown;

[0026] Figure 2A A schematic diagram of an L2 prefetcher in a processor prefetching an L2 cache is shown;

[0027] Figure 2B A schematic diagram of an L2 prefetcher in a processor prefetching L2 cache and L1D cache is shown;

[0028] Figure 2C A schematic diagram showing prefetching of an L2 prefetcher from an L2 cache and an LLC cache in a processor is shown;

[0029] Figure 2D A schematic diagram showing prefetching of an L2 prefetcher from an L2 cache and an LLC cache in a processor is shown;

[0030] Figure 3 A flow chart of a cache synthesis prefetching method provided in some embodiments of the present disclosure;

[0031] Figure 4 for Figure 3 An exemplary flow chart of step S20 in FIG.

[0032] Figure 5 for Figure 3 Another exemplary flow chart of step S20 in FIG.

[0033] Figure 6 A schematic block diagram of a cache synthesis prefetching device provided in some embodiments of the present disclosure;

[0034] Figure 7 A schematic block diagram of an electronic device provided for some embodiments of the present disclosure;

[0035] Figure 8 A schematic block diagram of another electronic device provided for some embodiments of the present disclosure. DETAILED DESCRIPTION

[0036] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0037] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0038] The present disclosure is described below through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components. When any component of an embodiment of the present disclosure appears in more than one figure, the component is represented by the same or similar reference numeral in each figure.

[0039] In typical CPU architectures, program instructions and data are stored in memory. However, the processor core runs at a much higher frequency than memory. Therefore, retrieving data or instructions from memory requires hundreds of clock cycles. This often causes the processor core to idle, unable to continue executing related instructions, resulting in performance loss. Therefore, modern high-performance processors incorporate a multi-level cache architecture to store recently accessed data and pre-fetch upcoming data and instructions into the cache. By pre-fetching data and instructions into the cache, corresponding read and write operations can hit the cache, thereby reducing latency.

[0040] For example, Figure 1 This is a schematic diagram of the architecture of a multi-core processor. Figure 1As shown, the processor has 4 processor cores (CPU Core). At the same time, the processor also has multi-level cache, such as the first-level cache (L1 Cache), the second-level cache (L2 Cache) and the last-level cache (Last Level Cache, LLC). In this example, the last-level cache is actually the third-level cache (L3 Cache). Of course, the embodiments of the present disclosure are not limited to this. The processor can have any number of multi-level caches, so the last-level cache can also be a cache of any level, which can be determined according to actual needs. For example, the multi-level cache can include the first-level cache space to the N-th level cache space, where N is an integer greater than 2. The first-level cache space is farthest from the memory and closest to the processor core; the N-level cache space is closest to the memory and farthest from the processor core. For example, in Figure 1 In the example shown, the processor includes N=3 levels of cache space. Of course, the embodiments of the present disclosure are not limited thereto, and N can be any integer greater than 2, such as 4, 5, 6, etc. Accordingly, the processor has a 4-level cache architecture, a 5-level cache architecture, a 6-level cache architecture, etc.

[0041] For example, a dedicated first-level cache can be set up separately for each processor core, and the first-level cache is set inside the processor core. For example, the first-level cache may include a first-level instruction cache (L1I cache) and a first-level data cache (L1D cache), which are used to cache instructions and data, respectively. The processor core implements instruction delivery and data reading through a multi-level cache and a data cache mechanism of the memory. Of course, the embodiments of the present disclosure are not limited to this. In other examples, it is also possible not to distinguish between the L1I cache and the L1D cache, but only to set up an L1 cache, which is used to store both data and instructions.

[0042] For example, in this example, the last-level cache is shared by multiple processor cores, while the second-level cache is private to each processor core. That is, multiple processor cores share a single last-level cache, while each processor core is provided with a dedicated second-level cache. The last-level cache and the second-level cache are used to store instructions and data, and the last-level cache is connected to the memory. It should be noted that in other examples, the second-level cache may also be a shared cache, and the embodiments of the present disclosure are not limited to this.

[0043] For example, the first-level cache to the N-level cache are connected in sequence to form a communication link, thereby enabling data acquisition from one level to another. For example, when the processor core needs to obtain data, it first queries the first-level cache. If there is no hit, it continues to query the second-level cache. If there is still no hit, it queries the last-level cache. If the last-level cache still misses, it retrieves the data from the memory. For example, the first-level cache has the fastest cache speed but the smallest capacity, the last-level cache has the largest capacity but the slowest speed, and the cache speed and capacity of the second-level cache are between the first-level cache and the last-level cache.

[0044] For example, the processor can use a prefetcher (e.g., a prefetch circuit) to implement a data prefetching function, so that data that the CPU will access in the future can be retrieved from the memory in advance. Specifically, the prefetcher predicts the data access address and stores the data stored at these addresses in any target cache in the multi-level cache (e.g., the first-level cache, the second-level cache, or the last-level cache, etc.). For example, the prefetcher can be set near a certain level of cache, that is, the prefetcher and the nearby cache are set to the same level, that is, the same path level. For example, the prefetcher at the same level of the L1D cache can be called an L1D prefetcher (not shown in the figure), and the prefetcher at the same level of the L2 cache can be called an L2 prefetcher (e.g., Figures 2A-2D It should be noted that the present disclosure does not limit the implementation of the prefetcher. For example, the prefetcher can be implemented through software programs, hardware, or a combination of software programs and hardware, as long as the data prefetching function is implemented. Furthermore, the prefetcher can be combined with the existing memory controller structure to jointly implement the data prefetching function.

[0045] Figure 2A-2D FIG2 shows a schematic diagram of the architecture of a processor. In this processor, an L2 prefetcher is provided at the same level as the L2 cache. For example, a prefetcher can prefetch data into the cache at the same level. This prefetcher is called a "single prefetcher". Figure 2A As shown, when the L2 prefetcher is a single prefetcher, it can only prefetch data into the L2 cache. For example, a prefetcher can also prefetch data into multiple levels of cache. This type of prefetcher is called a "synthetic prefetcher". For example, an L1D prefetcher at the same level as the L1D cache can prefetch data into the L1D cache and the L2 cache, or an L2 prefetcher at the same level as the L2 cache can prefetch data into the L1D cache, L2 cache, LLC cache, etc. Figure 2B As shown in FIG, when the L2 prefetcher is a synthetic prefetcher, data is prefetched into the L1D cache and the L2 cache. Figure 2C As shown in FIG, when the L2 prefetcher is a synthetic prefetcher, data is prefetched into the L1D cache and the L2 cache. Figure 2DAs shown, when the L2 prefetcher is a synthetic prefetcher, data is prefetched into the L1D cache, the L2 cache, and the LLC cache. Figure 2B to Figure 2D In FIG, the cache diagram filled with slashes is the cache operated by the synthetic prefetcher.

[0046] For example, a prefetcher sends a prefetch request to a cache at the same level before a cache failure may occur. For example, a prefetch request can be a special read request that includes the address of the read data, the type of the read data, and one or more target caches for the prefetched read data. When the data is actually used, the cache receiving the prefetch request has already fetched the data into the target cache, thereby avoiding processor stalls caused by cache failures. For example, assuming the L2 prefetcher is a single prefetcher, the L2 prefetcher can send a prefetch request to the L2 cache at the same level. The L2 cache parses the prefetch request to obtain information such as the address of the read data, the type of the read data, and whether the target cache is the L2 cache. Based on the address of the read data, the L2 cache retrieves the read data in a step-by-step query along the path from the cache to the memory, and caches the retrieved read data in a target cache, namely the L2 cache, completing the prefetch process. For example, a composite prefetcher can merge two prefetchers into one, and can dynamically determine which level of cache to send the prefetch request to based on different information (such as prefetch accuracy). For example, assuming that the L2 prefetcher is a synthetic prefetcher, the L2 prefetcher can send the data prefetched from the memory or other cache to two levels of target cache. The two levels of target cache are divided into low-level cache (Cache low) and high-level cache (Cache high). The low-level cache is closer to the processor core (for example, L1 cache), and the high-level cache is farther away from the processor core (for example, LLC cache). Specifically, the L2 prefetcher can send a prefetch request to the L2 cache of the same level. The L2 cache parses the prefetch request to obtain the address of the read data, the type of the read data, and multiple target caches for prefetching the read data (for example, the low-level cache is the L1 cache and the high-level cache is the LLC cache), etc., and obtains the read data in a step-by-step query manner in the path from the cache to the memory based on the address of the read data, caches the obtained read data in the L2 cache, and then the L2 cache forwards the read data to the L1 cache and LLC cache to complete the prefetch process. It should be pointed out that the cache used to receive the prefetch request generated by the prefetcher and the target cache are not necessarily caches of the same level.

[0047] For example, the prefetcher can be trained based on past data access patterns to better predict data access addresses. The prefetcher is in communication with the processor core and can perform training and prefetching through the following steps S1 to S3.

[0048] Step S1: The prefetcher receives the virtual addresses and other attributes of at least some (e.g., all) access requests (e.g., historical access requests) from the CPU core, uses the virtual addresses and other attributes of the above access requests (e.g., historical access requests) for training to obtain the access rules of the CPU core, and forms prefetch requests based on the above access rules. For example, the L1 prefetcher can use the virtual address and other attributes for training to generate a virtual address prefetch request. For example, the prefetcher can also use the physical address and other attributes of the access request for training to generate a physical address prefetch request. For example, the L2 prefetcher or the LLC prefetcher can use the physical address and other attributes for training to generate a physical address prefetch request.

[0049] Step S2: Determine whether the target data or instruction of the prefetch request exists in a cache at the same level of the prefetcher based on the prefetch virtual address corresponding to the virtual address prefetch request or the prefetch physical address corresponding to the physical address prefetch request. If the target data or instruction of the prefetch request exists in the cache at the same level of the prefetcher, discard the prefetch request. If the target data or instruction does not exist in the cache at the same level of the prefetcher, execute step S3.

[0050] Step S3: Based on the prefetch physical address or prefetch virtual address, obtain the target data or instruction of the prefetch request from the next level cache of the cache at the same level as the prefetcher (for example, the cache at the same level as the prefetcher is the second cache, and the next level cache is the last level cache memory, Last LevelCache) or memory (for example, DRAM), so that the cache at the same level as the prefetcher can send the obtained target data or instruction to the target cache.

[0051] For example, prefetchers are usually trained by read requests from the same level cache. For example, the L2 prefetcher can only be trained by read and write requests from the L2 cache (all or miss). This is because the L2 cache cannot see the data read and write requests that hit the L1 cache, so these read and write requests that hit the L1 cache cannot be used to train an L2 prefetcher, but can be used to train an L1 prefetcher. Figure 2B As shown, the L2 prefetcher can communicate with the high-level cache, i.e., the L2 cache, but does not need to communicate with the low-level cache, i.e., the L1D cache. This is because the prefetched data originally sent to the low-level cache (i.e., L1D) and the high-level cache (i.e., L2 cache) can be sent to the high-level cache through the L2 prefetcher. That is, the high-level cache needs to save the prefetched data of the low-level cache. If the current prefetched data hits the high-level cache or is obtained from the next-level cache / memory, the current prefetched data originally sent to the high-level cache will be Stash (inserted) to send the current prefetched data to the low-level cache. Stash (insert) is used to indicate that the request to send the prefetched data to the cache does not come from the processor core, so the low-level cache needs to support the Stash (insert) operation. As shown Figure 2CAs shown, the L2 prefetcher can communicate with the lower level cache (L1D cache) and the higher level cache (LLC cache). The L2 prefetcher sends prefetched data to the lower level cache (L1D cache) and the higher level cache (LLC cache) to train the L2 prefetcher.

[0052] Three factors influence instruction prefetch effectiveness: timeliness, coverage, and accuracy. Timeliness measures whether prefetch requests are provided exactly when the processor needs them. Serving them too late results in performance penalties, while serving them too early takes up available cache space. Accuracy measures the number of useful prefetch requests—those where data prefetched into the target cache based on the prefetch request is actually used by the program. Coverage measures the extent to which the first number of useful prefetch requests covers the second number of program data read requests.

[0053] For example, a type of local prefetcher is suitable for prefetching data read requests that are local (access addresses within a range, such as 2KB) but have irregular access addresses and order. This type of prefetcher uses bits to record data accesses within a local area. A bit position of 0 indicates that the corresponding cache line or lines are not accessed, while a bit position of 1 indicates that the corresponding cache line or lines are accessed. A cache line can be understood as the smallest cache unit in the CPU cache. Data movement between memory and cache, or between caches, is not accomplished in single bytes or even bytes. Instead, the smallest data unit of movement is called a cache line, sometimes called a cache block. For example, the cache line size of a CPU cache is 64 bytes. Assuming the first-level cache is 512 bytes, then based on the 64-byte cache unit size, the number of cache lines that this level of cache can store is 512 / 64 = 8. When the prefetcher receives a trigger signal again, such as the same access instruction or access address, the prefetcher uses the current access address and the bitset to calculate the addresses of multiple prefetch requests and sends these prefetch requests to the cache at the same level as the prefetcher. If the data prefetched to the target cache by the prefetch request has a high accuracy rate, the latency can be reduced. However, if too much data is prefetched to the target cache, a large amount of useful data in the target cache will be replaced, resulting in performance loss. This phenomenon is called "cache pollution."

[0054] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals in different drawings will be used to refer to the same elements described above.

[0055] At least one embodiment of the present disclosure provides a cache synthesis prefetching method, apparatus, processor, and electronic device. The cache synthesis prefetching method can effectively reduce cache contamination and improve the overall performance of the processor core.

[0056] At least one embodiment of the present disclosure provides a processor comprising at least a processor core, a first cache, a second cache, and a prefetcher, wherein the first cache is closer to the processor core than the second cache. The processor may be a multi-core processor or a single-core processor. Here, "first cache" and "second cache" are used to refer to caches that are relatively closer to the processor core and caches that are relatively farther away from the processor core in a multi-level cache, rather than specifically referring to a specific cache or a specific level of cache. For example, the first cache is a first-level cache and the second cache is a second-level cache, or the first-level cache is a second-level cache and the second cache is a third-level cache. The prefetcher may be a "synthetic prefetcher" that prefetches multiple levels of cache. For example, the prefetcher may be set at the same level as the L1D cache and prefetch data into the L1D cache and the L2 cache. For example, the prefetcher may be set at the same level as the L2 cache and prefetch data into the L1D cache and the L2 cache. For example, in one example, the first cache is the L1D cache (first-level cache) that is closer to the processor core, and the second cache is the L2 cache (second-level cache) that is farther away from the processor core. For another example, the prefetcher can be set at the same level as the L2 cache to prefetch data into the LLC cache and the L2 cache, or the prefetcher can be set at the same level as the LLC cache to prefetch data into the LLC cache and the L2 cache. For example, the first cache is the L2 cache (second-level cache) closer to the processor core, and the second cache is the LLC cache (third-level cache) farther away from the processor core.

[0057] Figure 3 This is a flow chart of a cache synthesis prefetching method provided in some embodiments of the present disclosure, which is used to prefetch a first cache and a second cache. The cache synthesis prefetching method includes:

[0058] Step S10: obtaining utilization information of the pre-fetched information source;

[0059] Step S20: determining a prefetching mode for the first cache and the second cache according to the utilization information of the prefetching information source, wherein the prefetching modes for the first cache and the second cache are different.

[0060] For example, in step S10, the prefetcher can obtain utilization information of the prefetch information source. The prefetch information source stores program instructions and data. For example, the prefetch information source can be memory or a cache shared by multiple processor cores, such as the last-level cache (LLC). Utilization information is used to indicate the busyness of the prefetch information source itself. For example, utilization information can be the bandwidth used by the processor to access the memory or the cache shared by multiple processor cores. Generally, a larger bandwidth indicates a higher busyness. Memory (DDR) or a cache shared by multiple processor cores typically has a maximum bandwidth, and the bandwidth utilization of the processor (CPU) accessing the memory or the cache shared by multiple processor cores changes dynamically. That is, current bandwidth utilization = current access bandwidth / maximum bandwidth also changes dynamically. For example, assuming the maximum bandwidth of the memory is 5 GB / s and the current memory access bandwidth is 4 GB / s, the current bandwidth utilization is 80% (4 / 5).

[0061] For example, in step S20, the prefetcher may determine prefetching methods for the first cache and the second cache based on utilization information of the prefetch information source, and send a prefetch request to a cache at the same level as the prefetcher. The cache prefetches the data into a target cache, for example, the first cache and the second cache. Simultaneously, the prefetcher determines to use different prefetching methods for the first cache and the second cache.

[0062] For example, Figure 4 for Figure 3 In some examples, the above step S20 may further include the following operations.

[0063] Step S201: providing a first prefetch trigger mode and a second prefetch trigger mode, wherein the first prefetch trigger mode represents prefetch accuracy information, and the second prefetch trigger mode represents prefetch coverage information.

[0064] Step S202: generating a first mode from the first prefetch trigger mode; and generating a second mode from the first prefetch trigger mode and the second prefetch trigger mode.

[0065] Step S203: Prefetching is performed on the first cache using the first mode, and prefetching is performed on the second cache using the second mode or no prefetching is performed.

[0066] For example, in step S201, the prefetch accuracy information can be expressed as the ratio of the number of prefetch requests (or prefetch data obtained) hit by program requirements to the total number of prefetch data obtained by the prefetch requests, that is, the accuracy of the prefetch data prefetched into the target cache being used by subsequent program requirements. The prefetch coverage information can be expressed as the ratio of the number of prefetch requests (or prefetch data obtained) hit by program requirements to the total number of program requirements, where the total number of program requirements is the number of read and write operations performed by the program according to the requirements. For example, the first prefetch trigger mode is expressed as the accuracy bias bit mode AP, and the second prefetch trigger mode is expressed as the coverage bias bit mode CP.

[0067] For example, in step S202, the prefetcher uses the first prefetch trigger mode and the second prefetch trigger mode to trigger different prefetching methods for different target caches (for example, the first cache and the second cache). For example, the first mode is generated by the first prefetch trigger mode, and the second mode is jointly generated by the first prefetch trigger mode and the second prefetch trigger mode. That is, the first mode is generated by the accuracy bias bit pattern AP, and the second mode is jointly generated by the accuracy bias bit pattern AP and the coverage bias bit pattern CP, wherein the prefetch accuracy of the first mode is higher than the prefetch accuracy of the second mode, and the prefetch coverage of the first mode is lower than the prefetch coverage of the second mode. For example, the accuracy bias bit pattern AP and the coverage bias bit pattern CP both represent prefetch requests through bits (bitset). For example, the first prefetch trigger mode and the second prefetch trigger mode have the same number of bits, each bit has a value of 1 or 0, and the second prefetch trigger mode includes all bits of the first prefetch trigger mode that are 1. For example, CP bitset= 111 11 111 0000 means the coverage bias bit pattern CP generates 8 prefetch requests with higher coverage, AP bitset = 111 00 111 0000 indicates that the accuracy bias bit pattern AP generates 6 prefetch requests with higher accuracy, and the prefetch requests generated by the coverage bias bit pattern CP include the prefetch requests generated by the accuracy bias bit pattern AP (see the six underlined and underlined bits that are 1).

[0068] In one example, the third prefetch trigger mode is obtained by (~AP) & CP, and the second mode is generated by the third prefetch trigger mode. 111 00 111 0000 Each data bit is inverted to obtain ~AP bitset= 000 11 000 1111, and CP bitset= 111 11 111 0000 performs an "AND" operation and obtains (~AP)&CP=000 11 000 0000. The bitset obtained by "(~AP)&CP" is used to generate a prefetch request, resulting in the third prefetch trigger mode. That is, among the prefetch requests with higher coverage, some prefetch requests with higher accuracy are selected to prefetch the data obtained by these prefetch requests into the higher-level cache, thereby reducing the pollution of the lower-level cache.

[0069] For example, in step S203, the prefetcher adopts the first mode to perform prefetching for the first cache, for example, prefetching data with high accuracy required by subsequent programs is sent to a low-level cache (first cache) close to the processor core. The prefetcher adopts the second mode to perform prefetching for the second cache or does not perform prefetching. For example, the prefetcher adopts the second mode to perform prefetching for the second cache, that is, prefetching data with low accuracy but high coverage required by subsequent programs is sent to a high-level cache (second cache) far from the processor core, effectively reducing cache pollution of the high-level cache (second cache).

[0070] For example, Figure 5 for Figure 4 An exemplary flowchart of step S20 in the flowchart, step S20 includes: in response to utilization information of the prefetch information source being greater than or equal to a first threshold, determining whether the first prefetch trigger mode is saturated; and in response to the first prefetch trigger mode being unsaturated, prefetching one of the first cache and the second cache using the first mode and not prefetching the other cache; and in response to the first prefetch trigger mode being saturated, prefetching neither the first cache nor the second cache.

[0071] For example, the first threshold is a threshold for memory access bandwidth utilization. In response to utilization information being greater than or equal to the first threshold, the prefetcher can use a saturation counter to measure whether the first prefetch trigger pattern, represented by the accuracy bias bit pattern AP, is saturated. This means that the number of prefetch requests represented by the bit set generated by the accuracy bias bit pattern AP increases until a certain threshold is reached, indicating "saturation." For example, during training, if a large number of bits in the AP bit set are set to zero (e.g., more than 75% of the bits are set to zero), the AP bit set is cleared and training is repeated. If the first prefetch trigger pattern is saturated, two different prefetching methods can be used for the first cache and the second cache. For example, the first cache (lower-level cache) can use the first method for prefetching, while the second cache (higher-level cache) cannot be prefetched, or the second cache (higher-level cache) can use the first method for prefetching, while the first cache (lower-level cache) cannot be prefetched.

[0072] For example, when the utilization information is greater than or equal to a first threshold, a first mode is used to prefetch data for the first cache (lower-level cache). For example, the prefetcher sends a prefetch request generated by the AP to a cache at the same level. The cache sends the high-accuracy prefetch data obtained from the memory to the first cache (lower-level cache) based on the prefetch request, and does not prefetch data for the second cache (higher-level cache), thereby preventing cache pollution in the second cache (higher-level cache). Alternatively, the first mode is used to prefetch data for the second cache (higher-level cache). The prefetcher sends a prefetch request generated by the AP to a cache at the same level. The cache sends the high-accuracy prefetch data obtained from the memory to the second cache (higher-level cache) based on the prefetch request, and does not prefetch data for the first cache (lower-level cache), thereby preventing cache pollution in the first cache (lower-level cache).

[0073] For example, step S20 also includes: in response to the utilization information of the prefetch information source being less than a first threshold and greater than or equal to a second threshold, determining whether the second prefetch trigger mode is saturated, and in response to the second prefetch trigger mode being saturated, prefetching one of the first cache and the second cache using the first mode, and not prefetching the other of the first cache and the second cache, wherein the second threshold is less than the first threshold, and the prefetch accuracy of the first mode is higher than the prefetch accuracy of the second mode.

[0074] For example, the second threshold is the threshold of the utilization rate of the memory access bandwidth, and the second threshold is less than the first threshold. In response to the utilization information being less than the first threshold and greater than or equal to the second threshold, the prefetcher can use a saturation counter to measure whether the second prefetch trigger mode represented by the coverage bias bit pattern CP is saturated, that is, the number of prefetch requests represented by the bit (bitset) generated by the coverage bias bit pattern CP will increase until a certain threshold is reached, which is "saturated". For example, during the training process, the number of bits set to 1 in the CP bitset is relatively large (for example, more than 75% of the bits of the threshold are all 1). At this time, the CP bitset is cleared and training is performed again. If the second prefetch trigger mode is saturated, then there can be two different prefetching methods for the first cache and the second cache. For example, the first cache (low-level cache) can be prefetched using both the first mode and the second mode, and the second cache (high-level cache) can be prefetched using both the first mode and the second mode. When prefetching is performed on the first cache (lower-level cache) using the first mode, the second cache (higher-level cache) is not prefetched. For example, the prefetcher sends a prefetch request generated by the AP to a cache at the same level. The cache sends the high-accuracy prefetched data obtained from the memory to the first cache (lower-level cache) based on the prefetch request, and does not prefetch the second cache (higher-level cache), thereby preventing cache pollution in the second cache (higher-level cache). Alternatively, when prefetching is performed on the second cache (higher-level cache) using the first mode, the first cache (lower-level cache) is not prefetched. For example, the prefetcher sends a prefetch request generated by the AP to a cache at the same level. The cache sends the high-accuracy prefetched data obtained from the memory to the second cache (higher-level cache) based on the prefetch request, and does not prefetch the first cache (lower-level cache), thereby preventing cache pollution in the first cache (lower-level cache).

[0075] For example, step S20 also includes: in response to the utilization information of the prefetch information source being less than a first threshold and greater than or equal to a second threshold, determining whether the second prefetch trigger mode is saturated, and in response to the second prefetch trigger mode being unsaturated, using the first mode to prefetch the first cache and using the second mode to prefetch the second cache.

[0076] For example, step S20 further includes: in response to the utilization information of the prefetch information source being less than a second threshold, prefetching the first cache in the first mode and prefetching the second cache in the second mode.

[0077] For example, in response to the utilization information being less than a first threshold and greater than or equal to a second threshold, the prefetcher can use a saturation counter to measure whether the second prefetch trigger mode represented by the coverage bias bit pattern CP is saturated. If the second prefetch trigger mode is not saturated, then a different prefetching method can be used for the first cache and the second cache. For example, the first mode is used to prefetch the first cache (low-level cache) and the second mode is used to prefetch the second cache (high-level cache).

[0078] For example, in response to the utilization information being less than a second threshold, the prefetcher may have a different prefetching method for the first cache and the second cache, for example, prefetching the first cache (low-level cache) using the first mode and prefetching the second cache (high-level cache) using the second mode.

[0079] For example, the prefetcher sends the prefetch request generated by the AP to the cache at the same level. The cache sends the prefetch data with high accuracy obtained from the memory to the first cache (low-level cache) according to the prefetch request, and prefetches the second cache using the second mode, that is, selecting the prefetch data with lower accuracy from the prefetch data with higher coverage and sending it to the second cache (high-level cache), which will not cause cache pollution to the second cache.

[0080] Figure 6 A cache synthesis prefetch device is provided for some embodiments of the present disclosure. The cache synthesis prefetch device is set to the same level as a first cache or a second cache, and the first cache is closer to the processor core than the second cache.

[0081] The cache synthesis prefetching device includes a prefetch information source utilization monitoring module 10 and a prefetch mode selection module 20. The prefetch information source utilization monitoring module 10 is configured to obtain utilization information of the prefetch storage source, and the prefetch mode selection module 20 is configured to determine the prefetch mode for the first cache and the second cache based on the utilization information of the prefetch storage source, wherein the prefetch modes for the first cache and the second cache are different.

[0082] For example, in the cache synthesis prefetching apparatus provided in some embodiments of the present disclosure, the prefetching mode selection module 20 includes a first mode selection unit and a second mode selection unit. The first mode selection unit is configured to use a first mode to prefetch the first cache, and the second mode selection unit is configured to use a second mode to prefetch or not prefetch the second cache, wherein the prefetching accuracy of the first mode is higher than the prefetching accuracy of the second mode.

[0083] For example, the cache synthesis prefetching apparatus provided in some embodiments of the present disclosure further includes a prefetch prediction module 30; the prefetch prediction module 30 is configured to provide a first prefetch trigger mode. For example, the first prefetch trigger mode represents prefetch accuracy information, and the first mode selection unit is further configured to: in response to the utilization information being greater than or equal to a first threshold, determine whether the first prefetch trigger mode is saturated; and in response to the first prefetch trigger mode being saturated, perform prefetching on one of the first cache and the second cache using the first mode, and not perform prefetching on the other of the first cache and the second cache.

[0084] For example, in the cache synthesis prefetch device provided in some embodiments of the present disclosure, the prefetch prediction unit is further configured to provide a second prefetch trigger mode. For example, the second prefetch trigger mode represents prefetch coverage information. The first mode selection unit is further configured to: in response to the utilization information being less than the first threshold and greater than or equal to the second threshold, determine whether the second prefetch trigger mode is saturated, and in response to the second prefetch trigger mode being saturated, adopt the first mode to prefetch one of the first cache and the second cache, and do not prefetch the other of the first cache and the second cache, or in response to the second prefetch trigger mode being unsaturated, adopt the first mode to prefetch the first cache. The second mode selection unit is further configured to: in response to the utilization information being less than the first threshold and greater than or equal to the second threshold, determine whether the second prefetch trigger mode is saturated, and in response to the second prefetch trigger mode being saturated, adopt the second mode to prefetch the second cache, wherein the second threshold is less than the first threshold, and the prefetch accuracy of the first mode is higher than the prefetch accuracy of the second mode.

[0085] For example, in the cache synthesis prefetch device provided in some embodiments of the present disclosure, the first mode selection unit is further configured to: in response to the utilization information being less than the second threshold, adopt the first mode to prefetch the first cache; the second mode selection unit is further configured to: in response to the utilization information being less than the second threshold, adopt the second mode to prefetch the second cache.

[0086] For example, in the cache synthesis prefetching apparatus provided in some embodiments of the present disclosure, the first mode selection unit is further configured to: perform prefetching on the first cache using the first mode and not perform prefetching on the second cache.

[0087] For example, in the cache synthesis prefetch device provided in some embodiments of the present disclosure, the prefetch prediction module 30 is further configured to: obtain a third prefetch trigger mode from the first prefetch trigger mode and the second prefetch trigger mode, so that the third prefetch trigger mode generates the second mode.

[0088] At least one embodiment of the present disclosure further provides a processor, which includes the cache synthesis prefetching device provided in any embodiment of the present disclosure. The processor can be a single-core processor or a multi-core processor, and can also include multi-level cache, memory, etc. as needed.

[0089] At least one embodiment of the present disclosure further provides an electronic device comprising a processor provided by any embodiment of the present disclosure. The electronic device can reduce address translation latency while implementing a data / instruction prefetching function, effectively reducing latency in data / instruction read and write operations and improving overall system performance.

[0090] Figure 7 This is a schematic block diagram of an electronic device provided in some embodiments of the present disclosure. Figure 7 As shown, the electronic device 100 includes a processor 110, which is a processor provided by any embodiment of the present disclosure, for example, Figure 7 The electronic device 100 can be used in new application scenarios such as big data, cloud computing, and artificial intelligence (AI). Accordingly, the electronic device 100 can be a big data computing device, a cloud computing device, an artificial intelligence device, etc., and the embodiments of the present disclosure are not limited to this.

[0091] Figure 8 This is a schematic block diagram of another electronic device provided in some embodiments of the present disclosure. Figure 8 As shown, the electronic device 200 is suitable for implementing the information pre-fetching method provided by the embodiment of the present disclosure. The electronic device 200 can be a terminal device or a server. It should be noted that Figure 8 The electronic device 200 shown is merely an example and does not impose any limitation on the functions and scope of use of the embodiments of the present disclosure.

[0092] like Figure 8 As shown, the electronic device 200 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 21, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 22 or a program loaded from a storage device 28 to a random access memory (RAM) 23. For example, the processing device 21 may be a processor provided by any embodiment of the present disclosure, such as Figure 7 The processor shown. Various programs and data required for the operation of the electronic device 200 are also stored in the RAM 23. The processing device 21, the ROM 22, and the RAM 23 are connected to each other via a bus 24. An input / output (I / O) interface 25 is also connected to the bus 24.

[0093] Typically, the following devices may be connected to the I / O interface 25: an input device 26 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 27 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; the electronic device 200 may further include a storage device 28 such as a magnetic tape, a hard disk, etc., and a communication device 29. The communication device 29 may allow the electronic device 200 to communicate with other electronic devices wirelessly or by wire to exchange data. Although Figure 8 The electronic device 200 is shown with various devices, but it should be understood that it is not required to implement or possess all of the devices shown, and the electronic device 200 may instead implement or possess more or fewer devices.

[0094] For detailed description and technical effects of the electronic device 100 / electronic device 200, please refer to the above description of the processor and information prefetching method, which will not be repeated here.

[0095] There are a few points to note:

[0096] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0097] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0098] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A cache synthesis prefetching method for prefetching a first cache and a second cache, wherein the first cache is closer to a processor core than the second cache. The method comprises: Acquiring utilization information of a prefetch information source, wherein the utilization information is information indicating a busyness of the prefetch information source itself; A prefetching mode for the first cache and the second cache is determined according to the utilization information of the prefetching information source, wherein the prefetching mode for the first cache and the second cache are different.

2. The method according to claim 1, wherein Determining a prefetching mode for the first cache and the second cache according to the utilization information of the prefetch information source includes: Prefetching the first cache using a first mode; The second cache is pre-fetched or not pre-fetched using a second mode, wherein the pre-fetching accuracy of the first mode is higher than the pre-fetching accuracy of the second mode.

3. The method according to claim 2, wherein: The prefetch coverage of the first mode is smaller than the prefetch coverage of the second mode.

4. The method according to claim 2, wherein: Also includes: Providing a first prefetch trigger mode, wherein the first prefetch trigger mode represents prefetch accuracy information, Determining a prefetching mode for the first cache and the second cache according to the utilization information of the prefetch information source includes: In response to the utilization information being greater than or equal to a first threshold, determining whether the first prefetch trigger mode is saturated; and In response to the first prefetch triggering mode being unsaturated, prefetching one of the first cache and the second cache using the first mode, and not prefetching the other of the first cache and the second cache; In response to the first prefetch triggering mode being saturated, no prefetching is performed on the first cache and the second cache.

5. The method according to claim 4, wherein Also includes: providing a second prefetch trigger mode, wherein the second prefetch trigger mode indicates prefetch coverage information, Determining a prefetching mode for the first cache and the second cache according to the utilization information of the prefetch information source further includes: In response to the utilization information being less than a first threshold and greater than or equal to a second threshold, determining whether the second prefetch trigger mode is saturated, and in response to the second prefetch trigger mode being saturated, performing prefetching on one of the first cache and the second cache using the first mode and not performing prefetching on the other of the first cache and the second cache, or in response to the second prefetch trigger mode being unsaturated, performing prefetching on the first cache using the first mode and prefetching on the second cache using the second mode, The second threshold is smaller than the first threshold, and the prefetching accuracy of the first mode is higher than the prefetching accuracy of the second mode.

6. The method according to claim 5, wherein: Determining a prefetching mode for the first cache and the second cache according to the utilization information of the prefetch information source further includes: In response to the utilization information being less than the second threshold, prefetching is performed on the first cache using the first mode, and prefetching is performed on the second cache using the second mode.

7. The method according to claim 5, wherein: Prefetching one of the first cache and the second cache using the first mode, and not prefetching the other of the first cache and the second cache, comprising: The first cache is pre-fetched using the first mode, while the second cache is not pre-fetched.

8. The method according to claim 5, wherein The first mode is generated by the first prefetch trigger mode; the second mode is generated by the first prefetch trigger mode and the second prefetch trigger mode.

9. The method according to claim 5, wherein: The first prefetch trigger pattern and the second prefetch trigger pattern have the same number of bits, each bit is 1 or 0, and the second prefetch trigger pattern includes all bits of the first prefetch trigger pattern that are 1.

10. The method according to claim 9, wherein: The first prefetch trigger mode is represented by an accuracy bias bit pattern AP, and the second prefetch trigger mode is represented by a coverage bias bit pattern CP. Generating a second mode by combining the first prefetch trigger mode and the second prefetch trigger mode includes: A third prefetch trigger pattern is obtained by (~AP) & CP, and the second pattern is generated by the third prefetch trigger pattern.

11. The method according to claim 1, wherein The first cache is a first-level cache and the second cache is a second-level cache; or the first-level cache is a second-level cache and the second cache is a third-level cache.

12. The method according to claim 1, wherein The pre-fetch information source is a memory, and the utilization information is a memory access bandwidth for the memory.

13. A cache synthesis prefetching device, arranged at the same level as a first cache or a second cache, wherein the first cache is closer to a processor core than the second cache, in, The cache synthesis prefetching device comprises: A utilization monitoring module is configured to obtain utilization information of a prefetch storage source, wherein the utilization information is information indicating how busy the prefetch information source itself is. The prefetch mode selection module is configured to determine the prefetch mode for the first cache and the second cache according to the utilization information of the prefetch storage source, wherein the prefetch mode for the first cache and the second cache are different.

14. The device according to claim 13, wherein The prefetch mode selection module includes: a first mode selection unit configured to prefetch the first cache using the first mode; The second mode selection unit is configured to adopt the second mode to prefetch or not prefetch the second cache, wherein the prefetch accuracy of the first mode is higher than the prefetch accuracy of the second mode.

15. The apparatus according to claim 14, further comprising: A prefetch prediction module is configured to provide a first prefetch trigger mode, wherein the first prefetch trigger mode represents prefetch accuracy information, The first mode selection unit is further configured to: in response to the utilization information being greater than or equal to a first threshold, determine whether the first prefetch trigger mode is saturated; and in response to the first prefetch trigger mode being unsaturated, perform prefetch on one of the first cache and the second cache using the first mode, and do not perform prefetch on the other of the first cache and the second cache; and in response to the first prefetch trigger mode being saturated, perform prefetch on neither the first cache nor the second cache.

16. The device according to claim 15, wherein The prefetch prediction unit is further configured to provide a second prefetch trigger mode, wherein the second prefetch trigger mode represents prefetch coverage information, The first mode selection unit is further configured to: in response to the utilization information being less than a first threshold and greater than or equal to a second threshold, determine whether the second prefetch trigger mode is saturated; and in response to the second prefetch trigger mode being saturated, perform prefetching on one of the first cache and the second cache in the first mode and not perform prefetching on the other of the first cache and the second cache; or in response to the second prefetch trigger mode being unsaturated, perform prefetching on the first cache in the first mode. The second mode selection unit is also configured to: in response to the utilization information being less than a first threshold and greater than or equal to a second threshold, determine whether the second prefetch trigger mode is saturated; and in response to the second prefetch trigger mode being saturated, use the second mode to prefetch the second cache, wherein the second threshold is less than the first threshold, and the prefetch accuracy of the first mode is higher than the prefetch accuracy of the second mode.

17. The device according to claim 16, wherein The first mode selection unit is further configured to: in response to the utilization information being less than the second threshold, prefetch the first cache using the first mode, The second mode selection unit is further configured to: in response to the utilization information being less than the second threshold, perform prefetching on the second cache using the second mode.

18. The device according to claim 16, wherein The first mode selection unit is further configured to: perform prefetching on the first cache using the first mode and not perform prefetching on the second cache.

19. The device according to claim 16, wherein The prefetch prediction module is further configured to obtain a third prefetch trigger mode from the first prefetch trigger mode and the second prefetch trigger mode, so that the third prefetch trigger mode generates the second mode.

20. A processor comprising the cache synthesis prefetching device according to any one of claims 13 to 19.

21. An electronic device comprising the processor according to claim 20.

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