A through hole etching method
By employing a method of multiple-step etching and adjusting the etching selectivity, the problem of controlling the endpoint of via etching in semiconductor manufacturing was solved, ensuring precise stopping of vias at different depths and improving the etching morphology and capacitor reliability.
Patent Information
- Application Number
- CN202111508943.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-12-10
- Publication Date
- 2026-02-06
- Estimated Expiration
- 2041-12-10
AI Technical Summary
In the semiconductor manufacturing process, there is a step difference between the upper and lower metal layers of the interlayer capacitor, which makes it difficult to control the etching endpoint of the via. In addition, the chemical mechanical polishing process causes the dielectric thickness difference between the middle and edge of the wafer, resulting in poor via morphology and failure of the interlayer capacitor breakdown voltage.
A method of multiple-step etching and adjustment of etching selectivity is adopted to etch vias through a mask, and the etching selectivity is adjusted after each etching to control the precise stopping of vias at different target depths. This includes using photoresist layers and adhesive layers to improve adhesion and ensure the accuracy of via morphology and depth.
It enables precise stopping of vias at different target locations, improves etching morphology, avoids problems such as poor via morphology and interlayer capacitance breakdown, and improves etching accuracy and reliability.
Smart Images
Figure CN114284205B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a via etching method. BACKGROUND
[0002] In the semiconductor manufacturing process, the back-end-of-line (BEOL) refers to the process of completing the metal interconnection of a chip. In the prior art, an interlayer capacitor structure is usually prepared between the metal layers of the metal interconnection layer of the chip to improve the utilization efficiency of the chip area.
[0003] The BEOL of existing embedded flash memory, power devices, power management chips and various chips generally includes the preparation process of an interlayer capacitor. In the preparation process of the interlayer capacitor, a via is etched to connect the upper and lower metal layers constituting the interlayer capacitor. In the process of etching the via, the upper and lower metal layers of the interlayer capacitor have different step differences, making it difficult to control the etching endpoint of the via. The chemical mechanical polishing process of the precursor causes a pattern effect of a large difference in the thickness of the medium in the middle and edge of the wafer due to the load effect. On this basis, if a traditional etching process is used to etch the contact via of the interlayer capacitor, the via morphology is poor, as shown in FIG. 1, and the plate of the interlayer capacitor is easily broken down, resulting in electrical failures such as breakdown voltage. Figures 1-3 SUMMARY
[0004] In view of the above problems in the prior art, a via etching method is provided. The specific technical solutions are as follows.
[0005] A via etching method, comprising the following steps,
[0006] Step S1, providing a composite structure, the composite structure at least comprising a first material medium layer, and a second material medium layer covering the upper surface of the first material medium layer, the second material medium layer comprising a step structure, the step structure comprising a plurality of steps, the step structure comprising,
[0007] a first metal layer,
[0008] a second metal layer located above the first metal layer, and the projection of the second metal layer covering part of the first metal layer,
[0009] a medium layer filled between the first metal layer and the second metal layer, covering the part of the first metal layer exposed to the second metal layer, and the upper surface of the second metal layer;
[0010] Step S2, providing a mask covering the composite structure, and opening windows corresponding to a plurality of vias to be etched on the mask;
[0011] Step S3, etching a plurality of the through holes through the mask;
[0012] Step S4, providing an etching selection ratio, etching a plurality of the through holes according to the etching selection ratio, and adjusting the etching selection ratio after each etching to reduce the etching amount of the first material medium layer and / or the medium layer, so that the bottoms of a plurality of the through holes stop at different depths.
[0013] Preferably, the step further comprises an interconnection layer, and the first material medium layer covers the upper surface of the interconnection layer.
[0014] Preferably, the step further comprises an interlayer capacitance.
[0015] Preferably, in the step S3, the through holes comprise,
[0016] a first type of through hole, the bottom of which stops on each step of the step structure,
[0017] a second type of through hole, the bottom of which stops in the first material medium layer.
[0018] Preferably, in the step S4, each etching stops in the through hole whose bottom does not reach the target position, and the target position of the through hole with the shallowest etching depth is a predetermined distance above the target position.
[0019] Preferably, the material of the first material medium layer comprises silicon nitride or nitrogen-doped silicon carbide.
[0020] Preferably, the material of the second material medium layer comprises silicon oxide.
[0021] Preferably, the material of the medium layer comprises silicon nitride or nitrogen-doped silicon carbide.
[0022] Preferably, in the step 2, the mask is a photoresist layer.
[0023] Preferably, the step further comprises an adhesion layer arranged between the mask and the upper surface of the composite structure to improve the adhesion of the mask.
[0024] The technical solution of the present application has the beneficial effect of ensuring the appearance of the through hole while controlling the through hole at different target positions to stop at the required depth. BRIEF DESCRIPTION OF DRAWINGS
[0025] Reference is made to the accompanying drawings to more fully describe embodiments of the present application. However, the accompanying drawings are only used for illustration and explanation, and do not constitute a limitation on the scope of the present application.
[0026] Figures 1-3 A defect image caused by etching an interlayer capacitance contact through hole in the prior art traditional process;
[0027] Figure 4 This is a flowchart illustrating the steps of an embodiment of the through-hole etching method of the present invention;
[0028] Figures 5-10 This is a state change diagram of an embodiment of the through-hole etching method of the present invention;
[0029] Figures 11-12 This is an image of a through-hole formed by etching according to an embodiment of the through-hole etching method of the present invention. Detailed Implementation
[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0031] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.
[0032] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.
[0033] like Figure 4 , Figures 5-9 As shown, the technical solution of the present invention includes a through-hole etching method, which includes the following steps:
[0034] Step S1: A composite structure is provided, the composite structure including at least a first material dielectric layer 101 and a second material dielectric layer 102 covering the upper surface of the first material dielectric layer 101. The second material dielectric layer 102 includes a step structure 400, the step structure including a plurality of steps. When the step structure 400 has two steps, the step structure 400 may include...
[0035] First metal layer 401;
[0036] A second metal layer 402 is located above the first metal layer 401, and the projection of the second metal layer 402 covers part of the first metal layer 401, that is, at least one part of the first metal layer 401 extends out of the area covered by the projection of the second metal layer 402, thereby forming two steps.
[0037] A dielectric layer 403 is filled between the first metal layer 401 and the second metal layer 402, so that the first metal layer 401, the dielectric layer 403 and the second metal layer 402 form a capacitor structure, the first metal layer 401 and the second metal layer 402 respectively form upper and lower electrodes of the capacitor structure, the dielectric layer 403 also covers the part of the first metal layer 401 exposing the second metal layer 402, and the upper surface of the second metal layer 402;
[0038] Step S2, a mask 200 is provided to cover the composite structure, and windows 201 corresponding to the plurality of through holes to be etched are opened on the mask 200;
[0039] Step S3, etching the plurality of through holes through the mask 200;
[0040] Step S4, an etching selection ratio is provided, the plurality of through holes are etched one by one according to the etching selection ratio, and the etching selection ratio is adjusted after each etching to reduce the etching amount of the first material dielectric layer 101 and / or the dielectric layer 403, so that the bottoms of the plurality of through holes can be stopped at different depths.
[0041] In the above technical solution, by multiple step-by-step etching of the through holes and adjusting the etching selection ratio at each etching, the etching amount of the first material dielectric layer 101 and / or the dielectric layer 403 is reduced, that is, the etching amount of the second material dielectric layer 102 is relatively increased, so that the bottoms of the through holes with different target depth positions can be stopped at the target depth positions respectively, and the morphology of the etched through holes can be improved.
[0042] On the basis of the above technical solution, preferably, in step 2, the mask 200 can include a photoresist layer. The photoresist layer can be formed by spin coating process, and the windows 201 corresponding to the through holes to be etched are opened by exposure and development process.
[0043] Further preferably, an adhesion layer 202 can also be included, which is arranged between the mask 200 and the upper surface of the composite structure to improve the adhesion of the mask 200. Preferably, in the case where the mask 200 is photoresist, the adhesion layer 202 can use a dielectric antireflection layer to improve the adhesion of the photoresist, which can prevent the photoresist from warping or collapsing.
[0044] On the basis of this, further preferably, after the through hole etching is completed, a step of removing the mask 200 can also be included, as shown in Figure 10 Further preferably, in the case where the mask uses photoresist, a gray etching process can be used to remove the photoresist.
[0045] On the basis of the above technical solution, preferably, it also includes an interconnection layer 103, and the first material dielectric layer 101 covers the upper surface of the interconnection layer.
[0046] On the basis of the above technical solution, the step structure 400 can include an interlayer capacitance structure.
[0047] In a preferred embodiment, in step S3, the through holes can include,
[0048] First type of through holes, the bottom part stops on each step of the step structure 400 respectively,
[0049] Second type of through holes, the bottom part stops in the first material medium layer 101.
[0050] On the basis of the above technical solution, further, in step S4, in the through holes whose bottom part has not reached the target position, the through hole with the shallowest predetermined etching depth is selected, the etching can be stopped at a predetermined distance above the target position of the selected through hole, and the selected through hole is regarded as the bottom part having reached the target position.
[0051] In a preferred embodiment, before step S4, a pre-etching step can be performed, so that the bottom part of each through hole stays in the second material medium layer.
[0052] In one embodiment, as the first via 301 in the first type of via, the target position is the bottom of the dielectric layer 403 above the upper electrode of the capacitor structure of the interlayer capacitor, i.e., the second metal layer 402. As the second via 302 in the first type of via, the target position is the bottom of the dielectric layer 403 above the lower electrode of the capacitor structure of the interlayer capacitor, i.e., the first metal layer 401. As the third via in the second type of via, the target position is the bottom of the first material dielectric layer 101 above the interconnection layer 103. Further, the bottom of the first via 301, the second via 302, and the third via 303 is in the second material dielectric layer 102 by first-step pre-etching through the mask 200. At this time, the etching thickness of all the vias is THK1. Then, the first etching is performed. At this time, the bottom of all the vias does not reach the target position, and the target position of the first via 301 is the shallowest. Therefore, the etching is terminated at a predetermined distance above the target position of the first via 301. The etching is completed at this time, and the etching thickness of all the vias is THK2. The first via 301 is considered to have reached the target position. The etching selectivity is changed, the etching amount of the first material dielectric layer 101 and / or the dielectric layer 403 is reduced, and the etching amount of the second material dielectric layer 102 is relatively increased. The second etching is started. In the second etching, the vias whose bottom does not reach the target position include the second via 302 and the third via 303. Since the target position of the second via 302 is the shallowest, the etching is terminated at a predetermined distance above the target position of the second via 302. The etching is completed at this time, and the etching thickness of the second via 302 and the third via 303 is THK3. The first via 301 is slowed down in etching speed due to the blocking of the dielectric layer 403 on the upper surface of the second metal layer 402 and the second metal layer 402, and finally stays at the second metal layer 402. The etching selectivity is changed again, the etching amount of the first material dielectric layer 101 and / or the dielectric layer 403 is reduced, and the etching amount of the second material dielectric layer 102 is relatively increased. The third etching is started. In the third etching, the via whose bottom does not reach the target position is only the third via 303. Therefore, the etching is terminated at a predetermined distance above the target position of the third via 303. The etching is completed at this time, and the etching thickness of the third via 303 is THK4. The first via 301 stays at the second metal layer 402 due to the blocking of the second metal layer 402. The second via 302 is slowed down in etching speed due to the blocking of the dielectric layer 403 on the upper surface of the first metal layer 401 and the first metal layer 401, and finally stays at the first metal layer 401. The third via 303 stays at the first material dielectric layer 101. This embodiment describes a technical solution in which vias with three different target depths are accurately guided to different target positions by step etching and different etching selectivity. As a description of feasibility, the etching selectivity in the above three etchings can be as follows:
[0053] The etching ratio of the second material medium layer 102 to the first material medium layer 101 and / or the medium layer 403 is 1:1-2:1 in the first etching;
[0054] The etching ratio of the second material medium layer 102 to the first material medium layer 101 and / or the medium layer 403 is 4:1-7:1 in the second etching
[0055] The etching ratio of the second material medium layer 102 to the first material medium layer 101 and / or the medium layer 403 is 7:1-10:1 in the third etching
[0056] If there is a fourth etching, the etching ratio of the second material medium layer 102 to the first material medium layer 101 and / or the medium layer 403 is 9:1-13:1 in the fourth etching, and if there is a fifth etching, the etching ratio can be adjusted according to the above-mentioned etching selection ratio change rule.
[0057] Figure 11 、 Figure 12 The above-mentioned embodiment can complete the appearance image of the through hole, and it can be seen that the appearance of the through hole is obviously due to Figures 1-3 The effect of the traditional etching process.
[0058] It should be noted that the present application is not limited to the etching of three target depth through holes, and the number of target depths can be increased or decreased according to the device structure needs, such as in the above-mentioned embodiment, if the through hole 303 is etched again, it will be blocked by the medium and metal in the interconnection layer 103, so that the third through hole 303 is exposed to the metal in the interconnection layer.
[0059] On the basis of the above technical solutions, further, the material of the first material medium layer 101 can include silicon nitride or nitrogen-doped silicon carbide; on the basis of this, the material of the second material medium layer 102 can include silicon oxide; on the basis of this, the material of the medium layer 403 can include silicon nitride or nitrogen-doped silicon carbide.
[0060] The above-mentioned is only the preferred embodiment of the present application, and is not limited to the implementation and protection range of the present application. For those skilled in the art, it should be realized that any equivalent replacement and obvious change made by using the content of the present application can be included in the protection range of the present application.
Claims
1. A method of via etching, the method comprising: The method comprises the following steps: S1. providing a composite structure, which comprises at least a first material medium layer and a second material medium layer covering the upper surface of the first material medium layer, wherein the second material medium layer comprises a step structure, the step structure comprises a plurality of steps, and the step structure comprises, a first metal layer, a second metal layer above the first metal layer, and the projection of the second metal layer covers part of the first metal layer, a medium layer filled between the first metal layer and the second metal layer, covering the exposed part of the first metal layer and the upper surface of the second metal layer; and S2. providing a mask covering the composite structure and opening a plurality of windows corresponding to the through holes to be etched on the mask; S3. etching a plurality of through holes through the mask; S4. providing an etching selection ratio, etching a plurality of through holes according to the etching selection ratio, and adjusting the etching selection ratio after each etching to reduce the etching amount of the first material medium layer and / or the medium layer, so that the bottoms of a plurality of through holes stop at different depths; Each etching stops in the through hole whose bottom does not reach the target position, the target position of the through hole with the shallowest predetermined etching depth, and a predetermined distance above.
2. The via etching method of claim 1, wherein, The composite structure further comprises an interconnection layer, and the first material medium layer covers the upper surface of the interconnection layer.
3. The via etch method of claim 1, wherein The step structure comprises an interlayer capacitance.
4. The via etch method of claim 1, wherein, In the step S3, the through holes comprise, first type of through holes, the bottoms of which stop on each step of the step structure respectively, second type of through holes, the bottoms of which stop in the first material medium layer.
5. The via etch method of claim 1, wherein, The material of the first material medium layer comprises silicon nitride or nitrogen-doped silicon carbide.
6. The via etch method of claim 1, wherein, The material of the second material medium layer comprises silicon oxide.
7. The via etch method of claim 1, wherein, The material of the medium layer comprises silicon nitride or nitrogen-doped silicon carbide.
8. The via etch method of claim 1, wherein, In the step S2, the mask is a photoresist layer.
9. The via etch method of claim 1, wherein, Further comprising an adhesion layer arranged between the mask and the upper surface of the composite structure to improve the adhesion of the mask.
Citation Information
Patent Citations
Multiple Depth Vias In An Integrated Circuit
US20130334659A1