Integrated etching method

Abstract

The application discloses an integrated etching method, which comprises the following steps: depositing an LK film on a hard mask NDC layer; depositing a TEOS film on the LK film; sequentially forming a barrier layer, a dielectric layer, a bottom anti-reflective coating layer and a photoresist layer on the TEOS film; performing metal hard mask etching; performing photoetching of a through hole to define a through hole pattern; forming a through hole on the photoresist layer; removing part of the bottom anti-reflective coating layer; etching the dielectric layer and the barrier layer, which will be used for filling copper material later; and protecting the exposed barrier layer by using a gas containing fluorocarbon. The exposed area of the barrier layer is greatly reduced by using the gas containing fluorocarbon to protect the exposed barrier layer, and the generation of TixFy residues is reduced during subsequent etching, so that the problem of through hole opening is fundamentally solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, in particular to a method for integrated etching. BACKGROUND

[0002] At present, the semiconductor integrated circuit (IC) manufacturing mainly grows semiconductor devices on the wafer device surface of silicon substrate and carries out interconnection. The semiconductor devices are made in the device layer, taking the metal oxide semiconductor field effect transistor (MOSFET) device as an example, the main structure of the MOSFET device includes: active region, source, drain and gate, wherein the active region is located in the silicon substrate, the gate is located above the active region, the active regions on both sides of the gate are ion implanted to form the source and the drain, the gate has a conductive channel below, and the gate and the conductive channel have a gate dielectric layer between. According to the working principle of the MOSFET device, the MOSFET device must be turned on and off by applying different voltages to the source, gate and drain of the MOSFET respectively, so after the main structure of the MOSFET device is made, tungsten (W) contact (CT) and tungsten plug are made in the device layer to electrically connect each part of the MOSFET device, and the device layer process of the MOSFET device is completed.

[0003] After the device layer where the MOSFET device is located is made, a metal interconnection layer is made above the device layer to provide physical guarantee for signal transmission between the MOSFET devices. The production of the metal interconnection layer is called metal interconnection layer process, BEOL (Back-end Of Line), AIO (integrated etching) process is carried out for BEOL. When the via line width formed by lithography is greater than the width of the metal line, a large amount of TixFy residue will be accumulated at the bottom of the via after etching due to the three-side exposure of the barrier layer at the end of the Metal line, which will cause the etching to stop and finally cause the problem of Via Open. SUMMARY

[0004] In view of the above problems, in order to overcome the defects of the prior art, the present application provides a method for integrated etching.

[0005] The present application solves the above technical problems by the following technical scheme: a method for integrated etching, characterized in that it comprises the following steps:

[0006] Step one, depositing LK film on the hard mask NDC layer;

[0007] Step two, depositing TEOS film on the LK film;

[0008] Step three, forming a barrier layer, a medium layer, a bottom anti-reflective coating layer and a photoresist layer on the TEOS film in sequence;

[0009] Step four, etching with a metal hard mask;

[0010] Step five, photoetching for a via hole to define a via hole pattern;

[0011] Step six, forming a via hole on the photoresist layer;

[0012] Step seven, removing part of the bottom anti-reflective coating layer;

[0013] Step eight, etching the medium layer and the barrier layer;

[0014] Step nine, protecting the exposed barrier layer with a gas containing fluorocarbon;

[0015] Step ten, etching the TEOS film to expose the LK film;

[0016] Step eleven, etching part of the LK film.

[0017] Preferably, the step one is cured by ultraviolet rays.

[0018] Preferably, the barrier layer is made of silicon nitride or aluminum nitride.

[0019] Preferably, the barrier layer is directly deposited on the TEOS film by plasma enhanced chemical vapor deposition.

[0020] Preferably, the medium layer is made of an oxide containing Sn element and at least one of Zn element, Zr element, Si element and Ga element.

[0021] Preferably, the step three is followed by a cleaning before the step four.

[0022] Preferably, the step seven is performed by using plasma etching with the photoresist layer as a mask.

[0023] Preferably, the step ten is followed by ion implanting carbon element or nitrogen element on the surface of the LK film before the step eleven.

[0024] Preferably, the ratio of fluorine to carbon in the fluorocarbon is 1:2.

[0025] The positive progress effect of the present application is that the present application protects the exposed barrier layer with a gas containing fluorocarbon, greatly reduces the area of the exposed barrier layer, reduces the generation of TixFy residue in subsequent etching, and fundamentally solves the problem of via hole opening. BRIEF DESCRIPTION OF DRAWINGS

[0026] Fig. 1The flow chart of the integrated etching method of the present application.

[0027] Figs. 2-4 The process step chart of the integrated etching method of the present application. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application.

[0029] As shown in the figure, Figs. 1-4 the integrated etching method of the present application comprises the following steps:

[0030] Step one, depositing a LK (LK is a low dielectric constant material) thin film 12 on a hard mask NDC (Nitride Doped Silicon Carbide, doped silicon carbide) layer 11;

[0031] Step two, depositing a TEOS (tetraethyl orthosilicate) thin film 13 on the LK thin film;

[0032] Step three, sequentially forming a barrier layer 14, a dielectric layer 15, a bottom anti-reflection coating (BARC) 16 and a photoresist layer 17 on the TEOS thin film;

[0033] Step four, making a metal hard mask etching;

[0034] Step five, making a photoetching of a through hole to define a through hole pattern;

[0035] Step six, forming a through hole on the photoresist layer;

[0036] Step seven, removing part of the bottom anti-reflection coating;

[0037] Step eight, etching the dielectric layer and the barrier layer, which will be used for filling copper material later;

[0038] Step nine, protecting the exposed barrier layer with a gas containing fluorocarbon (the ratio of fluorine to carbon is 1:2), greatly reducing the area of the exposed barrier layer, and reducing the generation of TixFy residue during subsequent etching, thereby fundamentally solving the problem of through hole opening;

[0039] Step ten, etching the TEOS thin film to expose the LK thin film;

[0040] Step eleven, etching part of the LK thin film.

[0041] The step one is cured by UV (ultraviolet), the by-products (such as hydroxide, organic debris or other bonds not designed) generated in the step one deposition process can be reduced or eliminated by UV radiation, and the layer produced by the deposition process can be cured or densified by UV radiation to reduce the heat accumulation in the wafer and shorten the manufacturing time of semiconductor components.

[0042] The barrier layer is made of titanium nitride (TIN) or aluminum nitride, so that the thickness is reduced and the subsequent effective conductivity is increased.

[0043] The barrier layer is directly deposited on the TEOS film by plasma enhanced chemical vapor deposition (PECVD), which greatly simplifies the process flow.

[0044] The dielectric layer is formed by an oxide containing Sn element and at least one of Zn element, Zr element, Si element and Ga element, so as to further reduce the leakage current and improve the interface stability.

[0045] The cleaning is performed after the step three and before the step four, so as to improve the cleanliness and ensure the quality of wafer devices.

[0046] The photoresist layer is used as a mask and plasma etching is used to remove part of the bottom anti-reflective coating, so as to improve the etching rate.

[0047] The surface of the LK film is implanted with carbon element or nitrogen element before the step ten and the step eleven, so that there is no loss and the groove has accurate size.

[0048] The step eleven is followed by the trench etching and liner removal (LRM) process.

[0049] The above specific embodiments are preferred embodiments of the present application, and cannot limit the present application, and any changes or other equivalent replacement methods without departing from the technical solutions of the present application are included in the protection scope of the present application.

Claims

1. An integrated etching method, characterized by, It comprises the following steps: Step one, depositing a low dielectric constant film on a hard mask NDC layer; Step two, depositing a TEOS film on the low dielectric constant film; Step three, sequentially forming a barrier layer, a dielectric layer, a bottom anti-reflective coating layer and a photoresist layer on the TEOS film; Step four, making a metal hard mask etching; Step five, making a via photoetching to define a via pattern; Step six, forming a via on the photoresist layer; Step seven, removing part of the bottom anti-reflective coating layer; Step eight, etching the dielectric layer and the barrier layer; Step nine, protecting the exposed barrier layer with a gas containing fluorocarbon; Step ten, etching the TEOS film to expose the low dielectric constant film; Step eleven, etching part of the low dielectric constant film.

2. The integrated etching method of claim 1, wherein, The step one uses ultraviolet rays for curing.

3. The integrated etching method of claim 1, wherein The barrier layer uses silicon nitride or aluminum nitride.

4. The integrated etching method of claim 1, wherein The barrier layer is directly deposited on the TEOS film via plasma-enhanced chemical vapor deposition.

5. The integrated etching method of claim 1, wherein The dielectric layer is formed of an oxide containing Sn element and at least one of Zn element, Zr element, Si element and Ga element.

6. The integrated etching method of claim 1, wherein, The step three is followed by cleaning before the step four.

7. The integrated etching method of claim 1, wherein, The step seven uses plasma etching with the photoresist layer as a mask.

8. The integrated etching method of claim 1, wherein, The step ten is followed by ion implanting carbon element or nitrogen element into the surface of the low dielectric constant film before the step eleven.

9. The integrated etching method of claim 1, wherein, The ratio of fluorine to carbon in the fluorocarbon is 1:2.

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