Semiconductor memory device

Abstract

A semiconductor memory device includes a bit line extending in a first direction; a channel pattern on the bit line, the channel pattern including first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions; first and second word lines provided on the horizontal portion and between the first and second vertical portions and extending in a second direction crossing the bit line; and a gate insulating pattern provided between the first word line and the channel pattern and between the second word line and the channel pattern.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a vertical channel transistor and a manufacturing method thereof. BACKGROUND

[0002] As a design rule of a semiconductor device is reduced, an integration density and an operation speed of the semiconductor device can be increased, but a new technology is required to improve or maintain a yield. Recently, a semiconductor device having a vertical channel transistor has been proposed to increase an integration density of the semiconductor device and to improve a resistance and a current driving characteristic of a transistor. SUMMARY

[0003] Embodiments of the present disclosure provide a semiconductor memory device having improved electrical characteristics and an increased integration density.

[0004] According to an aspect of the present disclosure, a semiconductor memory device includes a bit line extending in a first direction; a channel pattern on the bit line, the channel pattern including first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions; first and second word lines provided on the horizontal portion and between the first and second vertical portions, the first and second word lines extending in a second direction crossing the bit line; and a gate insulating pattern provided between the first word line and the channel pattern and between the second word line and the channel pattern.

[0005] According to an aspect of the disclosure, a semiconductor memory device includes a peripheral circuit structure including a plurality of peripheral circuits on a semiconductor substrate and a lower insulating layer covering the plurality of peripheral circuits; a plurality of bit lines extending in a first direction on the peripheral circuit structure; a first insulating pattern defining a trench, the first insulating pattern crossing the plurality of bit lines and extending in a second direction; a plurality of channel patterns provided in the trench and spaced apart from each other in the second direction, each of the plurality of channel patterns including first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions; first and second word lines provided on the horizontal portion of each of the plurality of channel patterns, the first and second word lines extending in the second direction, the first word line being adjacent to the first vertical portion of each of the plurality of channel patterns, the second word line being adjacent to the second vertical portion of each of the plurality of channel patterns; a gate insulating pattern for each of the plurality of channel patterns, extending in the second direction, disposed between the channel pattern and the first word line, and between the channel pattern and the second word line; a second insulating pattern covering the first and second word lines in the trench; a plurality of first data storage patterns disposed on the respective first vertical portions of the plurality of channel patterns; and a plurality of second data storage patterns disposed on the respective second vertical portions of the plurality of channel patterns.

[0006] According to an aspect of the disclosure, a semiconductor memory device includes a bit line extending in a first direction; a channel pattern on the bit line, the channel pattern including first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions; a first word line extending in a second direction to cross the bit line, the first word line being disposed on the horizontal portion and between the first and second vertical portions; and a gate insulating pattern interposed between the first word line and the channel pattern. BRIEF DESCRIPTION OF DRAWINGS

[0007] The above and other aspects, features, and advantages of certain embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a block diagram of a semiconductor memory device including a semiconductor device according to an embodiment.

[0009] Figure 2 and Figure 3 is a perspective view schematically showing a semiconductor memory device according to an embodiment.

[0010] Figure 4A is a top view of a semiconductor memory device according to an embodiment.

[0011] Figure 4B and Figure 4C are cross-sectional views taken along lines A-A', B-B', C-C', and D-D' of Figure 4A to illustrate a semiconductor memory device according to an embodiment.

[0012] Figure 5A , Figure 5B , Figure 5C and Figure 5D are enlarged cross-sectional views showing a portion P1 of Figure 4B .

[0013] Figure 6A is a plan view of a semiconductor memory device according to an embodiment.

[0014] Figure 6B and Figure 6C are cross-sectional views taken along lines B-B' and E-E' of Figure 6A to illustrate a semiconductor memory device according to an embodiment.

[0015] Figure 7 is a plan view of a semiconductor memory device according to an embodiment.

[0016] Figure 8A is a plan view of a semiconductor memory device according to an embodiment.

[0017] Figure 8B is a cross-sectional view taken along line C-C' of Figure 8A to illustrate a semiconductor memory device according to an embodiment.

[0018] Figure 9A is a plan view of a semiconductor memory device according to an embodiment.

[0019] Figure 9B is a cross-sectional view taken along line A-A' of Figure 9A to illustrate a semiconductor memory device according to an embodiment.

[0020] Figure 10A is a plan view of a semiconductor memory device according to an embodiment.

[0021] Figure 10B and Figure 10C are cross-sectional views taken along lines A-A', B-B', C-C', and D-D' of Figure 10A to illustrate a semiconductor memory device according to an embodiment.

[0022] Figure 11 is a plan view of a semiconductor memory device according to an embodiment.

[0023] Figure 12Ais a plan view of a semiconductor storage device according to an embodiment.

[0024] Figure 12B is a sectional view taken along Figure 12A line A-A' of FIG. 1 to show a semiconductor storage device according to an embodiment.

[0025] Figure 13A is a plan view of a semiconductor storage device according to an embodiment.

[0026] Figure 13B and Figure 13C are sectional views taken along Figure 13A lines A-A', B-B', C-C', and D-D' of FIG. 1, respectively, to show a semiconductor storage device according to an embodiment.

[0027] Figure 14 is a plan view of a semiconductor storage device according to an embodiment.

[0028] Figure 15A is a plan view of a semiconductor storage device according to an embodiment.

[0029] Figure 15B is a sectional view taken along Figure 15A line A-A' of FIG. 1 to show a semiconductor storage device according to an embodiment.

[0030] Figure 15A are sectional views taken along Figure 15B lines A-A' and D-D' of FIG. 1 to show a semiconductor storage device according to an embodiment.

[0031] Figure 13A is a plan view of a semiconductor storage device according to an embodiment.

[0032] Figure 13B and Figure 13C are sectional views taken along Figure 16 lines I-I' and line II-II' of FIG. 1, respectively, to show a semiconductor storage device according to an embodiment.

[0033] Figure 4A , Figure 16 , Figure 17A , Figure 17B , Figure 17C and Figure 17A are plan views showing a method of manufacturing a semiconductor storage device according to an embodiment.

[0034] Figure 17A , Figure 17B , Figure 17A , Figure 17C , Figure 17B and Figures 18A-23Aand Figures 18B-23B , Figures 18C-23C , Figure 18A , Figure 18B , Figure 18C and Figure 19A are cross-sectional views showing a method of manufacturing a semiconductor storage device according to an embodiment.

[0035] Figure 19B is a top view of a semiconductor storage device according to an embodiment.

[0036] Figure 19C is a cross-sectional view taken along line I-I' of Figure 20A to show a semiconductor storage device according to an embodiment.

[0037] Figure 20B , Figure 20C and Figure 21A are top views showing a method of manufacturing a semiconductor storage device according to an embodiment.

[0038] Figure 21B , Figure 21C and Figure 22A and Figure 22B , Figure 22C and Figure 5C are cross-sectional views showing a method of manufacturing a semiconductor storage device according to an embodiment.

[0039] Figure 5D is a top view of a semiconductor storage device according to an embodiment.

[0040] Figure 23A is a cross-sectional view taken along line I-I' of Figure 23B to show a semiconductor storage device according to an embodiment.

[0041] It should be noted that these drawings are intended to illustrate the general characteristics of methods, structures and / or materials utilized in certain example embodiments and to supplement the written description provided below. These drawings are not, however, intended to define or limit the scope of the value or properties disclosed by example embodiments and should not be interpreted in that manner. For example, relative thicknesses and positions of molecular, layer, regional, and / or structural elements can be exaggerated or reduced in the drawings for clarity. The use of similar or identical reference numerals in various drawings is intended to indicate like or similar elements or features. DETAILED DESCRIPTION

[0042] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments are shown. Like

[0043] It will be understood that when an element or layer is referred to as being "on" or "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," or "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. Like reference numerals refer to like elements throughout.

[0044] To facilitate description, spatial terms, such as "on," "above," "over," "upper," "below," "under," "lower," and the like, can be used herein to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatial terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "under" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptions used herein interpreted accordingly.

[0045] For the sake of brevity, traditional elements of a semiconductor device can or can not be described in detail herein.

[0046] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. As used herein, when a phrase such as "at least one of a, b, and c" appears, it is intended to mean a, b, or c individually or any combination of a, b, and c. As used herein, the term "about" when used in reference to a particular recited numerical value, means that the value can vary from the recited value by no more than 1%, 2%, 5%, 10%, or 20% of the recited value.

[0047] Figure 23C is a block diagram of a semiconductor memory device including a semiconductor device according to an embodiment.

[0048] Referring to Figure 4A , the semiconductor memory device can include an array of memory cells 1, a row decoder 2, a sense amplifier 3, a column decoder 4, and control logic 5.

[0049] The memory cell array 1 can include a plurality of memory cells MC arranged in two or three dimensions. Each memory cell MC can be provided between and connected to a word line WL and a bit line BL, which are disposed to cross each other.

[0050] Each memory cell MC can include a selection element TR and a data storage element DS electrically connected in series. The selection element TR can be provided between and connected to the data storage element DS and the word line WL, and can be provided between and connected to the data storage element DS and the bit line BL. The selection element TR can be a field effect transistor FET, and the data storage element DS can be implemented using at least one of a capacitor, a magnetic tunnel junction pattern, and a variable resistor. As an example, the selection element TR can include a transistor, a gate electrode of which can be connected to the word line WL, and a drain / source terminal of which can be connected to the bit line BL and the data storage element DS, respectively.

[0051] The row decoder 2 can be configured to decode address information input from the outside, and select one of the word lines WL of the memory cell array 1 based on the decoded address information. The address information decoded by the row decoder 2 can be provided to the row driver, which can provide respective voltages to the selected one of the word lines WL and the non-selected one of the word lines WL in response to control by the control circuit.

[0052] The sense amplifier 3 can be configured to sense, amplify, and output a voltage difference between one of the bit lines BL selected based on address information decoded by the column decoder 4 and a reference bit line.

[0053] The column decoder 4 can provide a data transmission path between the sense amplifier 3 and an external device (e.g., a memory controller). The column decoder 4 can be configured to decode address information input from the outside, and select one of the bit lines BL based on the decoded address information.

[0054] The control logic 5 can be configured to generate a control signal for controlling a data write or read operation with respect to the memory cell array 1.

[0055] Figure 4B and Figure 4C is a perspective view schematically showing a semiconductor memory device according to an embodiment.

[0056] Referring to Figure 24A , the semiconductor memory device can include a peripheral circuit structure PS on a semiconductor substrate 100 and a cell array structure CS on the peripheral circuit structure PS.

[0057] The peripheral circuit structure PS can include a core and a peripheral circuit formed on the semiconductor substrate 100. The core and the peripheral circuit can include the peripheral circuit structure PS, the core and the peripheral circuit can include the control logic 5, the row decoder 2, the column decoder 4, and the sense amplifier 3.Figure 24B The row decoder 2 and the column decoder 4, the sense amplifier 3, and the control logic 5 described with reference to

[0058] Referring to Figure 24A , the cell array structure CS can include a memory cell array 1 including memory cells MC arranged two-dimensionally or three-dimensionally on a first semiconductor substrate 100 (see, for example, Figure 24A ). As described above, the memory cell array 1 (for example, the memory cell array of Figure 24B ) can include word lines WL, bit lines BL, and memory cells connected therebetween.

[0059] The peripheral circuit structure PS can include a core and peripheral circuits formed on a second semiconductor substrate 200. The core and peripheral circuits can include the row decoder 2 and the column decoder 4, the sense amplifier 3, and the control logic 5 described with reference to Figure 24A

[0060] The lower metal pads LMP can be provided at the highest level of the cell array structure CS. The lower metal pads LMP can be electrically connected to the memory cell array 1 (see, for example, Figures 25A-27A ). The upper metal pads UMP can be provided at the highest level of the peripheral circuit structure PS. The upper metal pads UMP can be electrically connected to the core and peripheral circuits 2, 3, 4, and 5 (see, for example, Figures 25B-27B ).

[0061] The lower metal pads LMP and the upper metal pads UMP can have substantially the same size and arrangement. The lower metal pads LMP and the upper metal pads UMP can be formed of or include at least one of, for example, copper (Cu), aluminum (Al), nickel (Ni), cobalt (Co), tungsten (W), titanium (Ti), tin (Sn), and alloys thereof.

[0062] The semiconductor memory device can be manufactured by forming the cell array structure CS including memory cells on the first semiconductor substrate 100, forming the peripheral circuit structure PS including a core and peripheral circuits on a second semiconductor substrate 200 different from the first semiconductor substrate 100, and then connecting the first semiconductor substrate 100 and the second semiconductor substrate 200 in a bonding manner. In other words, the lower metal pads LMP of the cell array structure CS can be electrically and physically connected to the upper metal pads UMP of the peripheral circuit structure PS in a bonding manner, respectively. In other words, the lower metal pads LMP can be in direct contact with the upper metal pads UMP.

[0063] Figures 25C-27C is a top view of a semiconductor memory device according to an embodiment. Figure 25A and​Figure 25B are cross-sectional views taken along lines A-A', B-B', C-C', and D-D' of Figure 25C to illustrate a semiconductor memory device according to an embodiment. Figure 26A , Figure 26B , Figure 26C and Figure 19A are enlarged cross-sectional views illustrating a portion P1 of Figure 19B .

[0064] The semiconductor device can include a peripheral circuit structure PS and a cell array structure CS on the peripheral circuit structure PS.

[0065] The peripheral circuit structure PS can include a core and a peripheral circuit SA (see, for example, Figure 19C ) integrated on the semiconductor substrate 100 and a lower insulating layer 110 provided to cover the core and the peripheral circuit SA.

[0066] The semiconductor substrate 100 can be a single-crystal silicon substrate. The core and the peripheral circuit SA can include the row decoder 2 and the column decoder 4, the sense amplifier 3, and the control logic 5 described with reference to Figure 20A . As an example, the core and the peripheral circuit can include NMOS transistors and PMOS transistors integrated on the semiconductor substrate 100. The core and the peripheral circuit SA can be electrically connected to the bit lines BL through peripheral interconnection lines and peripheral contact plugs. In other words, the sense amplifiers can be electrically connected to the bit lines BL, and each sense amplifier can amplify and output a voltage level between voltages sensed by a pair of bit lines BL.

[0067] The lower insulating layer 110 can cover the core and the peripheral circuit, the peripheral interconnection lines, and the peripheral contact plugs on the semiconductor substrate 100. The lower insulating layer 110 can include a plurality of stacked insulating layers. For example, the lower insulating layer 110 can include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a low-k dielectric layer.

[0068] The cell array structure CS can include memory cells including vertical channel transistors VCT. The vertical channel transistor can refer to a transistor whose channel region is elongated in a direction perpendicular to a top surface of the semiconductor substrate 100. The cell array structure CS can include a plurality of bit lines BL, a channel pattern CP, first and second word lines WL1 and WL2, a gate insulating pattern Gox, and a data storage pattern DSP.

[0069] On the lower insulating layer 110, bit lines BL can extend in the first direction D1 and can be spaced apart from each other in the second direction D2. Spaces between the bit lines BL can be filled with an insulating material. The bit lines BL can have a first width W1 in the second direction D2, and in an embodiment, the first width W1 can be in a range of about 1 nm to 50 nm.

[0070] For example, the bit lines BL can include at least one of doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, and combinations thereof. The bit lines BL can be formed of at least one of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, and combinations thereof, but the present disclosure is not limited to these examples. The bit lines BL can have a single layer or a multi-layer structure composed of at least one of the above materials. In an embodiment, the bit lines BL can include a two-dimensional semiconductor material (e.g., graphene, carbon nanotube, or combinations thereof).

[0071] In an embodiment, the first insulating pattern 115 can be disposed on the bit lines BL, and the first insulating pattern 115 can extend in the second direction D2 to cross the bit lines BL and can define trenches T spaced apart from each other in the first direction D1.

[0072] In each of the trenches T, the channel patterns CP can be spaced apart from each other in the second direction D2. In other words, the first insulating pattern 115 can be disposed between the channel patterns CP adjacent to each other in the first direction D1 (e.g., see Figure 20B ). A top surface of the first insulating pattern 115 can be located at substantially the same level as top surfaces of the first vertical portions VP1 and the second vertical portions VP2 of the channel patterns CP (e.g., see Figure 20C ). The first insulating pattern 115 can include, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a low-k dielectric layer.

[0073] The channel patterns CP can be disposed on the bit lines BL. The channel patterns CP disposed on each of the bit lines BL can be spaced apart from each other in the first direction D1. In other words, the channel patterns CP can be arranged two-dimensionally in two different directions (e.g., the first direction D1 and the second direction D2).

[0074] Each of the channel patterns CP can have a first length L1 in the first direction D1 and can have a second width W2 in the second direction D2, which is substantially equal to or greater than the first width W1 of the bit line BL. A distance between the channel patterns CP in the first direction D1 can be different from the first length L1 of the channel patterns CP in the first direction D1. As an example, the distance between the channel patterns CP in the first direction D1 can be less than the first length L1 of the channel patterns CP in the first direction D1. Alternatively, the distance between the channel patterns CP in the first direction D1 can be substantially equal to the first length L1 of the channel patterns CP in the first direction D1. A distance between the channel patterns CP in the second direction D2 can be substantially equal to or less than the second width W2 of the channel patterns CP.

[0075] Each of the channel patterns CP can include a horizontal portion HP disposed on the bit line BL, and first and second vertical portions VP1 and VP2 extending perpendicularly from the horizontal portion HP to face each other in the first direction D1 (see, for example, Figure 10A ). Each of the first and second vertical portions VP1 and VP2 can have inner and outer side surfaces opposite to each other, and the inner side surfaces of the first and second vertical portions VP1 and VP2 can face each other in the first direction D1. In addition, the outer side surfaces of the first and second vertical portions VP1 and VP2 of adjacent ones of the channel patterns CP can face each other. The outer side surfaces of the first and second vertical portions VP1 and VP2 of the channel patterns CP can be in contact with side surfaces of the first insulating pattern 115.

[0076] The first and second vertical portions VP1 and VP2 can have a vertical length in a direction perpendicular to the top surface of the semiconductor substrate 100, and can have a width in the first direction D1. The vertical length of each of the first and second vertical portions VP1 and VP2 can be about 2 to 10 times its width, but the present disclosure is not limited to this example. The width of the first and second vertical portions VP1 and VP2 in the first direction D1 can be in the range of several nanometers to several tens of nanometers. For example, the width of the first and second vertical portions VP1 and VP2 can be in the range of 1 nm to 30 nm (specifically, from 1 nm to 10 nm).

[0077] The horizontal portion HP of the channel pattern CP can be in direct contact with the top surface of the bit line BL. In an embodiment, the thickness of the horizontal portion HP on the top surface of the bit line BL can be substantially equal to the thickness of the first and second vertical portions VP1 and VP2 on the side surface of the first insulating pattern 115.

[0078] In each channel pattern CP, the horizontal portion HP can include a common source / drain region, a top of the first vertical portion VP1 can include a first source / drain region, and a top of the second vertical portion VP2 can include a second source / drain region. The first vertical portion VP1 can include a first channel region between the first source / drain region and the common source / drain region, and the second vertical portion VP2 can include a second channel region between the second source / drain region and the common source / drain region. In one embodiment, the first channel region of the first vertical portion VP1 can be controlled by a first word line WL1, and the second channel region of the second vertical portion VP2 can be controlled by a second word line WL2.

[0079] The channel pattern CP can be formed of at least one oxide semiconductor material (e.g., In x Ga y Zn z O, In x Ga y Si z O, In x Sn y Zn z O, In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O, Hf x In y Zn z O, Ga x Zn y Sn z O, Al x Zn y Sn z O, Yb x Ga y Zn z O, In x Ga yO and combinations thereof. As an example, the channel pattern CP can be formed of or include indium gallium zinc oxide (IGZO). The channel pattern CP can include a single layer or multiple layers made of the oxide semiconductor material. The channel pattern CP can be formed of or include an amorphous, single-crystal, or polycrystalline oxide semiconductor material. In an embodiment, the channel pattern CP can have a band gap energy greater than that of silicon. For example, the channel pattern CP can have a band gap energy of about 1.5 eV to 5.6 eV. For example, when the channel pattern CP has a band gap energy of about 2.0 eV to 4.0 eV, they can have optimized channel characteristics. In an embodiment, the channel pattern CP can have a polycrystalline or amorphous structure, although the disclosure is not limited to this example. For example, the channel pattern CP can be formed of or include a two-dimensional semiconductor material (e.g., graphene, carbon nanotube, or combinations thereof).

[0080] The first and second word lines WL1 and WL2 can extend in the second direction D2 to cross the bit line BL and can be alternately arranged in the first direction D1. A pair of the first and second word lines WL1 and WL2 can be disposed between the first and second vertical portions VP1 and VP2 and on the horizontal portion HP of each channel pattern CP (see FIG. 2, for example). Figure 10B

[0081] Each of the first and second word lines WL1 and WL2 can have inner and outer side surfaces opposite to each other, and the inner side surfaces of the first and second word lines WL1 and WL2 can be disposed on the horizontal portion HP to face each other. The outer side surface of the first word line WL1 can be adjacent to the inner side surface of the first vertical portion VP1, and the outer side surface of the second word line WL2 can be adjacent to the inner side surface of the second vertical portion VP2. The first word line WL1 can be adjacent to the first channel region of the first vertical portion VP1, and the second word line WL2 can be adjacent to the second channel region of the second vertical portion VP2. The top surfaces of the first and second word lines WL1 and WL2 can be located at a lower level than the top surfaces of the first and second vertical portions VP1 and VP2 of the channel pattern CP. In addition, the first and second word lines WL1 and WL2 can have a spacer-like shape. For example, each of the first and second word lines WL1 and WL2 can have a rounded top surface.

[0082] The first and second word lines WL1 and WL2 can have a third width W3 in the first direction D1, which is smaller than the first width W1 of the bit line BL. The third width W3 of the first and second word lines WL1 and WL2 can be in a range from about 1 nm to 50 nm. ​

[0083] The first word line WL1 and the second word line WL2 can be formed of, or include, at least one of, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, and combinations thereof. The first word line WL1 and the second word line WL2 can be formed of at least one of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, and combinations thereof, although the present disclosure is not limited to these examples. The first word line WL1 and the second word line WL2 can have a single layer or a multi-layer structure composed of at least one of the above materials. In an embodiment, the first word line WL1 and the second word line WL2 can include a two-dimensional semiconductor material (e.g., graphene, carbon nanotube, or combinations thereof).

[0084] The gate insulating pattern Gox can be disposed between the channel pattern CP and the first word line WL1 and the second word line WL2. The gate insulating pattern Gox can cover the surface of the channel pattern CP with a uniform thickness. In a region between adjacent channel patterns CP, the gate insulating pattern Gox can be in direct contact with the top surface of the lower insulating layer 110 and the side surface of the first insulating pattern 115 (see, for example, Figure 10C and Figure 27A ).

[0085] In the channel pattern CP, the gate insulating pattern Gox can be interposed between the bottom surface of the first word line WL1 and the second word line WL2 and the horizontal portion HP of the channel pattern CP, between the outer side surface of the first word line WL1 and the inner side surface of the first vertical portion VP1, and between the outer side surface of the second word line WL2 and the inner side surface of the second vertical portion VP2.

[0086] The gate insulating pattern Gox can be formed of, or include, at least one of silicon oxide, silicon oxynitride, high-k dielectric material, and combinations thereof. The high-k dielectric material can have a dielectric constant higher than that of silicon oxide, and can include a metal oxide or a metal oxynitride. For example, the high-k dielectric material for the gate insulating pattern Gox can include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or combinations thereof, although the present disclosure is not limited to this example.

[0087] Referring to Figure 27BA portion of the channel pattern CP and a portion of the gate insulating pattern Gox can be located between the first word line WL1 and the second word line WL2. The horizontal portion HP of the channel pattern CP can connect the first vertical portion VP1 and the second vertical portion VP2 to a corresponding bit line BL. In the semiconductor memory device according to an embodiment, a pair of selection transistors can be provided to share a corresponding one of the bit lines BL. The corresponding bit line BL and one of the first vertical portion VP1 and the second vertical portion VP2 can be electrically connected to each other by signals applied to the first word line WL1 and the second word line WL2.

[0088] Referring to Figure 27C A first gate insulating pattern Gox1 and a second gate insulating pattern Gox2 spaced apart from each other can be disposed on the horizontal portion HP of the channel pattern CP. The first gate insulating pattern Gox1 can be interposed between a bottom surface of the first word line WL1 and the horizontal portion HP of the channel pattern CP and between an outer lateral surface of the first word line WL1 and the first vertical portion VP1 of the channel pattern CP. The second gate insulating pattern Gox2 can be interposed between a bottom surface of the second word line WL2 and the horizontal portion HP of the channel pattern CP and between an outer lateral surface of the second word line WL2 and the second vertical portion VP2 of the channel pattern CP. In the first direction D1, the first gate insulating pattern Gox1 and the second gate insulating pattern Gox2 can be mirror-symmetrical with respect to each other.

[0089] The horizontal portion HP of the channel pattern CP can be in contact with the second insulating pattern 141 between the first word line WL1 and the second word line WL2.

[0090] Referring to Figure 10A The first gate insulating pattern Gox1 and the second gate insulating pattern Gox2 can be spaced apart from each other on the horizontal portion HP of the channel pattern CP. A thickness of the horizontal portion HP of the channel pattern CP can be smaller between the first gate insulating pattern Gox1 and the second gate insulating pattern Gox2 than under the first gate insulating pattern Gox1 and the second gate insulating pattern Gox2.

[0091] Referring to Figure 10B A first channel pattern CP1 and a second channel pattern CP2 can be disposed on the bit line BL to be spaced apart from each other in the first direction D1 and mirror-symmetrical with respect to each other. The first channel pattern CP1 can include a first horizontal portion HP1 in contact with the bit line BL and a first vertical portion VP1 vertically extending from the first horizontal portion HP1 to be adjacent to an outer lateral surface of the first word line WL1. The second channel pattern CP2 can include a second horizontal portion HP2 in contact with the bit line BL and a second vertical portion VP2 vertically extending from the second horizontal portion HP2 to be adjacent to an outer lateral surface of the second word line WL2.

[0092] The side surface of the first horizontal portion HP1 of the first channel pattern CP1 and the side surface of the first gate insulating pattern Gox1 can be aligned with the inner side surface of the first word line WL1. Similarly, the side surface of the second horizontal portion HP2 of the second channel pattern CP2 and the side surface of the second gate insulating pattern Gox2 can be aligned with the inner side surface of the first word line WL1.

[0093] The landing pad LP can be disposed on the first vertical portion VP1 and the second vertical portion VP2 of the channel pattern CP. The landing pad LP can be in direct contact with the first vertical portion VP1 and the second vertical portion VP2. The landing pad LP can have various shapes such as a circular shape, an elliptical shape, a rectangular shape, a square shape, a diamond shape, a hexagonal shape when viewed in a top view.

[0094] The landing pad LP can be formed of at least one of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, and combinations thereof, but the present disclosure is not limited to these examples.

[0095] The interlayer insulating layer 150 can be provided on the first insulating pattern 115 and the second insulating pattern 141 to fill spaces between the landing pads LP.

[0096] In an embodiment, data storage patterns can be respectively disposed on the landing pads LP. The data storage patterns DSP can be electrically connected to the first vertical portion VP1 and the second vertical portion VP2 of the channel pattern CP, respectively, through the landing pads LP. As Figure 10C As shown, the data storage patterns DSP can be arranged along the first direction D1 and the second direction D2, or in a matrix shape.

[0097] In an embodiment, each data storage pattern can be a capacitor including a bottom electrode, a top electrode, and a capacitor dielectric layer interposed therebetween. In this case, the bottom electrode can be in contact with the landing pad LP when viewed in a top view, and the bottom electrode can have various shapes such as a circular shape, an elliptical shape, a rectangular shape, a square shape, a diamond shape, a hexagonal shape.

[0098] Alternatively, the data storage pattern DSP can be a variable resistance pattern whose resistance is switchable to one of at least two states by an electric pulse applied thereto. For example, the data storage pattern DSP can be formed of, or include, at least one of a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, and an antiferromagnetic material.

[0099] Hereinafter, a semiconductor device according to an embodiment will be described in more detail. In the following description, for the sake of brevity, the foregoing description of elements can be identified by the same reference numerals as those described previously, without repeating overlapping descriptions thereof.

[0100] Figure 28A is a top view of a semiconductor storage device according to an embodiment. Figure 28B and Figure 28A are cross-sectional views taken along lines B-B' and E-E' of Figure 28A to illustrate a semiconductor storage device according to an embodiment.

[0101] Referring to Figure 28B and ​ , the first insulating patterns 117 can be disposed to be spaced apart from one another in the second direction D2, and the gate insulating patterns Gox can be provided to fill spaces between the first insulating patterns 117 adjacent to one another in the second direction D2. For example, the gate insulating patterns Gox can be provided to surround each of the first insulating patterns 117 and can extend in the second direction D2, when viewed in a top view. The first word line WL1 and the second word line WL2 can extend in the second direction D2 while having a substantially constant width in the first direction D1.

[0102] ​ is a top view of a semiconductor storage device according to an embodiment.

[0103] As shown in ​ , the data storage patterns can be arranged in a zigzag shape or a honeycomb shape. The data storage patterns DSP can completely or partially overlap the landing pads LP. Each of the data storage patterns DSP can be in contact with an entire or partial area of a top surface of a corresponding one of the landing pads LP.

[0104] ​ is a top view of a semiconductor storage device according to an embodiment. ​ is a cross-sectional view taken along line C-C' of ​ to illustrate a semiconductor storage device according to an embodiment.

[0105] Referring to ​ and ​A first shield structure or a first air gap SL1 can be provided between adjacent bit lines BL. The first shield structure SL1 or the first air gap SL1 can extend in parallel to the bit lines BL in the first direction D1. The first shield structure SL1 can be formed of or include at least one conductive material (e.g., a metallic material). In a case where the first shield structure SL1 is formed between the bit lines BL, the formation of the first shield structure SL1 can include forming a gap region in an insulating layer between the bit lines BL after the formation of the bit lines BL, and then filling the gap region of the insulating layer with a conductive material. In a case where the first air gap SL1 is formed between the bit lines BL, the formation of the first air gap SL1 can include filling a space between the bit lines BL with an insulating material after the formation of the bit lines BL, using a deposition method having a poor step coverage characteristic.

[0106] ​ is a top view of a semiconductor memory device according to an embodiment. ​ is a cross-sectional view taken along line A-A' of ​ to illustrate a semiconductor memory device according to an embodiment.

[0107] Referring to ​ and ​ A second shield structure or a second air gap SL2 can be provided between adjacent first word lines WL1 and second word lines WL2, respectively. The second shield structure or the second air gap SL2 can extend in parallel to the first word lines WL1 and the second word lines WL2 in a second direction D2. Also, a third shield structure or a third air gap SL3 can be provided between adjacent channel patterns CP, respectively. The third shield structure or the third air gap SL3 can extend in parallel to each other in the second direction D2.

[0108] When the second insulating pattern 141 is formed after the formation of the first word lines WL1 and the second word lines WL2, the second shield structure SL2 can be locally formed in the second insulating pattern 141 by forming a gap region in an insulating layer, and then filling the gap region of the insulating layer with a conductive material. When the first insulating pattern 115 is formed, the third shield structure SL3 can be locally formed in the first insulating pattern 115 by forming a gap region in an insulating layer, and then filling the gap region of the insulating layer with a conductive material.

[0109] When the second insulating pattern 141 is formed, the second air gap SL2 can be locally formed in the second insulating pattern 141 by depositing an insulating layer using a deposition method having a poor step coverage characteristic. When the first insulating pattern 115 is formed, the third air gap SL3 can be locally formed in the second insulating pattern 141 by depositing an insulating layer using a deposition method having a poor step coverage characteristic.

[0110] ​ is a plan view of a semiconductor memory device according to an embodiment. ​ and ​ are cross-sectional views taken along lines A-A', B-B', C-C', and D-D' of ​ , respectively, to illustrate a semiconductor memory device according to an embodiment.

[0111] Referring to ​ and ​ , a bit line BL extending in a first direction D1 can be disposed on a lower insulating layer 110 of a peripheral circuit structure PS.

[0112] A channel pattern CP can be disposed on the bit line BL. The channel patterns CP disposed on each bit line BL can be spaced apart from each other in the first direction D1. In other words, the channel patterns CP can be two-dimensionally arranged in two different directions (e.g., the first direction D1 and a second direction D2).

[0113] As described above, each channel pattern CP can include a horizontal portion HP disposed on the bit line BL and first and second vertical portions VP1 and VP2 extending perpendicularly from the horizontal portion HP to face each other in the first direction D1.

[0114] First and second word lines WL1 and WL2 can extend to cross the bit line BL in the second direction D2 and can be alternately arranged in the first direction D1. Each first word line WL1 can extend to cover the first vertical portions VP1 of the channel patterns CP arranged in the second direction D2. Each second word line WL2 can extend to cover the second vertical portions VP2 of the channel patterns CP arranged in the second direction D2.

[0115] In an embodiment, each first word line WL1 can include a first inner gate electrode GE1a and a first outer gate electrode GE1b, and each second word line WL2 can include a second inner gate electrode GE2a and a second outer gate electrode GE2b.

[0116] The first inner gate electrode GE1a can be adjacent to an inner side surface of the first vertical portion VP1 of the channel pattern CP, and the first outer gate electrode GE1b can be adjacent to an outer side surface of the first vertical portion VP1. The second inner gate electrode GE2a can be adjacent to an inner side surface of the second vertical portion VP2 of the channel pattern CP, and the second outer gate electrode GE2b can be adjacent to an outer side surface of the second vertical portion VP2.

[0117] Each first vertical portion VP1 can be disposed between the first inner gate electrode GE1a and the first outer gate electrode GE1b, and each second vertical portion VP2 can be disposed between the second inner gate electrode GE2a and the second outer gate electrode GE2b. In other words, the semiconductor memory device can have a dual-gate transistor structure.

[0118] The inner gate insulating pattern Goxa can cover the inner side surface of the channel pattern CP with a uniform thickness, and the outer gate insulating pattern Goxb can cover the outer side surface of the channel pattern CP with a uniform thickness. Specifically, the inner gate insulating pattern Goxa can be interposed between the bottom surfaces of the first inner gate electrode GE1a and the second inner gate electrode GE2a and the horizontal portion HP of the channel pattern CP, between the outer side surface of the first inner gate electrode GE1a and the first vertical portion VP1, and between the outer side surface of the second inner gate electrode GE2a and the second vertical portion VP2. The outer gate insulating pattern Goxb can be interposed between the bottom surfaces of adjacent ones of the first outer gate electrode GE1b and the second outer gate electrode GE2b and the bit line BL, between the side surface of the first outer gate electrode GE1b and the first vertical portion VP1, and between the side surface of the second outer gate electrode GE2b and the second vertical portion VP2. The outer gate insulating pattern Goxb can be in contact with the bit line BL between adjacent ones of the first outer gate electrode GE1b and the second outer gate electrode GE2b.

[0119] The first inner gate electrode GE1a and the first outer gate electrode GE1b can be connected to each other between the first vertical portions VP1 arranged in the second direction D2. The second inner gate electrode GE2a and the second outer gate electrode GE2b can be connected to each other between the second vertical portions VP2 arranged in the second direction D2.

[0120] The insulating pattern 141 can be provided to fill spaces between the first inner gate electrode GE1a and the second inner gate electrode GE2a and between the first outer gate electrode GE1b and the second outer gate electrode GE2b. A top surface of the insulating pattern 141 can be located at substantially the same level as top surfaces of the first vertical portions VP1 and the second vertical portions VP2.

[0121] The landing pad LP and the data storage pattern DSP can be disposed on the first vertical portion VP1 and the second vertical portion VP2 of the channel pattern CP, respectively. Each data storage pattern DSP can overlap the first inner gate electrode GE1a and the first outer gate electrode GE1b, or can overlap the second inner gate electrode GE2a and the second outer gate electrode GE2b.

[0122] The landing pad LP and the data storage pattern DSP can be disposed at the center of the first vertical portion VP1 and the second vertical portion VP2 to form a matrix-like arrangement when viewed in a plan view.

[0123] ​ is a plan view of a semiconductor memory device according to an embodiment.

[0124] In ​ the embodiment illustrated, the landing pad LP and the data storage pattern DSP can be electrically connected to the first vertical portion VP1 and the second vertical portion VP2, but can be disposed at positions deviated from the center of the first vertical portion VP1 and the second vertical portion VP2. For example, the landing pad LP and the data storage pattern DSP can be arranged in a zigzag shape or a honeycomb shape.

[0125] ​ is a plan view of a semiconductor memory device according to an embodiment. ​ is a cross-sectional view taken along line A-A' of ​ to illustrate a semiconductor memory device according to an embodiment.

[0126] Referring to ​ and ​ in the embodiments described with reference to ​ , ​ and ​ , the second shielding structure SL2 or the second air gap SL2 extending in the second direction D2 can be respectively provided between adjacent internal gate electrodes among the first internal gate electrodes GE1a and the second internal gate electrodes GE2a.

[0127] In addition, the third shielding structure SL3 or the third air gap SL3 extending in the second direction D2 can be respectively provided between adjacent external gate electrodes among the first external gate electrodes GE1b and the second external gate electrodes GE2b.

[0128] ​ and ​ the second shielding structure and the third shielding structure or the second air gap and the third air gap in the embodiments can be formed by substantially the same method as the shielding structures and the air gaps described with reference to ​ and ​ above.

[0129] ​ is a plan view of a semiconductor memory device according to an embodiment. ​ and ​ are cross-sectional views taken along lines A-A', B-B', C-C', and D-D' of ​ to illustrate a semiconductor memory device according to an embodiment.

[0130] Referring to ​ , ​ and ​ , the bit lines BL can extend in a first direction D1 on the peripheral circuit structure and can be spaced apart from each other in a second direction D2.

[0131] The first word lines WL1 and the second word lines WL2 can extend in the second direction D2 on the bit lines BL. The first word lines WL1 and the second word lines WL2 can be alternately arranged in the first direction D1. Here, a width of each of the first word lines WL1 and the second word lines WL2 can be greater than half of a distance between the first vertical portions VP1 and the second vertical portions VP2 of each of the channel patterns CP (see, for example, ​ ).

[0132] The channel patterns CP can be respectively disposed between the first word lines WL1 and the second word lines WL2 and the bit lines BL. The channel patterns CP on each of the bit lines can be spaced apart from each other in the first direction D1. As described above, each of the channel patterns CP can include the first vertical portion VP1 and the second vertical portion VP2 facing each other and the horizontal portion HP connecting the first vertical portion VP1 and the second vertical portion VP2 to each other. The horizontal portion HP can be in contact with a top surface of the bit line, and the first vertical portion VP1 and the second vertical portion VP2 can each be adjacent to a respective side surface of the first word line WL1 or the second word line WL2. The insulating pattern 141 can be disposed on a top surface of each of the first word lines WL1 and the second word lines WL2. The top surfaces of the first word lines WL1 and the second word lines WL2 can be located at a lower level than top surfaces of the first vertical portions VP1 and the second vertical portions VP2 of the channel patterns CP. According to an embodiment, channel regions of the first vertical portions VP1 and the second vertical portions VP2 of each of the channel patterns CP can be commonly controlled by the first word line WL1 or the second word line WL2.

[0133] The gate insulating pattern Gox can be interposed between the channel patterns CP and side surfaces and a bottom surface of each of the first word lines WL1 and the second word lines WL2. The gate insulating pattern Gox can be in direct contact with the side surfaces and the bottom surface of each of the first word lines WL1 and the second word lines WL2.

[0134] The channel patterns CP can be spaced apart from each other in the first direction D1 by the third insulating pattern 116 and can be spaced apart from each other in the second direction D2 by the fourth insulating pattern 118. The top surfaces of the first vertical portions VP1 and the second vertical portions VP2 of the channel patterns CP can be located at substantially the same level as top surfaces of the third insulating pattern 116 and the fourth insulating pattern 118.

[0135] The landing pads LP can be respectively provided on the channel pattern CP, and each of the landing pads LP can be commonly coupled to the first vertical part VP1 and the second vertical part VP2.

[0136] The data storage patterns DSP can be respectively provided on the landing pads LP, and each of the data storage patterns DSP can be commonly coupled to the first vertical part VP1 and the second vertical part VP2 of the channel pattern CP through the landing pads LP. The data storage patterns DSP can be respectively arranged at the intersection points of the first word line WL1 and the second word line WL2 and the bit line BL when viewed in a plan view. For example, the data storage patterns DSP can be arranged in a matrix shape or in a zigzag shape in the first direction D1 and the second direction D2.

[0137] ​ is a plan view of a semiconductor memory device according to an embodiment.

[0138] As ​ indicated, the data storage patterns DSP can be arranged in a zigzag shape or a honeycomb shape when viewed in a plan view.

[0139] ​ is a plan view of a semiconductor memory device according to an embodiment. ​ is a cross-sectional view taken along line A-A' of ​ to illustrate a semiconductor memory device according to an embodiment.

[0140] Referring to ​ and ​ , in the embodiments described with reference to ​ , ​ and ​ , the shielding structures SL or air gaps SL extending in the second direction D2 can be respectively provided between adjacent word lines among the first word line WL1 and the second word line WL2. The shielding structures or air gaps SL can be locally provided in the third insulating pattern 116 and the fourth insulating pattern 118.

[0141] ​ is a cross-sectional view taken along lines A-A' and D-D' of ​ to illustrate a semiconductor memory device according to an embodiment.

[0142] Referring to ​The semiconductor memory device can include a cell array structure CS including a lower metal pad LMP provided at a highest level thereof, and a peripheral circuit structure PS including an upper metal pad UMP provided at a highest level thereof. Here, the lower metal pad LMP of the cell array structure CS can be electrically and physically connected to the upper metal pad UMP of the peripheral circuit structure PS in a bonding manner, respectively. The lower metal pad LMP and the upper metal pad UMP can be formed of or include at least one of metallic materials (e.g., copper (Cu)).

[0143] In detail, the cell array structure CS can include data storage patterns DSP provided on the first semiconductor substrate 100, first and second word lines WL1 and WL2 provided on the data storage patterns DSP, extending in a second direction D2, and alternately arranged in a first direction D1, bit lines BL provided on the first and second word lines WL1 and WL2, extending in the first direction D1, and spaced apart from each other in the second direction D2, and a lower metal pad LMP electrically connected to the bit lines BL.

[0144] In more detail, a plate conductive layer PL can be disposed on the first semiconductor substrate 100, and a mold layer ML can be disposed on the plate conductive layer PL. The mold layer ML can have mold openings separated from each other in the first and second directions D1 and D2.

[0145] Each data storage pattern DSP can include a plate electrode PE provided to conformingly cover a surface of the mold layer ML having the mold openings, a capacitor dielectric layer CIL provided to conformingly cover a surface of the plate electrode PE, and a storage electrode BE provided in the mold openings provided with the plate electrode PE and the capacitor dielectric layer CIL, respectively.

[0146] Landing pads LP can be disposed on the storage electrodes BE, respectively, and an interlayer insulating layer 150 can be provided to fill spaces between the landing pads LP.

[0147] The first and second word lines WL1 and WL2 can be disposed on the landing pads LP arranged in the second direction D2, respectively. As described above, the first and second word lines WL1 and WL2 can extend in the second direction D2, and can be spaced apart from each other in the first direction D1.

[0148] The channel patterns CP can be respectively disposed on the landing pads LP, and each channel pattern CP can include a horizontal portion HP in contact with the landing pad LP and a vertical portion VP extending perpendicularly from the horizontal portion HP and adjacent to an outer side surface of the first word line WL1 or the second word line WL2. The channel patterns CP can be spaced apart from each other in the first direction D1 and the second direction D2, and a pair of channel patterns CP adjacent to each other in the first direction D1 can be disposed to be mirror-symmetrical about each other.

[0149] Each bit line BL can be in contact with a top surface of the vertical portion VP of the channel pattern CP, the vertical portion VP of the channel pattern CP being aligned in the first direction D1. The bit line BL can be electrically connected to the lower metal pad LMP through the cell interconnection line CCL and the cell contact plug CCT. The lower metal pad LMP can be disposed in the uppermost insulating layer 170 of the cell array structure CS.

[0150] In the case where the bit line BL is provided at a higher level than the first word line WL1 and the second word line WL2 as described above, a copper line formed through a damascene process can be used as the bit line BL. In this case, the resistance of the bit line BL can be improved.

[0151] The peripheral circuit structure PS can include a core and a peripheral circuit SA integrated on the second semiconductor substrate 200, a peripheral contact plug PCT and a peripheral interconnection line PCL electrically connected to the core and the peripheral circuit SA, and an upper metal pad UMP electrically connected to the peripheral interconnection line PCL. The upper metal pad UMP can be disposed in the uppermost insulating layer 220 of the peripheral circuit structure PS.

[0152] ​ is a top view of a semiconductor memory device according to an embodiment. ​ and ​ are cross-sectional views taken along lines I-I' and II-II' of ​ to illustrate a semiconductor memory device according to an embodiment.

[0153] Referring to ​ and ​ , a plate conductive layer PL can be disposed on the semiconductor substrate 100, and a mold layer ML can be disposed on the plate conductive layer PL. The mold layer ML can have mold openings separated from each other in the first direction D1 and the second direction D2.

[0154] Each data storage pattern DSP can include a plate electrode PE provided to conformingly cover a surface of the mold layer ML having the mold openings, a capacitor dielectric layer CIL provided to conformingly cover a surface of the plate electrode PE, and a storage electrode BE provided in the mold openings in which the plate electrode PE and the capacitor dielectric layer CIL are provided, respectively.

[0155] Landing pads LP can be respectively disposed on the storage electrodes BE, and an interlayer insulating layer 150 can be provided to fill spaces between the landing pads LP. The landing pads LP can be in direct contact with the storage electrodes BE, and can be connected to the storage electrodes BE through contact plugs.

[0156] First and second word lines WL1 and WL2 can be respectively disposed on the landing pads LP arranged in the second direction D2. As described above, the first and second word lines WL1 and WL2 can extend in the second direction D2, and can be spaced apart from each other in the first direction D1.

[0157] Separation insulating patterns SIP can be disposed between adjacent ones of the first and second word lines WL1 and WL2. The separation insulating patterns SIP can fill spaces between adjacent ones of the gate insulating patterns Gox and the channel patterns CP.

[0158] Channel patterns CP can be respectively disposed on the landing pads LP, and each of the channel patterns CP can include a horizontal portion HP in contact with the landing pad LP and a vertical portion VP extending perpendicularly from the horizontal portion HP and adjacent to an outer surface of the first or second word line WL1 or WL2.

[0159] In an embodiment, the channel patterns CP can be disposed in interlayer insulating patterns 151, 153, and 155 each formed to have a trench extending in the second direction D2. The interlayer insulating patterns 151, 153, and 155 can include a first insulating pattern 151, a second insulating pattern 153, and a third insulating pattern 155 sequentially stacked, and the second insulating pattern 153 can be formed of or include an insulating material selected to have an etching selectivity with respect to the first and third insulating patterns 151 and 155.

[0160] The channel patterns CP can be spaced apart from each other in the first and second directions D1 and D2, and a pair of the channel patterns CP adjacent to each other in the first direction D1 can be disposed to be mirror-symmetric about each other. The channel patterns CP adjacent to each other in the second direction D2 can be spaced apart from each other by the second insulating layer 153. Each of the channel patterns CP can have an ‘L’-shaped cross-section in the first direction D1, and can have a ‘U’-shaped cross-section in the second direction D2.

[0161] The channel pad PAD can collectively cover top surfaces of adjacent ones of the first and second word lines WL1 and WL2. The channel pad PAD can be formed of or include the same material as the channel pattern CP. That is, the channel pad PAD can be formed of or include at least one of silicon, germanium, silicon germanium, and an oxide semiconductor material. A top surface of the channel pad PAD can be located at substantially the same level as a top surface of the interlayer insulation pattern 155.

[0162] The gate insulation pattern Gox can conformingly cover bottom, outer side, and top surfaces of the first and second word lines WL1 and WL2. The gate insulation patterns Gox can be spaced apart from each other in the first direction D1 by the separation insulation pattern SIP.

[0163] The bit line BL can be disposed on the upper interlayer insulation layer 160 covering the channel pad PAD and can be electrically connected to the channel pad PAD through a bit line contact plug provided to penetrate the upper interlayer insulation layer 160. Each bit line contact plug can be commonly connected to a pair of channel patterns CP through the channel pad PAD.

[0164] Referring to ​ and ​ The plurality of memory cell array layers MCA1 and MCA2 can be stacked on the semiconductor substrate 100. As an example, the second memory cell array layer MCA2 can be disposed on the first memory cell array layer MCA1, in which case the bit line BL can be shared by the first and second memory cell array layers MCA1 and MCA2.

[0165] The first memory cell array layer MCA1 can include first data storage patterns DSP1 arranged two-dimensionally on the first plate conductive layer PL1, lower channel patterns CPa respectively disposed on the first data storage patterns DSP1, first and second lower word lines WL1a and WL2a provided on the first channel patterns CP1 and extending in the second direction D2, and the bit line BL provided on the first and second lower word lines WL1a and WL2a and extending in the first direction D1. In an embodiment, the first memory cell array layer MCA1 can have the same structure as the first memory cell array layer MCA1 described with reference to ​The described semiconductor memory device has substantially the same structure. In the first memory cell array layer MCA1, the lower channel patterns CPa can be spaced apart from each other in the first direction D1 and the second direction D2. Each of the lower channel patterns CPa can have an ‘L’-shaped cross section in the first direction D1 and can have a ‘U’-shaped cross section in the second direction D2. The lower channel pads PADa can be commonly disposed on top surfaces of the first lower word line WL1a and the second lower word line WL1b. The lower separation insulating patterns SIPa can be disposed between adjacent word lines among the first lower word line WL1a and the second lower word line WL1b.

[0166] The second memory cell array layer MCA2 can include second data storage patterns DSP2 arranged two-dimensionally on the second plate conductive layer PL2, upper channel patterns CPb respectively disposed on the second data storage patterns DSP2, first and second upper word lines WL1b and WL2b provided on the upper channel patterns CPb and extending in the second direction D2, and bit lines BL provided on the first and second upper word lines WL1b and WL2b and extending in the first direction D1. Upper separation insulating patterns SIPb can be disposed between adjacent word lines among the first and second upper word lines WL1b and WL2b.

[0167] The upper channel pads PADb can be respectively disposed on top surfaces of the first and second upper word lines WL1b and WL2b, and the upper channel pads PADb can be respectively electrically connected to the upper landing pads LP2.

[0168] The upper channel patterns CPb can include horizontal portions HP commonly covering bottom surfaces of the first and second upper word lines WL1b and WL2b adjacent to each other.

[0169] ​ is a plan view illustrating a method of manufacturing a semiconductor memory device according to an embodiment. ​ and ​ is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to an embodiment.

[0170] Referring to ​ , ​ and ​ , NMOS and PMOS transistors constituting the core and peripheral circuits SA can be formed on the semiconductor substrate 100. Further, a peripheral interconnection line and a peripheral contact plug electrically connected to the core and peripheral circuits SA can be formed on the semiconductor substrate 100.

[0171] A lower insulating layer 110 can be formed on the semiconductor substrate 100 to cover the core and peripheral circuits SA, the peripheral interconnection lines, and the peripheral contact plugs. The lower insulating layer 110 can include a plurality of stacked insulating layers. For example, the lower insulating layer 110 can include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a low-k dielectric layer.

[0172] Bit lines BL extending in the first direction D1 and spaced apart from each other in the second direction D2 can be formed on the lower insulating layer 110. An insulating material can be formed to fill spaces between the bit lines BL. The bit lines BL can be formed by depositing a conductive layer on the lower insulating layer 110 and patterning the conductive layer.

[0173] A first insulating pattern 115 extending in the second direction D2 can be formed on the bit lines BL to define trenches T spaced apart from each other in the first direction D1. The trenches T can be formed to cross the bit lines BL. The first insulating pattern 115 can be formed of or include at least one of, for example, a silicon oxide, a silicon nitride, a silicon oxynitride, and / or a low-k dielectric material.

[0174] Referring to ​ , ​ and ​ , preliminary channel patterns 121 can be formed in the trenches T, respectively. The preliminary channel patterns 121 can extend in the second direction D2.

[0175] The formation of the preliminary channel patterns 121 can include conformally depositing a channel layer on the lower insulating layer 110 on which the first insulating pattern 115 is formed, forming a sacrificial layer on the channel layer to fill the trenches T, and planarizing the sacrificial layer and the channel layer to expose top surfaces of the first insulating pattern 115. Accordingly, the preliminary channel patterns 121 and the sacrificial patterns 123 on the preliminary channel patterns 121 can be formed in each of the trenches T.

[0176] The channel layer can be formed using at least one of physical vapor deposition (PVD), thermal chemical vapor deposition (thermal CVD), low pressure chemical vapor deposition (LP-CVD), plasma enhanced chemical vapor deposition (PE-CVD), and atomic layer deposition (ALD) techniques. The channel layer can be formed to cover the bottom surface and the inner surface of the trench T with a substantially constant thickness. The thickness of the channel layer can be less than half the width of the trench. The channel layer can be deposited to have a thickness of several nanometers to several tens of nanometers (particularly 1 nm to 30 nm or more, particularly 1 nm to 10 nm). The channel layer can be formed of, or include, at least one of a semiconductor material, an oxide semiconductor material, and a two-dimensional semiconductor material. For example, the channel layer can be formed of, or include, at least one of silicon, germanium, silicon germanium, and indium gallium zinc oxide (IGZO).

[0177] The sacrificial pattern 123 can be formed of, or include, an insulating material having etching selectivity with respect to the first insulating pattern 115. As an example, the sacrificial pattern 123 can be formed of one of an insulating material and silicon oxide, which is formed using a spin-on-glass (SOG) technique.

[0178] Referring to ​ , ​ and ​ , the preliminary channel pattern 121 and the sacrificial pattern 123 can be patterned to form the channel pattern CP spaced apart from each other in the second direction D2 in each trench T.

[0179] The formation of the channel pattern CP can include forming a mask pattern MP on the preliminary channel pattern 121 and the sacrificial pattern 123 and then sequentially etching the sacrificial pattern 123 and the preliminary channel pattern 121 using the mask pattern MP as an etching mask to form the opening OP exposing the lower insulating layer 110.

[0180] For example, the opening OP can be a strip-shaped region elongated in the first direction D1 and can be spaced apart from each other in the first direction D1 and the second direction D2. When viewed in a top view, the opening OP can be spaced apart from the bit line BL. As another example, the opening OP can be a linear region parallel to the bit line BL or extending in the first direction D1 and can be formed to extend in a direction crossing the first insulating pattern 115.

[0181] In a case where the channel pattern CP is formed by the above-described method, each channel pattern CP can include a horizontal portion HP in contact with the bit line BL and a vertical portion VP covering both side surfaces of the trench.

[0182] After the formation of the channel pattern CP, an ashing process can be performed to remove the mask pattern MP, and the sacrificial pattern 123 can be removed using an etching recipe having etching selectivity with respect to the first insulating pattern 115 and the channel pattern CP.

[0183] Referring to ​ , ​ and ​ , the gate insulating layer 131 and the gate conductive layer 133 can be sequentially deposited to conformally cover the channel pattern CP. The gate insulating layer 131 and the gate conductive layer 133 can be formed using at least one of a physical vapor deposition (PVD), a thermal chemical vapor deposition (thermal CVD), a low pressure chemical vapor deposition (LP-CVD), a plasma enhanced chemical vapor deposition (PE-CVD), and an atomic layer deposition (ALD) technique.

[0184] The gate insulating layer 131 and the gate conductive layer 133 can cover the horizontal portions HP and the vertical portions VP of the channel pattern CP with a substantially constant thickness.

[0185] The sum of the thicknesses of the gate insulating layer 131 and the gate conductive layer 133 can be less than half of the width of the trench T. Accordingly, the gate conductive layer 133 can be formed on the gate insulating layer to define a gap region in the trench T.

[0186] In the regions between the channel patterns CP, the gate insulating layer 131 can be formed in direct contact with the side surfaces of the lower insulating layer 110 and the first insulating pattern 115.

[0187] Next, referring to ​ , ​ and ​ , an anisotropic etching process can be performed on the gate conductive layer 133 to form the first word line WL1 and the second word line WL2 spaced apart from each other in each trench T. The anisotropic etching process on the gate conductive layer 133 can be performed in a manner that the top surfaces of the first word line WL1 and the second word line WL2 are lower than the top surface of the channel pattern CP. Alternatively, an additional etching process can be further performed to recess the top surfaces of the first word line WL1 and the second word line WL2.

[0188] In certain embodiments, the gate insulating layer 131 can also be etched during the anisotropic etching process on the gate conductive layer 133, in which case the channel pattern CP can be exposed. Accordingly, a pair of gate insulating patterns Gox can be formed, as ​is shown. In certain embodiments, the gate insulation pattern Gox and the channel pattern CP can be sequentially etched to expose the lower insulation layer 110 during the anisotropic etching process of the gate conductive layer 133. Thus, a pair of first and second channel patterns CP1 and CP2 spaced apart from each other can be formed in each trench T, as shown. ​ is shown. Hereinafter, the gate insulation layer 131 on which the etching process has been performed will be referred to as a gate insulation pattern Gox.

[0189] Referring to ​ , ​ and ​ , after the formation of the first and second word lines WL1 and WL2, a second insulation pattern 141 can be formed to fill the trench T. The second insulation pattern 141 can be formed of, or include, at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k dielectric material.

[0190] The formation of the second insulation pattern 141 can include depositing an insulation layer to completely fill the trench T in which the first and second word lines WL1 and WL2 are formed and then performing a planarization process to expose the top surface of the channel pattern CP.

[0191] Thereafter, referring to ​ , ​ and ​ , an interlayer insulation layer can be formed on the first and second insulation patterns 115 and 141 and the channel pattern CP.

[0192] Next, landing pads LP respectively in contact with the vertical portions of the channel pattern CP can be formed in the interlayer insulation layer 150. The formation of the landing pads LP can be formed by patterning the interlayer insulation layer to form holes respectively exposing the vertical portions of the channel pattern CP and then filling the holes with a conductive material.

[0193] Next, data storage patterns DSP can be formed on the landing pads LP, respectively. For example, in the case where the data storage patterns DSP include capacitors, a bottom electrode, a capacitor dielectric layer, and a top electrode can be sequentially formed.

[0194] ​ is a top view of a semiconductor memory device according to an embodiment. ​ is a cross-sectional view taken along the line I-I' of ​ to illustrate a semiconductor memory device according to an embodiment.

[0195] Referring to ​ and ​The semiconductor substrate can include a first edge region ER1 and a second edge region ER2 and a cell array region CAR therebetween.

[0196] The first word line WL1 and the second word line WL2 can extend from the cell array region CAR to the first edge region ER1 and the second edge region ER2.

[0197] Each of the first word line WL1 and the second word line WL2 can include a line portion extending in the second direction D2 and a protruding portion extending in the first direction D1 and connected to the line portion. As an example, the protruding portion of the first word line WL1 can be provided in the first edge region ER1 and the protruding portion of the second word line WL2 can be provided in the second edge region ER2, as shown, for example, in ​

[0198] In the first edge region ER1, the first word line contact plug CT1 can be coupled to the first word line WL1 and in the second edge region ER2, the second word line contact plug CT2 can be coupled to the second word line WL2.

[0199] The first separation insulating pattern 155a and the second separation insulating pattern 155b can be provided in the first edge region ER1 and the second edge region ER2, respectively. The first separation insulating pattern 155a can be provided to vertically penetrate the first word line WL1 and the second word line WL2 in the first edge region ER1. The second separation insulating pattern 155b can be provided to vertically penetrate the first word line WL1 and the second word line WL2 in the second edge region ER2. In the first edge region ER1 and the second edge region ER2, the first word line WL1 and the second word line WL2 can be electrically separated from each other by the first separation insulating pattern 155a and the second separation insulating pattern 155b.

[0200] ​ is a plan view showing a method of manufacturing a semiconductor memory device according to an embodiment. ​ and ​ is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to an embodiment.

[0201] Referring to ​ , ​ and ​ , a first sacrificial pattern SP can be formed on the lower insulating layer 110, where bit lines BL extending in the first direction D1 are formed on the lower insulating layer 110, here, the first sacrificial pattern SP can extend in the second direction D2 to define trenches T spaced apart from each other in the first direction D1.

[0202] ​The first sacrificial pattern can be formed of or include an insulating material having etch selectivity with respect to the lower insulating layer 110. The first sacrificial pattern can be formed of or include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k dielectric material.

[0203] Referring to ​ , ​ and ​ , a channel pattern CP can be formed in each of the trenches T, spaced apart from each other. Here, as previously described with reference to ​ , ​ and ​ , the formation of the channel pattern CP can include forming a preliminary channel pattern 121 in the trench T, forming a second sacrificial pattern 123 to fill the trench T provided with the preliminary channel pattern 121, and forming an opening to penetrate the second sacrificial pattern 123, the first sacrificial pattern SP, and the preliminary channel pattern 121 and extend in the first direction D1.

[0204] Here, the second sacrificial pattern 123 can be formed of or include the same insulating material as the first sacrificial pattern SP. Further, the opening can be formed to have a bar shape, as previously described with reference to ​ , ​ and ​ .

[0205] Each of the channel patterns CP formed by the above-described method can include a horizontal portion HP in contact with the bit line BL and first and second vertical portions VP1 and VP2 extending perpendicularly from the horizontal portion HP to face each other, as previously described with reference to ​ , ​ and ​ .

[0206] After the formation of the channel pattern CP, an etching process can be performed to remove the first and second sacrificial patterns 116 and 123. Accordingly, the surface of the channel pattern CP can be exposed. For example, the inner and outer side surfaces of the channel pattern CP can be exposed.

[0207] Referring to ​ , ​ and ​ , the first word line WL1 can be formed to extend in the second direction D2 and surround the first vertical portion VP1 of the channel pattern CP, and the second word line WL2 can be formed to extend in the second direction D2 and surround the second vertical portion VP2 of the channel pattern CP.

[0208] The forming of the first word line WL1 and the second word line WL2 can include sequentially and conformally depositing a gate insulating layer and a gate conductive layer on the lower insulating layer 110 on which the channel pattern CP is formed, and then performing an anisotropic etching process on the gate conductive layer to expose the horizontal portion HP of the gate insulating layer or the channel pattern CP. The first word line WL1 can be formed to be adjacent to the outer side surface and the inner side surface of the first vertical portion of the channel pattern CP. The second word line WL2 can be formed to be adjacent to the outer side surface and the inner side surface of the second vertical portion of the channel pattern CP.

[0209] Thereafter, the insulating pattern 141 can be formed to fill the space between the first word line WL1 and the second word line WL2. The insulating pattern 141 can cover the top surfaces of the first word line WL1 and the second word line WL2. The forming of the insulating pattern 141 can include forming an insulating layer to cover the top surfaces of the first word line WL1 and the second word line WL2 and fill the space between the first word line WL1 and the second word line WL2, and then performing a planarization process to expose the top surface of the channel pattern CP.

[0210] Next, referring to ​ , ​ and ​ , an interlayer insulating layer 150 can be formed on the insulating pattern 141 and the channel pattern CP.

[0211] The landing pad LP can be formed to penetrate the interlayer insulating layer 150 and contact the vertical portion of the channel pattern CP, and then a data storage pattern DSP can be formed on the landing pad LP.

[0212] ​ is a top view of a semiconductor memory device according to an embodiment. ​ is a cross-sectional view taken along the line I-I' of ​ to illustrate a semiconductor memory device according to an embodiment.

[0213] Referring to ​ and ​ , the semiconductor substrate 100 can include first and second edge regions ER1 and ER2 and a cell array region CAR therebetween.

[0214] The first word line WL1 and the second word line WL2 can extend from the cell array region CAR to the first and second edge regions ER1 and ER2. Each of the first and second word lines WL1 and WL2 can fill the space between a corresponding pair of channel patterns CP adjacent to each other in the second direction D2.

[0215] In the second edge region ER2, the first word line contact plugs CT1 can be coupled to the first word lines WL1, respectively. In the first edge region ER1, the second word line contact plugs CT2 can be coupled to the second word lines WL2, respectively.

[0216] The distance between the first word line contact plugs CT1 can be greater than the distance between the first word lines WL1 when measured in the first direction D1. Similarly, the distance between the second word line contact plugs CT2 can be greater than the distance between the second word lines WL2 when measured in the first direction D1.

[0217] According to an embodiment, a vertical channel transistor having a mirror-symmetrical channel pattern can be implemented. In this case, the integration density of the semiconductor memory device can be increased.

[0218] The mirror-symmetrical channel pattern can be formed by a deposition method, and thus, technical problems such as voids or seams can be prevented. Accordingly, the electrical characteristics and reliability characteristics of the transistor can be improved. Since the channel pattern is formed using a deposition method, each channel pattern can be used to implement a pair of transistors, and thus, the size of a unit memory cell can be reduced.

[0219] Further, since an oxide semiconductor material is used for the channel pattern, the leakage current of the transistor can be reduced. Further, a peripheral circuit can overlap the cell array layer, and thus, the integration density of the semiconductor memory device can be further increased.

[0220] While example embodiments have been particularly shown and described, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope of the claims.

[0221] This application is based on Korean Patent Application No. 10-2020-0126251 filed on September 28, 2020, in the Korean Intellectual Property Office, and claims priority under 35 U.S.C. § 119 to the Korean Patent Application No. 10-2020-0126251, the disclosure of which is incorporated by reference herein in its entirety.

Claims

1. A semiconductor memory device, comprising: a bit line extending in a first direction; a plurality of channel patterns spaced apart from each other in the first direction on the bit line, each of the channel patterns including first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions; first and second word lines provided on the horizontal portion of each of the channel patterns and between the first and second vertical portions of each of the channel patterns, the first and second word lines extending in a second direction crossing the bit line; and a gate insulating pattern provided between the first word line and a corresponding one of the channel patterns and between the second word line and the corresponding one of the channel patterns.

2. The semiconductor memory device according to claim 1, wherein the channel patterns include an oxide semiconductor material. a portion of the horizontal portion is disposed between the first and second word lines.

3. The semiconductor memory device according to claim 1, wherein, 4. The semiconductor memory device according to claim 1, wherein top surfaces of the first and second word lines are located at a level lower than top surfaces of the first and second vertical portions.

5. The semiconductor memory device according to claim 1, wherein the gate insulating pattern includes: a first portion provided between the first vertical portion and an outer side surface of the first word line; a second portion provided between the second vertical portion and an outer side surface of the second word line; and a third portion provided between a bottom surface of the first word line and the horizontal portion and between a bottom surface of the second word line and the horizontal portion.

6. The semiconductor memory device according to claim 1, wherein the bit line has a first width in the second direction, and wherein the horizontal portion of each of the channel patterns has a second width in the second direction equal to or greater than the first width.

7. The semiconductor memory device according to claim 1, wherein the channel patterns have a first length in the first direction, and wherein each of the first and second word lines has a third width in the first direction smaller than half of the first length.

8. The semiconductor memory device according to claim 1, wherein the horizontal portion of each of the channel patterns has a first thickness at a position facing a bottom surface of the first word line and a bottom surface of the second word line, and wherein the first and second vertical portions of each of the channel patterns each have a second thickness equal to the first thickness at a position facing an outer side surface of the first word line and an outer side surface of the second word line.

9. The semiconductor memory device according to claim 1, further comprising: a first data storage pattern connected to the first vertical portion; and a second data storage pattern connected to the second vertical portion.

10. The semiconductor memory device according to claim 9, further comprising: a first landing pad disposed between the first vertical portion and the first data storage pattern; and a second landing pad disposed between the second vertical portion and the second data storage pattern. ​ ​ ​ a second landing pad disposed between the second vertical portion and the second data storage pattern.

11. The semiconductor storage device according to claim 1, further comprising: a semiconductor substrate including a first edge region, a second edge region, and a cell array region between the first edge region and the second edge region; a first word line contact plug coupled to the first word line in the first edge region; and a second word line contact plug coupled to the second word line in the second edge region.

12. The semiconductor storage device according to claim 11, further comprising: a first separation insulating pattern disposed between the first word line and the second word line in the first edge region; and a second separation insulating pattern disposed between the first word line and the second word line in the second edge region.

13. A semiconductor storage device, comprising: a peripheral circuit structure including a plurality of peripheral circuits on a semiconductor substrate and a lower insulating layer covering the plurality of peripheral circuits; a plurality of bit lines extending in a first direction on the peripheral circuit structure; a first insulating pattern defining a trench, the first insulating pattern crossing the plurality of bit lines and extending in a second direction; a plurality of channel patterns provided in the trench and spaced apart from each other in the second direction, each of the plurality of channel patterns including first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions; first and second word lines provided on the horizontal portion of each of the plurality of channel patterns, the first and second word lines extending in the second direction, the first word line being adjacent to the first vertical portion of each of the plurality of channel patterns, the second word line being adjacent to the second vertical portion of each of the plurality of channel patterns; a gate insulating pattern with respect to each of the plurality of channel patterns, extending in the second direction, disposed between the channel pattern and the first word line, and between the channel pattern and the second word line; a second insulating pattern covering the first and second word lines in the trench; a plurality of first data storage patterns disposed on respective first vertical portions of the plurality of channel patterns; and a plurality of second data storage patterns disposed on respective second vertical portions of the plurality of channel patterns.

14. The semiconductor storage device according to claim 13, wherein outer side surfaces of the first and second vertical portions of each of the plurality of channel patterns are in contact with the first insulating pattern.

15. The semiconductor storage device according to claim 13, wherein top surfaces of the first and second vertical portions of each of the plurality of channel patterns are located at the same level as top surfaces of the first and second insulating patterns.

16. The semiconductor storage device according to claim 13, wherein the gate insulating pattern includes: a first gate insulating pattern disposed between the first word line and the channel pattern; and a second gate insulating pattern disposed between the second word line and the channel pattern. ​ a first portion provided between an outer side surface of the first word line and the first vertical portion of each of the plurality of channel patterns; a second portion provided between an outer side surface of the second word line and the second vertical portion of each of the plurality of channel patterns; and a third portion provided between a bottom surface of the first word line and the horizontal portion and between a bottom surface of the second word line and the horizontal portion.

17. The semiconductor memory device according to claim 16, wherein the first and second portions of the gate insulating pattern are in contact with side surfaces of the first insulating pattern between each pair of channel patterns of the plurality of channel patterns adjacent to each other in the second direction.

18. A semiconductor memory device, comprising: a bit line extending in a first direction; a plurality of channel patterns spaced apart from each other in the first direction on the bit line, each of the channel patterns including first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions; a first word line extending in a second direction to cross the bit line, the first word line being disposed on the horizontal portion of each of the channel patterns and between the first and second vertical portions of each of the channel patterns; and a gate insulating pattern interposed between the first word line and a corresponding one of the channel patterns.

19. The semiconductor memory device according to claim 18, further comprising a data storage pattern commonly connected to the first and second vertical portions of each of the channel patterns.

20. The semiconductor memory device according to claim 18, wherein the first word line includes first and second side surfaces opposite to each other, wherein the first vertical portion of each of the channel patterns covers the first side surface of the first word line, and wherein the second vertical portion of each of the channel patterns covers the second side surface of the first word line. ​ ​

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