Semiconductor Structure and Its Preparation Method, Memory, Storage System, Electronic Device

Abstract

The present disclosure provides a semiconductor structure, a method for manufacturing the same, a memory, a storage system, and an electronic device, relating to the technical field of semiconductor chips, so as to reduce the mutual interference between storage units and improve device performance. The semiconductor structure includes a stacked layer, a channel structure, and a plurality of second dielectric layers. The stacked layer includes a plurality of first dielectric layers and a plurality of gate layers stacked alternately. The channel structure penetrates the stacked layer; the boundary of the first dielectric layer close to the channel structure is recessed inward compared with the boundary of the gate layer close to the channel structure. In a direction parallel to the plane where the stacked layer is located, the second dielectric layer is located between the first dielectric layer and the channel structure; in a direction perpendicular to the plane where the stacked layer is located, the second dielectric layer is located between two adjacent gate layers, and the dielectric constant of the second dielectric layer is less than the dielectric constant of the first dielectric layer. The above semiconductor structure is applied to a memory to implement read and write operations of data.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular, to a semiconductor structure, a method for manufacturing the same, a memory, a storage system, and an electronic device. Background Art

[0002] As the feature size of memory cells approaches the process limit, planar processes and manufacturing technologies become challenging and costly, resulting in the storage density of 2D or planar NAND flash memories approaching the upper limit.

[0003] To overcome the limitations posed by 2D or planar NAND flash memories, the industry has developed three-dimensional (3D) NAND memories, which improve storage density by arranging memory cells three-dimensionally on a substrate.

[0004] However, to increase storage density, the size of the memory is getting smaller and smaller. During the programming operation, the mutual interference between memory cells cannot be ignored, which affects the device performance. Summary of the Invention

[0005] Embodiments of the present disclosure provide a semiconductor structure, a method for manufacturing the same, a memory, a storage system, and an electronic device, so as to reduce the mutual interference between memory cells and improve device performance.

[0006] To achieve the above object, embodiments of the present disclosure adopt the following technical solutions:

[0007] On the one hand, a semiconductor structure is provided. The semiconductor structure includes a stacked layer, a channel structure, and a plurality of second dielectric layers. The stacked layer includes a plurality of first dielectric layers and a plurality of gate layers stacked alternately. The channel structure penetrates the stacked layer; the boundary of the first dielectric layer close to the channel structure is retracted compared with the boundary of the gate layer close to the channel structure. In a direction parallel to the plane where the stacked layer is located, the second dielectric layer is located between the first dielectric layer and the channel structure; in a direction perpendicular to the plane where the stacked layer is located, the second dielectric layer is located between two adjacent gate layers; the dielectric constant of the second dielectric layer is less than the dielectric constant of the first dielectric layer.

[0008] In the semiconductor structure provided by the above embodiments of the present disclosure, the first dielectric layer and the second dielectric layer can be made of different materials respectively. That is to say, both the first dielectric layer and the second dielectric layer can select suitable materials according to their respective design requirements, with relatively low costs. Exemplarily, the first dielectric layer can select a material with a large elastic modulus to support the stacked layer. Among them, the first dielectric layer does not need to consider whether the dielectric constant of the material is too high; in this way, there are more types of materials that can be selected for the first dielectric layer, and the cost is relatively low. The second dielectric layer can select a material with a relatively low dielectric constant to reduce the electric field coupling between the transistors in the same memory cell string, thereby improving the device performance. Among them, the second dielectric layer does not need to consider whether the elastic modulus of the material is too low; in this way, there are more types of materials that can be selected for the second dielectric layer, and the cost is relatively low.

[0009] In some embodiments, one side of the second dielectric layer is in contact with the first dielectric layer, and the other side is in contact with the channel structure.

[0010] In some embodiments, the dielectric constant of the second dielectric layer is less than or equal to 3.

[0011] In some embodiments, the material of the second dielectric layer includes any one of carbon-doped silicon oxide, carbon-doped silicon hydroxide, and fluorine-doped silicon oxide.

[0012] In some embodiments, the elastic modulus of the first dielectric layer is greater than the elastic modulus of the second dielectric layer.

[0013] In some embodiments, the elastic modulus of the first dielectric layer is 70 GPa to 100 GPa.

[0014] In some embodiments, the distance between the boundary of the second dielectric layer close to the first dielectric layer and the boundary of the second dielectric layer far from the first dielectric layer is 0.5 nm to 5 nm.

[0015] On the other hand, a method for manufacturing a semiconductor structure is provided, including: forming an initial stacked layer, where the initial stacked layer includes a plurality of sacrificial layers and a plurality of first dielectric layers arranged alternately. Forming a channel hole penetrating the initial stacked layer. Removing an edge portion of the first dielectric layer close to the channel hole through the channel hole, so that the boundary of the first dielectric layer close to the channel hole is retracted compared with the boundary of the sacrificial layer close to the channel hole to form a groove. Forming a second dielectric layer in the groove; the dielectric constant of the second dielectric layer is less than the dielectric constant of the first dielectric layer. Forming a channel structure in the channel hole; in a direction parallel to the plane where the initial stacked layer is located, the second dielectric layer is located between the first dielectric layer and the channel structure.

[0016] In some embodiments, forming the second dielectric layer in the groove includes: depositing a target material to form a second dielectric thin film; the dielectric constant of the target material being less than that of the material of the first dielectric layer. Removing the portions of the second dielectric thin film that cover the initial stack layer and the inner walls of the channel holes to form the second dielectric layer.

[0017] In some embodiments, after forming the channel structure, the manufacturing method further includes: forming a gate line gap that penetrates the initial stack layer. Removing the sacrificial layer through the gate line gap to form a sacrificial gap. Forming a gate layer in the sacrificial gap.

[0018] In some embodiments, between forming the initial stack layer and forming the channel holes, the manufacturing method further includes: forming a covering layer; the covering layer is disposed on the initial stack layer.

[0019] In some embodiments, during the process of forming the channel holes, the channel holes also penetrate the covering layer. During the process of removing the edge portion of the first dielectric layer near the channel holes, a part of the covering layer is also removed. After forming the second dielectric layer, the manufacturing method further includes: planarizing the side of the covering layer away from the initial stack layer.

[0020] In another aspect, a memory is provided. The memory includes the semiconductor structure according to some of the above embodiments, and peripheral devices, and the peripheral devices are electrically connected to the semiconductor structure.

[0021] In another aspect, a storage system is provided, including: the memory as described above, and a controller, and the controller is coupled to the memory to control the memory to store data.

[0022] In another aspect, an electronic device is provided, characterized in that it includes the storage system as described above.

[0023] It can be understood that for the manufacturing method, memory, storage system and electronic device of the semiconductor structure provided by the above embodiments of the present disclosure, the beneficial effects that can be achieved can refer to the beneficial effects of the semiconductor structure in the above text, and will not be elaborated here. Description of the Drawings

[0024] To more clearly illustrate the technical solutions in the present disclosure, the accompanying drawings required for some embodiments of the present disclosure will be briefly introduced below. Obviously, the accompanying drawings in the following description are only the accompanying drawings of some embodiments of the present disclosure. For those of ordinary skill in the art, other accompanying drawings can also be obtained based on these drawings. In addition, the accompanying drawings in the following description can be regarded as schematic diagrams and do not limit the actual dimensions of the products, the actual processes of the methods, the actual timings of the signals, etc. involved in the embodiments of the present disclosure.

[0025] Figure 1 Schematic three-dimensional structure diagram of a memory according to some embodiments;

[0026] Figure 2 Cross-sectional view of a memory according to some embodiments;

[0027] Figure 3 For Figure 1 Cross-sectional view of a memory cell string along the section line AA' in the shown memory;

[0028] Figure 4 Equivalent circuit diagram of the memory cell string;

[0029] Figures 5 to 14 Preparation step diagram of a method for manufacturing a semiconductor structure according to some embodiments;

[0030] Figure 15 Structural diagram of a semiconductor structure according to some embodiments;

[0031] Figures 16 to 19 Flowchart of a method for manufacturing a semiconductor structure according to some embodiments;

[0032] Figure 20 Block diagram of a memory system according to some embodiments;

[0033] Figure 21 Block diagram of a memory system according to some other embodiments. Detailed implementation manners

[0034] Next, the technical solutions in some embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present disclosure, rather than all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0035] In the description of the present disclosure, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present disclosure.

[0036] Unless otherwise required by the context, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, i.e., "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples", etc. are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0037] Hereinafter, the terms "first" and "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise specified, the meaning of "a plurality" is two or more.

[0038] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical contact or electrical contact with each other. Another example is that when describing some embodiments, the term "coupled" may be used to indicate that two or more components have direct physical contact or electrical contact. However, the term "coupled" may also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0039] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0040] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0041] As used herein, the use of "configured to" or "adapted to" means open and inclusive language that does not exclude devices that are adapted to or configured to perform additional tasks or steps.

[0042] Additionally, the use of "based on" means open and inclusive because a process, step, calculation, or other action "based on" one or more of the stated conditions or values can in practice be based on additional conditions or values beyond those stated.

[0043] As used herein, "about," "substantially," or "approximately" includes the stated value and an average within an acceptable deviation range of the particular value, where the acceptable deviation range is determined by one of ordinary skill in the art in view of the measurement being discussed and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system).

[0044] In the context of the present disclosure, the meanings of "on," "above," and "over" should be construed in the broadest sense such that "on" not only means "directly on something," but also includes "on something" with intervening features or layers therebetween, and "above" or "over" not only means "above" or "over" something, but also includes "above" or "over" something with no intervening features or layers therebetween (i.e., directly on something).

[0045] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary figures. In the figures, the thickness of layers and regions is exaggerated for clarity. Accordingly, variations in shape relative to the figures due to, for example, manufacturing techniques and / or tolerances are contemplated. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations resulting from, for example, manufacturing. For example, an etched region shown as rectangular will typically have curved features. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to depict the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0046] As used herein, the term "substrate" refers to a material upon which subsequent layers of material can be added. The substrate itself can be patterned. The material added to the substrate can be patterned or can remain unpatterned. Additionally, the substrate can include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or a sapphire wafer.

[0047] The term "3D memory" refers to a semiconductor device formed by an array of memory cell transistor strings (referred to herein as "memory cell strings", such as NAND memory cell strings) arranged on the main surface of a substrate or a source layer and extending in a direction perpendicular to the substrate or the source layer. As used herein, the term "vertical / perpendicularly" means nominally perpendicular to the main surface (i.e., the lateral surface) of the substrate or the source layer.

[0048] Figure 1 Schematic perspective view of a memory provided for some embodiments of the present disclosure, Figure 2 Cross-sectional view of the memory, Figure 3 is Figure 1 Cross-sectional view of a memory cell string in the memory along the section line AA', Figure 4 is Figure 3 Equivalent circuit diagram of the memory cell string in

[0049] See Figure 1 and Figure 2 For some embodiments of the present disclosure, a memory 10 is provided. The memory 10 may include a semiconductor structure 200. The memory 10 may further include a source layer SL coupled to the semiconductor structure 200, and a peripheral device 100 coupled to the semiconductor structure 200. The peripheral device 100 may be disposed on a side of the semiconductor structure 200 away from the source layer SL.

[0050] The material of the source layer SL may include semiconductor materials, such as single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Exemplarily, the source layer SL may include a doped region doped with a p-type dopant. The source layer SL may further include an undoped region.

[0051] The semiconductor structure 200 may include an array of memory cell transistor strings 400 (referred to herein as "memory cell strings", such as NAND memory cell strings). The source layer SL may be coupled to the source ends of a plurality of memory cell strings 400.

[0052] Specifically, see Figure 3 and Figure 4 The memory cell string 400 may include a plurality of transistors T, and one transistor T (such as Figure 4 T1-T6 in

[0053] It should be noted that Figures 1 to 4 the number of transistors in

[0053] is only illustrative. The memory cell strings of the memory provided by the embodiments of the present disclosure may also include other numbers of transistors, such as 4, 16, 32, 64.

[0054] Further, along the third direction Z, the lowermost gate line among the multiple gate lines G (for example, the gate line closest to the source layer SL among the multiple gate lines G) is configured as the source select gate SGS. The source select gate SGS is configured to control the on-state of the transistor T6, and thus control the on-state of the source channel in the memory cell string 400. The uppermost gate line among the multiple gate lines G (for example, the gate line farthest from the source layer SL among the multiple gate lines G) is configured as the drain select gate SGD. The drain select gate SGD is configured to control the on-state of the transistor T1, and thus control the on-state of the drain channel in the memory cell string 400. The gate lines located in the middle among the multiple gate lines G may be configured as multiple word lines WL, such as including word line WL0, word line WL1, word line WL2, and word line WL3. By writing different voltages on the word line WL, data writing, reading, and erasing of each memory cell (such as transistor T) in the memory cell string 400 can be completed.

[0055] It should be noted that the above-mentioned memory 10 extends in the X-Y plane. The first direction X and the second direction Y are, for example, two orthogonal directions in the plane where the semiconductor structure 200 is located (for example, the plane where the source layer SL is located): The first direction X is, for example, the extending direction of the word line WL, and the second direction Y is, for example, the extending direction of the bit line BL. The third direction Z is perpendicular to the plane where the semiconductor structure 200 is located, that is, perpendicular to the X-Y plane.

[0056] As used in the present disclosure, whether a component (such as a layer, a structure, or a device) is "on", "above", or "below" another component (such as a layer, a structure, or a device) of a semiconductor device (such as a memory) is determined in the third direction Z with respect to the substrate or the source layer of the semiconductor device when the substrate or the source layer is located in the lowest plane of the semiconductor device in the third direction Z. Throughout the present disclosure, the same concept is applied to describe the spatial relationship.

[0057] Continuing to refer to Figure 1 and Figure 2 , in some embodiments, the semiconductor structure 200 may further include an array interconnect layer 290. The array interconnect layer 290 may be coupled to the memory cell string 400. The array interconnect layer 290 may include the drain end (i.e., the bit line BL) of the memory cell string 400, and the drain end may be coupled to the semiconductor channels of the transistors T in each of at least one memory cell string 400.

[0058] The array interconnect layer 290 may include one or more first interlayer insulating layers 292, and may further include a plurality of contacts insulated from each other through these first interlayer insulating layers 292. The contacts include, for example, bit line contacts BL-CNT, which are coupled to the bit line BL; and drain end select gate contacts SGD-CNT, which are coupled to the drain end select gate SGD. The array interconnect layer 290 may further include one or more first interconnect conductor layers 291. The first interconnect conductor layer 291 may include a plurality of connection lines, such as the bit line BL, and word line connection lines WL-CL coupled to the word line WL. The materials of the first interconnect conductor layer 291 and the contacts may be conductive materials, such as one or a combination of tungsten, cobalt, copper, aluminum, and metal silicides, or other suitable materials. The material of the first interlayer insulating layer 292 is an insulating material, such as one or a combination of silicon oxide, silicon nitride, and high-k insulating materials, or other suitable materials.

[0059] The peripheral device 100 may include peripheral circuits. The peripheral circuits are configured to control and sense the array devices. The peripheral circuits may be any suitable digital, analog, and / or mixed-signal control and sensing circuits for supporting the operation (or work) of the array devices, including but not limited to page buffers, decoders (such as row decoders and column decoders), sense amplifiers, drivers (such as word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuits (such as transistors, diodes, resistors, or capacitors). The peripheral circuits may further include any other circuits compatible with advanced logic processes, including logic circuits (such as processors and programmable logic devices (PLD)) or memory circuits (such as static random access memories (SRAM)).

[0060] Specifically, in some embodiments, the peripheral device 100 may include a substrate 110, transistors 120 disposed on the substrate 110, and a peripheral interconnect layer 130 disposed on the substrate 110. The peripheral circuits may include the transistors 120.

[0061] Among them, the material of the substrate 110 may be single-crystalline silicon, or other suitable materials, such as silicon germanium, germanium, or silicon-on-insulator thin films.

[0062] The peripheral interconnect layer 130 is coupled to the transistor 120 to enable the transmission of electrical signals between the transistor 120 and the peripheral interconnect layer 130. The peripheral interconnect layer 130 may include one or more second interlayer insulating layers 131, and may also include one or more second interconnect conductor layers 132. Different second interconnect conductor layers 132 may be coupled through contacts. The materials of the second interconnect conductor layers 132 and the contacts may be conductive materials, such as one or more combinations of tungsten, cobalt, copper, aluminum, and metal silicides, or other suitable materials. The material of the second interlayer insulating layer 131 is an insulating material, such as one or more combinations of silicon oxide, silicon nitride, and high-k insulating materials, or other suitable materials.

[0063] The peripheral interconnect layer 130 may be coupled to the array interconnect layer 290, such that the semiconductor structure 200 and the peripheral device 100 can be coupled. Specifically, since the peripheral interconnect layer 130 is coupled to the array interconnect layer 290, the peripheral circuits in the peripheral device 100 can be coupled to the memory cell strings in the semiconductor structure 100 to enable the transmission of electrical signals between the peripheral circuits and the memory cell strings. In some possible implementation manners, a bonding interface 500 may be provided between the peripheral interconnect layer 130 and the array interconnect layer 290. Through the bonding interface 500, the peripheral interconnect layer 130 and the array interconnect layer 290 can be bonded and coupled to each other.

[0064] To increase the storage density, the size of the memory 10 is getting smaller and smaller, and the distance between the transistors T in the memory cell string 400 is also getting smaller and smaller. In this case, when programming the transistor T, due to the electric field coupling effect, the threshold voltages of the other transistors T adjacent to the transistor T being programmed in the same memory cell string 400 will increase, thereby affecting the device performance.

[0065] Based on this, in some embodiments, as Figure 15 shown, the above semiconductor structure 200 includes a stacked layer 210, a channel structure 220, and a plurality of second dielectric layers 230.

[0066] Combined with Figure 2 and Figure 15 , the stacked layer 210 may be disposed on the source layer SL, that is, the stacked layer 210 is located on one side of the source layer SL in the thickness direction (i.e., the third direction Z in Figure 2 ). The stacked layer 210 includes a plurality of first dielectric layers 211 and a plurality of gate layers 212, and the first dielectric layers 211 and the gate layers 212 are alternately stacked along the third direction Z (refer to Figure 1 ).

[0067] It should be noted that the material of the first dielectric layer 211 may include insulating materials, and the insulating materials include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxides (such as aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials.

[0068] Among them, the gate layer 212 may include a conductor layer 2121, and the material of the conductor layer 2121 may include conductive materials, such as at least one of tungsten, cobalt, copper, aluminum, doped silicon, and silicide.

[0069] In some embodiments, as Figure 15 shown, the gate layer 212 may further include a metal compound layer 2122. The metal compound layer 2122 is located between the conductor layer 2121, the channel structure 40, and the first dielectric layer 211. The metal compound layer 2122 is configured as an adhesion layer to improve the adhesion between the conductor layer 2121 and the first dielectric layer 211. Among them, the material of the metal compound layer 2122 includes at least one of titanium nitride, tantalum nitride, and tungsten carbide.

[0070] In some embodiments, as Figure 15 shown, the gate layer 212 may further include a high-k dielectric layer 2123. The high-k dielectric layer 2123 is located between the metal compound layer 2122, the channel structure 40, and the first dielectric layer 211 to reduce the risk of charge flow from the channel structure 40 to the conductor layer 2121. Among them, the dielectric constant value of the high-k dielectric layer 323 is greater than or equal to 7. Exemplarily, the material of the high-k dielectric layer 323 includes at least one of aluminum oxide, hafnium oxide, and tantalum oxide.

[0071] In some embodiments, the stacked layer 210 is in contact with the source layer SL. In other embodiments, other functional layers are further provided between the stacked layer 210 and the source layer SL. For example, a semiconductor layer 281 and a third dielectric layer 282 are further provided between the stacked layer 210 and the source layer SL. The semiconductor layer 281 is in contact with the stacked layer 210, and the third dielectric layer 282 is in contact with the source layer SL. Among them, the layer of the stacked layer 210 closest to the source layer SL may be the first dielectric layer 211.

[0072] It should be noted that the material of the semiconductor layer 281 includes semiconductor materials, such as single crystal silicon, polycrystalline silicon, single crystal germanium, III-V group compound semiconductor materials, II-VI group compound semiconductor materials, and other suitable semiconductor materials. The material of the third dielectric layer 282 includes insulating materials, and the insulating materials may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxides (such as aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials.

[0073] Embodiments of the present disclosure do not limit the number of layers of the stacked layer 210. For example, the number of layers of the stacked layer 210 can be 8, 64, 128, etc. It can be understood that the more layers the stacked layer 210 has, the higher the integration degree, and the more transistors T in the memory cell string 400 formed thereby.

[0074] As Figure 15 shown, the channel structure 220 penetrates the stacked layer 210. Wherein, when the stacked layer 210 can be disposed on the source layer SL, and a semiconductor layer 281 and a third dielectric layer 282 are further disposed between the stacked layer 210 and the source layer SL, the channel structure 220 also penetrates the semiconductor layer 281 and the third dielectric layer 282, so that the channel structure 220 can be coupled to the source layer SL.

[0075] In some embodiments, referring to Figure 15 , the channel structure 220 includes a storage functional layer 221 and a semiconductor channel layer 222. One side of the storage functional layer 221 is in contact with the first dielectric layer 211 and the side surface of the gate line layer 212, and the other side is in contact with the semiconductor channel layer 222; that is, the storage functional layer 221 is located between the semiconductor channel layer 222 and the first dielectric layer 211 and the gate line layer 212.

[0076] It should be noted that the material of the semiconductor channel layer 222 includes semiconductor materials, such as single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials.

[0077] Among them, the storage functional layer 221 includes a blocking layer 2211, a charge trapping layer 2212, and a tunneling layer 2213. The materials of the blocking layer 2211, the charge trapping layer 2212, the tunneling layer 2213, and the semiconductor channel layer 222 can be silicon oxide, silicon nitride, silicon oxide, and polycrystalline silicon, respectively, to form a "SONO" structure.

[0078] In some embodiments, as Figure 15 shown, the channel structure 220 further includes a channel filling layer 223. The channel filling layer 223 is disposed on the side of the semiconductor channel layer 222 away from the storage functional layer 221 to provide a mechanical support function. It should be noted that the material of the channel filling layer 223 includes insulating materials, and the insulating materials can include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicate glass, dielectric metal oxides (such as aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials.

[0079] Among them, the first dielectric layer 211 is close to the edge of the channel structure 220 and is recessed compared to the edge of the gate layer 212 close to the channel structure 220. Along the direction parallel to the plane where the stacked layer 210 is located (i.e., Figure 1 the plane determined by X-Y in Figure 1 ), the second dielectric layer 230 is located between the first dielectric layer 211 and the channel structure 220. Along the direction perpendicular to the plane where the stacked layer 210 is located (i.e.,

[0080] the Z direction in

[0081] ), the second dielectric layer 230 is located between two adjacent gate 212 layers. The dielectric constant of the second dielectric layer 230 is less than that of the first dielectric layer 211.

[0082] Based on this, the first dielectric layer 211 and the second dielectric layer 230 can be made of different materials respectively. That is to say, both the first dielectric layer 211 and the second dielectric layer 230 can select suitable materials according to their respective design requirements, and the cost is relatively low.

[0083] Exemplarily, the first dielectric layer 211 can select a material with a large elastic modulus to play a role in supporting the stacked layer 210. Among them, the first dielectric layer 211 does not need to consider whether the dielectric constant of the material is too high; in this way, there are more types of materials that the first dielectric layer 211 can choose, and the cost is relatively low. The second dielectric layer 230 can select a material with a lower dielectric constant to play a role in reducing the electric field coupling between the transistors T in the same memory cell string 400, thereby improving the device performance. Among them, the second dielectric layer 230 does not need to consider whether the elastic modulus of the material is too low; in this way, there are more types of materials that the second dielectric layer 230 can choose, and the cost is relatively low.

[0084] In some embodiments, such as Figure 15As shown, one side of the second dielectric layer 230 is in contact with the first dielectric layer 211, and the other side is in contact with the channel structure 220. That is to say, the second dielectric layer 230 fills the gap between the first dielectric layer 211 and the channel structure 22, avoiding the problem of short circuit between the gate layers 212 of different layers during the preparation of the semiconductor structure 200, especially during the replacement of the gate layer 212.

[0085] In some embodiments, as Figure 15 shown, the boundary of the second dielectric layer 230 away from the first dielectric layer 211 is flush with the boundary of the gate layer 212 close to the channel structure 220, so that a second dielectric layer 230 with a lower dielectric constant is provided between the edge portions of different gate layers 212 close to the channel structure 220, reducing the effect of electric field coupling between the transistors T in the same memory cell string 400 as much as possible and improving the device performance.

[0086] Among them, the distance between the boundary of the second dielectric layer 230 close to the first dielectric layer 211 and the boundary of the second dielectric layer 230 away from the first dielectric layer 211 is 0.5 nm to 5 nm, that is, along Figure 15 the X direction in, the length range of the second dielectric layer 230 is 0.5 nm to 5 nm; this can avoid the risk of the stack layer 210 toppling due to the too large size of the second dielectric layer 230; and, avoid the electric field coupling between the transistors T in the same memory cell string 400 not being reduced to the preset requirements due to the too small size of the second dielectric layer 230. Exemplarily, the distance between the boundary of the second dielectric layer 230 close to the first dielectric layer 211 and the boundary of the second dielectric layer 230 away from the first dielectric layer 211 is any one of 0.5 nm, 1 nm, 2 nm, 3 nm, 4 nm and 5 nm.

[0087] In some embodiments, referring to Figure 15 , the semiconductor structure 200 may further include a gate line isolation structure 240, and the gate line isolation structure 240 penetrates the stack layer 210. Among them, the gate line isolation structure 240 includes an insulating isolation portion 241, and the insulating isolation portion 241 is in contact with the side surfaces of the first dielectric layer 211 and the gate line layer 212.

[0088] In some embodiments, as Figure 15 shown, the gate line isolation structure 240 may further include a gate line filling layer 242. The insulating isolation portion 241 is in contact with the side surfaces of the first dielectric layer 211 and the gate line layer 212, and there is a cavity inside the insulating isolation portion 241, and the gate line filling layer 242 fills the cavity to provide a mechanical support function. It should be noted that the material of the gate line filling layer 242 may be a conductive material or an insulating material, and the present disclosure does not make a specific limitation here.

[0089] In some embodiments, asFigure 15 As shown, the semiconductor structure 200 may further include a dummy channel structure 250.

[0090] Among them, the dummy channel structure 250 penetrates the stacked layer 210, and the dummy channel structure 250 is configured to provide mechanical support for the semiconductor structure 200. It should be noted that the dummy channel structure 250 may include an insulating material, such as one or a combination of silicon oxide, silicon nitride, and high-k insulating materials, or other suitable materials. The dummy channel structure 250 may include one or more air gaps 251, and the air gaps 251 can reduce the structural stress.

[0091] In some embodiments, referring to Figure 15 , the semiconductor structure 200 may further include a capping layer 260. The capping layer 260 may cover the stacked layer 210 to protect the semiconductor structure 200. Among them, the material of the capping layer 260 may include an insulating material, and the insulating material may include at least one of silicon oxide, silicon nitride, and high-k insulating materials, which is not limited in the present disclosure.

[0092] It should be noted that the surface of the capping layer 260 away from the stacked layer 210 needs to be processed by a chemical mechanical polishing process to make the surface of the capping layer 260 away from the stacked layer 210 flat comprehensively.

[0093] Embodiments of the present disclosure also provide a method for manufacturing a semiconductor structure 200. As Figure 16 shown, the manufacturing method includes steps S100 to S500.

[0094] S100: As Figure 5 shown, form an initial stacked layer 210'.

[0095] In the above steps, the initial stacked layer 210' includes a plurality of first dielectric layers 211 and a plurality of sacrificial layers 212' arranged alternately. Among them, any one of thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD) can be used to form the initial stacked layer 210' on the substrate 300.

[0096] It should be noted that the material of the first dielectric layer 211 can refer to the above text and will not be elaborated here. The material of the sacrificial layer 212' includes at least one of polysilicon, silicon nitride, and polycrystalline germanium, and the present disclosure is not limited thereto. Here, the material of the first dielectric layer 211 is different from that of the sacrificial layer 212' so that the first dielectric layer 211 and the sacrificial layer 212' have different etching selectivity ratios for the same etchant. Exemplarily, the material of the first dielectric layer 211 is silicon dioxide, and the material of the sacrificial layer 212' is silicon nitride.

[0097] Among them, the substrate 300 can be used to support the initial stacked layer 210' thereon and can be removed in subsequent processes. For details, refer to the following text. The material of the substrate 300 includes at least one of single crystal silicon (Si), polysilicon, single crystal germanium (Ge), III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0098] In some embodiments, as Figure 5 shown, the substrate 300 can be a composite substrate. Exemplarily, the substrate 300 can include a substrate 310, and a sacrificial silicon oxide layer 320 and a sacrificial polysilicon layer 330 are sequentially formed on the substrate 310. Among them, the material of the substrate 310 can include at least one of single crystal silicon (Si), polysilicon, single crystal germanium (Ge), III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art; the material of the sacrificial silicon oxide layer 320 can include silicon oxide; the material of the sacrificial polysilicon layer 330 can include polysilicon.

[0099] S200: As Figure 6 shown, a channel hole CH is formed through the initial stacked layer 210'.

[0100] In the above steps, the channel hole CH passing through the initial stacked structure 210' can be formed by a dry / wet etching process. Exemplarily, an anisotropic etching (any one of dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation, etc.) process is used to form the channel hole CH. Among them, the channel hole CH extends into the substrate 300. For example, when the substrate 300 is a composite substrate, the channel hole CH extends into the sacrificial polysilicon layer 330.

[0101] S300: As Figure 7 shown, the edge portion of the first dielectric layer 211 close to the channel hole CH is removed via the channel hole CH.

[0102] In the above steps, the trench hole CH is used as an etchant channel to etch the end of the first dielectric layer 211 exposed at the trench hole CH, and the etchant is used to etch the first dielectric layer 211. Among them, the boundary of the first dielectric layer 211 close to the trench hole CH is retracted compared with the boundary of the sacrificial layer 212' close to the trench hole CH to form a groove.

[0103] It should be noted that the above etching can be wet etching or vapor etching. An etching solution is used as the etchant in wet etching; an etching gas is used as the etchant in vapor etching.

[0104] S400: As Figure 8 and Figure 9 shown, a second dielectric layer 230 is formed in the groove.

[0105] In the above steps, the dielectric constant of the second dielectric layer 230 is less than that of the first dielectric layer 211. Among them, the second dielectric layer 230 can use the trench hole CH as a deposition channel, and a second dielectric layer 230 is formed in the groove by any one of the thin film deposition processes of CVD, PVD, and ALD. Specifically, reference can be made to S410 - S420, and the present disclosure will not elaborate here.

[0106] It should be noted that the material of the second dielectric layer 230 can refer to the above, and will not be elaborated here.

[0107] S500: As Figure 9 and Figure 10 shown, a channel structure 220 is formed in the trench hole CH.

[0108] In the above steps, any one of the thin film deposition processes of CVD, PVD, and ALD can be used to sequentially deposit a blocking layer 2211, a charge trapping layer 2212, a tunneling layer 2213, and a semiconductor channel layer 222 along the inner wall of the trench hole CH to form the channel structure 220. Among them, the blocking layer 2211, the charge trapping layer 2212, and the tunneling layer 2213 can be referred to as the storage functional layer 221.

[0109] Among them, along the direction parallel to the plane where the initial stacked layer 210' is located (i.e., Figure 1 the plane determined by X - Y in

[0110] ), the second dielectric layer 230 is located between the first dielectric layer 211 and the channel structure 220.

[0111] In some embodiments, after the storage functional layer 221 and the semiconductor channel layer 222 are sequentially formed in the channel hole CH, a channel filling layer 223 may also be formed in the channel hole CH. For example, any one of the thin film deposition processes such as CVD, PVD, and ALD may be used to fill the channel hole CH formed with the storage functional layer 221 and the semiconductor channel layer 222 with an insulating material such as silicon oxide to form a channel structure 220 having the storage functional layer 221, the semiconductor channel layer 222, and the channel filling layer 223.

[0112] In some embodiments, as Figure 17 shown, the above S400 includes S410 to S420.

[0113] S410: As Figure 8 shown, deposit a target material to form a second dielectric film 230'.

[0114] In the above steps, the dielectric constant of the target material is less than the dielectric constant of the material of the first dielectric layer 211. Specifically, any one of the thin film deposition processes such as CVD, PVD, and ALD may be used to deposit the target material. Among them, when depositing the target material, the target material is also formed on the upper side of the initial stack layer 210' and the inner wall of the channel hole CH.

[0115] It should be noted that the target material is the material of the second dielectric layer 230. For details, reference may be made to the above text and will not be elaborated here.

[0116] S420: As Figure 8 and Figure 9 shown, remove the portions of the second dielectric film 230' that cover the initial stack layer 210' and the inner wall of the channel hole CH to form a second dielectric layer 230.

[0117] In the above steps, the initial stack layer 210' covered with the second dielectric film 230' may be etched with an etchant for etching the target material.

[0118] Among them, during the process of etching the portions of the second dielectric film 230' that cover the initial stack layer 210' and the inner wall of the channel hole CH, the etching time can be controlled so that after the portions of the second dielectric film 230' that cover the initial stack layer 210' and the inner wall of the channel hole CH are removed, the etching stops, so that the boundary of the second dielectric layer 230 away from the first dielectric layer 211 is flush with the boundary of the sacrificial layer 212' near the channel hole CH.

[0119] In some embodiments, as Figure 18 shown, after S500, the above preparation method further includes S600 to S800.

[0120] S600: As shown in Figure 11 , a gate line gap GLS is formed through the initial stack layer 210'.

[0121] In the above steps, the gate line gap GLS through the initial stack layer 210' can be formed by a dry / wet etching process. Exemplarily, an anisotropic etching (any one of dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation, etc.) process is used to form the gate line gap GLS. Among them, the gate line gap GLS extends into the substrate 300. For example, the substrate 300 is a composite substrate, and the gate line gap GLS extends into the sacrificial polysilicon layer 330.

[0122] It should be noted that the channel hole CH formed through the initial stack layer 210' in the above S200 and the gate line gap GLS formed through the initial stack layer 210' in the above S600 are performed in different processes to prevent the second dielectric film 230' from being formed in the gate line gap GLS; for example, the channel hole CH is formed by one etching process, and the gate line gap GLS is formed by another etching process. The present disclosure does not limit the sequence of the above two steps.

[0123] S700: As shown in Figure 11 and Figure 12 , the sacrificial layer 212' is removed via the gate line gap GLS to form a sacrificial gap.

[0124] In the above steps, the gate line gap GLS is used as an etchant channel, and an isotropic etching is used to remove the sacrificial layer 212' to form a sacrificial gap. The isotropic etching can use a selective wet etching or a gas-phase etching. An etching solution is used as the etchant in the wet etching; an etching gas is used as the etchant in the gas-phase etching.

[0125] It should be noted that when the material of the first dielectric layer 211 is silicon oxide and the material of the sacrificial layer 212' is silicon nitride, phosphoric acid solution can be used as the etchant in the wet etching; at least one of C4F8, C4F6, and CH2F2 can be used as the etching gas in the gas-phase etching.

[0126] S800: As shown in Figure 12 and Figure 13 , a gate electrode layer 212 is formed in the sacrificial gap.

[0127] In the above steps, the gate line gap GLS can be used as a deposition channel, and a gate electrode layer 212 can be formed in the sacrificial gap by any one of the thin film deposition processes such as CVD, PVD, and ALD.

[0128] It should be noted that the structure and materials of the gate layer 212 can be referred to the above, and the present disclosure will not elaborate herein. In addition, after forming the gate layer 212, as Figure 13 and Figure 14 shown, a gate line isolation structure 240 can be formed within the gate line gap GLS. The gate line isolation structure 240 can be referred to the above, and the present disclosure will not elaborate herein.

[0129] Based on the above, as Figure 13 shown, a stacked layer 210 can be formed. The stacked layer 210 includes alternately stacked first dielectric layers 211 and gate layers 212.

[0130] In some embodiments, as Figure 19 shown, between S100 and S200, the above preparation method further includes S110.

[0131] S110: Refer to Figure 5 , and form a cover layer 260.

[0132] In the above steps, any one of the thin film deposition processes of CVD, PVD, and ALD can be used to form the cover layer 260 on the initial stacked layer 210'. That is, the cover layer 260 is disposed on the initial stacked layer 210'. Among them, the materials of the cover layer 260 can be referred to the above, and the present disclosure will not elaborate herein.

[0133] In this case, during the process of forming the channel hole CH in S200, the channel hole CH also penetrates through the cover layer 260. Similarly, during the process of forming the gate line gap GLS in S600, the gate line gap GLS also penetrates through the cover layer 260. At this time, when the material of the cover layer 260 is the same as that of the first dielectric layer 211, during the process of removing the edge portion of the first dielectric layer 211 close to the channel hole CH in S300, a part of the cover layer 260 is also removed. For example, the edge portion of the cover layer 260 close to the channel hole CH is removed, and a part of the cover layer 260 far from the initial stacked layer 210' is removed.

[0134] On this basis, after S400, as Figure 19 shown, the above preparation method further includes S120.

[0135] S120: Refer to Figure 9 , and perform a planarization process on the side of the cover layer 260 far from the initial stacked layer 210'.

[0136] In the above steps, a chemical mechanical polishing process can be used to process the surface of the cover layer 260 far from the initial stacked layer 210' to make the surface of the cover layer 260 far from the initial stacked layer 210' comprehensively planar.

[0137] In some embodiments, after S120, the above preparation method further includes S900.

[0138] S900: Remove the substrate 300.

[0139] In the above steps, the substrate 300 can be removed by Chemical Mechanical Planarization (CMP for short), dry / wet etching process.

[0140] Exemplarily, the substrate 300 is a composite substrate, and the wet etching process can be used to sequentially remove the substrate 310, the sacrificial silicon oxide layer 320, and the sacrificial polysilicon layer 330 to expose the part of the channel structure 220 extending into the sacrificial polysilicon layer 330.

[0141] Figure 20 It is a block diagram of a storage system according to some embodiments. Figure 21 It is a block diagram of a storage system according to other embodiments.

[0142] Please refer to Figure 20 and Figure 21 Some embodiments of the present disclosure also provide a storage system 1000. The storage system 1000 includes a controller 20 and a memory 10 as in some of the above embodiments. The controller 20 is coupled to the memory 10 to control the memory 10 to store data.

[0143] Among them, the storage system 1000 can be integrated into various types of storage devices. For example, it is included in the same package (for example, Universal Flash Storage (UFS) package or Embedded Multi Media Card (eMMC) package). That is to say, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones (such as cell phones), desktop computers, tablet computers, laptop computers, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, Virtual Reality (VR) devices, Augmented Reality (AR) devices or any other suitable electronic devices with a memory.

[0144] In some embodiments, referring to Figure 20 , the storage system 1000 includes a controller 20 and a memory 10, and the storage system 1000 can be integrated into a memory card.

[0145] Among them, the memory card includes any one of a PC card (PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD) card, and a Universal Flash Storage (UFS).

[0146] In some other embodiments, referring to Figure 21 , the storage system 1000 includes a controller 20 and a plurality of memories 10, and the storage system 1000 is integrated into a Solid State Drive (SSD).

[0147] In the storage system 1000, in some embodiments, the controller 20 is configured to operate in a low-duty-cycle environment, for example, an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0148] In some other embodiments, the controller 20 is configured to operate in a high-duty-cycle environment of an SSD or an eMMC, and the SSD or eMMC is used as a data storage for mobile devices such as smart phones, tablets, laptops, etc. and enterprise storage arrays.

[0149] In some embodiments, the controller 20 may be configured to manage the data stored in the memory 10 and communicate with external devices (such as a host). In some embodiments, the controller 20 may also be configured to control the operations of the memory 10, such as read, erase, and program operations. In some embodiments, the controller 20 may also be configured to manage various functions regarding the data stored in or to be stored in the memory 10, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, the controller 20 is also configured to process the error correction code for the data read from or written to the memory 10.

[0150] Of course, the controller 20 may also perform any other suitable functions, such as formatting the memory 10; for example, the controller 20 may communicate with external devices (such as a host) through at least one of various interface protocols.

[0151] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and Firewire protocol.

[0152] Some embodiments of the present disclosure also provide an electronic device. The electronic device can be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0153] The electronic device may include the storage system 1000 described above, and may also include at least one of a Central Processing Unit (CPU) and a cache.

[0154] The above are only the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A stacked layer including a plurality of first dielectric layers and a plurality of gate layers stacked alternately; A channel structure penetrating the stacked layer; The boundary of the first dielectric layer close to the channel structure is retracted compared with the boundary of the gate layer close to the channel structure; A plurality of second dielectric layers, in a direction parallel to the plane where the stacked layer is located, the second dielectric layers are located between the first dielectric layer and the channel structure; in a direction perpendicular to the plane where the stacked layer is located, the second dielectric layers are located between two adjacent gate layers, and the dielectric constant of the second dielectric layer is less than that of the first dielectric layer.

2. The semiconductor structure according to claim 1, characterized in that, One side of the second dielectric layer contacts the first dielectric layer, and the other side contacts the channel structure.

3. The semiconductor structure according to claim 1, wherein The dielectric constant of the second dielectric layer is less than or equal to 3.

4. The semiconductor structure according to claim 3, wherein, The material of the second dielectric layer includes any one of carbon-doped silicon oxide, carbon-doped silicon hydroxide, and fluorine-doped silicon oxide.

5. The semiconductor structure according to claim 1, wherein The elastic modulus of the first dielectric layer is greater than that of the second dielectric layer.

6. The semiconductor structure according to claim 5, wherein The elastic modulus of the first dielectric layer is 70 GPa to 100 GPa.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that, The distance between the boundary of the second dielectric layer close to the first dielectric layer and the boundary of the second dielectric layer far from the first dielectric layer is 0.5 nm to 5 nm.

8. A method for preparing a semiconductor structure, characterized in that, Comprising: Forming an initial stacked layer; The initial stacked layer includes a plurality of sacrificial layers and a plurality of first dielectric layers arranged alternately; Forming a channel hole penetrating the initial stacked layer; Removing the edge portion of the first dielectric layer close to the channel hole through the channel hole, so that the boundary of the first dielectric layer close to the channel hole is retracted compared with the boundary of the sacrificial layer close to the channel hole to form a groove; Forming a second dielectric layer in the groove; the dielectric constant of the second dielectric layer is less than that of the first dielectric layer; Forming a channel structure in the channel hole; in a direction parallel to the plane where the initial stacked layer is located, the second dielectric layer is located between the first dielectric layer and the channel structure.

9. The preparation method according to claim 8, characterized in that, The forming of the second dielectric layer in the groove includes: Depositing a target material to form a second dielectric film; the dielectric constant of the target material is less than that of the material of the first dielectric layer; Removing the portion of the second dielectric film covering the initial stacked layer and the portion covering the inner wall of the channel hole to form the second dielectric layer.

10. The preparation method according to claim 8, wherein After forming the channel structure, it further includes: Forming a gate line gap penetrating the initial stacked layer; Removing the sacrificial layer through the gate line gap to form a sacrificial gap; Forming a gate layer in the sacrificial gap.

11. The preparation method according to any one of claims 8 to 10, characterized in that, Before forming the initial stacked layer and forming the channel hole, it further includes: Forming a covering layer covering the initial stacked layer.

12. The preparation method according to claim 11, wherein, During the process of forming the channel hole, the channel hole also penetrates the covering layer; during the process of removing the edge portion of the first dielectric layer close to the channel hole, a part of the covering layer is also removed; After forming the second dielectric layer, the preparation method further includes: Performing a planarization process on the side of the covering layer far from the initial stacked layer.

13. A memory, characterized in that, Comprising: A semiconductor structure, which is the semiconductor structure according to any one of claims 1 to 7; Peripheral devices, electrically connected to the semiconductor structure.

14. A storage system, characterized in that, Comprising: A memory, which is the memory according to claim 13; A controller, coupled to the memory to control the memory to store data.

15. An electronic device, characterized in that, Including the storage system according to claim 14.

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