Semiconductor device

Abstract

A semiconductor device that further reduces the recovery loss during the FWD operation. A transistor and a diode are formed on a common semiconductor substrate. The semiconductor substrate has a transistor region and an outer peripheral region surrounding them. The transistor region is divided by a plurality of strip-shaped gate electrodes into a plurality of channel regions where channels are formed and a plurality of non-channel regions where channels are not formed. The plurality of non-channel regions have a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fifth semiconductor layer, a first electrode, and a second electrode. The third semiconductor layer and the fifth semiconductor layer are electrically connected to the second electrode via contact holes. The fifth semiconductor layer is selectively provided so as not to contact an impurity layer of a first conductivity type, and the impurity layer of the first conductivity type is provided in the outer peripheral region to define a boundary with the cell region.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device with reduced recovery loss. Background Art

[0002] Generally, power devices are required to have capabilities such as withstand voltage retention and a guaranteed safe operating area to prevent device breakdown during operation. Among these requirements, one is low loss. In terms of low loss of power devices, it has effects such as miniaturization and weight reduction of the device, and generally has the effect of protecting the global environment due to reduced energy consumption. Moreover, it is required to achieve power devices that can obtain these effects at the lowest possible cost.

[0003] As a means to meet the above requirements, for example, as disclosed in Non-Patent Document 1, a reverse-conducting IGBT (RC-IGBT: Reverse-Conducting IGBT) has been proposed, which achieves the characteristics of an IGBT (Insulated Gate Bipolar Transistor) and a free-wheeling diode (FWD) through one structure.

[0004] Regarding this RC-IGBT, there are several technical problems, one of which is a large recovery loss during diode operation. In an RC-IGBT, during FWD operation, the pn junction formed by the anode portion (p-type anode) of the diode portion and the p + -type contact layer and the n - -type drift layer becomes forward-biased, and holes flow into the n - -type drift layer, causing conductivity modulation, thereby reducing the forward voltage drop. Conversely, when the p-type impurity concentration in the anode region is high, if there are a large number of excess carriers, there is a problem that it is difficult to discharge the carriers inside the device, and the recovery loss increases.

[0005] Several structures that solve these problems are disclosed in Patent Document 1. In Patent Document 1, the IGBT region has a trench gate and is divided into a channel region where a channel is formed and a non-channel region where a channel is not formed. The non-channel region is alternately formed by a p-type base region and a p + -type contact layer of the IGBT portion.

[0006] In this way, by reducing the average concentration of p-type impurities in the non-channel region, the recovery loss during FWD operation is reduced.

[0007] Patent Document 1: Japanese Patent Application Laid-Open No. 2017-157673

[0008] Non-Patent Document 1: Proceedings of International symposium on PowerSemiconductor devices 2004 pp.133-136

[0009] In the technology disclosed in Patent Document 1, no countermeasure was taken against the inflow of holes from the peripheral region, and the improvement of the recovery loss was insufficient. Summary of the Invention

[0010] The present invention is proposed to solve the above problems, and its object is to provide a semiconductor device with further reduced recovery loss during FWD operation.

[0011] The semiconductor device according to the present invention is a semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate. The semiconductor substrate includes: a transistor region in which the transistor is formed; a diode region in which the diode is formed; and a peripheral region that surrounds a cell region including the transistor region and the diode region. The transistor region is divided by a plurality of strip-shaped gate electrodes into a plurality of channel regions where channels are formed and a plurality of non-channel regions where the channels are not formed. The plurality of channel regions include: a first semiconductor layer of a first conductivity type provided on the second main surface side of the semiconductor substrate; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer; a third semiconductor layer of the first conductivity type provided closer to the first main surface of the semiconductor substrate than the second semiconductor layer; a fourth semiconductor layer of the second conductivity type selectively provided in an upper portion of the third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively provided in such a manner that side surfaces thereof are in contact with side surfaces of the fourth semiconductor layer; a first electrode electrically connected to the first semiconductor layer; and a second electrode electrically connected to the fourth semiconductor layer and the fifth semiconductor layer. At least one of the plurality of non-channel regions includes: the first semiconductor layer; the second semiconductor layer; the third semiconductor layer; the fifth semiconductor layer; the first electrode; and the second electrode. The third semiconductor layer and the fifth semiconductor layer of the at least one non-channel region are electrically connected to the second electrode via a contact hole. The fifth semiconductor layer of the at least one non-channel region is a first non-channel region selectively provided in an upper portion of the third semiconductor layer in such a manner as not to contact an impurity layer of the first conductivity type that is provided in the peripheral region and defines a boundary with the cell region.

[0012] Effects of the Invention

[0013] In the semiconductor device according to the present invention, the third semiconductor layer and the fifth semiconductor layer of at least one non-channel region are electrically connected to the second electrode via a contact hole, and the fifth semiconductor layer of at least one non-channel region is selectively provided on the upper portion of the third semiconductor layer so as not to contact the impurity layer of the first conductivity type, wherein the impurity layer of the first conductivity type is provided in the peripheral region and defines the boundary with the cell region, thereby further reducing the recovery loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 FIG. is a top view of the entire chip of the RC-IGBT according to Embodiment 1.

[0015] Figure 2 FIG. is a partial top view of the RC-IGBT according to Embodiment 1.

[0016] Figure 3 FIG. is a partial cross-sectional view of the RC-IGBT according to Embodiment 1.

[0017] Figure 4 FIG. is a partial cross-sectional view of the RC-IGBT according to Embodiment 1.

[0018] Figure 5 FIG. is a partial cross-sectional view of the RC-IGBT according to Embodiment 1.

[0019] Figure 6 FIG. is a partial top view of the RC-IGBT according to Embodiment 2.

[0020] Figure 7 FIG. is a partial cross-sectional view of the RC-IGBT according to Embodiment 2.

[0021] Figure 8 FIG. is a partial cross-sectional view of the RC-IGBT according to Embodiment 2.

[0022] Figure 9 FIG. is a partial cross-sectional view of the RC-IGBT according to Embodiment 2.

[0023] Figure 10 FIG. is a partial top view of the RC-IGBT according to Embodiment 3.

[0024] Figure 11 FIG. is a partial cross-sectional view of the RC-IGBT according to Embodiment 3.

[0025] Figure 12 FIG. is a partial cross-sectional view of the RC-IGBT according to Embodiment 3.

[0026] Figure 13 FIG. is a partial cross-sectional view of the RC-IGBT according to Embodiment 3.

[0027] Figure 14 It is a partial top view of the RC-IGBT related to Embodiment 4.

[0028] Figure 15 It is a partial cross-sectional view of the RC-IGBT related to Embodiment 4.

[0029] Figure 16 It is a partial cross-sectional view of the RC-IGBT related to Embodiment 4.

[0030] Figure 17 It is a partial top view of the RC-IGBT related to Embodiment 5.

[0031] Figure 18 It is a partial cross-sectional view of the RC-IGBT related to Embodiment 5.

[0032] Figure 19 It is a partial cross-sectional view of the RC-IGBT related to Embodiment 5.

[0033] Figure 20 It is a partial top view of the RC-IGBT related to Embodiment 6.

[0034] Figure 21 It is a partial cross-sectional view of the RC-IGBT related to Embodiment 6.

[0035] Figure 22 It is a partial cross-sectional view of the RC-IGBT related to Embodiment 6.

[0036] Figure 23 It is a partial cross-sectional view of the RC-IGBT related to Embodiment 6.

[0037] Figure 24 It is a partial cross-sectional view of the RC-IGBT related to Embodiment 6.

[0038] Figure 25 It is a partial top view of the RC-IGBT related to Embodiment 7.

[0039] Figure 26 It is a partial cross-sectional view of the RC-IGBT related to Embodiment 7.

[0040] Figure 27 It is a partial cross-sectional view of the RC-IGBT related to Embodiment 7.

[0041] Figure 28 It is a partial cross-sectional view of the RC-IGBT related to Embodiment 7.

[0042] Figure 29 It is a partial top view of the RC-IGBT related to Embodiment 8.

[0043] Figure 30 is a partial cross-sectional view of the RC-IGBT according to Embodiment 8.

[0044] Figure 31 is a partial cross-sectional view of the RC-IGBT according to Embodiment 8.

[0045] Figure 32 is a top view showing other structures of the RC-IGBT.

[0046] Figure 33 is a top view showing other structures of the RC-IGBT.

[0047] Figure 34 is a partial top view showing other structures of the RC-IGBT.

[0048] Figure 35 is a partial cross-sectional view showing other structures of the RC-IGBT.

[0049] Figure 36 is a partial cross-sectional view showing other structures of the RC-IGBT.

[0050] Figure 37 is a partial top view showing other structures of the RC-IGBT.

[0051] Figure 38 is a partial cross-sectional view showing other structures of the RC-IGBT.

[0052] Figure 39 is a partial cross-sectional view showing other structures of the RC-IGBT.

[0053] Figure 40 is a partial cross-sectional view showing other structures of the RC-IGBT.

[0054] Figure 41 is a partial cross-sectional view showing other structures of the RC-IGBT.

[0055] Figure 42 is a partial cross-sectional view showing other structures of the RC-IGBT. Detailed Embodiment

[0056] <Preface>

[0057] In the following description, n-type and p-type represent the conductivity types of semiconductors. In the present invention, the first conductivity type is set to p-type and the second conductivity type is set to n-type for description, but the first conductivity type may also be set to n-type and the second conductivity type may be set to p-type. In addition, n - -type indicates that the impurity concentration is lower than that of the n-type, and n + +-type indicates that the impurity concentration is higher than that of the n-type. Similarly, p -The n-type indicates that the impurity concentration is lower than that of the p-type, and the p + -type indicates that the impurity concentration is higher than that of the p-type.

[0058] In addition, the accompanying drawings are schematically shown. Therefore, the sizes of the images respectively shown in different accompanying drawings and the mutual relationships of the positions are not necessarily accurately recorded and may be appropriately changed. In addition, in the following description, the same reference numerals are assigned to the same structural elements for illustration, and their names and functions are also the same. Therefore, the detailed descriptions thereof may sometimes be omitted.

[0059] In addition, in the following description, terms such as "upper", "lower", "side", "front", and "back" indicating specific positions and directions may sometimes be used. However, these terms are only used for the convenience of easily understanding the content of the embodiments and have nothing to do with the directions in actual implementation.

[0060] <Embodiment 1>

[0061] <Device Structure>

[0062] Figure 1 is a top view of the entire chip of the RC-IGBT 100 according to Embodiment 1, Figure 2 is a top view of the region X surrounded by the Figure 1 dashed line in. Figure 1 The RC-IGBT 100 shown is of a "strip type" in which the IGBT region 101 (transistor region) and the FWD region 102 (diode region) are arranged side by side in a strip shape.

[0063] As Figure 1 shown, a peripheral region 103 is provided so as to surround the IGBT region 101 and the FWD region 102, and a gate pad region 104 is locally provided in one of the IGBT regions 101. In addition, in the RC-IGBTs 200 to 800 of Embodiments 2 to 8 described later, the top views showing the entire chips are the same.

[0064] As Figure 2 shown, the IGBT region 101 is divided by a plurality of strip-shaped buried gate electrodes 8 having a trench structure into an IGBT channel region 106 where a channel is formed and an IGBT non-channel region 107 (first non-channel region) where a channel is not formed. The IGBT channel region 106 and the IGBT non-channel region 107 are collectively referred to as a unit cell region 105. In addition, the IGBT region 101 and the FWD region 102 are collectively referred to as a cell region.

[0065] The IGBT channel region 106 and the IGBT non-channel region 107 sandwich the buried gate electrode 8 therebetween and are alternately formed in the arrangement direction of the buried gate electrode 8, i.e., the X direction (horizontal direction). Contact holes 15 are provided in both the IGBT channel region 106 and the IGBT non-channel region 107.

[0066] In the IGBT channel region 106, in the extending direction of the buried gate electrode 8, i.e., the Y direction (vertical direction), an n + -type emitter layer 3 (fourth semiconductor layer) and a p + -type contact layer 4 (fifth semiconductor layer) are alternately formed.

[0067] In addition, in the IGBT non-channel region 107, in the Y direction, a p-type channel doping layer 2 (third semiconductor layer) and a p + -type contact layer 4 are alternately formed. This is referred to as the first feature of Embodiment 1.

[0068] Moreover, in the IGBT non-channel region 107, a p-type channel doping layer 2 is formed at the boundary with the p-type well layer 16 (impurity layer) of the outer peripheral region 103, and the p-type channel doping layer 2 is connected to the p-type well layer 16. This is referred to as the second feature of Embodiment 1.

[0069] In addition, the p + -type contact layer 4 of the IGBT non-channel region 107 is provided in such a manner that the area ratio thereof is lower than that of the p-type channel doping layer 2. Here, the area ratio refers to the area ratio of the p-type channel doping layer 2 and the p + -type contact layer 4 in the total area when viewed from above. This is referred to as the third feature of Embodiment 1. However, the p + -type contact layer 4 cannot be zero, and preferably, the area ratio of the p + -type contact layer 4 is set to at least about 20%.

[0070] On the other hand, in the IGBT channel region 106, a p + -type contact layer 4 is formed at the boundary with the p-type well layer 16 of the outer peripheral region 103, and the p + -type contact layer 4 is connected to the p-type well layer 16. In addition, the n + -type emitter layer 3 of the IGBT channel region 106 is provided in such a manner that the area ratio thereof is lower than that of the p + -type contact layer 4.

[0071] In addition, as Figure 2 shown, in the FWD region 102, the p-type anode layer 5 is divided into a plurality of anode regions 108 by a plurality of buried gate electrodes 8, and strip-shaped p + -type contact layers 6 extending in the Y direction are provided in each anode region 108. In addition, p +The type contact layer 6 is provided in such a manner as not to contact the p-type well layer 16 in the outer peripheral region 103. In addition, contact holes 15 are provided so as to straddle a plurality of anode regions 108.

[0072] Figure 3 Shows Figure 2 The arrow-direction cross-sectional view at the A-A line shown, Figure 4 Shows the arrow-direction cross-sectional view at the B-B line, Figure 5 Shows the arrow-direction cross-sectional view at the C-C line.

[0073] As Figures 3 - 5 Shown, the RC-IGBT 100 has an n - -type drift layer 1 (second semiconductor layer) composed of a semiconductor substrate such as a silicon (Si) substrate. The n - -type drift layer 1 has, for example, arsenic (As) or phosphorus (P) as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 12 / cm 3 ~1.0×10 15 / cm 3 .

[0074] The semiconductor substrate ranges from the n + -type emitter layer 3 and the p + -type contact layer 4 to the p-type collector layer 11 (first semiconductor layer) in the IGBT region 101, and ranges from the p + -type contact layer 6 to the n + -type cathode layer 12 in the FWD region 102.

[0075] In Figures 3 - 5 , the upper end of the paper surface of the n + -type emitter layer 3 and the p + -type contact layer 4 in the IGBT region 101 is referred to as the first main surface of the semiconductor substrate, and the lower end of the paper surface of the p-type collector layer 11 is referred to as the second main surface of the semiconductor substrate. In addition, in Figures 3 - 5 , the upper end of the paper surface of the p + -type contact layer 6 in the FWD region 102 is referred to as the first main surface of the semiconductor substrate, and the lower end of the paper surface of the n + -type cathode layer 12 is referred to as the second main surface of the semiconductor substrate. The first main surface of the FWD region 102 is coplanar with the first main surface of the IGBT region 101, and the second main surface of the FWD region 102 is coplanar with the second main surface of the IGBT region 101.

[0076] As Figures 3 - 5 Shown, in the IGBT region 101, a p-type channel doping layer 2 is provided on the first main surface side of the n - -type drift layer 1, and in the FWD region 102, in the n -A p-type anode layer 5 is provided on the first main surface side of the p-type drift layer 1. The p-type channel doping layer 2 is a semiconductor layer having, for example, boron (B) or aluminum (Al) as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 12 / cm 3 ~1.0×10 19 / cm 3 .

[0077] On the first main surface side of the p-type channel doped layer 2, Figure 3 In contact with the gate insulating film 7 that buries the gate electrode 8, an n + Type emitter layer 3, in Figure 4 There is p in + Type contact layer 4. + type emitter layer 3 and p + The type contact layer 4 constitutes the first main surface of the semiconductor substrate.

[0078] n + The emitter layer 3 is a semiconductor layer containing, for example, arsenic (As) or phosphorus (P) as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 17 / cm 3 ~1.0×10 20 / cm 3 .

[0079] p + The p-type contact layer 4 is a semiconductor layer containing boron (B) or aluminum (Al) as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 15 / cm 3 ~1.0×10 20 / cm 3 .

[0080] In addition, if Figures 3 - 5 As shown, RC-IGBT 100 is - The second main surface side of the drift layer 1 is provided with an n - The n-type buffer layer 10 has a higher concentration of n-type impurities than the n-type drift layer 1. The n-type buffer layer 10 is provided to suppress the punch-through of the depletion layer extending from the p-type channel doping layer 2 to the second main surface when the RC-IGBT 100 is in the off state. The n-type buffer layer 10 can be formed by, for example, implanting phosphorus (P) or protons (H + ) can also be formed by injecting phosphorus (P) and protons (H + ) are formed by the two. The concentration of n-type impurities in the n-type buffer layer 10 is 1.0×10 12 / cm 3 ~1.0×10 18 / cm 3 .

[0081] In addition, as Figures 3 - 5 shown, on the first main surface of the IGBT region 101 and the FWD region 102, a collector electrode 14 (first electrode) is provided. The collector electrode 14 functions as a cathode electrode in the FWD region 102. On the collector electrode 14, a p-type collector layer 11 is provided in the IGBT region 101, and an n + -type cathode layer 12 is provided in the FWD region 102.

[0082] The p-type collector layer 11 is a semiconductor layer having, for example, boron (B) or aluminum (Al) as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 16 / cm 3 ~1.0×10 20 / cm 3 .

[0083] The n + -type cathode layer 12 is a semiconductor layer having, for example, arsenic (As) or phosphorus (P) as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 16 / cm 3 ~1.0×10 21 / cm 3 .

[0084] In addition, as Figure 5 shown, in the peripheral region 103, a p-type well layer 16 is provided on the first main surface side of the n - -type drift layer 1. The p-type well layer 16 is provided so as to surround the IGBT region 101 and the FWD region 102, has, for example, arsenic (As) or phosphorus (P) as an n-type impurity, and is in contact with the side surface of the p-type channel doping layer 2 in the IGBT region 101. The upper end of the p-type well layer 16 in the plane of the paper becomes the first main surface of the semiconductor substrate, and a cover insulating film 9 is provided on the p-type well layer 16.

[0085] Although not shown in the figure, an FLR (Field Limiting Ring) that surrounds the cell region with a p-type well layer (end well layer) or a VLD (Variation of Lateral Doping) that surrounds the cell region with a p-type well layer having a concentration gradient can be provided on the outermost periphery of the p-type well layer 16. The number of the annular p-type well layers used for the FLR and the concentration distribution of the p-type well layers used for the VLD can be appropriately selected according to the breakdown voltage design of the RC-IGBT 100.

[0086] In addition, as Figure 3 and Figure 4As shown, a trench is formed in the IGBT region 101 that penetrates the p-type channel doping layer 2 from the first main surface of the semiconductor substrate and reaches the n - -type drift layer 1. A buried gate electrode 8 is provided in the trench with a gate insulating film 7 interposed therebetween. It is configured such that the gate insulating film 7 and the buried gate electrode 8 are covered with a cover insulating film 9, and the buried gate electrode 8 is not connected to the emitter electrode 13 (second electrode). In addition, the buried gate electrode 8 in the IGBT region 101 is electrically connected to the gate pad region 104 via a gate wiring (not shown) formed inside the IGBT region 101 and functions as an active trench gate.

[0087] In addition, as Figure 3 and Figure 4 shown, a trench is also formed in the FWD region 102 that penetrates the p-type channel doping layer 2 from the first main surface of the semiconductor substrate and reaches the n - -type drift layer 1. A buried gate electrode 8 is provided in the trench with a gate insulating film 7 interposed therebetween. The gate insulating film 7 and the buried gate electrode 8 in the FWD region 102 are connected to the emitter electrode 13, and the buried gate electrode 8 functions as a dummy trench gate.

[0088] In addition, as Figures 3 - 5 shown, a barrier metal 18 is formed above the region of the first main surface of the semiconductor substrate where the cover insulating film 9 is not provided and above the cover insulating film 9. The barrier metal 18 can be, for example, a conductor containing titanium (Ti), such as titanium nitride, or TiSi in which titanium is alloyed with Si. As Figure 3 shown, the barrier metal 18 makes an ohmic contact with the n + -type emitter layer 3, the p + -type contact layer 6, and the buried gate electrode 8 in the FWD region 102, and is electrically connected to the n + -type emitter layer 3, the p + -type contact layer 6, and the buried gate electrode 8 in the FWD region 102. The emitter electrode 13 is provided above the barrier metal 18. The emitter electrode 13 can be formed of an aluminum alloy such as an aluminum-silicon alloy (Al-Si based alloy), or can be an electrode composed of a multilayer metal film having a coating formed by electroless plating or electroplating on an electrode formed of an aluminum alloy. The coating formed by electroless plating or electroplating can be, for example, a nickel (Ni) coating.

[0089] Figure 1 The gate pad region 104 shown is connected to the gate wiring formed inside the IGBT region 101, an oxide film is formed directly below the gate pad region 104, and the gate pad region 104 is electrically separated from the emitter electrode 13. In addition, directly below the oxide film can be the n - -type drift layer 1, or a p-type end well layer can be provided.

[0090] Regarding the manufacturing method of the RC-IGBT 100 of the above-described Embodiment 1, the manufacturing technology of a general IGBT can be used. By changing the mask pattern during the photolithography process, the configuration pattern of the impurity layer in the IGBT channel region 106 and the IGBT non-channel region 107 can be changed, and thus the manufacturing can be carried out. Therefore, the detailed description is omitted.

[0091] <Operation>

[0092] The operation of the cell region of the RC-IGBT 100 will be described. For the RC-IGBT 100, a diode structure is formed by the p-type anode layer 5, the p + -type contact layer 6, the n - -type drift layer 1, and the n + -type cathode layer 12. In the on-state during the FWD operation, it becomes a state where a positive voltage is applied to the emitter electrode 13 with respect to the collector electrode 14 while the paired IGBTs are in the off-state. Holes flow in from the anode region composed of the p-type anode layer 5 and the p + -type contact layer 6, and electrons flow in from the cathode region composed of the n + -type cathode layer 12, thereby causing conductivity modulation and the diode becoming conductive.

[0093] Next, if the paired IGBTs become in the on-state, it becomes a state where a negative voltage is applied to the emitter electrode 13 with respect to the collector electrode 14. The holes in the n - -type drift layer 1 escape from the p-type anode layer 5 and the p + -type contact layer 6 to the emitter electrode 13, and electrons escape from the n + -type cathode layer 12 to the collector electrode. However, the current continues to flow until the excess carriers near the anode region disappear and the pn junction formed by the p-type anode layer 5, the p + -type contact layer 6, and the n - -type drift layer 1 becomes reverse-biased.

[0094] Moreover, if the excess carriers near the anode region escape and the pn junction formed by the p-type anode layer 5, the p + -type contact layer 6, and the n - -type drift layer 1 becomes reverse-biased, the reverse recovery current starts to decrease. If the excess carriers in the n - -type drift layer 1 are exhausted, the recovery process is completed and it becomes in the cut-off state.

[0095] In the RC-IGBT 100, an IGBT region 101 is formed adjacent to the FWD region 102. In the IGBT region 101, it is composed of the p-type channel doping layer 2, the p + -type contact layer 4, the n- type drift layer 1 and n + type cathode layer 12 form a parasitic diode structure. Therefore, in the above-described operation, current also flows through the IGBT region, which is one of the reasons for increased loss.

[0096] However, in the RC-IGBT 100, an IGBT non-channel region 107 formed by alternately forming a p-type channel doping layer 2 and a p + type contact layer 4 is provided, which is a structure that reduces the average concentration of p-type impurities in the anode structure portion of the IGBT non-channel region 107 (the first feature). Therefore, the holes flowing into the n - type drift layer 1 from the IGBT non-channel region 107 are reduced, and thus the recovery loss generated by the parasitic diode can be reduced.

[0097] In addition, in the IGBT non-channel region 107, by connecting the contact hole 15 to both the p-type channel doping layer 2 and the p + type contact layer 4, the current does not concentrate on the p+-type contact layer 4 with a high impurity concentration, and the amount of holes injected from the anode region of the parasitic diode is reduced, so that the recovery loss can be reduced.

[0098] In addition, in the RC-IGBT 100, the p-type channel doping layer 2 and the p + type contact layer 4 in the IGBT region 101 are electrically connected to the emitter electrode 13 via a barrier metal 18. As an example of the barrier metal, Ti or the like is used in the Si semiconductor. The formation of the barrier metal is carried out by forming a Ti film on the Si substrate by a sputtering method or the like, and then making the Si surface into a silicide and forming TiN by illumination annealing in a nitrogen (N2) atmosphere. In the first embodiment 1, as the barrier metal such that the contact in the IGBT region 101 does not become a Schottky contact, for example, TiSi is selected. Thus, a structure can be obtained that can maintain the effect of preventing leakage current at high temperatures, especially the increase in leakage current during IGBT operation, and reduce the recovery loss during diode operation.

[0099] In addition, in the IGBT non-channel region 107, the area of the p + type contact layer 4 with a high impurity concentration is made smaller than the area of the p-type channel doping layer 2 (the third feature). Thereby, the average concentration of p-type impurities in the anode structure portion of the IGBT non-channel region 107 can be reduced, and the recovery loss of the parasitic diode in the IGBT region 101 can be reduced.

[0100] Next, the operation of the peripheral region 103 of the RC-IGBT 100 will be described. A p-type well layer 16 with a relatively high concentration is formed in the peripheral region 103. The p-type well layer 16, n -Type drift layer 1 and n + Type cathode layer 12 forms a parasitic diode structure. Therefore, similar to the IGBT region 101, unwanted diode losses may occur.

[0101] However, in the RC-IGBT 100, in the IGBT non-channel region 107, a p-type contact layer 4 with a high impurity concentration is not formed near the p-type well layer 16, and a structure in which the lower-concentration p-type channel doping layer 2 is connected to the p-type well layer 16 (second feature). Therefore, injection of holes from the parasitic diode via the p-type well layer 16 is suppressed, and the recovery loss of the parasitic diode can be reduced. + In addition, in the RC-IGBT 100, the IGBT channel region 106 and the IGBT non-channel region 107 are alternately arranged with the same arrangement ratio, having good current balance.

[0102] In this way, in the RC-IGBT 100 of Embodiment 1, the recovery loss of the parasitic diode formed in the IGBT region 101 can be reduced by the first feature. In addition, the influence of the parasitic diode formed in the peripheral region 103 can be reduced by the second feature, and the recovery loss can be further reduced. By combining these first to third features, the recovery loss during diode operation of the entire device can be reduced. In addition, the operation of the parasitic diode in the IGBT region 101 can be more effectively reduced by the third feature.

[0103]

[0104]

[0105] Figures 6 - 9 Figure 1 Next, using Figures 6 - 9 , the RC-IGBT 200 according to Embodiment 2 will be described. In addition, the top view of the entire chip of the RC-IGBT 200 is the same as Figure 1 , and Figure 6 is the top view of the region X surrounded by the dotted line in Figure 1 . In addition, Figure 7 shows the cross-sectional view in the arrow direction at the A-A line shown in Figure 6 , Figure 8 shows the cross-sectional view in the arrow direction at the B-B line, Figure 9 shows the cross-sectional view in the arrow direction at the C-C line. In addition, in Figures 6 - 9 , the same reference numerals are given to the same structures as those of the RC-IGBT 100 described using Figures 2 - 5 , and repeated description is omitted.

[0106] As shown in Figure 6As shown, the IGBT region 101 is divided into an IGBT channel region 106 and an IGBT non-channel region 107 by a plurality of buried gate electrodes 8. In the IGBT non-channel regions 107 other than the IGBT non-channel region 107 (the first non-channel region) near the FWD region 102 among the plurality of IGBT non-channel regions 107 (the second non-channel region), a p + -type contact layer 4 is formed at the boundary between the p-type well layer 16 of the peripheral region 103, and the p + -type contact layer 4 is connected to the p-type well layer 16.

[0107] That is, in the IGBT non-channel region 107 adjacent to the FWD region 102 (the IGBT non-channel region 107 near the FWD region 102) near the IGBT channel region 106, similar to the RC-IGBT 100 of Embodiment 1, a p-type channel doping layer 2 is formed at the boundary between the p-type well layer 16 of the peripheral region 103, and the p-type channel doping layer 2 is connected to the p-type well layer 16. However, in the IGBT non-channel region 107 other than the IGBT non-channel region 107 near the FWD region 102 (the IGBT non-channel region 107 at a position far from the FWD region 102), a p + -type contact layer 4 is formed at the boundary between the p-type well layer 16 of the peripheral region 103, and the p + -type contact layer 4 is connected to the p-type well layer 16.

[0108] In addition, the area of the p + -type contact layer 4 disposed in the exposed region (the mesa region) of the Si surface of the IGBT non-channel region 107 near the FWD region 102 is smaller than the area of the mesa region of the IGBT non-channel region 107 at a position far from the FWD region 102 where the p + -type contact layer 4 is disposed.

[0109] In addition, in the RC-IGBT 200 of Embodiment 2, the IGBT non-channel region 107 near the FWD region 102 is provided in such a manner that the area ratio of the p + -type contact layer 4 with a high impurity concentration is lower than that of the p-type channel doping layer 2.

[0110] Regarding the IGBT region 101 located near the n + -type cathode layer 12, the influence caused by the operation of the parasitic diode is large. However, by providing the IGBT non-channel region 107, the effective anode concentration of this part decreases, and the recovery loss during the FWD operation can be reduced.

[0111] In addition, in the IGBT non-channel region 107 (the second non-channel region) at a position far from the FWD region 102, p +The type contact layer 4 is connected to the p-type well layer 16 in the outer peripheral region 103. Therefore, holes flowing in from the outer peripheral region 103 during the operation of the IGBT can flow through the low-resistance layer to the emitter electrode 13, minimizing the reduction of the reverse-biased safe operating area (RBSOA) and reducing the recovery loss during FWD operation.

[0112] In addition, if the type contact layer 4 is configured to not only be in side contact with the p-type well layer 16 in the outer peripheral region 103 but also penetrate into the p-type well layer 16, the reduction of the RBSOA can be further suppressed. That is, at a position far from the FWD region 102, the operation of the parasitic diode can be ignored, and even when the above structure is adopted, an improvement in the characteristics of the IGBT can be expected. + Even when the above structure is adopted, an improvement in the characteristics of the IGBT can be expected.

[0113] <Embodiment 3>

[0114] Next, the RC-IGBT 300 according to Embodiment 3 will be described using Figures 10 - 13 . In addition, the top view of the entire chip of the RC-IGBT 300 is the same as Figure 1 , Figure 10 and is the top view of the region X surrounded by the dashed line in Figure 1 . In addition, Figure 11 shows the longitudinal sectional view taken along the line A-A shown in Figure 10 , Figure 12 shows the longitudinal sectional view taken along the line B-B, Figure 13 shows the longitudinal sectional view taken along the line C-C. In addition, in Figures 10 - 13 , the same reference numerals are assigned to the same structures as those of the RC-IGBT 100 described using Figures 2 - 5 , and repeated descriptions are omitted.

[0115] As shown in Figure 10 , the IGBT region 101 is divided into an IGBT channel region 106 and an IGBT non-channel region 107 by a plurality of buried gate electrodes 8, and the p + -type contact layer 4 formed in the plurality of IGBT non-channel regions 107 is disposed at a position opposite to the n + -type emitter layer 3 in the IGBT channel region 106 that is separated from the buried gate electrodes 8 in a top view.

[0116] In addition, in the IGBT non-channel region 107, the following structure is the same as that of the RC-IGBT 100 in Embodiment 1, that is, the p-type channel doping layer 2 and the p + -type contact layer 4 are alternately formed, and a p-type channel doping layer 2 is formed at the boundary between the p-type well layer 16 in the outer peripheral region 103, and the p-type channel doping layer 2 is connected to the p-type well layer 16.

[0117] Next, the operation of the RC-IGBT 300 will be described. In the on state, the conductivity is modulated and the - The excess carriers accumulated in the p-type drift layer 1 are discharged, thereby completing the turn-off operation during the IGBT operation. However, at this time, holes are transported from the p-type channel doped layer 2 through the p-type channel doped layer 2. + The flow of n to the emitter electrode 13 is a normal operation. + If the sheet resistance of the p-type channel doping layer 2 directly below the n-type emitter layer 3 is high, when hole current concentration and other problems occur, the p-type channel doping layer 2 and the n-type emitter layer 3 are electrically connected. + When a forward bias is applied to the pn junction of the p-type emitter layer 3, holes may not flow from the p-type channel doping layer 2 to the p-type + The p-type contact layer 4 flows from the p-type channel doping layer 2 to the n-type + Type emitter layer 3 flows and fails to turn off.

[0118] As a countermeasure, it is effective to make the p-type channel doping layer 2 and the n-type channel doping layer 2 + The pn junction of the emitter layer 3 is not forward biased and latch-up occurs. + A high concentration p-type impurity layer, i.e., p + The type contact layer 4 is formed to reduce the resistance and connect to the emitter potential, thereby suppressing the potential increase.

[0119] In the third embodiment, in the plan view, n + Next to the emitter layer 3, a p + type contact layer 4, and, in the IGBT non-channel region 107, the p + The n-type contact layer 4 is arranged in the IGBT channel region 106 separated from the buried gate electrode 8 in a plan view. + The position of the type emitter layer 3 is opposite. Therefore, n + The emitter layer 3 is formed by p + The structure surrounded by the type contact layer 4 strengthens the connection to the emitter potential and can reduce the possibility of latch-up during IGBT operation.

[0120] In addition, in the IGBT non-channel region 107, the p-type channel doping layer 2 and the p + The p-type contact layer 4 is formed alternately to make the impurity concentration high + The area of ​​the p-type contact layer 4 is larger than that of the p-type channel doping layer 2 , but is made small to a degree that can reduce the recovery loss during the FWD operation.

[0121] <Implementation method 4>

[0122] Next, use Figures 14 - 16 to describe the RC-IGBT 400 related to Embodiment 4. In addition, the top view of the entire chip of the RC-IGBT 400 is the same as Figure 1 , Figure 14 and is the top view of the region X surrounded by the dashed line in Figure 1 . Additionally, Figure 15 shows Figure 14 the arrow-sectional view taken along the line A-A shown in Figure 16 , and Figures 14 - 16 shows the arrow-sectional view taken along the line B-B. In addition, in Figures 2 - 5 , the same structures as those of the RC-IGBT 100 described using

[0123] are labeled with the same reference numerals, and repeated descriptions are omitted. Figure 14 As shown, the IGBT region 101 is divided into an IGBT channel region 106 and an IGBT non-channel region 107 by a plurality of buried gate electrodes 8. In the IGBT non-channel regions 107 (the second non-channel regions) other than the IGBT non-channel regions 107 (the first non-channel regions) near the FWD region 102 among the plurality of IGBT non-channel regions 107, a p + -type contact layer 4 is formed on the entire surface of the Si surface.

[0124] That is, in Figure 14 , the IGBT non-channel region 107 (the IGBT non-channel region 107 near the FWD region 102) adjacent to the FWD region 102 and adjacent to the IGBT channel region 106 forms a p-type channel doping layer 2 at the boundary with the p-type well layer 16 of the peripheral region 103, and the p-type channel doping layer 2 is connected to the p-type well layer 16, similar to the RC-IGBT 100 of Embodiment 1. However, in the IGBT non-channel regions 107 other than the IGBT non-channel regions 107 near the FWD region 102 (the IGBT non-channel regions 107 at positions far from the FWD region 102), a p + -type contact layer 4 is formed on the entire surface of the Si surface, and the p + -type contact layer 4 is connected to the p-type well layer 16.

[0125] In addition, in the IGBT non-channel regions 107 near the FWD region 102, similar to the RC-IGBT 300 of Embodiment 3, the p + -type contact layer 4 is disposed at a position opposite to the n + -type emitter layer 3 of the IGBT channel region 106 spaced apart from the buried gate electrode 8 in a top view.

[0126] In the RC-IGBT 400, in the region of the IGBT non-channel region 107 near the back surface, i.e., near the n-type cathode layer 12 formed near the FWD region 102, the p-type channel doping layer 2 and the p + -type contact layer 4 are alternately formed to reduce the effective p-type impurity concentration, thereby reducing the recovery loss during FWD operation. + On the other hand, in the IGBT non-channel region 107 located at a position far from the FWD region 102, i.e., far from the n-type cathode layer 12 on the back surface and not easily operating as a parasitic diode, by forming the p

[0127] -type contact layer 4 over the entire surface, it is possible to suppress the application of a forward bias to the pn junction between the p-type channel doping layer 2 and the n + -type emitter layer 3 during IGBT operation and suppress the decrease in breakdown withstand such as RBSOA. + + + +

[0128] <Variation>

[0129] In the RC-IGBT 400 described above, in the IGBT non-channel region 107 near the FWD region 102, the p-type channel doping layer 2 and the p + -type contact layer 4 are alternately formed. However, it is not limited to this arrangement only. For the IGBT non-channel regions 107 in other columns, the structure in which the p-type channel doping layer 2 and the p + -type contact layer 4 are alternately formed can also be applied.

[0130] n + The p-type impurity region in the IGBT region 101 near the n-type cathode layer 12 operates as the anode region of the parasitic pin diode and becomes the current path. However, the farther away from the n + -type cathode layer 12, the smaller the influence of operating as the anode region. This is because it has the same effect as the increase in the thickness of the effective n - -type drift layer 1 of the parasitic pin diode. In the region that is away from the n-type cathode layer 12 by an amount equal to or about 1.5 times the substrate thickness, the influence caused by the parasitic diode is reduced. + +

[0131] Therefore, in the region that is away from the end of the n-type cathode layer 12, i.e., the end of the FWD region 102, by an amount equal to or about 1.5 times the substrate thickness, an IGBT non-channel region 107 in which the p-type channel doping layer 2 and the p + -type contact layer 4 are alternately formed is provided, thereby obtaining the effect of further reducing the recovery loss of the parasitic diode. + +

[0132] In addition, the area ratio of the p-channel doping layer 2 and the p + -type contact layer 4 in the IGBT non-channel region 107 near the FWD region 102 can be changed according to circumstances. Regarding the portion of the FWD region 102 where the influence of the parasitic diode is large, priority is given to reducing the recovery loss, and the area ratio of the p + -type contact layer 4 is reduced. As the distance from the FWD region 102 increases, the ratio of the p + -type contact layer 4 is increased. Thus, emphasis can be placed on improving the RBSOA tolerance during IGBT operation.

[0133] <Embodiment 5>

[0134] Next, Figures 17 - 19 will be used to describe the RC-IGBT 500 according to Embodiment 5. In addition, the top view of the entire chip of the RC-IGBT 500 is the same as Figure 1 and is the top view of the region X surrounded by the dashed line in Figure 17 . In addition, Figure 1 shows a sectional view in the arrow direction at the line A-A shown in Figure 18 , and Figure 17 shows a sectional view in the arrow direction at the line B-B. In addition, in Figure 19 , the same reference numerals are assigned to the same structures as those of the RC-IGBT 100 described using Figures 17 - 19 , and repeated descriptions are omitted. Figures 2 - 5 As shown in

[0135] , the IGBT region 101 is divided into an IGBT channel region 106 and an IGBT non-channel region 107 by a plurality of buried gate electrodes 8. The IGBT non-channel region 107 is arranged adjacent to the FWD region 102, and the IGBT channel region 106 is arranged adjacent thereto. Then, the IGBT non-channel region 107 and the IGBT channel region 106 are arranged alternately. In addition, in the IGBT non-channel region 107, a p-channel doping layer 2 and a p Figure 17 -type contact layer 4 are formed alternately. + -type contact layer 4.

[0136] In the RC-IGBT 500, by forming an IGBT non-channel region 107 with a reduced effective p-type impurity concentration in the region of the IGBT region 101 that is most likely to operate as a parasitic diode, i.e., the region adjacent to the FWD region 102, the recovery loss during FWD operation can be reduced.

[0137] <Embodiment 6>

[0138] Next, Figures 20 - 24, the RC-IGBT 600 related to Embodiment 6 will be described. In addition, the top view of the entire chip of the RC-IGBT 600 is the same as Figure 1 and Figure 20 is the top view showing the region X surrounded by the dashed line in Figure 1 . Additionally, Figure 21 shows Figure 20 the arrow-sectional view taken along the line A-A shown in Figure 22 shows the arrow-sectional view taken along the line B-B, Figure 23 shows the arrow-sectional view taken along the line C-C, Figure 24 shows the arrow-sectional view taken along the line D-D. In addition, in Figures 20 - 24 , the same structures as those of the RC-IGBT 100 described using Figures 2 - 5 are labeled with the same reference numerals, and repeated descriptions are omitted.

[0139] As Figure 20 shown, the IGBT region 101 is divided into an IGBT channel region 106 and an IGBT non-channel region 107 by a plurality of buried gate electrodes 8, and a p-type channel doping layer 2 and a p + -type contact layer 4 are formed in the IGBT non-channel region 107. Regarding the p + -type contact layer 4, the top view shape is an elongated rectangle extending in the Y direction and a plurality of them are provided. The plurality of p + -type contact layers 4 are arranged at intervals and discontinuously in a row along their length direction. The arrangement interval of the p + -type contact layer 4 in the IGBT non-channel region 107 is formed shorter than the length in the length direction (Y direction) of the p + -type contact layer 4.

[0140] In addition, the area ratio of the p + -type contact layer 4 in the mesa region (the part where the Si surface is exposed) of the IGBT non-channel region 107 can be set to the same level as that of the p + -type contact layer 4 of the RC-IGBT 100 in Embodiment 1.

[0141] In the RC-IGBT 600, in the IGBT region 101, by setting the area ratio of the p + -type contact layer 4 in the IGBT non-channel region 107 to be less than or equal to a certain value, the p-type impurity concentration in the IGBT non-channel region 107 effectively decreases. Therefore, it is possible to suppress the IGBT region 101 from operating as a parasitic diode and reduce the recovery loss during FWD operation.

[0142] And, by making the p +The type contact layer 4 is set to have an elongated rectangular shape in a plan view, and its arrangement interval is set to be shorter than the length in the length direction, so that the pattern size becomes larger, dimensional fluctuations during manufacturing can be suppressed, and fluctuations in recovery loss during FWD operation can be reduced.

[0143] <Embodiment 7>

[0144] Next, use Figures 25 - 28 , the RC-IGBT 700 according to Embodiment 7 will be described. In addition, the plan view of the entire chip of the RC-IGBT 700 is the same as Figure 1 and Figure 25 is a plan view showing the region X surrounded by the dashed line in Figure 1 . In addition, Figure 26 shows Figure 25 a cross-sectional view in the arrow direction at the line A-A shown in Figure 27 shows a cross-sectional view in the arrow direction at the line B-B, Figure 28 shows a cross-sectional view in the arrow direction at the line C-C. In addition, in Figures 25 - 28 , the same reference numerals are assigned to the same structures as those of the RC-IGBT 100 described using Figures 2 - 5 , and repeated descriptions are omitted.

[0145] As Figure 25 shown, the IGBT region 101 is divided into an IGBT channel region 106 and an IGBT non-channel region 107 by a plurality of buried gate electrodes 8, and a p-type channel doping layer 2 and a p + type contact layer 4 are formed in the IGBT non-channel region 107, but the p + type contact layer 4 is formed in a continuous linear shape extending in the Y direction in a plan view.

[0146] In addition, the area ratio of the p + type contact layer 4 in the mesa region (the part where the Si surface is exposed) of the IGBT non-channel region 107 can be set to the same level as that of the RC-IGBT 100 of Embodiment 1.

[0147] In the RC-IGBT 700, in the IGBT region 101, the p + type contact layer 4 in the IGBT non-channel region 107 is set to be less than or equal to a certain area ratio, and the p-type impurity concentration in the IGBT non-channel region 107 effectively decreases. Therefore, it is possible to suppress the IGBT region 101 from operating as a parasitic diode and reduce the recovery loss during FWD operation.

[0148] And by making the p +The type contact layer 4 is set to have an elongated rectangular shape in a top view and is set as a continuous line, so that the pattern size becomes larger, fluctuations in size during manufacturing can be suppressed, and fluctuations in recovery loss during FWD operation can be reduced.

[0149] <Embodiment 8>

[0150] Next, use Figures 29 - 31 , the RC-IGBT 800 according to Embodiment 8 will be described. In addition, the top view of the entire chip of the RC-IGBT 800 is the same as Figure 1 , Figure 29 is the top view of the region X surrounded by the dashed line in Figure 1 . Additionally, Figure 30 shows Figure 29 the cross-sectional view in the arrow direction at the line A-A shown in Figure 31 , and Figures 29 - 31 shows the cross-sectional view in the arrow direction at the line B-B. In addition, in Figures 2 - 5 , the same reference numerals are given to the same structures as those of the RC-IGBT 100 described using

[0151] As Figure 29 shown, the IGBT region 101 is divided into an IGBT channel region 106 and an IGBT non-channel region 107 by a plurality of buried gate electrodes 8, and the configuration ratio of the IGBT channel region 106 in the IGBT region 101 is 1 / 3.

[0152] In Figure 29 , the IGBT channel region 106 is arranged adjacent to the FWD region 102, the IGBT non-channel region 107 is arranged adjacent to the channel region 106, and the IGBT non-channel region 107 is also arranged adjacent to the IGBT non-channel region 107. By repeating such a configuration within the IGBT region 101, the ratio between the IGBT channel region 106 and the IGBT non-channel region 107 becomes 1 to 2.

[0153] Furthermore, if the IGBT channel region 106 and the IGBT non-channel region 107 are arranged as described above, there is a buried gate electrode 8 sandwiched by the IGBT non-channel region 107, and this buried gate electrode 8 is connected to the emitter electrode in a region not shown in the same manner as the dummy trench gate, becoming a buried emitter electrode 17, so the potential of the buried gate electrode 8 does not become a problem.

[0154] In the RC-IGBT 800, by reducing the number of IGBT channel regions 106, that is, by eliminating the IGBT channel regions 106 so-called, the saturation current and the short-circuit withstand can be set to desired values.

[0155] In addition, the p of the IGBT non-channel region 107 is reduced. + The p-type impurity concentration in the IGBT non-channel region 107 is effectively reduced by reducing the area ratio of the p-type contact layer 4, so that the saturation current and short-circuit withstand capacity during IGBT operation can be set to desired values ​​and the fluctuation of the recovery loss during FWD operation can be reduced.

[0156] Furthermore, in the above-described first to eighth embodiments, examples in which the present invention is applied to an RC-IGBT are described, but the present invention can also be applied to a MOSFET or the like.

[0157] Furthermore, although a manufacturing method using a Si substrate has been described as an example of the manufacturing method, a semiconductor substrate made of a different material such as silicon carbide (SiC) may also be used.

[0158] In addition, Figure 2 In the examples, a strip-shaped unit having a strip-shaped buried gate electrode 8 having a trench structure is illustrated, but the present invention can also be applied to a so-called grid-type unit extending vertically and horizontally, and can also be applied to a so-called planar-type unit structure having a planar gate.

[0159] <Other structural examples of RC-IGBT>

[0160] Next, another configuration example of the RC-IGBT is shown. Figure 32 1 is a top view showing a semiconductor device 1000 that is an RC-IGBT. Figure 33 1 is a plan view showing a semiconductor device 1001 which is an RC-IGBT. Figure 32 The semiconductor device 1000 shown is a semiconductor device in which the IGBT region 110 and the diode region 120 are arranged side by side in a stripe shape, which can be simply referred to as a “strip type”. Figure 33 The semiconductor device 1001 shown is a semiconductor device in which a plurality of diode regions 120 are arranged in the vertical direction and the horizontal direction, and an IGBT region 110 is arranged around the diode region 120 , which can be simply referred to as an “island type”.

[0161] <Strip-shaped overall plan structure>

[0162] exist Figure 32 In the embodiment, the semiconductor device 1000 includes an IGBT region 110 and a diode region 120 in one semiconductor device. The IGBT region 110 and the diode region 120 extend from one end of the semiconductor device 1000 to the other end, and are alternately arranged in stripes in a direction orthogonal to the extending direction of the IGBT region 110 and the diode region 120. Figure 32Among them, three IGBT regions 110 and two diode regions 120 are shown. A structure is shown in which all the diode regions 120 are sandwiched by the IGBT regions 110. However, the numbers of the IGBT regions 110 and the diode regions 120 are not limited to this. The number of the IGBT regions 110 can be greater than or equal to 3 or less than or equal to 3, and the number of the diode regions 120 can be greater than or equal to 2 or less than or equal to 2. In addition, it can also be a structure in which the positions of the IGBT regions 110 and the diode regions 120 of Figure 32 are swapped, or a structure in which all the IGBT regions 110 are sandwiched by the diode regions 120. In addition, it can also be a structure in which the IGBT regions 110 and the diode regions 120 are arranged adjacent to each other one by one.

[0163] As Figure 32 shown, a pad region 140 is arranged adjacent to the IGBT region 110 on the lower side of the paper surface. The pad region 140 is a region where a control pad 141 for controlling the semiconductor device 1000 is arranged. The IGBT region 110 and the diode region 120 are collectively referred to as a cell region. Around the region where the cell region and the pad region 140 are combined, a termination region 130 is arranged for maintaining the breakdown voltage of the semiconductor device 1000. A known breakdown voltage maintaining structure can be appropriately selected and arranged in the termination region 130. The breakdown voltage maintaining structure can be constituted, for example, by arranging an FLR that surrounds the cell region with a p-type terminal well layer of a p-type semiconductor and a VLD that surrounds the cell region with a p-type well layer provided with a concentration gradient on the front side, i.e., the first main surface side, of the semiconductor device 1000. The number of the annular p-type terminal well layers used for the FLR and the concentration distribution used for the VLD can be appropriately selected according to the breakdown voltage design of the semiconductor device 1000. In addition, a p-type terminal well layer can be arranged over substantially the entire region of the pad region 140, or IGBT cells and diode cells can be arranged in the pad region 140. The control pad 141 can be, for example, a current sensing pad 141a, a Kelvin emitter pad 141b, a gate pad 141c, a temperature sensing diode pad 141d, 141e. The current sensing pad 141a is a control pad for detecting the current flowing through the cell region of the semiconductor device 1000, and is electrically connected to an IGBT cell or a diode cell of a part of the cell region. When current flows through the cell region of the semiconductor device 1000, the current flowing through this control pad is one fraction to one ten-thousandth of the current flowing through the entire cell region.

[0164] The Kelvin emitter pad 141b and the gate pad 141c are control pads to which a gate drive voltage for controlling the on / off state of the semiconductor device 1000 is applied. The Kelvin emitter pad 141b is electrically connected to the p-type base layer of the IGBT unit, and the gate pad 141c is electrically connected to the gate trench electrode of the IGBT unit. The Kelvin emitter pad 141b and the p-type base layer may also be electrically connected via a p + -type contact layer. The temperature sensing diode pads 141d and 141e are control pads electrically connected to the anode and cathode of the temperature sensing diode provided in the semiconductor device 1000. The voltage between the anode and cathode of the temperature sensing diode (not shown) provided in the unit region is measured to measure the temperature of the semiconductor device 1000.

[0165] <Overall planar structure of island type>

[0166] In Figure 33 this, the semiconductor device 1001 has an IGBT region 110 and a diode region 120 within one semiconductor device. In the semiconductor device, when viewed from above, a plurality of diode regions 120 are arranged side by side in the longitudinal and lateral directions, and the periphery of the diode region 120 is surrounded by the IGBT region 110. That is, a plurality of diode regions 120 are provided in an island shape within the IGBT region 110. In Figure 33 this, a structure in which the diode regions 120 are arranged in a matrix of 4 columns in the left-right direction and 2 rows in the up-down direction on the paper surface is shown, but the number and arrangement of the diode regions 120 are not limited to this, and one or more diode regions 120 may be scattered within the IGBT region 110, and the periphery of each diode region 120 is surrounded by the IGBT region 110.

[0167] As Figure 33As shown, a pad region 140 is provided adjacent to the lower side of the paper surface of the IGBT region 110. The pad region 140 is a region where a control pad 141 for controlling the semiconductor device 1001 is provided. The IGBT region 110 and the diode region 120 are collectively referred to as a cell region. Around the region where the cell region and the pad region 140 are combined, a termination region 130 is provided for maintaining the breakdown voltage of the semiconductor device 1001. A known breakdown voltage maintaining structure can be appropriately selected and provided in the termination region 130. The breakdown voltage maintaining structure can be, for example, composed of an FLR that surrounds the region where the cell region and the pad region 140 are combined by a p-type terminal well layer of a p-type semiconductor on the front side, i.e., the first main surface side, of the semiconductor device 1001, and a VLD that surrounds the cell region by a p-type well layer with a concentration gradient. The number of the annular p-type terminal well layers used for the FLR and the concentration distribution used for the VLD can be appropriately selected according to the breakdown voltage design of the semiconductor device 1001. In addition, a p-type terminal well layer can be provided over substantially the entire region of the pad region 140, or IGBT cells and diode cells can be provided in the pad region 140.

[0168] The control pad 141 can be, for example, a current sensing pad 141a, a Kelvin emitter pad 141b, a gate pad 141c, temperature sensing diode pads 141d, 141e. The current sensing pad 141a is a control pad for detecting the current flowing through the cell region of the semiconductor device 1001, and is electrically connected to an IGBT cell or a diode cell that is a part of the cell region. When current flows through the cell region of the semiconductor device 1001, the current flowing through this control pad is one fraction to one ten-thousandth of the current flowing through the entire cell region.

[0169] The Kelvin emitter pad 141b and the gate pad 141c are control pads for applying a gate drive voltage for controlling the on / off of the semiconductor device 1001. The Kelvin emitter pad 141b is electrically connected to the p-type base layer and the n+-type source layer of the IGBT cell, and the gate pad 141c is electrically connected to the gate trench electrode of the IGBT cell. The Kelvin emitter pad 141b and the p-type base layer can be electrically connected via a p + type contact layer. The temperature sensing diode pads 141d, 141e are control pads that are electrically connected to the anode and the cathode of a temperature sensing diode provided in the semiconductor device 1001. The temperature of the semiconductor device 1001 is measured by measuring the voltage between the anode and the cathode of an unillustrated temperature sensing diode provided in the cell region.

[0170] <Local planar structure>

[0171] Figure 34 is toFigure 32 The semiconductor device 1000 or Figure 33 FIG. 1 is a partial top view showing an enlarged area 182 of the IGBT region 110 of the semiconductor device 1001 surrounded by a dotted line. Figure 34 As shown, in the IGBT region 110, the active trench gate 111 and the dummy trench gate 112 are arranged in a strip shape. As for the semiconductor device 1000, the active trench gate 111 and the dummy trench gate 112 extend along the length direction of the IGBT region 110, and the length direction of the IGBT region 110 becomes the length direction of the active trench gate 111 and the dummy trench gate 112. On the other hand, as for the semiconductor device 1001, for the IGBT region 110, the length direction and the width direction are not particularly distinguished, and the left-right direction of the paper can be set as the length direction of the active trench gate 111 and the dummy trench gate 112, and the up-down direction of the paper can also be set as the length direction of the active trench gate 111 and the dummy trench gate 112.

[0172] The active trench gate 111 is formed by providing a gate trench electrode 111a in a trench formed in a semiconductor substrate via a gate trench insulating film 111b. The dummy trench gate 112 is formed by providing a dummy trench electrode 112a in a trench formed in a semiconductor substrate via a dummy trench insulating film 112b. The gate trench electrode 111a of the active trench gate 111 is connected to the gate pad 141c ( Figure 32 , Figure 33 The dummy trench electrode 112 a of the dummy trench gate 112 is electrically connected to an emitter electrode provided on the first main surface of the semiconductor device 1000 or the semiconductor device 1001 .

[0173] n + The n+ type source layer 113 is provided on both sides of the active trench gate 111 in the width direction in contact with the gate trench insulating film 111b. The n+ type source layer 113 is a semiconductor layer having n-type impurities such as arsenic (As) or phosphorus (P), and the concentration of the n-type impurities is 1.0×10 17 / cm 3 ~1.0×10 20 / cm 3 .n + The type source layer 113 is connected to the p-type source layer 113 along the extension direction of the active trench gate 111. + The type contact layers 114 are arranged alternately. + The type contact layer 114 is also disposed between two adjacent dummy trench gates 112. + The p-type contact layer 114 is a semiconductor layer containing boron (B) or aluminum (Al) as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 15 / cm 3~1.0×10 20 / cm 3 。

[0174] As shown in Figure 34 , in the IGBT region 110 of the semiconductor device 1000 or the semiconductor device 1001, three dummy trench gates 112 are arranged adjacent to three adjacent active trench gates 111, and three active trench gates 111 are arranged adjacent to the three adjacent dummy trench gates 112. In this way, the IGBT region 110 has a structure in which groups of active trench gates 111 and groups of dummy trench gates 112 are arranged alternately. In Figure 34 , the number of active trench gates 111 included in one group of active trench gates 111 is set to three, but it may be greater than or equal to one. In addition, the number of dummy trench gates 112 included in one group of dummy trench gates 112 may be greater than or equal to one, and the number of dummy trench gates 112 may also be zero. That is, all the trenches provided in the IGBT region 110 may be active trench gates 111.

[0175] <Local cross-sectional structure>

[0176] Figure 35 is Figure 34 the arrow-sectional view taken along line A-A in Figure 35 . As shown in - , the semiconductor device 1000 or the semiconductor device 1001 has an n - -type drift layer 91 formed of a semiconductor substrate. The n 12 -type drift layer 91 is a semiconductor layer having, for example, arsenic (As) or phosphorus (P) as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 3 / cm 15 ~1.0×10 3 . In Figure 35 , the semiconductor substrate in the IGBT region 110 ranges from the n + -type source layer 113 and the p + -type contact layer 114 to the p-type collector layer 116.

[0177] In Figure 35 , the upper end of the paper surface of the n + -type source layer 113 and the p + -type contact layer 114 in the IGBT region 110 is referred to as the first main surface of the semiconductor substrate, and the lower end of the paper surface of the p-type collector layer 116 is referred to as the second main surface of the semiconductor substrate.

[0178] The first main surface of the semiconductor substrate is the main surface on the front side of the semiconductor device 1000 or the semiconductor device 1001, and the second main surface of the semiconductor substrate is the main surface on the back side of the semiconductor device 1000 or the semiconductor device 1001. In the unit region, that is, the IGBT region 110 of the semiconductor device 1000 or the semiconductor device 1001, an n - -type drift layer 91 is provided between the first main surface and the second main surface opposite to the first main surface.

[0179] As Figure 35 shown, in the IGBT region 110, an n - -type carrier accumulation layer 92 with a higher concentration of n-type impurities than that of the n - -type drift layer 91 is provided on the first main surface side of the n 13 -type drift layer 91. The n-type carrier accumulation layer 92 is a semiconductor layer having, for example, arsenic (As) or phosphorus (P) as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 3 / cm 17 ~1.0×10 3 / cm - . In addition, the semiconductor device 1000 and the semiconductor device 1001 may also have a structure in which the n-type carrier accumulation layer 92 is not provided and the n - -type drift layer 91 is also provided in the region of the n-type carrier accumulation layer 92. By providing the n-type carrier accumulation layer 92, the conduction loss when current flows through the IGBT region 110 can be reduced. The n-type carrier accumulation layer 92 and the n

[0180] -type drift layer 91 may be collectively referred to as a drift layer. - The n-type carrier accumulation layer 92 is formed by ion-implanting n-type impurities into the semiconductor substrate constituting the n - -type drift layer 91, and then diffusing the implanted n-type impurities into the n

[0181] -type drift layer 91, that is, the semiconductor substrate, by annealing. 12 / cm 3 ~1.0×10 19 / cm 3 . The p-type base layer 115 is in contact with the gate trench insulating film 111b of the active trench gate 111. On the first main surface side of the p-type base layer 115, an n + -type source layer 113 is provided in contact with the gate trench insulating film 111b of the active trench gate 111, and a p + -type contact layer 114 is provided in the remaining region. n+ type source layer 113 and p + type contact layer 114 form the first main surface of the semiconductor substrate. In addition, the p + type contact layer 114 is a region with a higher concentration of p-type impurities than the p-type base layer 115. When it is necessary to distinguish between the p + type contact layer 114 and the p-type base layer 115, they can be called separately, or the p + type contact layer 114 and the p-type base layer 115 can be collectively referred to as the p-type base layer.

[0182] In addition, the semiconductor device 1000 or the semiconductor device 1001 is provided with an n - type buffer layer 93 with a higher concentration of n-type impurities than the n - type drift layer 91 on the second main surface side of the n + type drift layer 91. The n-type buffer layer 93 is provided to suppress the punch-through of the depletion layer extending from the p-type base layer 115 to the second main surface side when the semiconductor device 1000 or the semiconductor device 1001 is in the off state. The n-type buffer layer 93 can be formed, for example, by implanting phosphorus (P) or protons (H + ), or by implanting both phosphorus (P) and protons (H 12 / cm 3 ~1.0×10 18 / cm 3 .

[0183] In addition, the semiconductor device 1000 or the semiconductor device 1001 may be a structure in which the n-type buffer layer 93 is not provided, and the n - type drift layer 91 is also provided in the region of the n-type buffer layer 93. The n-type buffer layer 93 and the n - type drift layer 91 can also be collectively referred to as the drift layer.

[0184] The semiconductor device 1000 or the semiconductor device 1001 is provided with a p-type collector layer 116 on the second main surface side of the n-type buffer layer 93. That is, a p-type collector layer 116 is provided between the n - type drift layer 91 and the second main surface. The p-type collector layer 116 is a semiconductor layer having, for example, boron (B) or aluminum (Al) as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 16 / cm 3 ~1.0×10 20 / cm 3。The p-type collector layer 116 forms the second main surface of the semiconductor substrate. The p-type collector layer 116 is provided not only in the IGBT region 110 but also in an end region 130 (not shown), and a portion of the p-type collector layer 116 provided in the end region 130 forms a p-type end collector layer 116a. In addition, the p-type collector layer 116 may be provided in such a manner that a part thereof extends from the IGBT region 110 toward the diode region 120.

[0185] As Figure 35 shown, in the IGBT region 110, a trench is formed that penetrates the p-type base layer 115 from the first main surface of the semiconductor substrate and reaches the n- - type drift layer 91. An active trench gate 111 is formed by disposing a trench gate electrode 111a in the trench with a trench gate insulating film 111b interposed therebetween. The trench gate electrode 111a faces the n- - type drift layer 91 with the trench gate insulating film 111b interposed therebetween. In addition, a dummy trench gate 112 is formed by disposing a dummy trench electrode 112a in the trench with a dummy trench insulating film 112b interposed therebetween. The dummy trench electrode 112a faces the n- - type drift layer 91 with the dummy trench insulating film 112b interposed therebetween. The trench gate insulating film 111b of the active trench gate 111 is in contact with the p-type base layer 115 and the n- + type source layer 113. If a gate drive voltage is applied to the trench gate electrode 111a, a channel is formed in the p-type base layer 115 in contact with the trench gate insulating film 111b of the active trench gate 111.

[0186] As Figure 35 shown, an interlayer insulating film 94 is provided on the trench gate electrode 111a of the active trench gate 111. A barrier metal 95 is formed on a region of the first main surface of the semiconductor substrate where the interlayer insulating film 94 is not provided and on the interlayer insulating film 94. The barrier metal 95 may be, for example, a conductor containing titanium (Ti), such as titanium nitride, or TiSi obtained by alloying titanium and silicon (Si). As Figure 35 shown, the barrier metal 95 makes an ohmic contact with the n- + type source layer 113, the p- + type contact layer 114, and the dummy trench electrode 112a, and makes an ohmic contact with the n- + type source layer 113, the p- +The type contact layer 114 and the dummy trench electrode 112a are electrically connected. An emitter electrode 96 is provided on the barrier metal 95. The emitter electrode 96 can be formed of an aluminum alloy such as an aluminum-silicon alloy (Al-Si alloy), or can be an electrode composed of a multi-layer metal film with a coating formed by electroless plating or electroplating on an electrode formed of an aluminum alloy. The coating formed by electroless plating or electroplating can be, for example, a nickel (Ni) coating. In addition, when there is a minute region such as between adjacent interlayer insulating films 94, that is, a region where good filling cannot be achieved by the emitter electrode 96, tungsten (W) with better filling property than the emitter electrode 96 can be disposed in the minute region, and the emitter electrode 96 can be provided on the tungsten. Further, the barrier metal 95 may not be provided, and the emitter electrode 96 may be provided on the n + type source layer 113, p + type contact layer 114, and the dummy trench electrode 112a. In addition, the emitter electrode 96 can be provided only on the n + type source layer 113 and other n-type semiconductor layers. The barrier metal 95 and the emitter electrode 86 may be collectively referred to as the emitter electrode. Further, in Figure 35 , a diagram is shown in which the interlayer insulating film 94 is not provided on the dummy trench electrode 112a of the dummy trench gate 112, but the interlayer insulating film 94 can also be formed on the dummy trench electrode 112a of the dummy trench gate 112. When the interlayer insulating film 94 is formed on the dummy trench electrode 112a of the dummy trench gate 112, it is only necessary to electrically connect the emitter electrode 96 and the dummy trench electrode 112a in other cross-sections.

[0187] A collector electrode 97 is provided on the second main surface side of the p-type collector layer 116. Similar to the emitter electrode 96, the collector electrode 97 can also be formed of an aluminum alloy or a combination of an aluminum alloy and a coating. In addition, the collector electrode 97 can also have a structure different from that of the emitter electrode 96. The collector electrode 97 makes an ohmic contact with the p-type collector layer 116 and is electrically connected to the p-type collector layer 116.

[0188] Figure 36 is Figure 34 a cross-sectional view in the arrow direction at the B-B line in Figure 36 The cross-sectional structure of the IGBT region 110 shown is a cross-sectional structure along the arrangement direction of the p + type contact layer 114, and thus the difference from Figure 35 is that p + type contact layer 114 is entirely provided on the first main surface side of the p-type base layer 115, and the n + type source layer 113 is not visible. That is, as Figure 34 shown, the n +The type source layer 113 is selectively provided on the first main surface side of the p-type base layer. In addition, the p-type base layer mentioned here refers to the p-type base layer in the case of collectively referring to the p-type base layer 115 and the p + -type contact layer 114.

[0189] <Structure of Diode Region>

[0190] <Local Planar Structure>

[0191] Figure 37 It is Figure 32 a partial top view showing an enlarged view of the region 183 surrounded by a dotted line of the diode region 120 of the semiconductor device 1000 shown in Figure 33 or the semiconductor device 1001. As Figure 37 shown, in the diode region 120, the diode trench gate 121 extends from one end side of the unit region, that is, the diode region 120, toward the opposite end side along the first main surface of the semiconductor device 1000 or the semiconductor device 1001. The diode trench gate 121 is constituted by disposing a diode trench electrode 121a in a trench of the semiconductor substrate formed in the diode region 120 with a diode trench insulating film 121b interposed therebetween. The diode trench electrode 121a faces the n - -type drift layer 91 with the diode trench insulating film 121b interposed therebetween. A p + -type contact layer 124 and a p-type anode layer 125 are provided between two adjacent diode trench gates 121.

[0192] The p + -type contact layer 124 is a semiconductor layer having, for example, boron (B) or aluminum (Al) as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 15 / cm 3 ~1.0×10 20 / cm 3 . The p-type anode layer 125 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 12 / cm 3 ~1.0×10 19 / cm 3 . The p + -type contact layer 124 and the p-type anode layer 125 are alternately provided along the length direction of the diode trench gate 121.

[0193] <Local Cross-sectional Structure>

[0194] Figure 38 It is Figure 37 a sectional view in the vector direction at the C-C line in Figure 38As shown, the semiconductor device 1000 or the semiconductor device 1001 also has an n-type drift layer 1 made of a semiconductor substrate in the diode region 120, similar to the IGBT region 110. - The n-type drift layer 1 of the diode region 120 and the n-type drift layer 1 of the IGBT region 110 are continuously formed integrally and are made of the same semiconductor substrate. - In - this case, the semiconductor substrate ranges from the p-type contact layer 124 to the n-type cathode layer 126. Figure 38 In + this case, the upper end of the p-type contact layer 124 on the paper surface is referred to as the first main surface of the semiconductor substrate, and the lower end of the n-type cathode layer 126 on the paper surface is referred to as the second main surface of the semiconductor substrate. The first main surface of the diode region 120 is coplanar with the first main surface of the IGBT region 110, and the second main surface of the diode region 120 is coplanar with the second main surface of the IGBT region 110. + In Figure 38 this case, the upper end of the p-type contact layer 124 on the paper surface is referred to as the first main surface of the semiconductor substrate, and the lower end of the n-type cathode layer 126 on the paper surface is referred to as the second main surface of the semiconductor substrate. The first main surface of the diode region 120 is coplanar with the first main surface of the IGBT region 110, and the second main surface of the diode region 120 is coplanar with the second main surface of the IGBT region 110. + type contact layer 124 to the n + type cathode layer 126. In

[0195] As Figure 38 shown, in the diode region 120, similar to the IGBT region 110, an n-type carrier accumulation layer 92 is provided on the first main surface side of the n-type drift layer 91, and an n-type buffer layer 93 is provided on the second main surface side of the n-type drift layer 91. The n-type carrier accumulation layer 92 and the n-type buffer layer 93 provided in the diode region 120 have the same structure as the n-type carrier accumulation layer 92 and the n-type buffer layer 93 provided in the IGBT region 110. In addition, the following structure can also be adopted, that is, it is not necessary to provide an n-type carrier accumulation layer 92 in the IGBT region 110 and the diode region 120. Even when an n-type carrier accumulation layer 92 is provided in the IGBT region 110, a structure in which the n-type carrier accumulation layer 92 is not provided in the diode region 120 can be adopted. Also, similar to the IGBT region 110, the n - type drift layer 91, the n-type carrier accumulation layer 92, and the n-type buffer layer 93 can also be collectively referred to as the drift layer. - type drift layer 91, the n-type carrier accumulation layer 92, and the n-type buffer layer 93 can also be collectively referred to as the drift layer. - type drift layer 91, the n-type carrier accumulation layer 92, and the n-type buffer layer 93 can also be collectively referred to as the drift layer.

[0196] An p-type anode layer 125 is provided on the first main surface side of the n-type carrier accumulation layer 92. The p-type anode layer 125 is provided on the n -Between the p-type drift layer 91 and the first main surface. Regarding the p-type anode layer 125, the concentration of the p-type impurity can also be set to the same concentration as that of the p-type base layer 115 in the IGBT region 110, so that the p-type anode layer 125 and the p-type base layer 115 are formed simultaneously. Additionally, it can also be configured such that the concentration of the p-type impurity in the p-type anode layer 125 is lower than the concentration of the p-type impurity in the p-type base layer 115 in the IGBT region 110, reducing the amount of holes injected into the diode region 120 during diode operation. By reducing the amount of injected holes during diode operation, the recovery loss during diode operation can be reduced.

[0197] On the first main surface side of the p-type anode layer 125, a p + -type contact layer 124 is provided. The p + -type contact layer 124 can have the same concentration of p-type impurity as that of the p + -type contact layer 114 in the IGBT region 110, or a different concentration. The p + -type contact layer 124 constitutes the first main surface of the semiconductor substrate. In addition, the p + -type contact layer 124 is a region with a higher concentration of p-type impurity than the p-type anode layer 125. When it is necessary to distinguish between the p + -type contact layer 124 and the p-type anode layer 125, they can be referred to separately, or the p + -type contact layer 124 and the p-type anode layer 125 can be collectively referred to as the p-type anode layer.

[0198] In the diode region 120, an n + -type cathode layer 126 is provided on the second main surface side of the n-type buffer layer 93. The n + -type cathode layer 126 is provided between the n - -type drift layer 91 and the second main surface. The n + -type cathode layer 126 is a semiconductor layer having, for example, arsenic or phosphorus as the n-type impurity, and the concentration of the n-type impurity is 1.0×10 16 / cm 3 ~1.0×10 21 / cm 3 . As shown in Figure 38 , the n + -type cathode layer 126 is provided in a part or all of the diode region 120. The n + -type cathode layer 126 constitutes the second main surface of the semiconductor substrate. In addition, although not shown, as described above, p-type impurity can be selectively injected further into the region where the n + -type cathode layer 126 is formed, and a p-type cathode layer can be provided with a part of the region where the n + -type cathode layer 126 formed as a p-type semiconductor. In this way, the n+ type cathode layer and p + A diode in which type cathode layers are alternately arranged along the second main surface of a semiconductor substrate is called an RFC (Relaxed Field of Cathode) diode.

[0199] As Figure 38 shown, in the diode region 120 of the semiconductor device 1000 or the semiconductor device 1001, a trench is formed that penetrates the p-type anode layer 125 from the first main surface of the semiconductor substrate and reaches the n - type drift layer 91. A diode trench gate 121 is formed by disposing a diode trench electrode 121a in the trench of the diode region 120 with a diode trench insulating film 121b interposed therebetween. The diode trench electrode 121a faces the n - type drift layer 91 with the diode trench insulating film 121b interposed therebetween.

[0200] As Figure 38 shown, a barrier metal 95 is disposed above the diode trench electrode 121a and the p + type contact layer 124. The barrier metal 95 makes an ohmic contact with the diode trench electrode 121a and the p + type contact layer 124 and is electrically connected to the diode trench electrode and the p + type contact layer 124. The barrier metal 95 may have the same structure as the barrier metal 95 in the IGBT region 110. An emitter electrode 96 is disposed above the barrier metal 95. The emitter electrode 96 disposed in the diode region 120 is formed continuously with the emitter electrode 96 disposed in the IGBT region 110. In addition, similar to the case of the IGBT region 110, the barrier metal 95 may not be provided, and the diode trench electrode 121a and the p + type contact layer 124 may make an ohmic contact with the emitter electrode 96. In addition, in Figure 38 , a diagram is shown in which an interlayer insulating film 94 is not disposed above the diode trench electrode 121a of the diode trench gate 121, but the interlayer insulating film 94 may be formed above the diode trench electrode 121a of the diode trench gate 121. In the case where the interlayer insulating film 94 is formed above the diode trench electrode 121a of the diode trench gate 121, it is only necessary to electrically connect the emitter electrode 96 and the diode trench electrode 121a in other cross-sections.

[0201] A collector electrode 97 is disposed on the second main surface side of the n + type cathode layer 126. Similar to the emitter electrode 96, the collector electrode 97 in the diode region 120 is formed continuously with the collector electrode 97 disposed in the IGBT region 110. The collector electrode 97 makes an ohmic contact with the n + type cathode layer 126 and is in contact with the n+ is electrically connected to the type cathode layer 126.

[0202] Figure 39 is Figure 37 a vector sectional view at the D-D line in Figure 39 The sectional structure of the diode region 120 shown is a sectional structure along the arrangement direction of the p-type anode layer 125, and thus is different from Figure 38 in that a p+-type contact layer 124 is not provided between the p-type anode layer 125 and the barrier metal 95, and the p-type anode layer 125 constitutes the first main surface of the semiconductor substrate. That is, as shown in Figure 37 the p+-type contact layer 124 is selectively provided on the first main surface side of the p-type anode layer 125.

[0203] Figure 40 is Figure 32 a vector sectional view at the G-G line of the semiconductor device 1000 shown in Figure 33 or the semiconductor device 1001 shown in, showing the structure of the boundary portion between the IGBT region 110 and the diode region 120.

[0204] As Figure 40 shown, the p-type collector layer 116 provided on the second main surface side of the IGBT region 110 is provided to extend a distance U1 from the boundary between the IGBT region 110 and the diode region 120 toward the diode region 120. Thus, by providing the p-type collector layer 116 to extend toward the diode region 120, the distance between the n + type cathode layer 126 and the active trench gate 111 can be increased, and even when a gate drive voltage is applied to the active trench gate 111 during the operation of the freewheeling diode, current flowing from the channel formed adjacent to the active trench gate 111 of the IGBT region 110 to the n + type cathode layer 126 can be suppressed. The distance U1 can be, for example, 100 μm. In addition, depending on the use of the RC-IGBT, that is, the semiconductor device 1000 or the semiconductor device 1001, the distance U1 can also be zero or a distance less than 100 μm.

[0205] <Structure of the terminal region>

[0206] Figure 41 is Figure 32 a vector sectional view at the E-E line of the semiconductor device 1000 shown in Figure 33 or the semiconductor device 1001 shown in, showing the structure of the boundary portion between the IGBT region 110 and the terminal region 130.

[0207] As Figure 41As shown, the end region 130 of the semiconductor device 1000 or the semiconductor device 1001 has an n - -type drift layer 91 between the first main surface and the second main surface of the semiconductor substrate. The first main surface and the second main surface of the end region 130 are coplanar with the first main surface and the second main surface of the IGBT region 110 and the diode region 120, respectively. In addition, the n - -type drift layer 91 of the end region 130 has the same structure as the n - -type drift layers 91 of the respective IGBT regions 110 and diode regions 120, and is formed continuously and integrally with them.

[0208] On the first main surface side of the n - -type drift layer 91, that is, between the first main surface of the semiconductor substrate and the n - -type drift layer 91, a p-type end well layer 131 is provided. The p-type end well layer 131 is a semiconductor layer having, for example, boron (B) or aluminum (Al) as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 14 / cm 3 ~1.0×10 19 / cm 3 . The p-type end well layer 131 is provided so as to surround the cell region including the IGBT region 110 and the diode region 120. The p-type end well layer 131 is provided in a plurality of rings, and the number of the p-type end well layers 131 provided is appropriately selected according to the breakdown voltage design of the semiconductor device 1000 or the semiconductor device 1001. In addition, an n + -type channel cutoff layer 132 is provided on the outermost edge side of the p-type end well layer 131, and the n + -type channel cutoff layer 132 surrounds the p-type end well layer 131.

[0209] On the second main surface of the semiconductor substrate, a p-type end collector layer 116a is provided between the n - -type drift layer 91 and the second main surface of the semiconductor substrate. The p-type end collector layer 116a is formed continuously and integrally with the p-type collector layer 116 provided in the cell region. Therefore, the p-type end collector layer 116a may also be included and referred to as the p-type collector layer 116.

[0210] On the second main surface of the semiconductor substrate, a collector electrode 97 is provided. The collector electrode 97 is formed continuously and integrally from the cell region including the IGBT region 110 and the diode region 120 to the end region 130. On the other hand, an emitter electrode 96 continuous from the cell region and an end electrode 96a separated from the emitter electrode 96 are provided on the first main surface of the semiconductor substrate in the end region 130.

[0211] The emitter electrode 96 is electrically connected to the terminal electrode 96a via the semi-insulating film 133. The semi-insulating film 133 can be, for example, sinSiN (semi-insulating Silicon Nitride). The terminal electrode 96a is electrically connected to the p-type terminal well layer 131 and the n + -type channel cutoff layer 132 via contact holes formed in the interlayer insulating film 94 on the first main surface provided in the terminal region 130. In addition, in the terminal region 130, a terminal protective film 134 is provided to cover the emitter electrode 96, the terminal electrode 96a, and the semi-insulating film 133. The terminal protective film 134 can be formed of polyimide, for example.

[0212] Figure 42 is Figure 32 a vector sectional view at the F-F line of the semiconductor device 1000 shown or Figure 33 the semiconductor device 1001 shown, showing the structure of the boundary portion between the IGBT region 110 and the terminal region 130.

[0213] As Figure 42 shown, the end portion of the p-type terminal collector layer 116a on the diode region 120 side extends toward the diode region 120 by a distance U2. Thus, by arranging the p-type terminal collector layer 116a to extend toward the diode region 120, the distance between the n + -type cathode layer 126 and the p-type terminal well layer 131 can be increased, and the p-type terminal well layer 131 can be prevented from operating as the anode of the diode. The distance U2 can be 100 μm, for example.

[0214] In addition, the present invention can freely combine the respective embodiments within the scope of the present invention, or appropriately deform or omit the respective embodiments.

[0215] Description of reference numerals

[0216] 1 n - -type drift layer, 2 p-type channel doping layer, 3 n + -type source layer, 4 p + -type contact layer, 5 p-type anode layer, 8 buried gate electrode, 10 n-type buffer layer, 11 p-type collector layer, 13 emitter electrode, 14 collector electrode, 15 contact hole, 16 p-type well layer, 101 IGBT region, 102 FWD region, 103 peripheral region, 106 IGBT channel region, 107 IGBT non-channel region.

Claims

1. A semiconductor device, which is a semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate, wherein, The semiconductor substrate has: a transistor region in which the transistor is formed; a diode region in which the diode is formed; and an outer peripheral region that surrounds a cell region including the transistor region and the diode region, the transistor region is divided by a plurality of strip-shaped gate electrodes into a plurality of channel regions where channels are formed and a plurality of non-channel regions where the channels are not formed, the plurality of channel regions have: a first semiconductor layer of a first conductivity type, which is provided on the second main surface side of the semiconductor substrate; a second semiconductor layer of a second conductivity type, which is provided on the first semiconductor layer; a third semiconductor layer of the first conductivity type, which is provided closer to the first main surface of the semiconductor substrate than the second semiconductor layer; a fourth semiconductor layer of the second conductivity type, which is selectively provided in an upper portion of the third semiconductor layer; a fifth semiconductor layer of the first conductivity type, which is selectively provided in such a manner that side surfaces thereof are in contact with side surfaces of the fourth semiconductor layer; a first electrode, which is electrically connected to the first semiconductor layer; and a second electrode, which is electrically connected to the fourth semiconductor layer and the fifth semiconductor layer, at least one non-channel region among the plurality of non-channel regions is a first non-channel region, and the first non-channel region has: the first semiconductor layer; the second semiconductor layer; the third semiconductor layer; the fifth semiconductor layer; the first electrode; and the second electrode, in the first non-channel region, the third semiconductor layer and the fifth semiconductor layer are electrically connected to the second electrode via a contact hole, the fifth semiconductor layer is selectively provided in an upper portion of the third semiconductor layer so as not to contact an impurity layer of the first conductivity type, and the impurity layer of the first conductivity type is provided in the outer peripheral region and defines a boundary with the cell region.

2. The semiconductor device according to claim 1, wherein, the plurality of non-channel regions include a second non-channel region, the second non-channel region has: the first semiconductor layer; the second semiconductor layer; the third semiconductor layer; the fifth semiconductor layer; the first electrode; and the second electrode, in the second non-channel region, the third semiconductor layer and the fifth semiconductor layer are electrically connected to the second electrode via the contact hole, the fifth semiconductor layer is selectively provided in an upper portion of the third semiconductor layer so as to contact the impurity layer in the outer peripheral region.

3. The semiconductor device according to claim 1 or 2, wherein, In the first non-channel region, the ratio of the area of the fifth semiconductor layer in a plan view to the total area of the third semiconductor layer and the fifth semiconductor layer in the plan view is smaller than the ratio of the area of the third semiconductor layer in the plan view to the total area.

4. The semiconductor device according to claim 1, wherein, The fifth semiconductor layer in the first non-channel region is disposed at a position opposite to the fourth semiconductor layer in the channel region separated from the gate electrode in a plan view.

5. The semiconductor device according to claim 1, wherein, the plurality of non-channel regions include a second non-channel region, the second non-channel region has: the first semiconductor layer; the second semiconductor layer; the third semiconductor layer; the fifth semiconductor layer; the first electrode; and the second electrode, In the second non-channel region, the fifth semiconductor layer is disposed on the entire upper surface of the third semiconductor layer in contact with the impurity layer in the outer peripheral region, and is electrically connected to the second electrode via the contact hole.

6. The semiconductor device according to claim 1 or 2, wherein, The first non-channel region is disposed adjacent to the diode region.

7. The semiconductor device according to claim 1, wherein, Regarding the fifth semiconductor layer in the first non-channel region, the shape in a plan view is an elongated rectangle extending along the extending direction of the plurality of gate electrodes, and a plurality of them are provided. The fifth semiconductor layers in the plurality of first non-channel regions are arranged at intervals so as to form a line along their length directions. The interval is set to be shorter than the length in the length direction.

8. The semiconductor device according to claim 1, wherein, The fifth semiconductor layer in the first non-channel region is disposed such that the shape in a plan view is a continuous linear shape extending along the extending direction of the plurality of gate electrodes.

9. The semiconductor device according to claim 1, wherein, Regarding the plurality of channel regions and the plurality of non-channel regions, The channel regions and the non-channel regions are alternately arranged.

10. The semiconductor device according to claim 1, wherein, The plurality of channel regions and the plurality of non-channel regions are arranged such that the arrangement ratio of the plurality of channel regions in the transistor region is smaller than the arrangement ratio of the plurality of non-channel regions.

11. The semiconductor device according to claim 10, wherein, The gate electrode sandwiched between two non-channel regions among the plurality of gate electrodes is connected to the potential of the second electrode.

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