Methods and systems for determining timing paths and coordinating topologies in superconducting circuit designs

Abstract

Systems and methods are provided for determining timing paths and coordinating topologies in a superconducting circuit design. The design may include a first timing path having a first set of timing pins associated with a first set of timing constraints, the first set of timing constraints including a first timing endpoint and a second timing endpoint. An example method includes processing (step 1510) the first set of timing constraints to assign a first valid start time to the first timing endpoint and a second valid start time to the second timing endpoint. The method also includes inserting (step 1520) a first shaded element (FIG. 9:914) representing a first physical connection component on the timing path, wherein the first shaded element precedes the first timing endpoint or follows the second timing endpoint. The method also includes resolving (step 1530) any changes to the first or second valid start time caused by the insertion of the first shaded element on the timing path.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to the field of computers, and more specifically, to a method and system for determining timing paths and coordinating topologies in superconducting circuit design. Background Technology

[0002] Semiconductor-based integrated circuits used in electronic devices such as digital processors include digital circuits based on complementary metal-oxide-semiconductor (CMOS) technology. However, CMOS technology is reaching its limits in terms of device size. Furthermore, the power consumption of CMOS-based digital circuits at high clock speeds is increasingly becoming a limiting factor for high-performance digital circuits and systems. For example, servers in data centers consume increasingly more power. Even when CMOS circuits are inactive, power consumption is partly due to power loss caused by energy dissipation. This is because even when such circuits are inactive and do not consume any dynamic power, they still consume power to maintain the state of the CMOS transistors.

[0003] An additional approach to using CMOS-based processors and related components is to use superconducting logic-based components and devices. Superconducting logic-based circuits can also be used to process quantum information, such as qubits. Many superconducting logic circuits include Josephson junctions, which can be controlled using high-speed clocks or microwave signals. Such circuits may include active transmission elements, which can complicate the creation of a properly timed design. Summary of the Invention

[0004] In one aspect, this disclosure relates to a method implemented by a processor for determining a critical timing path in a superconducting circuit design, wherein the superconducting circuit design includes at least one logic gate, the at least one logic gate including at least one Josephson junction, and wherein the at least one logic gate has a first phase assigned to it in association with a clock signal used for timing the at least one logic gate. The method may include providing timing information regarding a plurality of source terminals of the at least one logic gate coupled to a first absorption terminal of the at least one logic gate. The method may further include using the processor to determine, based on the first phase assigned to the at least one logic gate and in view of the timing information, whether the first absorption terminal is reachable by a single-through-quantum (SFQ) pulse within a predetermined arrival time range.

[0005] In another aspect, this disclosure relates to a method implemented by a processor for determining a critical timing path in a superconducting circuit design, wherein the superconducting circuit design includes a plurality of logic gates, and wherein each of the plurality of logic gates includes at least one Josephson junction. The method may include: providing timing information regarding a plurality of source terminals associated with the plurality of logic gates. The method may further include: receiving a selection from a plurality of absorb terminals associated with a target logic gate, the target logic gate being selected from the plurality of logic gates. The method may further include: receiving a phase assignment to the target logic gate. The method may further include: for each of a plurality of absorber terminals: using a processor, determining whether each of the plurality of absorber terminals is reachable by a corresponding single-through-quantum (SFQ) pulse within a predetermined arrival time range; and if the first absorber terminal is not reachable within the predetermined arrival time range, inserting a Josephson transmission line (JTL) between the source terminal associated with the target logic gate and the first absorber terminal determined to be unreachable within the predetermined arrival time range; and, upon determining that the first absorber terminal is reachable, removing the first absorber terminal from the plurality of absorber terminals associated with the critical timing path within the predetermined arrival time range after inserting the JTL.

[0006] In another aspect, this disclosure relates to a system configured to determine a critical timing path in a superconducting circuit design, wherein the superconducting circuit design includes at least one logic gate, the at least one logic gate including at least one Josephson junction, and wherein the at least one logic gate has a first phase assigned to it in association with a clock signal used for timing the at least one logic gate. The system may include a first subsystem configured to provide timing information regarding a plurality of source terminals of the at least one logic gate coupled to a first absorption terminal of the at least one logic gate. The system may also include a second subsystem, including a processor, configured to determine, based on the first phase assigned to the at least one logic gate and in view of the timing information, whether the first absorption terminal can be reached by a single-flux quantum (SFQ) pulse within a predetermined arrival time range.

[0007] In another aspect, this disclosure relates to a method implemented by a processor for determining timing paths and coordinating topologies in a superconducting circuit design, wherein the superconducting circuit design includes a first timing path comprising a first set of timing pins, and wherein a first subset of the first set of timing pins is associated with a first set of timing constraints, the first set of timing constraints including a first timing endpoint and a second timing endpoint. The method may include: using the processor, processing the first set of timing constraints to assign a first valid start time to the first timing endpoint and a second valid start time to the second timing endpoint. The method may further include: inserting a first shading element representing a first physical connection component on the timing path, wherein the first shading element precedes the first timing endpoint or follows the second timing endpoint. The method may further include: resolving any changes to the first or second valid start time caused by the insertion of the first shading element on the timing path.

[0008] In another aspect, this disclosure relates to a method implemented by a processor for determining timing paths and coordinating topologies in a superconducting circuit design, wherein the superconducting circuit design includes a first timing path, the first timing path including a first timing endpoint associated with a first circuit component and a second timing endpoint associated with a second circuit component, and wherein each of the first and second circuit components includes a Josephson junction, and wherein the first circuit component is assigned a first phase and the second circuit component is assigned a second phase. The method may include: using the processor, determining a first valid start time for the first timing endpoint on the timing path, and determining a second valid start time for the second timing endpoint on the timing path. The method may further include: inserting a first shading element representing a first physical connection component on the timing path, wherein the first shading element precedes the first circuit component on the timing path. The method may further include: inserting a second shading element representing a second physical connection component on the timing path, wherein the second shading element follows the second circuit component on the timing path. The method may further include: resolving any changes in the first and second valid start times caused by the insertion of the first and second shading elements on the timing path.

[0009] In another aspect, this disclosure relates to a system configured to determine timing paths and coordinate topologies in a superconducting circuit design, wherein the superconducting circuit design includes a first timing path comprising a first timing endpoint associated with a first circuit component and a second timing endpoint associated with a second circuit component, and wherein each of the first and second circuit components includes a Josephson junction, and wherein the first circuit component is assigned a first phase and the second circuit component is assigned a second phase. The system may include: a processor; and a memory including instructions. The instructions may be configured to: (1) determine a first valid start time of the first timing endpoint on the timing path and determine a second valid start time of the second timing endpoint on the timing path, (2) insert a first shadow element representing a first physical connection component on the timing path, wherein the first shadow element precedes the first circuit component on the timing path, (3) insert a second shadow element representing a second physical connection component on the timing path, wherein the second shadow element follows the second circuit component on the timing path, and (4) resolve any changes in the first and second valid start times caused by the insertion of the first and second shadow elements on the timing path.

[0010] This summary is provided to present a simplified description of the selection of concepts further described below. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. Attached Figure Description

[0011] This disclosure is illustrated by way of example and is not limited to the accompanying drawings, wherein the same reference numerals indicate similar elements. The elements in the drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale.

[0012] Figure 1 It is a block diagram based on an example system environment;

[0013] Figure 2 It is a block diagram based on an example object model;

[0014] Figure 3 A diagram is shown, based on an example, including a timing component and its relationship to an object model;

[0015] Figure 4 This illustrates an example that can be used to implement and Figure 1 The computing platform with functions related to the system environment;

[0016] Figure 5 A schematic diagram of an example logic circuit being timed is shown, based on an example example.

[0017] Figure 6 This is a flowchart 600 illustrating an example method for determining the validity of timing paths in a superconducting circuit design;

[0018] Figure 7 This is a flowchart 700, based on another example, of a method for determining and solving critical timing paths in superconducting circuit design;

[0019] Figure 8 A circuit diagram is shown representing an example of a timing constraint group (TCG), which includes timing pins as part of the constraint group;

[0020] Figure 9 The diagram shown includes a shaded component corresponding to a timing constraint group (TCG) as part of an example superconducting circuit design. Figure 8 Before or after the TCG;

[0021] Figure 10 It shows the direction to Figure 8 A diagram showing the addition of active transmission elements to a TCG.

[0022] Figure 11 This is a diagram showing the timing information and phase assignments for filling in other timing constraint groups, as well as additional JTLs (as needed);

[0023] Figure 12 This is based on an example shown. Figure 8 A diagram showing the timing changes in the head of a TCG.

[0024] Figure 13 This is based on an example shown. Figure 8 The timing variations of the remaining components of the TCG are plotted as the result of the solution steps.

[0025] Figure 14 This is a diagram illustrating timing variations of other TCGs, based on an example.

[0026] Figure 15 This is a flowchart illustrating an example method for determining timing paths and coordinating topologies in superconducting circuit design; and

[0027] Figure 16 This is a flowchart illustrating an example of a method for determining timing paths and coordinating topologies in a superconducting circuit design. Detailed Implementation

[0028] The examples described in this disclosure relate to systems and methods for determining timing paths and coordinating topologies in superconducting circuit designs. Certain other examples relate to systems and methods for determining critical timing paths in superconducting circuit designs. Superconducting circuits can use Josephson junctions to implement circuit-related functionality. An exemplary Josephson junction may comprise two superconductors coupled via regions that impede current. These impeding regions may be physical narrowings of the superconductors themselves, metallic regions, or thin insulating barriers. As an example, a superconductor-insulator-superconductor (SIS) type Josephson junction may be implemented as part of a superconducting circuit. As an example, a superconductor is a material that can carry direct current (DC) without an electric field. Superconductors have a critical temperature (Tc) below which their resistance is zero. Niobium is one such superconductor with a critical temperature (Tc) of 9.3 Kelvin. Below Tc, niobium is superconducting; however, above Tc, it behaves like a common metal with resistance. Therefore, in an SIS type Josephson junction, the superconductor may be a niobium superconductor, and the insulator may be an Al₂O₃ barrier. In SIS-type junctions, superconducting electrons are described by quantum mechanical wave functions. The phase difference between the phases of the superconducting electron wave functions of two superconductors, which varies with time, corresponds to the potential difference between the two superconductors.

[0029] Various superconducting circuits, including transmission lines, can be formed as needed by coupling multiple Josephson junctions via inductors or other components. Microwave pulses can propagate through these transmission lines under the control of at least one clock. Microwave pulses can be positive, negative, or a combination thereof. Microwave pulses can have frequencies up to 10 GHz or higher. Clock hands can also have frequencies up to 10 GHz or higher.

[0030] In one example, the logic of the circuit can be referred to as waveform pipeline logic, and the digital data can be encoded using a pair of positive and negative SFQ pulses. As an example, a single logic bit can be encoded as a pair of SFQ pulses generated in the positive and negative phases of a sinusoidal clock. A logic zero bit can be encoded by the absence of a positive / negative pulse pair during the clock cycle. A positive SFQ pulse can arrive during the positive portion of the clock, while a negative pulse can arrive during the negative portion. A positive SFQ pulse can arrive before the positive portion of the clock but will not propagate before the arrival of the positive clock. Similarly, a negative SFQ pulse can arrive before the negative portion of the clock but will not propagate before the arrival of the negative clock.

[0031] Some examples also involve timing designs for superconducting circuits based on phase-mode logic (PML). These superconducting circuits can also utilize devices based on PML. In PML-based devices, logic '1' can be encoded as phase high, and logic '0' can be encoded as phase low. The transition between phase high and phase low can be triggered by a single-flux quantum (SFQ) pulse event. In phase-mode logic-based superconducting circuits, digital values ​​can be encoded as Josephson junction (JJ) phases. A high phase can indicate logic '1', and a low phase can indicate logic '0'. Unlike waveform pipeline logic encoding, these values ​​remain constant throughout the clock cycle because no negative pulse is needed to reset the JJ phase. As an example, if an AC clock with four phases is used to power a phase-mode logic superconducting circuit, the output of the phase-mode logic circuit can remain constant across all four phases of the AC clock. In one example, the four-phase clock can be derived from two AC clock sources. The four phases of the clock can provide directionality for single-flux quantum (SFQ) pulses. Therefore, as an example, relative to a four-phase clock, a positive pulse can cross the leading edge of the clock from one phase to the next and arrive at the output after a delay period, while a negative pulse can follow half of the separation period. Other types of timing arrangements can also be used, including timing with more than four phases.

[0032] The building blocks of superconducting circuits can include various types of logic gates. Example logic gates include AND gates, OR gates, A-NAND-B (AanB) gates, and AND-OR (AndOr) gates. An AanB gate may have two inputs and one output (Q). Input pulse A may propagate to output Q unless input pulse B arrives first. An AndOr gate may have two inputs and two outputs (Q1 and Q2). The first input pulse, input pulse A, or input pulse B enters output Q1, and the second input pulse enters output Q2. The logical behavior of these gates can be based on the previously mentioned reciprocal data encoding or on the previously mentioned phase-mode logic-based data encoding.

[0033] Figure 1This is a block diagram of an example system environment 100. System environment 100 illustrates example blocks for performing methods and systems related to timing determination and phase assignment of superconducting circuits. System environment 100 may include a user interface (UI) block 110, a design block 120, a timing and phase block (TPB) 130, an object model 150, a component type system 160, and a timing library 170. UI block 110 may include code for enabling the user interface, which allows a designer or another user to interact with the system. As an example, UI block 110 may include code and data structures that allow a user to: determine the critical path in the superconducting circuit, assign phase, and modify the timing-related design of the superconducting circuit. Design block 120 may include at least one object that can specify design definitions related to various parameters associated with the timing-related design. As an example, design block 120 may be an object that specifies the frequency associated with the timing design. As another example, design block 120 may specify which timing library should be used with the superconducting circuit or a set of superconducting circuits associated with an integrated circuit.

[0034] Continue to refer to Figure 1 The TPB 130 may include a timing engine 132, a timing result 134, a circuit analyzer 136, and a delay determination 138. The timing engine 132 can calculate pulse propagation and timing constraints based on timing data. In this example, the output of the timing engine 132 may be a set of minimum hold times and maximum set times for each arc between timing pins (also called timing terminals) in each direction. This information may be stored as part of the timing result 134. The circuit analyzer 136 can determine the topology of the timing circuit and store this topology for processing by the delay determination 138. The delay determination 138 can process the topology, including gates in the timing path, to determine the delays between timing pins. The delays thus determined may be stored in a lookup table or another data structure. The timing engine 132 can look up the individual delays between pins from the lookup table or another data structure and sum the results. Additionally, as described later, the timing engine 132 may provide additional information, including data related to critical timing paths, topology, relaxation paths, and the number of added Josephson transmission line (JTL) elements. In this example, the timing engine 132 can be implemented as a set of callable methods that allow the output of timing-related calculations and generation for use with circuit designs. High-level aspects of the timing engine 132 may include the features shown in Table 1 below:

[0035]

[0036] Table 1

[0037] Still refer to Figure 1The object model 150 may include data structures and code to support timing-related definitions to abstract entities (such as logic gates or circuits) that require timing design.

[0038] Table 2 below lists examples of data structures and their example descriptions.

[0039]

[0040]

[0041] Table 2

[0042] Continue to refer to Figure 1 The Component Type System (CTS) 160 can be used to store data associated with relevant timing libraries (e.g., timing library 170). In this example, adding or changing data associated with a timing library will require a one-time reinitialization of CTS 160. Timing library 170 may include information about frequency, AC amplitude, and other parameters (regarding the logic gate types associated with the design). As an example, logic gates may correspond to waveform pipeline logic gates or phase-mode logic gates. In this example, the timing library may include JSON and Verilog definitions of logic gates. These definitions may include rising / falling tables that coincide with the clock and signal types (return-to-zero / non-return-to-zero, etc.). In one example, these definitions might be Verilog characteristics of the gates. Although... Figure 1 Some blocks included as part of system environment 100 are shown, but there may be additional or fewer blocks. As an example, system environment 100 may include reporting blocks that can be used to generate reports about timing design. As another example, system environment 100 may include additional timing libraries that may include similar information that can be used to support superconducting circuits built for operation at different temperatures or using different manufacturing processes. Other timing libraries may be used solely for testing purposes.

[0043] Figure 2 This is a block diagram based on an example object model 200. Object model 200 is... Figure 1 An example of object model 150. Object model 200 may include timing diagram 220. In this example of the object model, a timing diagram (e.g., timing diagram 220) is shown, but timing components are not shown. Timing components and their relationship to the object model are relative to... Figure 3 Description. In one example, timing diagram 220 can be implemented as the data structure shown in Table 3.

[0044]

[0045] Table 3

[0046] Continue to refer to Figure 2 TimingConstraintGroup 210 may include a set of connected timing constraints (e.g., timing constraint 212, timing constraint 214, and timing constraint 216). Example information covered by the data structure corresponding to TimingConstraint may include: BeginTimingPin, EndTimingPin, hold, and set. Therefore, in this example, the data structure may include information about the timing pin at the start of the timing constraint (e.g., a terminal associated with a logic gate) and the timing pin at the end of the timing constraint. The data structure may also include information about hold and set times. Table 4 shows an example of the information included in the data structure used to implement TimingConstraintGroup 210.

[0047]

[0048] Table 4

[0049] Still refer to Figure 2 As shown in Table 4, TimingConstraintGroup 210 may include a set of timing constraint-related information, including TimingConstraint 212, TimingConstraint 214, and TimingConstraint 216. Each of these can be implemented using a data structure, and each can point to a data structure associated with a timing pin to indicate that the timing constraint is associated with that specific timing pin or the set of timing pins. The following...

[0050] Table 5 shows a sample set of information included in the TimingConstraint data structure.

[0051]

[0052] Table 5

[0053] Each timing pin (or timing terminator) can also have a corresponding data structure, which can include information about items such as ExtraJTLs and information about the type of pin (or terminator) it is. As an example, each pin can be a source pin or a sink pin of a gate. Figure 2 The object model 200 shown includes timing pins: TimingPin 221, 222, 223, 224, 225, 226, 227, 228, and 229, each of which can have a corresponding data structure derived from the TimingPinBase data structure. In one example, the TimingPinBase data structure may include the information shown in Table 6 below.

[0054]

[0055]

[0056] Table 6

[0057] Continue to refer to Figure 2 Table 7 shows the information contained in the data structure corresponding to the source pin. In this example table, an arc refers to the timing relationship between the input and output times of each pin.

[0058]

[0059] Table 7

[0060] As shown above, Table 8 is an example of the information contained in the data structure corresponding to the absorb pin.

[0061]

[0062] Table 8

[0063] Figure 3 A block diagram of another timing object model 300 according to another example is shown. Object model 300 is Figure 1 An example of object model 150. In this example, timing diagrams and timing components are shown. In this example, earlier relative to Figure 2 The described similar data structures are used to model pin and timing constraints associated with an object model that corresponds to a circuit design including active transmission elements (such as JTL). Therefore, TimingGraph 310 can be implemented in a similar manner and with similar information as previously described with respect to Table 3. Similarly, TimingConstraintGroup 320 can be implemented using similar information as previously described with respect to Table 4. In this example, TimingConstraintGroup 320 can point to TimingConstraintPair 330. In one example, the information included in the data structure corresponding to TimingConstraintPair 330 is shown in Table 9 below.

[0064]

[0065] Table 9

[0066] Continue to refer to Figure 3Object model 300 may include timing components, including timing components 340, 350, 360, and 370, which can represent components to be timed and can be used to find relevant timing constraint groups for physically connected components in different timing diagrams during the coordination step. A graph is constructed using the timing components of all physically connected components on a timing path. The mapping of each graph can contain all the timing components owned by that graph. Except for the header, all components on a timing path are owned by their timing diagram. The header is owned by its predecessor timing diagram. Figure 3 The object model 300 shown includes timing pins: TimingPin 342, 344, 346, 348, 362, 366 and 368, each of which can have a corresponding data structure derived from TimingPinBase, as previously described with respect to Table 6.

[0067] Figure 4 It shows what can be used to implement with Figure 1 The system environment 100 includes a computing platform 400 with associated functions. The computing platform 400 may include processor(s) 402, I / O components(s) 404, memory 406, presentation components(s) 408, sensors(s) 410, database(s) 412, network interfaces(s) 414, and I / O ports(s) 416, which may be interconnected via a bus 420. The processor(s) 402 may execute instructions or code stored in memory 406. These instructions may correspond to various algorithms described in this disclosure. Therefore, the algorithms can be implemented using a programming language and compiled into an executable file, which can then be executed. The I / O components(s) 404 may include components such as a keyboard, mouse, voice recognition processor, or touchscreen. Memory 406 may be any combination of non-volatile storage devices or volatile storage devices (e.g., flash memory, DRAM, SRAM, or other types of memory). The presentation components(s) 408 may be any type of display, such as LCD, LED, or other types of displays, or other types of output components, including audio or haptic output components. (Multiple) sensors 410 may include audio sensors, optical sensors or other types of sensors.

[0068] Continue to refer to Figure 4Multiple databases 412 can be used to store timing libraries and other timing-related information. Additionally, multiple databases 412 can also store data used to generate reports related to the timing libraries. Multiple network interfaces 414 can include communication interfaces such as Ethernet, cellular radio, Bluetooth radio, UWB radio, or other types of wireless or wired communication interfaces. Multiple I / O ports 416 can allow the computing platform 400 to communicate with the bus 420 or multiple other I / O components 404. Although... Figure 4 The computing platform 400 is shown as comprising a number of components arranged and coupled in a certain manner, but it may include fewer components or additional components arranged and coupled differently. Furthermore, the functionality associated with the computing platform 400 may be distributed or composite, depending on the requirements. Moreover, not all aspects of the computing platform 400 may be necessary to implement the various methods described herein.

[0069] Figure 5 A schematic diagram of an example logic circuit 500 being timed is shown. The example logic circuit 500 may include an AND gate 510 and multiple JTLs. The AND gate 510 may include two input terminals: ai and bi, and an output terminal: ao. JTLs 512 and 514 may be coupled to the input terminal ai, as shown below. Figure 5 As shown. Figure 5 As shown, JTL 516 and 518 can be coupled to input terminal bi. JTL 520 can be coupled to output JTL 516. Although not shown in the figure, JTL 520 can be used to couple logic circuit 500 to (multiple) other logic circuits. JTL 524 can be coupled to output terminal ao, as shown. Figure 5 As shown. Additional JTLs can be coupled as needed; for example, JTL 526 and JTL 528 can be coupled to JTL 524. JTL 526 and JTL 528 can be used to couple logic circuit 500 to (multiple) other logic circuits. For example... Figure 5 As shown, each JTL and logic gate included in logic circuit 500 can have an initial phase assignment. Assuming this example circuit operates with a four-phase clock, the phase assignments include 0 degrees, 90 degrees, 180 degrees, and 270 degrees. Logic circuits driven by clocks including fewer or more phases can also be designed. A single-through-quantum pulse can reach the input terminals of AND gate 510 via JTLs coupled to their respective input terminals. After being processed by AND gate 510, the SFQ pulse representing the logical AND value can be output via the output terminal. To ensure the correct operation of logic circuit 500, instructions corresponding to the algorithm stored in memory 406, when executed by processor(s) 402, can help the designer design the timing and phase assignment aspects of logic circuit 510. Example algorithms are shown in Table 10 below.

[0070]

[0071]

[0072] Table 10

[0073] The steps shown in Table 10 can be performed on every logic gate included in the design (e.g., logic gate 510 of logic circuit 500). The steps shown in Table 10 are relevant to any gate G that includes C number of snubber pins. The first step may include finding the snubber pin with the maximum rise time (MRT) for any arriving SFQ pulse from the set of C snubber pins. In one example, the MRT may be determined by the processor performing a step of looking up a table where the MRT value is stored. In step 2 of Table 10, the phase associated with the gate can be changed to P+ as needed. As an example, while the assignment of phase 0 may apply to one snubber pin of the gate, it may not apply to other snubber pins. In this case, the phase assigned to the gate can be increased by 90 degrees (assuming the logic circuit being designed is timed by a four-phase AC clock, where the next phase assignment is 90 degrees). If the phase assigned to the gate changes (e.g., increased by 90 degrees), then the phase assigned to downstream gates and JTLs is invalid.

[0074] Referring again to Table 10, in step 3, the target time T for the selected phase assignment can be assigned to the logic gate. In step 4, for each snub pin, the algorithm can determine whether the snub pin is reachable by time T, starting from a path without a JTL insertion. If the snub pin is unreachable, then an additional JTL can be inserted. Therefore, if logic gate 510 is initially assigned a 90-degree phase, and if the input terminal ai of logic gate 510 (one of the snub pins of the gate) is unreachable within time T (i.e., MRT is greater than T), then an additional JTL can be inserted. As an example, an additional buffer (e.g., JTL 514) can be inserted into the path leading to one of the snub pins. The delay associated with the sequence of buffers with added JTLs can be looked up in a lookup table. If MRT is still greater than T, then the snub pin is still unreachable by time T. A phase can be assigned to each buffer (e.g., each JTL) for the logic gate, starting from the phase of the source pin. As an example, if a 0-degree phase assignment for the logic gate does not work, then it can be assigned a 90-degree phase.

[0075] Continuing the algorithm description in Table 10, the component graph can be created for the logic circuit being designed using the CreateComponentGraph method. As an example, the component graph can be created for logic circuit 500. Next, the algorithm may include calling the RunLengthChecker method, which can create different reports based on the JTL added for timing. Next, the algorithm may include calling the WithinReach method to determine if an absorb pin is reachable from the target time T. If the absorb pin is reachable, it can be removed from C number of gates. If C is empty and all absorb pins associated with logic gate G have been processed, then in step 5, the critical path is identified as the last absorb pin removed from C. If C is not empty, then, as part of step 6 (in this example), the algorithm returns to step 2. After the critical path is determined, the logic gates and JTL require phase assignment. An example algorithm for phase assignment is described relative to Table 11.

[0076]

[0077] Table 11

[0078] As shown in Table 11, unless already determined, the first step requires identifying the critical path for the gate being processed. Next, in step 2, phases can be assigned to various JTLs and gates based on the critical path. As an example, as previously described relative to Table 10, phase assignments can change during the determination of the critical path. Using these phase assignments, in step 3, a method called ArePinRelativePhasesValid is invoked to determine whether the phase assignment is valid. This method can consider the logic of the superconducting circuit, including whether the logic is waveform pipeline logic or phase-mode logic.

[0079] Referring again to Table 11, the next step involves adding an additional JTL with assigned phase to disable constraints on critical pins. This may alter the gate's primary phase assignment if a phase change is required or desired. Failures here include failure to route or failure to add another required JTL to meet timing. Another failure may be related to exceeding the legal arrival time range (e.g., due to adding a JTL to cover distance). The next step involves adding an additional JTL with assigned phase to disable non-critical pins. As an example, if the absorb pin corresponding to input ai is determined to be a critical path relative to logic circuit 500, then this step involves adding an additional JTL as needed to ensure correct timing relative to the absorb pin corresponding to input bi of AND gate 510.

[0080] Figure 6This is a flowchart 600 illustrating an example method for determining the validity of timing paths in a superconducting circuit design. In this example, the various steps listed as part of flowchart 600 can be... Figure 1 The timing engine 132 executes this step. Step 610 may include providing timing information about a plurality of source terminals of at least one logic gate coupled to a first absorb terminal of at least one logic gate. In one example, this information may be provided via... Figure 1 The timing library 170 provides this.

[0081] Step 620 may include: determining, based on a first phase assigned to at least one logic gate and in view of timing information, whether a first absorption terminal can be reached by a single-flux quantum (SFQ) pulse within a predetermined arrival time range. In this example, when the code / algorithm associated with timing engine 132 (e.g., stored in...) Figure 4 The code or algorithm in memory 406 is processed by a processor (e.g., Figure 4 When the (multiple) processors 402) execute, this step can be performed by the timing engine 132. When the timing engine 132 is loaded into memory (e.g., Figure 4 When the timing engine 132 is in the memory 406), it can access the timing library 170. As an example, the timing engine 132 can perform step 4 in the steps shown in Table 10 to determine, based on the first phase assigned to at least one logic gate, whether the first absorption terminal can be reached by a single-through-quantum (SFQ) pulse within a predetermined arrival time range, given the timing information. Although Figure 6 A specific number of steps are shown to be performed in a particular order, but method 600 may include more or fewer steps performed in a different order.

[0082] Figure 7 This is a flowchart 700, based on another example, of a method for determining and solving critical timing paths in superconducting circuit design. In this example, the various steps listed as part of flowchart 700 can be derived by... Figure 1 The timing engine 132 executes this step. Step 710 may include providing timing information about multiple source terminals associated with multiple logic gates. In one example, this information may be provided via... Figure 1 The timing library 170 associated with system 100 is provided to timing engine 132.

[0083] Step 720 may include receiving a selection from a plurality of snubber terminals associated with a target logic gate, the target logic gate being selected from the plurality of logic gates. In this example, when the code / algorithm associated with timing engine 132 (e.g., stored in...) Figure 4 The code or algorithm in memory 406 is processed by a processor (e.g., Figure 4When the (multiple) processors 402) are executing, this step can be performed by the timing engine 132. In this example, the timing engine 132 can perform step 1 shown in Table 10. Therefore, as an example, the timing engine 132 can find the snubber pin with the minimum maximum rise time (MRT) in the set of C snubber pins. In one example, the timing engine 132 can do this by looking up a lookup table (which can be stored in...). Figure 4 The absorption pin is located in memory 406.

[0084] Step 730 may include receiving a phase assignment to the target logic gate. In this example, when the code / algorithm associated with the timing engine 132 (e.g., stored in...) Figure 4 The code or algorithm in memory 406 is processed by a processor (e.g., Figure 4 When executed by the (multiple) processors 402, this step can be performed by the timing engine 132. In this example, the timing engine 132 can perform step 1 shown in Table 10. Therefore, as an example, the timing engine 132 can assign an initial phase to the target logic gate. As an example, logic gate 510 is initially assigned a phase of 180 degrees relative to logic circuit 500. This phase assignment may vary based on topological changes in the design of logic circuit 500.

[0085] Step 740 may include, for each of a plurality of absorber terminals: (1) determining whether each of the plurality of absorber terminals is reachable by a corresponding single-through-quantum (SFQ) pulse within a predetermined arrival time range, and (2) if the first absorber terminal is not reachable within the predetermined arrival time range, inserting a Josephson transmission line (JTL) between the source terminal associated with the target logic gate and the first absorber terminal determined to be unreachable within the predetermined arrival time range, and, upon determining that the first absorber terminal is reachable, removing the first absorber terminal from the plurality of absorber terminals associated with the critical timing path within the predetermined arrival time range after inserting the JTL. In this example, when the code / algorithm associated with timing engine 132 (e.g., stored in...) Figure 4 The code or algorithm in memory 406 is processed by a processor (e.g., Figure 4 When the (multiple) processors 402) execute, this step can be performed by the timing engine 132. In this example, the timing engine 132 can perform step 4 as shown in Table 10. Although Figure 7 The method illustrates a specific number of steps performed in a particular order, but may include more or fewer steps performed in a different order.

[0086] To decompose TimingPins into a set of runs that can be processed asynchronously, TimingConstraintGroups can be formed from a collection of connected TimingConstraints. A design can have multiple TimingConstraintGroups. Each design may have a large TimingConstraintGroup and several smaller TimingConstraintGroups. (As previously mentioned...) Figure 2 As explained in Tables 4 and 5, TimingConstraintGroup 210 may include a set of timing constraint-related information, including TimingConstraint 212, TimingConstraint 214, and TimingConstraint 216. Each of these may be implemented using a data structure, and each may point to a data structure associated with a timing pin to indicate that the timing constraint is associated with that particular timing pin or the set of timing pins. TimingGraph may point to the TimingPins graph within TimingConstraintGroup.

[0087] TimingGraph can be constructed from the timing components of all physically connected components along the timing path. Each graph has a mapping that contains all the timing components owned by that graph. All components along the timing path, except the header, are owned by their respective timing graphs. The header is owned by the timing graph of its predecessor. Table 12 provides examples of algorithms for solving and coordinating constraint groups.

[0088]

[0089]

[0090] Table 12

[0091] Step 1 involves identifying the critical path and assigning phase to the set of timing endpoints associated with all constraint groups being analyzed (e.g., timing constraint groups that may be part of a timing path). In this example, timing endpoints are pins that define individual timing "runs" that can be independently timed and verified based on their timing and phase constraints. They are defined by the circuit designer and are explicit components in the circuit design. Different types of timing endpoints can be specified depending on whether the logic associated with the circuit is implemented using phase-mode logic or waveform pipeline logic. For waveform pipeline logic circuits or phase-mode logic circuits, the presence or absence of arcs in the library data will indicate whether a timing pin is a start or end timing endpoint. In this example, the set of timing endpoints includes timing endpoints associated with timing pins that are part of the same timing constraint group. As an example, the timing pins associated with logic circuit 500 may be part of the same timing constraint group. The set of timing endpoints may also include timing endpoints associated with timing constraint groups within a specific number of hops. In one example, these groups may include groups that are two hops backward and one hop forward, or two hops forward and one hop backward. To analyze these timing pins, "shaded" elements can be created to represent physical connection elements on the timing path.

[0092] Referring again to Table 12, step 2 may include coordinating all TimingComponents. The winner of the coordination step is the value in the TimingConstraintGroup that "owns" the timing pin. For all timing components and tails in the path, it is their TimingConstraintGroup. For the head, and when it is the tail, it is the TimingConstraintGroup of the TimingComponent. Therefore, in summary, this step may include setting values ​​for other timing paths physically connected to that gate using the gate's timing path, coordinating differences in arrival times and signal propagation elements (e.g., JTL insertion).

[0093] Referring back to Table 12, step 3 involves determining if there are any changes to the timing and phase assignments. If there are changes, the algorithm returns to step 3. If there are no changes, the process involves solving the timing constraint set to ensure that the timing information and the phase assignments of additional components (e.g., additional JTL) are accurate within the timing constraint set. Therefore, using the algorithm described in Table 12, iteration can be performed to a convergent solution where the iteration causes the timing and phase assignments to become fixed and no longer require modification. The application of the algorithm described in Table 12 is relative to... Figures 8 to 13 A sample circuit is provided as a part of the example circuit.

[0094] Figure 8A circuit diagram representing an example timing constraint group (TCG) 800 is shown. This example timing constraint group includes timing pins as part of the constraint group, which can be processed using the solving and coordination algorithms described relative to Table 12. The TCG 800 may include buffers 812, 814, and 816, which can be coupled to... Figure 8 The input and output terminals of gate 810 are shown. From a timing analysis perspective, the TCG 800 includes three timing endpoints. The first two timing endpoints correspond to the inputs of buffers 812 and 814, and the third timing endpoint corresponds to the output of buffer 816. The TimingConstraintGroup data structure can be used to represent the relevant details of the timing analysis of the TCG 800. Solving and reconciliation algorithms can handle the timing design in light of timing constraints imposed by other circuits in the design. In one example, as part of this analysis, the components within the depth of the three timing endpoints (called the shaded components) can be included. Additionally, as part of this analysis, the true components within the depth of the three timing endpoints can also be included. This is because timing varies not only with changes in the shaded components but also with changes in the true components.

[0095] Figure 9 Figure 900 shows shaded components corresponding to a Timing Constraint Group (TCG), which precede or follow the TCG 800 as part of the superconducting circuit design. These shaded components are part of other timing constraint groups and are not timed, except that they need to be considered to solve and reconcile the TCG 800. In this example, two backward timing endpoints and one forward timing endpoint are included as part of the analysis. In this example, TCG 910 may include buffers 918, 920, and 922, which, as... Figure 9 The TCG 910 is coupled and arranged as shown. It may also include logic gates 912, 914, and 916, as shown... Figure 9 As shown, they are coupled and arranged. TCG 930 may include buffers 934 and 936 and gate 932, which can be coupled and arranged as shown. Figure 9 The elements shown are coupled and arranged. Figure 9 The initial phase assignments for buffers 812 and 814 associated with the two timing endpoints are also shown. In this example, the phase assignments for both buffers 812 and 814 are 0. The first valid start time for the 0-degree phase assignments of these two timing endpoints is determined to be 13 picoseconds (ps), as... Figure 9 The marked time. In this example, the legal start time is determined based on timing constraints identified through hardware analysis of the implemented buffers and gates.

[0096] Figure 10Figure 1000 illustrates the addition of an active transmission element to the TCG 800. (As shown) Figure 10 As shown, the TCG 800 uses critical path and phase assignment for the initial solution step (this step corresponds to step 1 of the algorithm in Table 12). In this example, this step involves performing steps 1 through 4 shown in Table 11 relative to the timing pin associated with gate 810 of the TCG 800. The result of performing these steps is the addition of an active transfer element (e.g., JTLs 1012, 1014, and 1016) between one of the inputs of buffer 812 and gate 810. Additionally, JTLs 1018 and 1020 are added between the other input of buffer 814 and gate 810. The phase assignment of gate 810 also changes from 0 degrees to 90 degrees. Similarly, the phase assignment of buffer 816 changes from 0 degrees to 90 degrees. Furthermore, the first valid start time for the 90-degree phase of buffer 816 is calculated to be 57 picoseconds (ps). In this example, the changes in the timing / phase information of the TCG 800 and the insertion of additional JTLs require altering the timing information of other timing constraint groups affected by these changes.

[0097] Figure 11 Figure 1100 illustrates the timing information and phase assignments for filling in other timing constraint groups, as well as additional JTLs (as needed). Therefore, in this example, TCG 910 is shown as including additional JTLs 1110, 1112, and 1114 added between gate 912 and buffer 918. Additionally, gate 912 has been assigned a valid start time of 60 ps and a phase of 180 degrees. Buffer 918 has been assigned a valid start time of 97 ps and a phase of 270 degrees. Gate 916 has been assigned a valid start time of 108 ps and a phase of 0 degrees. Furthermore, TCG 910 includes additional JTLs 1116, 1118, and 1120, which are added between gate 914 and the input of buffer 814 of TCG 800. Gate 914 has been assigned a valid start time of 90 ps. Additional JTL1122, 1124, 1126, and 1128 have been added between the output of buffer 922 and one of the snub pins of gate 914. Buffer 920 has been assigned a legal start time of 88 ps and a phase of 270 degrees, and buffer 922 has been assigned a legal start time of 51 ps and a phase of 90 degrees.

[0098] Continue to refer to Figure 11The TCG 930 is shown with additional JTLs 1132 and 1134. Gate 932 has been assigned a legal start time of 89 ps and a phase of 270 degrees. Buffer 934 has been assigned a legal start time of 60 ps and a phase of 90 degrees. Buffer 936 has been assigned a legal start time of 75 ps and a phase of 180 degrees. For the TCG 930, timing and phase assignments can be determined in a similar manner to those for the TCG 800.

[0099] Figure 12 Figure 1200 illustrates an example of timing changes in the head of the TCG 800. Thus, in this example, the legal start time of buffer 812 has changed from 13 ps to 18 ps, and the legal start time of buffer 814 has changed from 13 ps to 16 ps. These timing changes can be determined as part of a coordination step (e.g., step 3 of the algorithm in Table 12). Next, the timing and phase information associated with the remaining components—gate 810 and buffer 816 in the TCG 800—is cleared. The TCG 800 then proceeds with the solution step again.

[0100] Figure 13 Figure 1300 illustrates, as an example, the timing changes of the remaining components of TCG 800 as a result of the solution steps. In this example, the legal start time of gate 810 changes from 54 ps to 56 ps, and the legal start time of buffer 816 changes from 57 ps to 58 ps. Although the solution steps do not change the phase assignments of gate 810 and buffer 816, they can be changed if needed. Next, the timing and phase assignments associated with the shadow components in other TCGs are updated.

[0101] Figure 14Figure 1400 illustrates timing variations for other TCGs (e.g., TCG 910 and TCG 930) as an example. In this example, the step is performed as part of applying the algorithm described relative to Table 12 to update the timing and phase assignment of the shadow components. In this example, the valid start time of gate 912 changes from 60 ps to 61 ps; the valid start time of gate 914 changes from 90 ps to 91 ps; and the valid start time of gate 916 changes from 108 ps to 109 ps. The valid start time of buffer 918 remains unchanged (97 ps); the valid start time of buffer 920 changes from 88 ps to 89 ps; and the valid start time of buffer 922 changes from 51 ps to 52 ps. Relative to TCG 930, the valid start time of gate 932 changes from 89 ps to 90 ps. The valid start time of buffer 934 changes from 60 ps to 61 ps, and the valid start time of buffer 936 changes from 75 ps to 76 ps. The coordination steps can be repeated until no conflicts related to timing and phase assignments exist. As an example, aside from the legal start time associated with buffer 918 changing from 97 ps to 98 ps, subsequent coordination steps can keep all timings the same. Therefore, in this example, Figures 8 to 14 The algorithm shown in Table 12 is used to find a convergent solution, where the iteration of the algorithm causes the timing and phase assignments to be fixed and no longer need to be changed.

[0102] Figure 15 This is a flowchart 1500 of an example method for determining timing paths and coordinating topologies in a superconducting circuit design. In this example, the superconducting circuit design may include a first timing path comprising a first set of timing pins, and a first subset of the first set of timing pins may be associated with a first set of timing constraints comprising a first timing endpoint and a second timing endpoint. Step 1510 may include processing the first set of timing constraints to assign a first valid start time to the first timing endpoint and a second valid start time to the second timing endpoint. In this example, when the code / algorithm associated with timing engine 132 (e.g., stored in...) Figure 4 The code or algorithm in memory 406 is processed by a processor (e.g., Figure 4 When the processor(s) 402 are executed, this step can be performed by the timing engine 132. In this example, the timing engine 132 can perform step 1 relative to the algorithm described in Table 12. As an example, this step may include determining the legal start time of each timing endpoint(s) in the timing endpoint(s) using the previously described critical timing path algorithm.

[0103] Step 1520 may include inserting a first shadow element representing the first physical connection component on the timing path, wherein the first shadow element precedes the first timing endpoint or follows the second timing endpoint. In this example, when the code / algorithm associated with the timing engine 132 (e.g., stored in...) Figure 4 The code or algorithm in memory 406 is processed by a processor (e.g., Figure 4 When executed by (multiple) processors 402), this step can be performed by timing engine 132. In this example, timing engine 132 can be performed relative to... Figure 9 This step is performed in a similar manner to that described. Therefore, given the timing constraints imposed by other circuitry in the design, the timing engine 132 can process the timing design. In one example, as part of this analysis, components within the depth of the three timing endpoints (referred to as shadow elements or shadow components) can be included. The legal start times of these endpoints, including those as part of the shadow elements, and the phase assignments of gates or buffers can be obtained in a similar manner to that described earlier.

[0104] Step 1530 may include resolving any changes to the first or second valid start time caused by the insertion of the first shadow element on the timing path. In this example, when the code / algorithm associated with the timing engine 132 (e.g., stored in...) Figure 4 The code or algorithm in memory 406 is processed by a processor (e.g., Figure 4 When the (multiple) processors 402) execute, this step can be performed by the timing engine 132. In this example, the timing engine 132 can execute steps 2 and 3 as described in Table 12. As an example, these steps are relative to... Figures 10 to 14 exist Figure 8 The example timing constraint group 800 is described with the help of this example. Although Figure 15 The method illustrates a specific number of steps performed in a particular order, but may include more or fewer steps performed in a different order.

[0105] Figure 16This is a flowchart 1600 of an example method for determining timing paths and coordinating topologies in a superconducting circuit design. In this example, the superconducting circuit design may include a first timing path comprising a first timing endpoint associated with a first circuit component and a second timing endpoint associated with a second circuit component, wherein each of the first and second circuit components includes a Josephson junction. The first circuit component is assigned a first phase, and the second circuit component is assigned a second phase. Step 1610 may include: using a processor, determining a first valid start time for the first timing endpoint on the timing path, and determining a second valid start time for the second timing endpoint on the timing path. In this example, when the code / algorithm associated with timing engine 132 (e.g., stored in...) Figure 4 The code or algorithm in memory 406 is processed by a processor (e.g., Figure 4 When the processor(s) 402 are executed, this step can be performed by the timing engine 132. In this example, the timing engine 132 can perform step 1 relative to the algorithm described in Table 12. As an example, this step may include determining the legal start time of each timing endpoint(s) in the timing endpoint(s) using the previously described critical timing path algorithm.

[0106] Step 1620 may include inserting a first shaded element representing a first physical connection component on the timing path, wherein the first shaded element precedes the first circuit component on the timing path. In this example, when the code / algorithm associated with timing engine 132 (e.g., stored in...) Figure 4 The code or algorithm in memory 406 is processed by a processor (e.g., Figure 4 When executed by (multiple) processors 402), this step can be performed by timing engine 132. In this example, timing engine 132 can be performed relative to... Figure 9 This step is performed in a similar manner to that described. Therefore, given the timing constraints imposed by other circuitry in the design, timing engine 132 can process the timing design. In one example, as part of this analysis, components within the depth of the three timing endpoints (referred to as shadow elements or shadow components) may be included. As part of step 1620, the first shadow element may be part of a group of timing constraints along the timing path prior to the first circuit component. Therefore, in this example, the first shadow element may be... Figure 9 Gate 914. The valid start times of these endpoints, which are part of the shaded element, and the phase assignment of the gate or buffer can be obtained in a similar manner as previously described.

[0107] Step 1630 may include inserting a second shaded element representing the second physical connection component on the timing path, wherein the second shaded element follows the second circuit component on the timing path. In this example, when the code / algorithm associated with the timing engine 132 (e.g., stored in...) Figure 4 The code or algorithm in memory 406 is processed by a processor (e.g., Figure 4 When executed by (multiple) processors 402), this step can be performed by timing engine 132. In this example, timing engine 132 can be performed relative to... Figure 9 This step is performed in a similar manner to that described. Therefore, given the timing constraints imposed by other circuitry in the design, timing engine 132 can process the timing design. In one example, as part of this analysis, components within the depth of the three timing endpoints (referred to as shadow elements or shadow components) may be included. As part of step 1630, the second shadow element may be part of a group of timing constraints following the second circuit component on the timing path. Therefore, in this example, the second shadow element may be... Figure 9 Gate 934. The valid start times of these endpoints, which are part of the shaded element, and the phase assignment of the gate or buffer can be obtained in a similar manner as previously described.

[0108] Step 1640 may include resolving any changes to the first and second valid start times caused by the insertion of the first and second shadow elements on the timing path. In this example, when the code / algorithm associated with the timing engine 132 (e.g., stored in...) Figure 4 The code or algorithm in memory 406 is processed by a processor (e.g., Figure 4 When the (multiple) processors 402) execute, this step can be performed by the timing engine 132. In this example, the timing engine 132 can execute steps 2 and 3 as described in Table 12. As an example, these steps are relative to... Figures 10 to 14 exist Figure 8 The example timing constraint group 800 is described with the help of this example. Although Figure 16 The method illustrates a specific number of steps performed in a particular order, but may include more or fewer steps performed in a different order.

[0109] In summary, this disclosure relates to a method implemented by a processor for determining a critical timing path in a superconducting circuit design, wherein the superconducting circuit design includes at least one logic gate, the at least one logic gate including at least one Josephson junction, and wherein the at least one logic gate has a first phase assigned to it in association with a clock signal used for timing the at least one logic gate. The method may include providing timing information regarding a plurality of source terminals of the at least one logic gate coupled to a first absorption terminal of the at least one logic gate. The method may further include using the processor to determine, based on the first phase assigned to the at least one logic gate and in view of the timing information, whether the first absorption terminal is capable of being reached by a single-flux quantum (SFQ) pulse within a predetermined arrival time range.

[0110] The method may further include: if the first absorb terminal cannot be reached by an SFQ pulse within a predetermined arrival time range, inserting a Josephson transmission line (JTL) element between at least one of the plurality of source terminals and the first absorb terminal. The method may further include: after inserting the JTL element, determining whether the first absorb terminal can be reached by an SFQ pulse within the predetermined arrival time range. The method may further include: if it is determined that the first absorb terminal can be reached by an SFQ pulse, after inserting the JTL element, removing the first absorb terminal from the plurality of absorb terminals associated with at least one logic gate, which is associated with a critical timing path, within the predetermined arrival time range.

[0111] The method may further include selecting a first absorption terminal from a plurality of absorption terminals associated with at least one logic gate based on a predetermined behavior. Selecting the first absorption terminal based on the predetermined behavior may include selecting an absorption terminal as the first absorption terminal, the absorption terminal having the minimum of the maximum rise time values ​​of the corresponding SFQ pulses associated with the plurality of absorption terminals.

[0112] The method may include, prior to the determination step, assigning a second phase to at least one logic gate by adding a phase shift to the first phase. Timing information may be provided via a timing library that includes at least timing constraints and enabled signal types, wherein the enabled signal types are selected from a group including waveform pipeline logic signal types or phase-mode logic signal types.

[0113] In another aspect, this disclosure relates to a method implemented by a processor for determining a critical timing path in a superconducting circuit design, wherein the superconducting circuit design includes a plurality of logic gates, and wherein each of the plurality of logic gates includes at least one Josephson junction. The method may include: providing timing information regarding a plurality of source terminals associated with the plurality of logic gates. The method may further include: receiving a selection from a plurality of absorb terminals associated with a target logic gate, the target logic gate being selected from the plurality of logic gates. The method may further include: receiving a phase assignment to the target logic gate. The method may further include: for each of a plurality of absorber terminals: using a processor, determining whether each of the plurality of absorber terminals is reachable by a corresponding single-through-quantum (SFQ) pulse within a predetermined arrival time range; and if the first absorber terminal is not reachable within the predetermined arrival time range, inserting a Josephson transmission line (JTL) between the source terminal associated with the target logic gate and the first absorber terminal determined to be unreachable within the predetermined arrival time range; and, upon determining that the first absorber terminal is reachable, removing the first absorber terminal from the plurality of absorber terminals associated with the critical timing path within the predetermined arrival time range after inserting the JTL.

[0114] The method may further include selecting a first absorption terminal from a plurality of absorption terminals associated with a target logic gate based on a predetermined behavior. Selecting the first absorption terminal based on the predetermined behavior may include selecting an absorption terminal as the first absorption terminal, the absorption terminal having the minimum of the maximum rise time values ​​of the corresponding SFQ pulses associated with the plurality of absorption terminals.

[0115] The method may further include: assigning a second phase to a target logic gate by adding a phase shift to the first phase prior to the determination step. Timing information may be provided via a timing library that includes at least timing constraints and enabled signal types, wherein the enabled signal types are selected from a group including waveform pipeline logic signal types or phase-mode logic signal types.

[0116] In another aspect, this disclosure relates to a system configured to determine a critical timing path in a superconducting circuit design, wherein the superconducting circuit design includes at least one logic gate, the at least one logic gate including at least one Josephson junction, and wherein the at least one logic gate has a first phase assigned to it in association with a clock signal used for timing the at least one logic gate. The system may include a first subsystem configured to provide timing information regarding a plurality of source terminals of the at least one logic gate coupled to a first absorption terminal of the at least one logic gate. The system may also include a second subsystem, including a processor, configured to determine, based on the first phase assigned to the at least one logic gate and in view of the timing information, whether the first absorption terminal can be reached by a single-flux quantum (SFQ) pulse within a predetermined arrival time range.

[0117] The system can also be configured to allow the insertion of a Josephson transmission line (JTL) element between at least one of the plurality of source terminals and the first absorb terminal if the first absorb terminal cannot be reached by an SFQ pulse within a predetermined arrival time range. The system can also be configured to determine, after inserting the JTL element, whether the first absorb terminal can be reached by an SFQ pulse within a predetermined arrival time range. The system can also be configured to, upon determining that the first absorb terminal can be reached by an SFQ pulse, remove the first absorb terminal from the plurality of absorb terminals associated with at least one logic gate, which is associated with a critical timing path, within a predetermined arrival time range after inserting the JTL element, within the predetermined arrival time range. The system can also be configured to select an absorb terminal as the first absorb terminal, the absorb terminal having the minimum of the maximum rise time values ​​of the corresponding SFQ pulses associated with the plurality of absorb terminals.

[0118] The system can also be configured to assign a second phase to at least one logic gate by adding a phase shift to the first phase. The system may also include a timing library, including at least timing constraints and enable signal types, wherein the enable signal types are selected from a group including waveform pipeline logic signal types or phase-mode logic signal types.

[0119] In another aspect, this disclosure relates to a method implemented by a processor for determining timing paths and coordinating topologies in a superconducting circuit design, wherein the superconducting circuit design includes a first timing path comprising a first set of timing pins, and wherein a first subset of the first set of timing pins is associated with a first set of timing constraints, the first set of timing constraints including a first timing endpoint and a second timing endpoint. The method may include: using the processor, processing the first set of timing constraints to assign a first valid start time to the first timing endpoint and a second valid start time to the second timing endpoint. The method may further include: inserting a first shading element representing a first physical connection component on the timing path, wherein the first shading element precedes the first timing endpoint or follows the second timing endpoint. The method may further include: resolving any changes to the first or second valid start time caused by the insertion of the first shading element on the timing path.

[0120] In this method, processing the first timing constraint set to assign a first legitimate start time to a first timing endpoint may include: determining whether the first timing endpoint can be reached by a single-flux quantum (SFQ) pulse within a first arrival time range, and wherein processing the first timing constraint set to assign a second legitimate start time to a second timing endpoint includes: determining whether the second timing endpoint can be reached by an SFQ pulse within a second arrival time range. The method may further include: if the second timing endpoint cannot be reached by an SFQ pulse within the second arrival time range, inserting a Josephson transmission line (JTL) element between the first and second timing endpoints.

[0121] The timing path may include a second timing constraint group and a third timing constraint group, wherein the second timing constraint group includes a third timing endpoint and a fourth timing endpoint, and the third timing constraint group includes a fifth timing endpoint and a sixth timing endpoint, and wherein the method further includes: processing the second timing constraint group to assign a third valid start time to the third timing endpoint and a fourth valid start time to the fourth timing endpoint, and processing the third timing constraint group to assign a fifth valid start time to the fifth timing endpoint and a sixth valid start time to the sixth endpoint.

[0122] The method may further include inserting a second shadow element representing a second physical connection component on the timing path, wherein the second shadow element precedes the first timing endpoint or follows the second timing endpoint. Resolving any changes to the first or second valid start time may include modifying the first valid start time to generate a first modified valid start time, or modifying the second valid start time to generate a second modified valid start time.

[0123] The method may further include: resolving any changes to the first or second modified valid start time caused by the insertion of a second shaded element on the timing path. Timing information regarding the timing path may be provided via a timing library that includes at least timing constraints and enabled signal types, wherein the enabled signal types are selected from a group including waveform pipeline logic signal types or phase-mode logic signal types.

[0124] In another aspect, this disclosure relates to a method implemented by a processor for determining timing paths and coordinating topologies in a superconducting circuit design, wherein the superconducting circuit design includes a first timing path, the first timing path including a first timing endpoint associated with a first circuit component and a second timing endpoint associated with a second circuit component, and wherein each of the first and second circuit components includes a Josephson junction, and wherein the first circuit component is assigned a first phase and the second circuit component is assigned a second phase. The method may include: using the processor, determining a first valid start time for the first timing endpoint on the timing path, and determining a second valid start time for the second timing endpoint on the timing path. The method may further include: inserting a first shading element representing a first physical connection component on the timing path, wherein the first shading element precedes the first circuit component on the timing path. The method may further include: inserting a second shading element representing a second physical connection component on the timing path, wherein the second shading element follows the second circuit component on the timing path. The method may further include: resolving any changes in the first and second valid start times caused by the insertion of the first and second shading elements on the timing path.

[0125] Determining a first legitimate start time for a first timing endpoint may include: determining whether the first timing endpoint can be reached by a single-flux quantum (SFQ) pulse within a first arrival time range, and wherein determining a second legitimate start time for a second timing endpoint includes: determining whether the second timing endpoint can be reached by an SFQ pulse within a second arrival time range. The method may further include: if the second timing endpoint cannot be reached by an SFQ pulse within the second arrival time range, inserting a Josephson transmission line (JTL) element between the first and second circuit components and assigning phase to the JTL. Resolving any changes to the first or second legitimate start time may include: modifying the first legitimate start time to generate a first modified legitimate start time, or modifying the second legitimate start time to generate a second modified legitimate start time.

[0126] The method may further include: resolving any changes to the first or second modified valid start time caused by the insertion of a second shaded element on the timing path. Timing information regarding the timing path may be provided via a timing library that includes at least timing constraints and enabled signal types, wherein the enabled signal types are selected from a group including waveform pipeline logic signal types or phase-mode logic signal types.

[0127] In another aspect, this disclosure relates to a system configured to determine timing paths and coordinate topologies in a superconducting circuit design, wherein the superconducting circuit design includes a first timing path comprising a first timing endpoint associated with a first circuit component and a second timing endpoint associated with a second circuit component, and wherein each of the first and second circuit components includes a Josephson junction, and wherein the first circuit component is assigned a first phase and the second circuit component is assigned a second phase. The system may include: a processor; and a memory including instructions. The instructions may be configured to: (1) determine a first valid start time of the first timing endpoint on the timing path and determine a second valid start time of the second timing endpoint on the timing path, (2) insert a first shadow element representing a first physical connection component on the timing path, wherein the first shadow element precedes the first circuit component on the timing path, (3) insert a second shadow element representing a second physical connection component on the timing path, wherein the second shadow element follows the second circuit component on the timing path, and (4) resolve any changes in the first and second valid start times caused by the insertion of the first and second shadow elements on the timing path.

[0128] The first shadow element may be coupled to the first circuit assembly via a first active transmission element, and the second circuit assembly may be coupled to the second shadow element via a second active transmission element. The first active transmission element may include a first Josephson transmission line (JTL), and the second active transmission element may include a second JTL.

[0129] The first active transmission element can be assigned a third phase, and the second active transmission element can be assigned a fourth phase. Each of the first, second, third, and fourth phases can be selected from a group consisting of 0-degree, 90-degree, 180-degree, and 270-degree phases. The system may also include a timing library containing timing information about timing paths, wherein the timing library includes at least timing constraints and enabled signal types, wherein the enabled signal types are selected from a group including waveform pipeline logic signal types or phase mode logic signal types.

[0130] It is important to understand that the methods, modules, and components described herein are merely exemplary. Alternatively or additionally, the functionality described herein may be implemented at least in part by one or more hardware logic components. For example, and not limitingly, illustrative types of hardware logic components that may be used include Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application Standard Products (ASSPs), Systems-on-Chip (SoCs), Complex Programmable Logic Devices (CPLDs), etc. In an abstract but still explicit sense, any arrangement of components that implements the same functionality is effectively “associated” such that the desired functionality is achieved. Therefore, any two components combined herein to achieve a particular functionality can be considered “associated” with each other such that the desired functionality is achieved, regardless of the architecture or intermediate components. Similarly, any two components so associated can also be considered “operably connected” or “coupled” with each other to achieve the desired functionality.

[0131] The functionality associated with the examples described in this disclosure may also include instructions stored in a non-transient medium. As used herein, the term "non-transient medium" refers to any medium that stores data and / or instructions that cause the machine to operate in a specific manner. Exemplary non-transient media include non-volatile media and / or volatile media. Non-volatile media include, for example, hard disks, solid-state drives, magnetic disks or magnetic tapes, optical disks or optical magnetic tapes, flash memory, EPROM, NVRAM, PRAM, or other such media or networking versions of such media. Volatile media include, for example, dynamic memory, such as DRAM, SRAM, cache, or other such media. Non-transient media are distinct from transport media but can be used in conjunction with transport media. Transport media are used to transfer data and / or instructions to or from a machine (such as processors 402). Example transport media include coaxial cables, fiber optic cables, copper wires, and wireless media such as radio waves.

[0132] Furthermore, those skilled in the art will recognize that the boundaries between the functionalities of the above-described operations are merely illustrative. The functionality of multiple operations can be combined into a single operation, and / or the functionality of a single operation can be distributed across additional operations. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be varied in various other embodiments.

[0133] While specific examples are provided in this disclosure, various modifications and alterations may be made without departing from the scope of this disclosure as set forth in the following claims. Therefore, the specification and drawings should be considered illustrative rather than restrictive, and all such modifications are intended to be included within the scope of this disclosure. Any benefits, advantages, or solutions to problems described herein with reference to specific examples are not intended to be construed as key, essential, or fundamental features or elements of any or all claims.

[0134] Furthermore, the terms “a” or “an” as used herein are defined as one or more. Moreover, the use of introductory phrases such as “at least one” and “one or more” in claims should not be construed as meaning that introducing another claim element with the indefinite article “a” or “an” limits any particular claim containing such an introduced claim element to an invention containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” along with indefinite articles (such as “a” or “an”). The same applies to the use of definite articles.

[0135] Unless otherwise specified, terms such as “first” and “second” are used to arbitrarily distinguish the elements described by such terms. Therefore, these terms are not necessarily intended to indicate the time or other priority of such elements.

Claims

1. A method implemented by a processor for determining a timing path and coordinating topology in a superconducting circuit design, wherein the superconducting circuit design includes a first timing path, the first timing path including a first set of timing pins, and wherein a first subset of the first set of timing pins is associated with a first set of timing constraints, the first set of timing constraints including a first timing endpoint and a second timing endpoint, the method comprising: Using the processor, the first timing constraint group is processed to assign a first valid start time to the first timing endpoint and a second valid start time to the second timing endpoint; Insert a first shadow element representing a first physical connection component on the timing path, wherein the first shadow element is before the first timing endpoint or after the second timing endpoint; as well as Resolve any changes to the first or second valid start time caused by the insertion of the first shadow element on the timing path.

2. The method of claim 1, wherein processing the first timing constraint group to assign the first valid start time to the first timing endpoint comprises: Determining whether the first timing endpoint can be reached by a single-flux quantum SFQ pulse within a first arrival time range, and wherein processing the first timing constraint group to assign the second legal start time to the second timing endpoint includes: determining whether the second timing endpoint can be reached by the SFQ pulse within a second arrival time range.

3. The method according to claim 2, further comprising: If the second timing endpoint cannot be reached by the SFQ pulse within the second arrival time range, a Josephson transmission line (JTL) element is inserted between the first timing endpoint and the second timing endpoint.

4. The method of claim 1, wherein the timing path includes a second timing constraint group and a third timing constraint group, wherein the second timing constraint group includes a third timing endpoint and a fourth timing endpoint, and the third timing constraint group includes a fifth timing endpoint and a sixth timing endpoint, and wherein the method further includes: The second timing constraint group is processed to assign a third valid start time to the third timing endpoint and a fourth valid start time to the fourth timing endpoint, and the third timing constraint group is processed to assign a fifth valid start time to the fifth timing endpoint and a sixth valid start time to the sixth timing endpoint.

5. The method according to claim 4, further comprising: A second shadow element representing a second physical connection component is inserted on the timing path, wherein the second shadow element is before the first timing endpoint or after the second timing endpoint.

6. The method of claim 5, wherein resolving any change in the first legal start time or the second legal start time comprises: Modify the first valid start time to generate a first modified valid start time, or modify the second valid start time to generate a second modified valid start time.

7. The method according to claim 6, further comprising: Resolve any changes to the first or second modified valid start time caused by the insertion of the second shadow element on the timing path.

8. The method of claim 1, wherein timing information regarding the timing path is provided via a timing library, the timing library including at least timing constraints and enabled signal types, wherein the enabled signal types are selected from the group consisting of waveform pipeline logic signal types or phase mode logic signal types.

9. A method implemented by a processor for determining a timing path and coordinating a topology in a superconducting circuit design, wherein the superconducting circuit design includes a first timing path, the first timing path including a first timing endpoint associated with a first circuit component and a second timing endpoint associated with a second circuit component, and wherein each of the first circuit component and the second circuit component includes a Josephson junction, and wherein the first circuit component is assigned a first phase and the second circuit component is assigned a second phase, the method comprising: Using the processor, a first valid start time for the first timing endpoint on the timing path is determined, and a second valid start time for the second timing endpoint on the timing path is determined; Insert a first shaded element representing a first physical connection component on the timing path, wherein the first shaded element precedes the first circuit component on the timing path; Insert a second shaded element representing the second physical connection component on the timing path, wherein the second shaded element follows the second circuit component on the timing path; and Resolve any changes in the first and second valid start times caused by the insertion of the first and second shadow elements on the timing path.

10. The method of claim 9, wherein determining the first valid start time of the first timing endpoint comprises: Determining whether the first timing endpoint can be reached by a single-flux quantum SFQ pulse within a first arrival time range, and wherein determining the second legitimate start time of the second timing endpoint includes: determining whether the second timing endpoint can be reached by the SFQ pulse within a second arrival time range.

11. The method of claim 10, further comprising: If the second timing endpoint cannot be reached by the SFQ pulse within the second arrival time range, a Josephson transmission line (JTL) element is inserted between the first circuit component and the second circuit component, and the phase is assigned to the JTL.

12. The method of claim 9, wherein resolving any change in the first legal start time or the second legal start time comprises: Modify the first valid start time to generate a first modified valid start time, or modify the second valid start time to generate a second modified valid start time.

13. The method of claim 12, further comprising: Resolve any changes to the first or second modified valid start time caused by the insertion of the second shadow element on the timing path.

14. The method of claim 9, wherein timing information regarding the timing path is provided via a timing library, the timing library including at least timing constraints and enabled signal types, wherein the enabled signal types are selected from the group consisting of waveform pipeline logic signal types or phase mode logic signal types.

15. A system configured to determine a timing path and a coordinated topology in a superconducting circuit design, wherein the superconducting circuit design includes a first timing path, the first timing path including a first timing endpoint associated with a first circuit component and a second timing endpoint associated with a second circuit component, and wherein each of the first circuit component and the second circuit component includes a Josephson junction, and wherein the first circuit component is assigned a first phase and the second circuit component is assigned a second phase, the system comprising: processor; as well as The memory includes instructions configured to: Determine a first valid start time for the first timing endpoint on the timing path, and determine a second valid start time for the second timing endpoint on the timing path. A first shaded element representing a first physical connection component is inserted on the timing path, wherein the first shaded element precedes the first circuit component on the timing path. A second shaded element representing the second physical connection component is inserted on the timing path, wherein the second shaded element follows the second circuit component on the timing path. Resolve any changes in the first and second valid start times caused by the insertion of the first and second shadow elements on the timing path.

16. The system of claim 15, wherein the first shadow element is coupled to the first circuit assembly via a first active transmission element, and wherein the second circuit assembly is coupled to the second shadow element via a second active transmission element.

17. The system of claim 16, wherein the first active transmission element comprises a first Josephson transmission line (JTL), and the second active transmission element comprises a second JTL.

18. The system of claim 17, wherein the first active transmission element is assigned a third phase, and wherein the second active transmission element is assigned a fourth phase.

19. The system of claim 18, wherein each of the first phase, the second phase, the third phase, and the fourth phase is selected from the group consisting of a 0-degree phase, a 90-degree phase, a 180-degree phase, and a 270-degree phase.

20. The system of claim 15 further includes a timing library, the timing library including timing information about the timing path, wherein the timing information includes at least timing constraints and enabled signal types, wherein the enabled signal types are selected from the group consisting of waveform pipeline logic signal types or phase mode logic signal types.

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