Display device

Abstract

The present invention relates to a display device, comprising a first gate line and a data line crossing each other, a pixel electrode, a switching element and a connecting part, the switching element comprising a gate electrode connected to the first gate line, a source electrode connected to the data line and a drain electrode connected to the pixel electrode, the connecting part connecting the drain electrode and the pixel electrode, and in a first direction perpendicular to the data line, the distance between the data line and the connecting part is smaller than the distance between the data line and the gate electrode.

Description

[0001] This application is a divisional application of a patent application with an application date of April 5, 2017, application number 201710219113.4, and invention name “Display Device”.

[0002] This application claims priority to Korean Patent Application No. 10-2016-0041128, filed on Apr. 4, 2016, and all benefits arising therefrom, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Exemplary embodiments of the present invention relate to a display device, and more particularly, to a display device improved in terms of aperture ratio. Background Art

[0004] A liquid crystal display ("LCD") device is one of the most widely used types of flat panel display ("FPD") devices. An LCD device generally includes two substrates including two electrodes respectively disposed thereon and a liquid crystal layer interposed therebetween. When voltages are respectively applied to the two electrodes, liquid crystal molecules of the liquid crystal layer are rearranged, so that the amount of transmitted light is controlled in the LCD device. Summary of the invention

[0005] Exemplary embodiments of the present invention relate to a display device improved in aperture ratio.

[0006] According to an exemplary embodiment of the present invention, a display device includes a first gate line and a data line crossing each other, a pixel electrode, a switching element and a connecting portion, the switching element includes a gate electrode connected to the first gate line, a source electrode connected to the data line and a drain electrode connected to the pixel electrode, and the connecting portion connects the drain electrode and the pixel electrode. In a first direction perpendicular to the data line, a distance between the data line and the connecting portion is smaller than a distance between the data line and the gate electrode.

[0007] In exemplary embodiments, the connection portion may be disposed between the data line and the gate electrode.

[0008] In an exemplary embodiment, the connection portion may be disposed in a region surrounded by the data line, the gate electrode, the first gate line, and the source electrode.

[0009] In exemplary embodiments, the drain electrode and the pixel electrode may be connected to each other through a contact hole located in a region corresponding to the connection portion.

[0010] In an exemplary embodiment, the display device may further include a compensation pattern extending from the first gate line and overlapping the drain electrode.

[0011] In an exemplary embodiment, the source electrode may include an electrode portion overlapping the gate electrode and an extension portion connecting the electrode portion and the data line.

[0012] In exemplary embodiments, the extending portion may overlap the first gate line.

[0013] In an exemplary embodiment, the display device may further include a second gate line crossing the data line and being closest to the first gate line among the gate lines in the display device.

[0014] In an exemplary embodiment, a distance between the first gate line and the second gate line may be in a range of about 30 micrometers (μm) to about 41 μm.

[0015] In an exemplary embodiment, the display device may further include a light blocking layer overlapping the first gate line and the second gate line and disposed between the first gate line and the second gate line.

[0016] In exemplary embodiments, the light blocking layer may have a width from about 35 μm to about 38 μm or from about 40 μm to about 47 μm.

[0017] The gate electrode may protrude from the first gate line toward the second gate line.

[0018] In an exemplary embodiment, the display device may further include a common line crossing the first gate line and the second gate line.

[0019] In an exemplary embodiment, the switching element may be disposed in a region surrounded by the first gate line, the second gate line, the data line, and the common line.

[0020] In exemplary embodiments, the pixel electrode may overlap the gate electrode, the drain electrode, the common line, and the first gate line.

[0021] In exemplary embodiments, the pixel electrode may overlap the first gate line.

[0022] In exemplary embodiments, the pixel electrode may overlap the gate electrode, the source electrode, the common line, and the second gate line.

[0023] In exemplary embodiments, the pixel electrode may overlap the source electrode and the second gate line.

[0024] According to an exemplary embodiment of the present invention, a display device includes a first gate line and a data line crossing each other and a first switching element, the first switching element including a first gate electrode connected to the first gate line, a first source electrode connected to the data line, and a first drain electrode including a portion disposed between the first gate electrode and the data line.

[0025] The foregoing is merely illustrative and is not intended to be limiting in any way. In addition to the illustrative exemplary embodiments and features described above, further exemplary embodiments and features will become apparent by reference to the drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0027] Figure 1 is a plan view showing an exemplary embodiment of a display device;

[0028] Figure 2 It shows Figure 1 A detailed view of an exemplary embodiment of region A;

[0029] Figure 3 is along Figure 2 A cross-sectional view taken along line II';

[0030] Figure 4 It shows Figure 2 An enlarged view of an exemplary embodiment of a switching element region of FIG.

[0031] Figure 5A , 5B , 5C, 5D, 5E, 5F, 5G, 5H, 5I, 5J, 5K and 5L are diagrams for manufacturing Figure 3 A cross-sectional view of an exemplary embodiment of a process for a display device;

[0032] Figure 6 It shows Figure 1 A detailed view of an alternative exemplary embodiment of region A of FIG.

[0033] Figure 7 It shows Figure 1 A detailed view of another alternative exemplary embodiment of region A of;

[0034] Figure 8 is a plan view showing an alternative exemplary embodiment of a display device; and

[0035] Fig. 9 It shows Figure 8 Detailed view of an exemplary embodiment of area B. DETAILED DESCRIPTION

[0036] The advantages and features of the present invention and the methods for realizing them will be clearly understood from the exemplary embodiments described in detail below with reference to the accompanying drawings. However, the present invention can be implemented in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein. On the contrary, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. The present invention is limited only by the scope of the claims. Therefore, well-known constituent elements, operations, and techniques are not described in detail in the exemplary embodiments to prevent the present invention from being vaguely interpreted. Throughout the specification, the same reference numerals refer to the same elements.

[0037] In the accompanying drawings, some elements or shapes may be shown in an enlarged or simplified manner to better illustrate the present invention, and other elements existing in actual products may also be omitted. Therefore, the accompanying drawings are intended to facilitate understanding of the present invention.

[0038] When a layer, region, or board is referred to as being "on" another layer, region, or board, it may be directly on the other layer, region, or board, or there may be an intermediate layer, region, or board therebetween. Conversely, when a layer, region, or board is referred to as being "directly on" another layer, region, or board, there may not be an intermediate layer, region, or board therebetween. In addition, when a layer, region, or board is referred to as being "below" another layer, region, or board, it may be directly below another layer, region, or board, or there may be an intermediate layer, region, or board therebetween. Conversely, when a layer, region, or board is referred to as being "directly below" another layer, region, or board, there may not be an intermediate layer, region, or board therebetween.

[0039] For ease of description, spatially relative terms "below," "beneath," "less," "above," "above," and the like are used herein to describe the relationship between one element or component and another element or component, as shown in the accompanying drawings. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, where the device shown in the accompanying drawings is flipped, a device that is "below" or "below" another device may be placed "above" the other device. Thus, the illustrative term "below" may include both lower and upper positions. The device may also be oriented in another direction, so the spatially relative terms may be interpreted differently depending on the direction.

[0040] Throughout the specification, when an element is referred to as being "connected" to another element, the element is "directly connected" to another element, or "electrically connected" to another element, with one or more intermediate elements inserted therebetween. It will also be understood that when used in this specification, the term "comprising" specifies the presence of the features, integral bodies, steps, operations, elements and / or parts, but does not exclude the presence or addition of one or more other features, integral bodies, steps, operations, elements, parts and / or combinations thereof. The terms used herein are only used for the purpose of describing a particular embodiment and are not intended to be limiting. As used herein, unless the content clearly states otherwise, the singular form "one" and its variants are intended to include plural forms, including "at least one". "At least one" is not interpreted as limiting "one". "Or" refers to "and / or". As used herein, the term "and / or" includes any and all combinations of one or more associated listed items.

[0041] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this article, the "first element" discussed below may be referred to as the "second element" or the "third element", and the "second element" and the "third element" may be referred to in the same manner.

[0042] As used herein, "about" or "approximately" includes the stated value and the average value within an acceptable range of deviation determined by one of ordinary skill in the art for a particular value, taking into account the measurement in question and the errors associated with the measurement of the particular value (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, 20%, 10%, 5%.

[0043] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present invention belongs. It should also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and will not be interpreted in an ideal or excessive form of meaning unless clearly defined in this specification.

[0044] In the following, reference will be made to Figures 1 to 9 A liquid crystal display device (LCD) and a method of manufacturing the LCD device are described in detail.

[0045] Figure 1 is a plan view showing an exemplary embodiment of a display device.

[0046] like Figure 1As shown, an exemplary embodiment of a display device may include a plurality of gate lines GL1, GL2, ..., a plurality of data lines DL1 to DLj, a plurality of common lines CL1 to CLj-1, a plurality of pixels RP, GP and BP, a plurality of first virtual pixels DP1 and a plurality of second virtual pixels DP2.

[0047] The plurality of pixels DP1, RP, GP, BP, and DP2 include a red pixel RP representing a red image, a green pixel GP representing a green image, a blue pixel BP representing a blue image, a first dummy pixel DP1, and a second dummy pixel DP2.

[0048] Although Figure 1 Although not shown in the figure, each of the pixels DP1, RP, GP, BP and DP2 includes a switching element and a pixel electrode connected to the switching element. Each switching element is connected to a corresponding one of the gate lines and a corresponding one of the data lines, and Figure 1 It shows which gate line and which data line each switching element of a pixel is connected to. In other words, Figure 1 The electrical connection relationship between each switching element of the pixel and the corresponding gate line and the electrical connection relationship between each switching element of the pixel and the corresponding data line are shown. In an exemplary embodiment, for example, the switching element included in the first virtual pixel DP1 in the pixels of the first horizontal line HL1 can be connected to the first gate line GL1 and the second data line DL2.

[0049] In an exemplary embodiment, Figure 1 The position of the pixel in the substantially corresponds to the position of the pixel electrode of the pixel among the components included in the corresponding pixel. In an exemplary embodiment, for example, in the pixel of the second horizontal line HL2, the first red pixel RP from the left side connected to the first data line DL1 may be disposed between the third gate line GL3 and the fourth gate line GL4. However, the switching element of the first red pixel RP is not disposed between the third gate line GL3 and the fourth gate line GL4, but is disposed between the fourth gate line GL4 and the fifth gate line GL5. Hereinafter, reference is made to Figure 1 The position of a pixel or virtual pixel described herein refers to the position of a pixel electrode of a pixel in a component included in a corresponding pixel. Figure 1 The description “the predetermined pixel is disposed between the first gate line GL1 and the second gate line GL2” means that the pixel electrode of the predetermined pixel is disposed between the first gate line GL1 and the second gate line GL2. Figure 1 The description “a predetermined pixel is disposed between the first data line DL1 and the first common line CL1 ” means that a pixel electrode of the predetermined pixel is disposed between the first data line DL1 and the first common line CL1 .

[0050] Each of the first virtual pixel DP1 and the second virtual pixel DP2 may be a pixel representing blue. The first virtual pixel DP1 is disposed at the leftmost portion of the corresponding horizontal line. The second virtual pixel DP2 is disposed at the rightmost portion of the corresponding horizontal line. The first virtual pixel DP1 and the second virtual pixel DP2 are formed by the light blocking layer 376 (refer to FIG. 3 ). Figure 3 )cover.

[0051] The first virtual pixel DP1 is arranged between the first data line DL1 and the first common line CL1, the first data line is the leftmost data line among the plurality of data lines DL1 to DLj, and the first common line is the leftmost common line among the plurality of common lines CL1 to CLj-1. The pixel electrode of the second virtual pixel DP2 is arranged between the jth data line DLj and the (j-1)th common line, the jth data line is the rightmost data line among the plurality of data lines DL1 to DLj, and the (j-1)th common line is the rightmost common line among the plurality of common lines CL1 to CLj-1.

[0052] Pixels DP1, RP, GP, BP, and DP2 arranged along the kth (k is a natural number) horizontal line are disposed between the (2k-1)th gate line and the 2kth gate line. In an exemplary embodiment, for example, pixels arranged along the third horizontal line HL3 may be disposed between the fifth gate line GL5 and the sixth gate line GL6.

[0053] Each of the common lines CL1 to CLj-1 is disposed between two adjacent data lines. In an exemplary embodiment, for example, the first common line CL1 may be disposed between the first data line DL1 and the second data line DL2. Each of the common lines CL1 to CLj-1 transmits a common voltage. Each of the common lines CL1 to CLj-1 is connected to a common electrode 330 (see Figure 3 ). A common voltage transmitted from each of the common lines CL1 to CLj- 1 is applied to the common electrode 330 .

[0054] Each of the pixels DP1, RP, GP, BP, and DP2 is disposed in an area surrounded by two gate lines, one data line, and one common line. In an exemplary embodiment, for example, among the pixels DP1, RP, GP, BP, and DP2 in the first horizontal line HL1, the red pixel RP connected to the second data line DL2 may be disposed in an area surrounded by the first gate line GL1, the second gate line GL2, the first common line CL1, and the second data line DL2.

[0055] The red pixel RP is connected to a gate line that is closer to the pixel electrode of the red pixel RP among the two gate lines close to the lower portion of the red pixel RP. In an exemplary embodiment, for example, the red pixel RP in the third horizontal line HL3 may be connected to the sixth gate line GL6 that is closer to the pixel electrode of the red pixel RP among the sixth and seventh gate lines GL6 and GL7 below the red pixel RP. However, only one gate line is provided below the red pixel RP in the last horizontal line, and thus the red pixel RP in the last horizontal line is connected to the one gate line.

[0056] The green pixel GP is connected to a gate line that is closer to the pixel electrode of the green pixel GP among the two gate lines close to the upper portion of the green pixel GP. In an exemplary embodiment, for example, the green pixel GP in the third horizontal line HL3 may be connected to the fifth gate line GL5, which is closer to the pixel electrode of the green pixel GP among the fourth and fifth gate lines GL4 and GL5 above the green pixel GP. However, in an exemplary embodiment, in the first horizontal line HL1, only one gate line (e.g., the first gate line GL1) is disposed above the green pixel GP, and therefore the green pixel GP in the first horizontal line HL1 is connected to the one gate line, e.g., the first gate line GL1.

[0057] The blue pixel BP is connected to a gate line that is closer to the pixel electrode of the blue pixel BP among the two gate lines close to the lower portion of the blue pixel BP, or is connected to a gate line that is closer to the pixel electrode of the blue pixel BP among the two gate lines close to the upper portion of the blue pixel BP. In an exemplary embodiment, for example, one of the blue pixels BP in the third horizontal line HL3 may be connected to the sixth gate line GL6, which is closer to the pixel electrode of the blue pixel BP among the sixth and seventh gate lines GL6 and GL7 below the blue pixel BP. In an alternative exemplary embodiment, another of the blue pixels BP in the third horizontal line HL3 is connected to the fifth gate line GL5, which is closer to the pixel electrode of the blue pixel BP among the fourth and fifth gate lines GL4 and GL5 above the blue pixel BP.

[0058] Each of the pixels DP1, RP, GP, BP, and DP2 arranged along the odd-numbered horizontal lines HL1, HL3, ... is connected to a data line closest to the corresponding pixel among the data lines on the right side of the corresponding pixel. In an exemplary embodiment, for example, the leftmost green pixel GP in the third horizontal line HL3 can be connected to the third data line DL3 closest to the green pixel GP among the data lines on the right side of the green pixel GP.

[0059] Each of the pixels DP1, RP, GP, BP, and DP2 arranged along the even-numbered horizontal lines HL2, HL4, ... is connected to a data line closest to the corresponding pixel among the data lines on the left side of the corresponding pixel. In an exemplary embodiment, for example, the leftmost green pixel GP in the fourth horizontal line HL4 may be connected to a second data line DL2 closest to the green pixel GP among the data lines on the left side of the green pixel GP.

[0060] Figure 2 It shows Figure 1 A detailed view of an exemplary embodiment of area A, and 3 is along Figure 2 A cross-sectional view taken along line II'.

[0061] In the following, Figure 1 Among the pixels in the region A, the red pixel RP in the second horizontal line HL2 is referred to as a first pixel, and among the pixels in the region A, the pixel disposed in the third horizontal line HL3 and connected to the fourth data line DL4 is referred to as a second pixel.

[0062] like Figure 2 and 3 As shown, the display device includes a first substrate 301, a plurality of gate lines GL3, GL4 and GL5, a plurality of gate electrodes GE1 and GE2, a gate insulating layer 311, a plurality of data lines DL4 and DL5, a plurality of source electrodes SE1 and SE2, a plurality of drain electrodes DE1 and DE2, a plurality of common lines CL3, CL4 and CL5, a first passivation layer 321, an insulating interlayer 352, a plurality of pixel electrodes PE1 and PE2, a second passivation layer 322, a common electrode 330, a second substrate 302, a light blocking layer 376, a color filter 354 and a liquid crystal layer 333.

[0063] like Figure 2 and 3 As shown, the first pixel includes a first switching element TFT1 and a first pixel electrode PE1.

[0064] The first switching element TFT1 is disposed in an area surrounded by the fourth gate line GL4, the fifth gate line GL5, the fourth data line DL4 and the fourth common line CL4. The first switching element TFT1 may be a thin film transistor. Hereinafter, an area surrounded by the fourth gate line GL4, the fifth gate line GL5, the first data line DL1 and the jth data line DLj is referred to as a switching element area.

[0065] The first switching element TFT1 includes a first gate electrode GE1, a first source electrode SE1 and a first drain electrode DE1. The first gate electrode GE1 is connected to the fourth gate line GL4, the first source electrode SE1 is connected to the fourth data line DL4, and the first drain electrode DE1 is connected to the first pixel electrode PE1.

[0066] The first gate electrode GE1 and the fourth gate line GL4 may be integral. The first gate electrode GE1 may have a shape protruding from the fourth gate line GL4 toward the fifth gate line GL5. The fifth gate line GL5 is disposed closest to the fourth gate line GL4 among the gate lines.

[0067] In an exemplary embodiment, although not shown, for example, an end portion of the fourth gate line GL4 may be connected to another layer or an external driving circuit.Although not shown, the end portion of the fourth gate line GL4 may include a larger planar area than another portion thereof.

[0068] The first source electrode SE1 and the fourth data line DL4 may be integrated. The first source electrode SE1 may have a shape protruding toward the first gate electrode GE1.

[0069] The first pixel electrode PE1 is disposed in an area surrounded by the third gate line GL3, the fourth gate line GL4, the fourth common line CL4 and the fifth data line DL5. Hereinafter, an area surrounded by the third gate line GL3, the fourth gate line GL4, the first data line DL1 and the jth data line DLj is referred to as a pixel electrode area.

[0070] like Figure 2 As shown, the first pixel electrode PE1 may include a plurality of branch electrodes 440 spaced apart from each other. One end of each branch electrode 440 is connected to the first connection electrode 771. Each branch electrode 440 may overlap with an adjacent gate line, which is adjacent to a corresponding branch electrode 440. In an exemplary embodiment, for example, an end of each branch electrode 440 may overlap with the third and fourth gate lines GL3 and GL4. A storage capacitor is provided in a corresponding overlapping region in each branch electrode 440 and the third and fourth gate lines GL3 and GL4.

[0071] The first pixel electrode PE1 is connected to the first switching element TFT1. In detail, the first pixel electrode PE1 is connected to the first drain electrode DE1 of the first switching element TFT1. The first pixel electrode PE1 and the first drain electrode DE1 may be connected to each other through the first connection electrode 771. The first connection electrode 771 extends from the first pixel electrode PE1 to the first drain electrode DE1. Figure 2 As shown, the first connection electrode 771 and the first pixel electrode PE1 may be integrated. The first connection electrode 771 may be a part of the first pixel electrode PE1.

[0072] The first connection electrode 771 overlaps the fourth common line CL4 and the fourth gate line GL4.

[0073] The first connection portion 651 is a connection portion between the first drain electrode DE1 of the first switching element TFT1 and the first pixel electrode PE1. Figure 2 and 3 As shown, the first connection portion 651 refers to a contact interface between the first drain electrode DE1 and the first pixel electrode PE1. The first pixel electrode PE1 may physically contact the first drain electrode DE1 through a first drain contact hole 901 defined in the first passivation layer 321, the insulating interlayer 352, and the second passivation layer 322.

[0074] The first connection portion 651 is disposed closer to the fourth data line DL4 than the first gate electrode GE1. Figure 2 and Figure 3 As shown, the distance d1 from the fourth data line DL4 to the first connection portion 651 may be less than the distance d2 from the fourth data line DL4 to the first gate electrode GE1. As used in this specification, the "distance" between two objects refers to the distance between the respective ends of the objects closest to the other object. Here, each of the distances d1 and d2 corresponds to Figure 3 The length of the horizontal line segment in . That is, Figure 3 The length of the line segment between the fourth data line DL4 and the first connection portion 651 in the horizontal direction corresponds to the distance d1. Figure 3 The length of a line segment between the fourth data line DL4 and the first gate electrode GE1 in the horizontal direction corresponds to the distance d2.

[0075] like Figure 2 As shown, the first connection portion 651 and a portion of the drain electrode DE1 may be disposed between the fourth data line DL4 and the first gate electrode GE1. In an exemplary embodiment, for example, Figure 2 As shown, the first connection portion 651 may be disposed in a region surrounded by the fourth data line DL4, the first gate electrode GE1, the fourth gate line GL4, and the first source electrode SE1.

[0076] The position of the first drain contact hole 901 may correspond to the position of the first connection portion 651 .

[0077] Since the first connection portion 651 is disposed between the fourth data line DL4 and the first gate electrode GE1, the first gate electrode GE1 may be disposed relatively far from the fourth data line DL4. Therefore, the distance between the two gate electrodes GE1 and GE2 adjacent to each other and having the fourth data line DL4 therebetween may be relatively increased. Therefore, in an exemplary embodiment, adjacent gate electrodes (e.g., the first gate electrode GE1 and the second gate electrode GE2) may not contact each other, even when the distance D1 between the gate lines (e.g., the fourth and fifth gate lines GL4 and GL5 to which the gate electrodes GE1 and GE2 are respectively connected) is reduced. Due to this structure, in an exemplary embodiment, the distance D1 between the gate lines GL4 and GL5 defining the length of the switching element region may be reduced without contacting the first gate electrode GE1 and the second gate electrode GE2, and the distance D2 between the gate lines (e.g., the third and fourth gate lines GL3 and GL4) defining the length of the pixel electrode region may be increased by the amount of reduction in the distance D1. As the distance D2 increases, the aperture ratio of the pixel may be increased.

[0078] In an exemplary embodiment, a distance D1 between the fourth gate line GL4 and the fifth gate line GL5 may be in a range of about 30 micrometers (μm) to about 41 μm. In an exemplary embodiment, for example, the distance D1 may be about 35 μm.

[0079] In the following, reference will be made to Figure 3 The vertical relationship between the components of the first pixel is described in detail.

[0080] The fourth gate line GL4 and the first gate electrode GE1 are disposed on the first substrate 301 .

[0081] In an exemplary embodiment, for example, at least one of the fourth gate line GL4 and the first gate electrode GE1 may include aluminum (Al) or its alloy, silver (Ag) or its alloy, copper (Cu) or its alloy, and / or molybdenum (Mo) or its alloy, or consist of these. In an alternative exemplary embodiment, for example, at least one of the fourth gate line GL4 and the first gate electrode GE1 may include one of chromium (Cr), tantalum (Ta), and titanium (Ti), or consist of them. In another alternative exemplary embodiment, for example, at least one of the fourth gate line GL4 and the first gate electrode GE1 may have a multilayer structure including at least two conductive layers having different physical properties from each other.

[0082] The gate insulating layer 311 is disposed on the fourth gate line GL4 and the first gate electrode GE1. In an exemplary embodiment, the gate insulating layer 311 is disposed on the entire surface of the first substrate 301 including the fourth gate line GL4 and the first gate electrode GE1.

[0083] In exemplary embodiments, the gate insulating layer 311 may include or consist of silicon nitride (SiNx) or silicon oxide (SiOx). The gate insulating layer 311 may have a multi-layer structure including at least two insulating layers having different physical properties.

[0084] The fourth data line DL4, the fourth common line CL4, and the semiconductor layer 344 are disposed on the gate insulating layer 311. Although not shown, in an exemplary embodiment, for example, an end portion of the fourth data line DL4 may be connected to another layer or an external driving circuit. The end portion of the fourth data line DL4 may include a larger plane area than a plane area of ​​another portion of the fourth data line DL4.

[0085] In order to ensure a significantly high transmittance of the display device, for example a maximum transmittance, such as Figure 2 As shown, in an exemplary embodiment, for example, a central portion of the fourth data line DL4 may be bent in a V-shape. In an exemplary embodiment, for example, central portions of the first pixel electrode PE1 and the fourth common line CL4 may be bent in a V-shape.

[0086] In an exemplary embodiment, the fourth data line DL4 may include a refractory metal (e.g., molybdenum, chromium, tantalum, and titanium) or an alloy thereof, or may be composed thereof. The fourth data line DL4 may have a multilayer structure including a refractory metal layer and a low resistance conductive layer. In an exemplary embodiment, for example, the multilayer structure may include a double-layer structure including a lower layer of chromium or molybdenum or any alloy thereof and an upper layer of aluminum or any alloy thereof, or the multilayer structure includes a triple-layer structure including a lower layer of molybdenum or any alloy thereof, an intermediate layer of aluminum or any alloy thereof, and an upper layer of molybdenum or any alloy thereof. In an alternative exemplary embodiment, for example, the fourth data line DL4 may include or be composed of any suitable metal or conductor other than the aforementioned materials.

[0087] The fourth common line CL4 may include the same material as that included in the fourth data line DL4 .

[0088] The semiconductor layer 344 overlaps with at least a portion of the first gate electrode GE1 .

[0089] In exemplary embodiments, for example, the semiconductor layer 344 may include amorphous silicon, polysilicon, or the like.

[0090] The first ohmic contact layer 321a and the second ohmic contact layer 321b are disposed on the semiconductor layer 344. The first ohmic contact layer 321a and the second ohmic contact layer 321b face each other with respect to a channel region of the first switching element TFT1 therebetween.

[0091] In an exemplary embodiment, at least one of the first ohmic contact layer 321a and the second ohmic contact layer 321b may include an n-type impurity ion (eg, phosphorus (P) or phosphine (PH)) doped at a high concentration. 3 ))'s silicide or n+ hydrogenated amorphous silicon.

[0092] The first source electrode SE1 is disposed on the first ohmic contact layer 321a. In an exemplary embodiment, although not shown, the first source electrode SE1 may be further disposed on the gate insulating layer 311. At least a portion of the first source electrode SE1 overlaps the semiconductor layer 344 and the first gate electrode GE1. The first source electrode SE1 may include a material substantially the same as that of the fourth data line DL4, and may have a structure substantially the same as that of the fourth data line DL4, for example, a multi-layer structure. The first source electrode SE1 and the fourth data line DL4 may be provided simultaneously in the same manufacturing process.

[0093] The first drain electrode DE1 is disposed on the second ohmic contact layer 321b and the gate insulating layer 311. At least a portion of the first drain electrode DE1 overlaps the semiconductor layer 344 and the first gate electrode GE1. The first drain electrode DE1 is connected to the first pixel electrode PE1. The first drain electrode DE1 may include a material substantially the same as that of the fourth data line DL4, and may have a structure substantially the same as that of the fourth data line DL4, for example, a multi-layer structure. The first drain electrode DE1 and the fourth data line DL4 may be provided simultaneously in the same manufacturing process.

[0094] The first passivation layer 321 is disposed on the fourth data line DL4, the first source electrode SE1, and the first drain electrode DE1. In an exemplary embodiment, the first passivation layer 321 may be disposed on the entire surface of the first substrate 301 including the fourth data line DL4, the first source electrode SE1, and the first drain electrode DE1 except for the first drain contact hole 901 and the common contact hole 904. The first drain contact hole 901 is defined above the first connection portion 651, and the common contact hole 904 is defined above the fourth common line CL4.

[0095] In an exemplary embodiment, the first passivation layer 321 may include an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), and in an exemplary embodiment, for example, an inorganic insulating material having photosensitivity and having a dielectric constant of about 4.0 may be used. In an exemplary embodiment, the first passivation layer 321 may have a double-layer structure including a lower inorganic layer and an upper organic layer. In an exemplary embodiment, for example, Figure 3 In the vertical direction, the first passivation layer 321 may have a thickness greater than or equal to about 5000 angstroms. The thickness, for example, is about To about within the range.

[0096] The insulating interlayer 352 is disposed on the first passivation layer 321. The insulating interlayer 352 defines a first drain contact hole 901 and a common contact hole 904. The first drain contact hole 901 is defined above the first connection portion 651, and the common contact hole 904 is defined above the fourth common line CL4.

[0097] The insulating interlayer 352 may include an organic layer having a low dielectric constant. In an exemplary embodiment, for example, the insulating interlayer 352 may include a photosensitive organic layer having a lower dielectric constant than that of the first passivation layer 321 .

[0098] The common electrode 330 is disposed on the insulating interlayer 352. The common electrode 330 is connected to the fourth common line CL4 through the common contact hole 904.

[0099] In an exemplary embodiment, the common electrode 330 may include a transparent metal layer including, for example, indium zinc oxide (“IZO”) or indium tin oxide (“ITO”).

[0100] The second passivation layer 322 is disposed on the common electrode 330 , the insulating interlayer 352 , the first passivation layer 321 , and the first drain electrode DE1 .

[0101] The second passivation layer 322 may include the same material as that included in the first passivation layer 321 .

[0102] The first pixel electrode PE1 and the first connection electrode 771 are disposed on the second passivation layer 322 . The first pixel electrode PE1 is connected to the first drain electrode DE1 . In detail, the first pixel electrode PE1 is connected to the first drain electrode DE1 through the first connection electrode 771 on the first drain contact hole 901 .

[0103] In an exemplary embodiment, the first pixel electrode PE1 may include, for example, a transparent metal layer such as IZO or ITO. In the case where the first pixel electrode PE1 includes IZO, the common electrode 330 may include ITO.

[0104] The light blocking layer 376 is disposed on the second substrate 302. The light blocking layer 376 is disposed in the region adjacent to the gate line, the data line, and the common line and the switching element region (refer to Figure 4) corresponding to the area. The light blocking layer 376 defines an aperture in the area corresponding to the pixel area. As the distance D2 of the pixel electrode area increases, the size of the aperture of the light blocking layer 376 may also increase. Although not shown, the light blocking layer 376 may be disposed on the first substrate 301 instead of the second substrate 302. In an exemplary embodiment, the light blocking layer 376 is disposed on the second passivation layer 322. In an exemplary embodiment, the light blocking layer 376 is also disposed on the area corresponding to the gate line, the data line and the common line and the switching element area.

[0105] The color filter 354 is disposed on the second substrate 302. In an exemplary embodiment, the color filter 354 is disposed in a portion of the aperture region corresponding to the pixel region. In an exemplary embodiment, the edge portion of the color filter 354 is disposed at Figure 3 On the aperture in the.

[0106] The protective layer 722 is disposed on the light blocking layer 376 and the color filter 354. The protective layer 722 may be disposed on substantially the entire surface of the second substrate 302 including the light blocking layer 376. In an exemplary embodiment, the protective layer 722 may effectively prevent a height difference between components of the second substrate 302 (i.e., the light blocking layer 376 and the color filter 354) from being transferred to the liquid crystal layer 333. In an alternative exemplary embodiment, the protective layer 722 may be omitted.

[0107] The liquid crystal layer 333 is disposed between the first substrate 301 and the second substrate 302. In an exemplary embodiment, the liquid crystal layer 333 may include, for example, isotropic liquid crystal molecules having negative dielectric anisotropy. In an alternative exemplary embodiment, the liquid crystal layer 333 may include a photopolymer material, and in an alternative exemplary embodiment, for example, the photopolymer material may be a reactive monomer or a reactive group.

[0108] like Figure 2 As shown, the second pixel includes a second switching element TFT2 and a second pixel electrode PE2.

[0109] The second switching element TFT2 is disposed in a region surrounded by the fourth gate line GL4, the fifth gate line GL5, the third common line CL3, and the fourth data line DL4. In an exemplary embodiment, the second switching element TFT2 may be, for example, a thin film transistor.

[0110] The second switching element TFT2 includes a second gate electrode GE2, a second source electrode SE2 and a second drain electrode DE2 connected to the fifth gate line GL5, the second source electrode SE2 connected to the fourth data line DL4, and the second drain electrode DE2 connected to the second pixel electrode PE2.

[0111] The second gate electrode GE2 and the fifth gate line GL5 may be integrally formed. The second gate electrode GE2 may have a shape protruding from the fifth gate line GL5 toward the fourth gate line GL4.

[0112] In an exemplary embodiment, although not shown, for example, an end portion of the fifth gate line GL5 may be connected to another layer or an external driving circuit.Although not shown, the end portion of the fifth gate line GL5 may include a larger planar area than another portion thereof.

[0113] The second source electrode SE2 and the fourth data line DL4 may be integrally formed. The second source electrode SE2 may have a shape protruding from the fourth data line DL4 toward the second gate electrode GE2.

[0114] The second pixel electrode PE2 is disposed in a region surrounded by the fifth gate line GL5 , the sixth gate line GL6 , the third common line CL3 , and the fourth data line DL4 .

[0115] like Figure 2 As shown, the second pixel electrode PE2 may include a plurality of branch electrodes 450 spaced apart from each other. One end of each branch electrode 450 is connected to the second connection electrode 772. Each branch electrode 450 may overlap with an adjacent gate line, which is adjacent to a corresponding branch electrode 450. In an exemplary embodiment, for example, an end of each branch electrode 450 may overlap with the fifth and sixth gate lines GL5 and GL6. A storage capacitor is provided in a corresponding overlapping region in each branch electrode 450 and the fifth and sixth gate lines GL5 and GL6.

[0116] The second pixel electrode PE2 is connected to the second switching element TFT2. In detail, the second pixel electrode PE2 is connected to the second drain electrode DE2 of the second switching element TFT2. The second pixel electrode PE2 and the second drain electrode DE2 may be connected to each other through the second connection electrode 772. The second connection electrode 772 extends from the second pixel electrode PE2 to the second drain electrode DE2. Figure 2 As shown, the second connection electrode 772 and the second pixel electrode PE2 may be integrated. The second connection electrode 772 may be a part of the second pixel electrode PE2.

[0117] The second connection electrode 772 overlaps the fifth gate line GL5.

[0118] The second connection portion 652 is a connection portion between the second drain electrode DE2 of the second switching element TFT2 and the second pixel electrode PE2. Figure 2As shown, the second connection portion 652 refers to a contact interface between the second drain electrode DE2 and the second pixel electrode PE2. The second pixel electrode PE2 can physically contact the second drain electrode DE2 through a second drain contact hole 902 defined in the first passivation layer 321, the insulating interlayer 352 and the second passivation layer 322.

[0119] The second connection portion 652 is disposed closer to the fourth data line DL4 than the second gate electrode GE2. In an exemplary embodiment, for example, the distance from the fourth data line DL4 to the second connection portion 652 may be smaller than the distance from the fourth data line DL4 to the second gate electrode GE2. Here, each of the distances corresponds to Figure 3 The length of the horizontal line segment in .

[0120] like Figure 2 As shown, the second connection portion 652 is disposed between the fourth data line DL4 and the second gate electrode GE2. In an exemplary embodiment, for example, Figure 2 As shown, the second connection portion 652 may be disposed in a region surrounded by the fourth data line DL4, the second gate electrode GE2, the fifth gate line GL5, and the second source electrode SE2.

[0121] The position of the second drain contact hole 902 may correspond to the position of the second connection portion 652 .

[0122] Since the first connection portion 651 and the second connection portion 652 are respectively disposed between the fourth data line DL4 and the gate electrode GE1 and between the fourth data line DL4 and the gate electrode GE2, and the gate electrodes GE1 and GE2 are respectively disposed adjacent to opposite sides of the fourth data line DL4, the first gate electrode GE1 and the second gate electrode GE2 may be disposed relatively far from the fourth data line DL4. Therefore, the distance between the two gate electrodes GE1 and GE2 adjacent to each other and having the fourth data line DL4 therebetween may be relatively increased. Therefore, in an exemplary embodiment, adjacent gate electrodes, such as the first gate electrode GE1 and the second gate electrode GE2, may not contact each other, even when the distance D1 between the gate lines (such as the fourth and fifth gate lines GL4 and GL5 to which the gate electrodes GE1 and GE2 are respectively connected) is reduced. Due to this structure, in an exemplary embodiment, the distance D1 between the gate lines GL4 and GL5 defining the length of the switching element region may be reduced without contacting the first electrode GE1 and the second electrode GE2, and the distance D2 between the gate lines (such as the third and fourth gate lines GL3 and GL4) defining the length of the pixel electrode region may be increased by the amount of reduction of the distance D1. As the distance D2 increases, the aperture ratio of the pixel may increase.

[0123] Each gate line and each gate electrode include the same material as that included in the first gate electrode GE1. Each source electrode, each drain electrode, each data line, and each common line include the same material as that included in the first source electrode SE1. Each pixel electrode and each connection electrode include the same material as that included in the first pixel electrode PE1.

[0124] Although not shown, an exemplary embodiment of the display device may further include a first polarizer and a second polarizer. In the case where the surfaces of the first substrate 301 and the second substrate 302 facing each other are respectively defined as the upper surfaces of the corresponding substrates, and the surfaces opposite to the upper surfaces are respectively defined as the lower surfaces of the corresponding substrates, the first polarizer is disposed on the lower surface of the first substrate 301, and the second polarizer is disposed on the lower surface of the second substrate 302.

[0125] The transmission axis of the first polarizer is perpendicular to the transmission axis of the second polarizer, and one of the transmission axes thereof is oriented parallel to the gate line GL. In an alternative exemplary embodiment, for example, the LCD device may include only one of the first polarizer and the second polarizer.

[0126] Although not shown, an exemplary embodiment of the display device may further include, for example, a light blocking electrode. The light blocking electrode may be disposed on the second passivation layer 322 to overlap with each data line (e.g., the fifth data line DL5). The light blocking electrode is disposed along the data line. The light blocking electrode includes the same material as that included in the first pixel electrode PE1.

[0127] The light blocking electrode receives a common voltage. The light blocking electrode prevents an electric field from being formed between the data line (e.g., the fifth data line DL5) and the pixel electrode (e.g., the first pixel electrode PE1). Since the light blocking electrode and the common electrode 330 receiving the same common voltage are equipotential, the light transmitted through the liquid crystal layer 333 between the light blocking electrode and the common electrode 330 is blocked by the second polarizer. Therefore, in an exemplary embodiment, light leakage in the area corresponding to the data line (e.g., the fifth data line DL5) is prevented. In addition, since the light blocking electrode can replace a portion of the light blocking layer 376 on the data line (e.g., the fifth data line DL5), in the case of using the light blocking electrode in the display device, the portion of the light blocking layer 376 on the data line (e.g., the fifth data line DL5) can be removed. Therefore, in the case of setting the light blocking electrode, the aperture ratio of the pixel can be further increased.

[0128] Figure 4 It shows Figure 2 An enlarged view of an exemplary embodiment of a switching element area.

[0129] like Figure 4As shown, a light blocking layer 376 is disposed on the regions of the gate lines GL4 and GL5, the data lines DL4 and DL5, the common lines CL3, CL4 and CL5, and the switching element region. The light blocking layer 376 overlaps each of the gate lines GL4 and GL5, each of the data lines DL4 and DL5, each of the common lines CL3, CL4 and CL5, and the switching element region.

[0130] In an exemplary embodiment, for example, the width D of the light blocking layer 376 on each of the gate lines GL4 and GL5 and the switching element region may be in the range of about 40 μm to about 47 μm. In an exemplary embodiment, for example, the width D of the light blocking layer 376 may be about 41 μm.

[0131] Figure 5A , 5B , 5C, 5D, 5E, 5F, 5G, 5H, 5I, 5J, 5K and 5L are diagrams for manufacturing Figure 3 A cross-sectional view of an exemplary embodiment of a process for a display device.

[0132] In an exemplary embodiment, although not shown, a gate metal layer may be disposed on the entire surface of the first substrate 301. In an exemplary embodiment, the gate insulating layer may be disposed by a physical vapor deposition ("PVD") method such as sputtering.

[0133] Then, if Figure 5A As shown, the gate metal layer is patterned by a photolithography process and an etching process, so that the gate line GL4 and the gate electrode GE1 are disposed on the first substrate 301 .

[0134] In exemplary embodiments, for example, the gate metal layer may be removed by a wet etching method using an etching solution.

[0135] The gate metal layer may include or consist of a material included in the gate line.

[0136] Then, if Figure 5B As shown, the gate insulating layer 311 is disposed on the entire surface of the first substrate 301 including the gate line GL4 and the gate electrode GE1. In an exemplary embodiment, for example, the gate insulating layer 311 may be disposed by a chemical vapor deposition ("CVD") method.

[0137] The gate insulating layer 311 may include or consist of the materials included in the aforementioned gate insulating layer 311 .

[0138] Subsequently, although not shown, a semiconductor material and an impurity semiconductor material are sequentially disposed on the entire surface of the first substrate 301 including the gate insulating layer 311. In an exemplary embodiment, for example, the semiconductor material and the impurity semiconductor material may be disposed by a CVD method.

[0139] The semiconductor material may include or consist of a material contained in the semiconductor layer 344 .

[0140] The impurity semiconductor material may include or consist of a material included in the first and second ohmic contact layers 321 a and 321 b .

[0141] Subsequently, the semiconductor material and the impurity semiconductor material are patterned by a photolithography process and an etching process, so that a semiconductor layer 344 overlapping with the gate electrode GE1 is disposed on the gate insulating layer 311, and a first impurity semiconductor pattern 841 is disposed on the semiconductor layer 344, as shown in FIG. Figure 5C shown.

[0142] In exemplary embodiments, for example, the semiconductor material and the impurity semiconductor material may be removed by a dry etching method using an etching gas.

[0143] Subsequently, although not shown, a source metal layer is disposed on the entire surface of the first substrate 301 including the semiconductor layer 344 and the impurity semiconductor pattern 841 .

[0144] The source metal layer may be made using a material included in the data line DL4 .

[0145] Subsequently, the source metal layer is patterned by a photolithography process and an etching process, so that the data line DL4 intersecting the gate line GL4 is disposed on the gate insulating layer 311, and the source electrode SE1 and the drain electrode DE1 overlapping opposite sides of the semiconductor layer 344 are disposed on the impurity semiconductor pattern 841, as shown in FIG. Figure 5D shown.

[0146] Subsequently, the impurity semiconductor pattern 841 is patterned by an etching process in a state where the source electrode SE1 and the drain electrode DE1 are used as masks, and Figure 5E As shown, a first ohmic contact layer 321 a and a second ohmic contact layer 321 b are provided. The first ohmic contact layer 321 a is disposed between the source electrode SE1 and the semiconductor layer 344 , and the second ohmic contact layer 321 b is disposed between the drain electrode DE1 and the semiconductor layer 344 .

[0147] In an exemplary embodiment, during the etching process of the impurity semiconductor pattern 841, a portion of the semiconductor layer 344 below the impurity semiconductor pattern 841 is removed. Therefore, a thickness of a portion corresponding to a channel region of the semiconductor layer 344 is reduced.

[0148] Then, if Fig. 5F As shown, the first passivation layer 321 is disposed on the entire surface of the first substrate 301 including the data line DL4 , the source electrode SE1 , the drain electrode DE1 , and the common line CL4 .

[0149] The first passivation layer 321 may include the material included in the aforementioned first passivation layer 321 .

[0150] Subsequently, although not shown, a photosensitive organic material is disposed on the entire surface of the first substrate 301 including the first passivation layer 321 .

[0151] Subsequently, as the photosensitive organic material is patterned by a photolithography process, an insulating interlayer 352 having a first drain contact hole 901 and a common contact hole 904 is disposed on the first passivation layer 321, as shown in FIG. Figure 5G shown.

[0152] Subsequently, the first passivation layer 321 is patterned by an etching process while using the insulating interlayer as a mask, so that the first drain contact hole 901 and the common contact hole 904 are defined in the first passivation layer 321, as shown in FIG. Figure 5H A portion of the drain electrode DE1 and a portion of the common line CL4 are exposed through the first drain contact hole 901 and the common contact hole 904 of the first passivation layer 321, respectively.

[0153] Then, if Fig.5I As shown, an ashing process is performed. Through the ashing process, the insulating interlayer 352 is Fig.5I The thickness in the vertical direction and Fig.5I The width in the horizontal direction of the insulating interlayer 352 is reduced. Therefore, the width of the first drain contact hole 901 of the insulating interlayer 352 and the width of the common contact hole 904 in the horizontal direction are relatively increased, and as the width increases, a portion of the first passivation layer 321 is exposed through the first drain contact hole 901 and the common contact hole 904 of the insulating interlayer 352. As the thickness of the insulating interlayer 352 decreases, the height of the inner wall of the first drain contact hole 901 and the common contact hole 904 decreases, and as the width of the insulating interlayer 352 decreases, the inner wall of the first drain contact hole 901 and the common contact hole 904 forms a step shape, although not shown. The ashing process of the insulating interlayer 352 is performed so as to effectively reduce the height difference of the insulating interlayer 352 generated by the first drain contact hole 901 and the common contact hole 904. Therefore, the short-circuit defect of the common electrode 330 and the short-circuit defect of the pixel electrode PE1 can be effectively prevented.

[0154] Subsequently, although not shown, a transparent metal layer is disposed on the entire surface of the first substrate 301 including the insulating interlayer 352 .

[0155] Subsequently, as the transparent metal layer is patterned by a photolithography process and an etching process, a common electrode 330 contacting the common line CL4 via the common contact hole 904 is disposed on the insulating interlayer 352 and the first passivation layer 321, as shown in FIG. Figure 5J shown.

[0156] The transparent metal layer may include a material included in the common electrode 330 .

[0157] Then, if Figure 5K As shown, the second passivation layer 322 is disposed on the common electrode 330, the first passivation layer 321 and the drain electrode DE1. Subsequently, the second passivation layer 322 is patterned by a photolithography process and an etching process. Therefore, a first drain contact hole 901 exposing the drain electrode DE1 is defined in the second passivation layer 322.

[0158] The second passivation layer 322 may include the material included in the aforementioned second passivation layer 322 .

[0159] Subsequently, although not shown, a transparent metal layer is disposed on the entire surface of the first substrate 301 including the second passivation layer 322 and the drain electrode DE1.

[0160] The transparent metal layer may include a material included in the pixel electrode PE1.

[0161] Subsequently, the transparent metal layer is patterned by a photolithography process and an etching process, and a pixel electrode PE1 and a first connection electrode 771 connected to the drain electrode DE1 via a first drain contact hole 901 are provided. Figure 5L shown.

[0162] Figure 6 It shows Figure 1 Detailed view of an alternative exemplary embodiment of area A of FIG.

[0163] The first source electrode SE1 of the first switching element TFT1 includes a first source extension portion 841 a and a first source electrode portion 841 b .

[0164] The first source electrode portion 841b is disposed on the first gate electrode GE1 and the fourth gate line GL4. An entire region of the first source electrode portion 841b may overlap the first gate electrode GE1 and the fourth gate line GL4.

[0165] The first source extension portion 841a extends from the fourth data line DL4 toward the first source electrode portion 841b. The first source extension portion 841a connects the fourth data line DL4 and the first source electrode portion 841b. In an exemplary embodiment, the first source extension portion 841a may overlap one of two gate lines GL4 and GL5 disposed adjacent to each other and including the first source extension portion 841a therebetween. In an exemplary embodiment, for example, Figure 6 As shown, the first source extension portion 841a may overlap with the fourth gate line GL4. In an exemplary embodiment, the fourth gate line GL4 may overlap with the entire area of ​​the first source extension portion 841a. In an alternative exemplary embodiment, although not shown, the first source extension portion 841a may overlap with the fifth gate line GL5. In an exemplary embodiment, the fifth gate line GL5 may overlap with the entire area of ​​the first source extension portion 841a.

[0166] The second source electrode SE2 of the second switching element TFT2 includes a second source extension portion 842 a and a second source electrode portion 842 b .

[0167] The second source electrode portion 842b is disposed on the second gate electrode GE2 and the fifth gate line GL5. An entire area of ​​the second source electrode portion 842b may overlap the second gate electrode GE2 and the fifth gate line GL5.

[0168] The second source extension portion 842a extends from the fourth data line DL4 toward the second source electrode portion 842b. The second source extension portion 842a connects the fourth data line DL4 and the second source electrode portion 842b. In an exemplary embodiment, the second source extension portion 842a may overlap one of two gate lines GL4 and GL5 disposed adjacent to each other and including the second source extension portion 842a therebetween. In an exemplary embodiment, for example, Figure 6 As shown, the second source extension portion 842a may overlap with the fifth gate line GL5. In an exemplary embodiment, the fifth gate line GL5 may overlap with the entire area of ​​the second source extension portion 842a. In an alternative exemplary embodiment, although not shown, the second source extension portion 842a may overlap with the fourth gate line GL4. In an exemplary embodiment, the fourth gate line GL4 may overlap with the entire area of ​​the second source extension portion 842a.

[0169] Therefore, in an exemplary embodiment, when the source electrode portion overlaps the gate line, the distance D3 between the gate lines (e.g., the fourth and fifth gate lines GL4 and GL5) defining the length of the switching element region can be further reduced, and the distance D4 between the gate lines (e.g., the third and fourth gate lines GL3 and GL4) defining the pixel electrode region can be further increased by the reduced length. As the distance D4 increases, the aperture ratio of the pixel can be further increased. Here, the distance D3 is less than the distance D1, and the distance D4 is greater than the distance D2.

[0170] In an exemplary embodiment, the distance D3 between the fourth gate line GL4 and the fifth gate line GL5 may be, for example, in the range of about 30 μm to about 41 μm. In an exemplary embodiment, for example, the distance D3 may be about 31 μm. In an exemplary embodiment, the width D of the light blocking layer 376 may be in the range of about 35 μm to about 38 μm. In an exemplary embodiment, for example, the width D may be about 37 μm.

[0171] In an exemplary embodiment, Figure 2 The first source extension portion of the first source electrode SE1 and the second source extension portion of the second source electrode SE2 are shown not overlapping any gate line. Except for the positions of the first source extension portion 841a and the second source extension portion 841b, Figure 2 The structure of the display device shown and Figure 6 The display devices shown are constructed identically to each other, so Figure 6 The description of the construction will refer to Figure 2 , 3 and 4 and their related descriptions.

[0172] Figure 7 It shows Figure 1 Detailed view of another alternative exemplary embodiment of area A of FIG.

[0173] like Figure 7 As shown, an alternative exemplary embodiment of the display device may further include, for example, at least one of a first compensation pattern 931 and a second compensation pattern 932 .

[0174] The first compensation pattern 931 extends from the fourth gate line GL4 to overlap the first drain electrode DE1. The first compensation pattern 931 and the fourth gate line GL4 may be integral. The first compensation pattern 931 includes the same material as that included in the fourth gate line GL4.

[0175] The first compensation pattern 931 may significantly reduce (e.g., minimize) a size change in the overlapped area between the first gate electrode GE1 and the first drain electrode DE1, which size change is caused by mask misalignment. In an exemplary embodiment, for example, in a case where the first drain electrode DE1 moves to the right from a normal position due to mask misalignment, the overlapped area between the first drain electrode DE1 and the first gate electrode GE1 may increase, while the overlapped area between the first drain electrode DE1 and the first compensation pattern 931 decreases. In an alternative exemplary embodiment, in a case where the first drain electrode DE1 moves to the left from a normal position due to mask misalignment, the overlapped area between the first drain electrode DE1 and the first gate electrode GE1 decreases, while the overlapped area between the first drain electrode DE1 and the first compensation pattern 931 increases. Therefore, although the first drain electrode DE1 moves to the left or right due to mask misalignment, the total size of the overlapped area between the first gate electrode GE1 and the first drain electrode DE1 may be substantially constant.

[0176] The second compensation pattern 932 extends from the fifth gate line GL5 to overlap the second drain electrode DE2. The second compensation pattern 932 and the fifth gate line GL5 may be integral. The second compensation pattern 932 may include the same material as that included in the fifth gate line GL5.

[0177] The second compensation pattern 932 may significantly reduce (eg, minimize) a size variation of an overlap region between the second gate electrode GE2 and the second drain electrode DE2 , the size variation being caused by mask misalignment.

[0178] The magnitude of the parasitic capacitance of the first switching element TFT1 may be stabilized by the first compensation pattern 931 , and the magnitude of the parasitic capacitance of the second switching element TFT2 may be stabilized by the second compensation pattern 932 .

[0179] In addition to the first and second compensation patterns 931 and 932, Figure 2 The structure of the display device shown and Figure 7 The display devices shown are constructed identically to each other, so Figure 7 The description of the construction will refer to Figure 2 , 3 and 4 and their related descriptions.

[0180] Figure 8 is a plan view showing an alternative exemplary embodiment of a display device.

[0181] like Figure 8As shown, an alternative exemplary embodiment of the display device may include a plurality of gate lines GL1, GL2, ..., a plurality of data lines DL1 to DLj, a plurality of common lines CL1 to CLj-1, a plurality of pixels RP, GP and BP, a plurality of first virtual pixels DP1 and a plurality of second virtual pixels DP2.

[0182] The plurality of pixels DP1, RP, GP, BP, and DP2 include a red pixel RP representing a red image, a green pixel GP representing a green image, a blue pixel BP representing a blue image, a first dummy pixel DP1, and a second dummy pixel DP2.

[0183] Although Figure 8 Although not shown in the figure, each of the pixels DP1, RP, GP, BP and DP2 includes a switching element and a pixel electrode connected to the switching element. Each switching element is connected to a corresponding gate line and a corresponding data line, and Figure 8 It shows which gate line and which data line each switching element of a pixel is connected to. In other words, Figure 8 The electrical connection relationship between each switching element of the pixel and the corresponding gate line and the electrical connection relationship between each switching element of the pixel and the corresponding data line are shown. In an exemplary embodiment, for example, among the pixels of the first horizontal line HL1, the switching element included in the first virtual pixel DP1 can be connected to the first gate line GL1 and the second data line DL2.

[0184] In an exemplary embodiment, Figure 8 The position of the pixel in the substantially corresponds to the position of the pixel electrode of the pixel among the components included in the corresponding pixel. In an exemplary embodiment, for example, in the pixel of the second horizontal line HL2, the first red pixel RP from the left side connected to the first data line DL1 may be disposed between the third gate line GL3 and the fourth gate line GL4. However, the switching element of the first red pixel RP is not disposed between the third gate line GL3 and the fourth gate line GL4, but is disposed between the fourth gate line GL4 and the fifth gate line GL5. Hereinafter, reference is made to Figure 8 The position of a pixel or a virtual pixel described herein refers to the position of a pixel electrode of the pixel among the components included in the corresponding pixel. Figure 8 The description “the predetermined pixel is disposed between the first gate line GL1 and the second gate line GL2” means that the pixel electrode of the predetermined pixel is disposed between the first gate line GL1 and the second gate line GL2. Figure 8 The description “a predetermined pixel is disposed between the first data line DL1 and the first common line CL1 ” means that a pixel electrode of the predetermined pixel is disposed between the first data line DL1 and the first common line CL1 .

[0185] The red pixel RP is connected to a gate line disposed farther from the pixel electrode of the red pixel RP among two gate lines close to the lower portion of the red pixel RP. In an exemplary embodiment, for example, the red pixel RP in the third horizontal line HL3 may be connected to the seventh gate line GL7, which is farther from the pixel electrode of the red pixel RP among the sixth and seventh gate lines GL6 and GL7 below the red pixel RP. However, only one gate line is disposed below the red pixel RP in the last horizontal line, and thus the red pixel RP in the last horizontal line is connected to the one gate line.

[0186] The green pixel GP is connected to a gate line disposed farther from the pixel electrode of the green pixel GP among two gate lines close to the upper portion of the green pixel GP. In an exemplary embodiment, for example, the green pixel GP in the third horizontal line HL3 may be connected to a fourth gate line GL4, which is farther from the pixel electrode of the green pixel GP among the fourth and fifth gate lines GL4 and GL5 above the green pixel GP. However, in an exemplary embodiment, in the first horizontal line HL1, only one gate line (e.g., the first gate line GL1) is disposed above the green pixel GP, and thus the green pixel GP in the first horizontal line HL1 is connected to the one gate line, e.g., the first gate line GL1.

[0187] In an exemplary embodiment, for example, the blue pixel BP is connected to a gate line disposed farther from the pixel electrode of the blue pixel BP among two gate lines close to the lower portion of the blue pixel BP, or is connected to a gate line disposed farther from the pixel electrode of the blue pixel BP among two gate lines close to the upper portion of the blue pixel BP. In an exemplary embodiment, for example, one of the blue pixels BP in the third horizontal line HL3 may be connected to the seventh gate line GL7, which is farther from the pixel electrode of the blue pixel BP among the sixth and seventh gate lines GL6 and GL7 below the blue pixel BP. In an alternative exemplary embodiment, another of the blue pixels BP in the third horizontal line HL3 is connected to the fourth gate line GL4, which is farther from the pixel electrode of the blue pixel BP among the fourth and fifth gate lines GL4 and GL5 above the blue pixel BP.

[0188] In addition to the connection position of the gate line, Figure 1 The structure of the display device shown and Figure 8 The display devices shown are constructed identically to each other, so Figure 8 The description of the construction will refer to Figure 1 and its related description.

[0189] Fig. 9 It shows Figure 8 Detailed view of an exemplary embodiment of area B.

[0190] like Fig. 9 As shown, the first gate electrode GE1 of the first switching element TFT1 and the fifth gate line GL5 may be integrated. The first gate electrode GE1 of the first switching element TFT1 may have a shape protruding from the fifth gate line GL5 toward the fourth gate line GL4.

[0191] That is to say, reference Fig. 9 , the first gate electrode GE1 of the first switching element TFT1 may be integrated with the fifth gate line GL5 which is farther away from the first pixel electrode PE1 among the two gate lines GL4 and GL5. Figure 2 , the first gate electrode GE1 of the first switching element TFT1 is integrated with the fourth gate line GL4 , which is closer to the first pixel electrode PE1 , among the two gate lines GL4 and GL5 .

[0192] like Fig. 9 As shown, the second gate electrode GE2 of the second switching element TFT2 is integral with the fourth gate line GL4. The second gate electrode GE2 of the second switching element TFT2 may have a shape protruding from the fourth gate line GL4 toward the fifth gate line GL5.

[0193] That is to say, reference Fig. 9 , the second gate electrode GE2 of the second switching element TFT2 may be integrated with the fourth gate line GL4 disposed farther away from the second pixel electrode PE2 among the two gate lines GL4 and GL5. Figure 2 The second gate electrode GE2 of the second switching element TFT2 is integrated with the fifth gate line GL5 which is closer to the second pixel electrode PE2 among the two gate lines GL4 and GL5.

[0194] according to Fig. 9 In the structure shown, since the first connection portion 651 and the second connection portion 652 are respectively disposed between the fourth data line DL4 and the gate electrode GE1 and between the fourth data line DL4 and the gate electrode GE2, and the gate electrodes GE1 and GE2 are respectively disposed adjacent to opposite sides of the fourth data line DL4, the first gate electrode GE1 and the second gate electrode GE2 can be disposed relatively far from the fourth data line DL4. Therefore, as described above, the aperture ratio of the pixel can be increased.

[0195] according to Fig. 9 In the structure shown, the first connection electrode 771 overlaps the fourth common line CL4 and the fourth gate line GL4, and the second connection electrode 772 overlaps the fifth gate line GL5.

[0196] In addition to the connection position of the gate line, Figure 2 The structure of the display device shown and Fig. 9The display devices shown are constructed identically to each other, so Fig. 9 The description of the construction will refer to Figure 2 , 3 and 4 and their related descriptions.

[0197] The structure of the exemplary embodiment of the display device may be applicable to various display devices, such as an LCD device and an organic light emitting diode ("OLED") display device.

[0198] As described above, according to one or more exemplary embodiments, the display device may provide the following effects.

[0199] According to one or more exemplary embodiments, the connection portion between the drain electrode of the switching element and the pixel electrode is arranged to be closer to the data line than the gate electrode to the data line. Therefore, the distance between the gate electrodes arranged on opposite sides of the adjacent data line can be increased. Due to this structure, the distance between the gate lines defining the length of the switching element area can be reduced, and the distance between the gate lines defining the length of the pixel electrode area can be increased by the reduced distance. As the length of the pixel electrode area increases, the aperture ratio of the pixel can be increased.

[0200] From the foregoing, it will be appreciated that various exemplary embodiments according to the present invention are described herein for illustrative purposes, and various modifications may be made without departing from the scope and spirit of this teaching. Therefore, the various exemplary embodiments disclosed herein are not intended to limit the true scope and spirit of this teaching. The various features of the above and other exemplary embodiments may be mixed and matched in any manner to produce other exemplary embodiments consistent with the present invention.

Claims

1. A display device, comprising: A first gate line and a data line crossing each other; Pixel electrode; a switching element, comprising a first gate electrode connected to the first gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode; a connecting portion, connecting the drain electrode to the pixel electrode, a portion of the connecting portion overlapping the drain electrode; as well as a second gate line crossing the data line, adjacent to the first gate line, and including a second gate electrode connected to the second gate line, wherein the first gate electrode and the second gate electrode are disposed in a region surrounded by the first gate line, the second gate line, the data line, and another data line adjacent to the data line, and when viewed along a direction in which the data line extends, the first gate electrode and the second gate electrode do not overlap each other, The portion of the connection portion overlapping the drain electrode is between the data line and the first gate electrode.

2. The display device of claim 1, wherein the connection portion is provided between the data line and the first gate electrode. 3 . The display device of claim 2 , wherein the connection portion is provided in a region surrounded by the data line, the first gate electrode, the first gate line, and the source electrode. 4 . The display device according to claim 1 , wherein the drain electrode and the pixel electrode are connected to each other through a contact hole located in a region corresponding to the connection portion. 5 . The display device of claim 1 , further comprising a compensation pattern extending from the first gate line and overlapping the drain electrode.

6. The display device according to claim 1, wherein the source electrode comprises: an electrode portion overlapping with the first gate electrode; as well as The electrode portion is connected to the extending portion of the data line. 7 . The display device of claim 6 , wherein the extending portion overlaps the first gate line. 8 . The display device of claim 1 , wherein a distance between the first gate line and the second gate line is in a range of 30 μm to 41 μm. 9 . The display device of claim 1 , further comprising a light blocking layer overlapping the first gate line and the second gate line and disposed between the first gate line and the second gate line. 10 . The display device of claim 9 , wherein the light blocking layer has a width of from 35 micrometers to 38 micrometers or from 40 micrometers to 47 micrometers. 11 . The display device of claim 1 , wherein the first gate electrode protrudes from the first gate line toward the second gate line. 12 . The display device of claim 1 , further comprising a common line crossing the first gate line and the second gate line. 13 . The display device of claim 12 , wherein the switching element is disposed in a region surrounded by the first gate line, the second gate line, the data line, and the common line. 14 . The display device of claim 12 , wherein the pixel electrode overlaps the first gate electrode, the drain electrode, the common line, and the first gate line.

15. The display device of claim 1, wherein the pixel electrode overlaps the first gate line. 16 . The display device of claim 12 , wherein the pixel electrode overlaps the first gate electrode, the source electrode, the common line, and the second gate line.

17. The display device of claim 1, wherein the pixel electrode overlaps the source electrode and the second gate line. 18 . The display device of claim 1 , wherein in a plan view, a distance between the data line and the connection portion is smaller than a distance between the data line and the first gate electrode in a first direction perpendicular to the data line.

19. The display device of claim 1, wherein the connection portion overlapping the drain electrode is closer to the data line than the source electrode.

20. The display device of claim 1, wherein the connection portion overlapping the drain electrode is closer to the data line than the first gate electrode.

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