Real-time clock calibration circuit, method and chip structure

Abstract

The embodiment of the present invention provides a real-time clock calibration circuit, method and chip structure, belonging to the field of chip technology. The real-time clock calibration circuit includes: a clock module, including a system clock, a real-time clock and a reference clock, wherein the reference clock is configured to have a fixed frequency; a statistical module, used to count the number of cycles of the real-time clock and the reference clock when the system clock, the real-time clock and the reference clock are in clock synchronization; and a calibration module, used to calibrate the real-time clock according to the respective frequencies and the number of cycles of the real-time clock and the reference clock. The real-time clock calibration circuit of the present invention overcomes the problems of inaccurate calibration and complex operation caused by the frequency instability of the system clock.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a real-time clock calibration circuit, method and chip structure. Background Art

[0002] As an indispensable part of the main control chip and metering chip, the real-time clock (RTC) is responsible for a series of application requirements such as timing, alarm clock, and perpetual calendar. Timing accuracy is the most important part of the real-time clock design, which directly affects the performance indicators of the real-time clock. Usually, the real-time clock uses a relatively stable internal crystal oscillator with a clock frequency of 32768Hz as the timing clock source. However, due to the influence of time or temperature, the frequency of the internal crystal oscillator will shift. In addition, some designs also use other external crystal oscillators with frequencies near 32768Hz as alternative clock sources, but their accuracy is not easy to guarantee. Therefore, the calibration scheme for the timing clock source has become an indispensable part of the RTC design.

[0003] The existing scheme mainly uses digital hardware circuits to realize RTC calibration, including: the first step, setting an appropriate number of RTC timing cycles through a statistical circuit, obtaining the number of system clocks within this number of cycles, and then obtaining the actual frequency division ratio of the system clock and the RTC clock; the second step, calculating the difference between the actual frequency division ratio and the ideal frequency division ratio (that is, the frequency division ratio of the system clock and the standard 32768Hz clock) through a calculation circuit, and obtaining calibration parameters through normalization, register shifting and other processing methods; the third step, performing the calibration operation of the real-time clock module according to the obtained calibration parameters.

[0004] However, the inventors of the present application found in the process of implementing the present invention that the existing solutions have at least the following defects:

[0005] 1) The clock source of the chip's system clock usually has multiple clocks of different frequencies to switch and the stability of each clock cannot be guaranteed, which makes the actual frequency division ratio obtained in the first step above substantially inaccurate.

[0006] 2) For the second step, a series of algorithms are required for the actual division ratio and the ideal division ratio to obtain the calibration parameters. Among them, the ideal division ratio is determined by the system clock, but there are many application scenarios for the chip, and different application scenarios require system clocks of different frequencies to complete. Therefore, it is impossible to ensure that the system clock for each RTC calibration is a fixed frequency. This will cause the algorithm configuration in the second step to change frequently, bringing complexity to the clock calibration operation. If the frequency of the system clock is fixed simply considering clock calibration, it will bring limitations to the application of the chip. Summary of the invention

[0007] The purpose of the embodiments of the present invention is to provide a real-time clock calibration circuit, method and chip structure, which are used to at least partially solve the above technical problems.

[0008] In order to achieve the above-mentioned purpose, an embodiment of the present invention provides a real-time clock calibration circuit, comprising: a clock module, including a system clock, a real-time clock and a reference clock, wherein the reference clock is configured to have a fixed frequency; a statistical module, used to count the number of cycles of the real-time clock and the reference clock when the system clock, the real-time clock and the reference clock are in clock synchronization; and a calibration module, used to calibrate the real-time clock according to the respective frequencies and the number of cycles of the real-time clock and the reference clock.

[0009] Furthermore, the statistical module includes: a counting unit, used to count the number of cycles of the real-time clock and the reference clock in a clock synchronization process relative to the system clock; and a synchronization unit, used to achieve clock synchronization of the system clock, the real-time clock and the reference clock, so that the counting unit counts the number of cycles of the real-time clock and the reference clock based on the synchronization clock.

[0010] Furthermore, the counting unit includes: a first counting circuit, which uses the real-time clock as a clock and starts counting the number of cycles of the real-time clock in response to a start signal from the system clock; and a second counting circuit, which uses the reference clock as a clock and starts counting the number of cycles of the reference clock in response to a start signal from the system clock.

[0011] Furthermore, the synchronization unit includes: a first clock synchronization unit, arranged between the system clock and the first counting circuit, for realizing clock synchronization between the system clock and the real-time clock; a second clock synchronization unit, arranged between the system clock and the second counting circuit, for realizing clock synchronization between the system clock and the reference clock; and a third clock synchronization unit, arranged between the first counting circuit and the second counting circuit, for realizing clock synchronization between the real-time clock and the reference clock.

[0012] Furthermore, the first counting circuit is configured to perform subtraction counting starting from a preset number of cycles, and the second counting circuit is configured to perform addition counting starting from zero; and, when the subtraction count reaches zero, the first counting circuit generates a stop signal, and sends the stop signal to the second counting circuit via the third clock synchronization unit, and the second counting circuit stops counting in response to receiving the stop signal.

[0013] Furthermore, the system clock generates the start signal using a control register, and sends the start signal to the first counting circuit through the first clock synchronization unit, and sends the start signal to the second counting circuit through the second clock synchronization unit.

[0014] Furthermore, the calibration module includes: a compensation cycle calculation circuit, used to calculate the number of cycles to be compensated of the real-time clock based on the ideal division ratio of the real-time clock and the reference clock and the number of cycles; and a clock compensation circuit, used to calibrate the real-time clock based on the calculated number of cycles to be compensated.

[0015] Furthermore, the compensation cycle calculation circuit calculates the number of cycles to be compensated Y of the real-time clock using the following formula:

[0016]

[0017] Wherein, C2 and C1 are the cycle numbers corresponding to the reference clock and the real-time clock, respectively. is the ideal frequency division ratio between the reference clock and the real-time clock, N is the fixed frequency of the reference clock, and M is the initial frequency of the real-time clock with a frequency error.

[0018] Furthermore, when the statistical module performs subtraction counting on the real-time clock to count the corresponding number of cycles, C1 is the preset number of cycles of the real-time clock in a clock synchronization count; and the compensation cycle calculation circuit is also used to improve the accuracy of the calculated number of cycles to be compensated of the real-time clock by increasing C1.

[0019] Furthermore, the clock compensation circuit calibrates the real-time clock according to the calculated number of cycles to be compensated, including: determining the frequency error X=Y*M of the real-time clock based on the number of cycles to be compensated Y and the initial frequency M of the real-time clock; if the number of cycles to be compensated Y is greater than zero, then when the real-time clock is in the timing stage, increasing the number of cycles of the real-time clock, so that the real-time clock compensates for the existing frequency error by timing M+X cycles; and if the number of cycles to be compensated Y is less than zero, then when the real-time clock is in the timing stage, reducing the number of cycles of the real-time clock, so that the real-time clock compensates for the existing frequency error by timing MX cycles.

[0020] Furthermore, the compensation cycle calculation circuit is also used for: when the calculated number of cycles to be compensated Y of the real-time clock is a decimal, updating the number of cycles to be compensated Y to Y*P, wherein P is a positive integer.

[0021] Furthermore, the system clock is a clock source with any clock frequency.

[0022] An embodiment of the present invention also provides a real-time clock calibration method, comprising: when a system clock, a real-time clock and a reference clock are in clock synchronization, counting the number of cycles of the real-time clock and the reference clock, wherein the reference clock is configured to have a fixed frequency; and calibrating the real-time clock according to the respective frequencies and the number of cycles of the real-time clock and the reference clock.

[0023] Furthermore, the counting of the number of cycles of the real-time clock and the reference clock includes: counting the number of cycles of the real-time clock and the reference clock in a clock synchronization process relative to the system clock; and when the system clock, the real-time clock and the reference clock are in clock synchronization, counting the number of cycles of the real-time clock and the reference clock based on the synchronization clock.

[0024] An embodiment of the present invention further provides a chip structure, comprising: a system clock, a real-time clock and a reference clock; and any of the above real-time clock calibration circuits, used for calibrating the real-time clock.

[0025] Through the above technical scheme, the real-time clock calibration scheme of the embodiment of the present invention introduces a reference clock with a fixed frequency, so that the calibration of the real-time clock no longer depends on the system clock of the chip, thereby overcoming the problems of inaccurate calibration and complex operation caused by the frequency instability of the system clock, or overcoming the problem of limited application range of the chip due to the fixed system clock.

[0026] Other features and advantages of the embodiments of the present invention will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0028] Figure 1 is a functional structure diagram of a real-time clock calibration circuit according to an embodiment of the present invention;

[0029] Figure 2 is a schematic structural diagram of an exemplary real-time clock calibration circuit according to an embodiment of the present invention;

[0030] Figure 3 is a schematic diagram of a flow chart of clock accuracy compensation in an embodiment of the present invention; and

[0031] Figure 4 The figure is a flow chart of a real-time clock calibration method according to an embodiment of the present invention.

[0032] Description of Reference Numerals

[0033] 100, clock module; 200, statistics module; 300, calibration module;

[0034] 210, counting unit; 220, synchronization unit;

[0035] 310, compensation period calculation circuit; 320, clock compensation circuit;

[0036] 211. A first counting circuit; 212. A second counting circuit. DETAILED DESCRIPTION

[0037] The specific implementation of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the present invention, and is not used to limit the embodiment of the present invention.

[0038] Figure 1 Schematic diagram of the functional structure of the real-time clock calibration circuit according to an embodiment of the present invention. Figure 1 As shown, the real-time clock calibration circuit includes: a clock module 100, including a system clock, a real-time clock (hereinafter also referred to as an RTC clock) and a reference clock, wherein the reference clock is configured to have a fixed frequency; a statistical module 200, used to count the number of cycles of the real-time clock and the reference clock when the system clock, the real-time clock and the reference clock are in clock synchronization; and a calibration module 300, used to calibrate the real-time clock according to the respective frequencies and the number of cycles of the real-time clock and the reference clock.

[0039] Among them, the reference clock is configured to have a fixed frequency, and it should be noted that the fixed frequency is free of frequency error. For example, the reference clock is a stable clock source with a clear frequency of 5MHz; the real-time clock refers to a clock used to provide real-time time information, which is a clock expected to be calibrated in the embodiment of the present invention, and is, for example, a 10MHz clock source with a frequency error of X; the system clock refers to the main clock inside the operating system that provides the working clock basis for each module. In the embodiment of the present invention, the system clock can be a clock source with any clock frequency. In the embodiment of the present invention, it is mainly responsible for the start and configuration parameters of the entire circuit (this will be described in detail below), and there is no clear requirement for the clock frequency.

[0040] The real-time clock calibration circuit of the embodiment of the present invention introduces a reference clock with a fixed frequency without frequency error, so that the calibration of the real-time clock is no longer dependent on the system clock of the chip, thereby overcoming the problems of inaccurate calibration and complex operation caused by the frequency instability of the system clock, or overcoming the problem of limited application range of the chip due to the fixed system clock.

[0041] In a preferred embodiment, the statistical module 200 may include: a counting unit 210, used to count the number of cycles of the real-time clock and the reference clock during a clock synchronization process relative to the system clock; and a synchronization unit 220, used to achieve clock synchronization of the system clock, the real-time clock and the reference clock, so that the counting unit 210 counts the number of cycles of the real-time clock and the reference clock based on the synchronization clock.

[0042] In another preferred embodiment, the calibration module 300 may include: a compensation period calculation circuit 310, used to calculate the number of periods to be compensated of the real-time clock based on the ideal division ratio of the real-time clock and the reference clock and the number of periods; and a clock compensation circuit 320, used to calibrate the real-time clock based on the calculated number of periods to be compensated.

[0043] The implementation of the statistical module 200 and the calibration module 300 in the above two preferred embodiments is specifically described below by way of examples. Figure 2 4 is a schematic diagram of the structure of an exemplary real-time clock calibration circuit according to an embodiment of the present invention.

[0044] like Figure 2 As shown, in this example, the counting unit 210 may include: a first counting circuit 211, which uses the real-time clock as a clock (i.e., CLK1) and starts counting the number of cycles of the real-time clock in response to a start signal (i.e., a start signal) from the system clock; and a second counting circuit 212, which uses the reference clock as a clock (i.e., CLK2) and starts counting the number of cycles of the reference clock in response to a start signal (i.e., a start signal) from the system clock.

[0045] Further, in this example, the synchronization unit 220 includes: a first clock synchronization unit sync1, which is arranged between the system clock and the first counting circuit 211, and is used to achieve clock synchronization between the system clock and the real-time clock; a second clock synchronization unit sync2, which is arranged between the system clock and the second counting circuit 212, and is used to achieve clock synchronization between the system clock and the reference clock; and a third clock synchronization unit sync2, which is arranged between the first counting circuit and the second counting circuit, and is used to achieve clock synchronization between the real-time clock and the reference clock.

[0046] The system clock can generate the start signal (start signal) by using the control register, and send the start signal to the first counting circuit 211 through the first clock synchronization unit sync1, and send the start signal to the second counting circuit 212 through the second clock synchronization unit sync2. It should be noted that the real-time clock and the reference clock can be interchanged at the input source positions of CLK1 and CLK2 to make the application of this example more flexible.

[0047] Among them, the first counting circuit 211 is configured to perform subtraction counting starting from a preset number of cycles, and the second counting circuit 212 is configured to perform addition counting starting from zero; and, when the first counting circuit 211 subtracts and counts to zero, it generates a stop signal (i.e., a stop signal), and sends the stop signal to the second counting circuit 212 via the third clock synchronization unit sync2, and the second counting circuit 212 stops counting in response to receiving the stop signal.

[0048] Based on the above, reference Figure 2 When the operation starts, the control register sends a start signal to the first counting circuit 211 and the second counting circuit 212 through the clock synchronization units sync1 and sync2 respectively. The first counting circuit 211 starts to count down from the number of cycles of CLK1 until it reaches 0, and sends a stop signal to the second counting circuit 212 through the clock synchronization unit syn3. The second counting circuit 212 starts to count up from 0, and stops counting after receiving the stop signal. The count value at this time is the number of cycles of CLK2. In this way, the number of cycles of CLK1 and CLK2 are obtained.

[0049] In the traditional solution with only system clock and real-time clock, since the system clock and real-time clock are asynchronous clocks, the signal interaction between the two may generate glitches, affecting the correct counting of the corresponding counting circuit. In this regard, this example not only introduces the reference clock, but also designs the above-mentioned solution of realizing dynamic and safe signal interaction of three clock sources through multiple synchronization units and two counting circuits, which overcomes the defect of signal glitches and can correctly count the number of cycles of CLK1 and CLK2.

[0050] Furthermore, regarding the compensation cycle calculation circuit 310, it can calculate the required number of cycles to be compensated by the following steps:

[0051] Assume that the frequency of CLK1 is M Hz, the frequency of CLK2 is N Hz, the number of cycles of CLK1 is C1, and the number of cycles of CLK2 is C2. In addition, CLK1 is the RTC clock to be calibrated, and its frequency error is X Hz; CLK2 is a known accurate reference clock with no frequency error. Based on this, according to the frequency ratio of CLK1 and CLK2, it can be known that:

[0052] (M+X) / N=C2 / C1 (1)

[0053] By transforming formula (1), we can obtain:

[0054]

[0055] The number of cycles to be compensated Y=X / M, and this formula is combined with the above formula (1) and formula (2), and the following formula (3) of the number of cycles to be compensated Y of the real-time clock can be obtained:

[0056]

[0057] In the formula, as above, C2 and C1 are the cycle numbers corresponding to the reference clock and the real-time clock, respectively, and is the ideal frequency division ratio between the reference clock and the real-time clock, N is the fixed frequency of the reference clock without frequency error, and M is the initial frequency of the real-time clock with frequency error.

[0058] In the example, when the statistical module 200 (specifically the first counting circuit 211) performs subtraction counting on the real-time clock to count the corresponding number of cycles, C1 is the preset number of cycles of the real-time clock in a clock synchronization count (i.e., the number of cycles of CLK1). Based on this, preferably, the compensation cycle calculation circuit 310 can also be used to increase the accuracy of the calculated number of cycles to be compensated of the real-time clock by increasing C1. That is, in the above calculation process, the accuracy of the number of compensation cycles can be effectively improved by increasing the number of cycles of CLK1, and the error caused by the incomplete counting clock cycle when the second counting circuit 212 receives the stop end can be reduced.

[0059] In an example, the clock compensation circuit 320 calibrates the clock by using the obtained number of cycles to be compensated. In combination with the above parameter definition, this process may include the following steps:

[0060] 1) Based on the number of cycles to be compensated Y and the initial frequency M of the real-time clock, determining the frequency error X=Y*M of the real-time clock;

[0061] 2) if the number of cycles to be compensated Y is greater than zero, when the real-time clock is in the timing phase, the number of cycles of the real-time clock is increased so that the real-time clock compensates for the existing frequency error by timing M+X cycles; and

[0062] 3) If the number of cycles to be compensated Y is less than zero, then when the real-time clock is in the timing stage, the number of cycles of the real-time clock is reduced so that the real-time clock compensates for the existing frequency error by timing MX cycles.

[0063] For example, one of the most common application scenarios of the real-time clock RTC is second timing, that is, timing one second. In this application scenario, if the ideal clock frequency of the RTC is M Hz, then the counter needs to count M cycles of the RTC clock to get an accurate 1 second. In this way, if Y>0, the real frequency M' of the RTC clock is greater than M, and the corresponding number of cycles needs to be increased during the RTC timing stage, that is, M+X cycles need to be counted to get an accurate 1 second; if Y<0, the real frequency M' of the RTC clock is less than M, and the corresponding number of cycles needs to be reduced during the RTC timing stage, that is, MX cycles need to be counted to get an accurate 1 second.

[0064] Through this example, it is easy to know that the real-time clock calibration circuit of the embodiment of the present invention involves the use of three clock sources: the system clock, the real-time clock and the reference clock, wherein the frequency of the reference clock is clear and stable, so that the calibration is based on the frequency ratio and cycle ratio of the reference clock and the real-time clock, and no longer depends on the frequency of the system clock, thus avoiding the problems of inaccurate calibration and complicated operation caused by the unstable frequency of the system clock. In addition, in this example, the system clock is only responsible for the start and configuration parameters of the entire calibration circuit, and does not require its clock frequency during the entire clock calibration process, so that the system clock can change its frequency according to the actual application scenario of the chip, expanding the applicability of the corresponding chip.

[0065] In addition, in this example, by processing the interaction of cross-clock domain signals through multiple clock synchronization units, the generation of signal glitches can be effectively reduced, the accuracy of clock calibration can be improved, and the reduction of signal glitches helps to ensure dynamic and safe interaction between clock signals. At the same time, this example provides a simple and accurate algorithm for calculating the number of cycles to be compensated (the above formulas (1)-(3)), which is easy to implement.

[0066] Please note that, following the above example, in the prior art, for example, taking one-second timing as an example, it is necessary to count 32768 cycles of the 32768Hz RTC clock to obtain an accurate 1s timing time; and through calibration, it is found that the actual RTC clock frequency may have some deviations from the standard 32768Hz. Assuming that the actual RTC clock frequency is found to be (32768-X)Hz, it is necessary to count 32768-X cycles to obtain an accurate 1s timing time; and if X is a decimal, assuming that the integer part is X1 and the decimal part is X2, X=X1+X2; according to the existing method, only the integer part X1 of X can be taken, and then 32768-X1 cycles are counted as above. However, in this case, the decimal part X2 will be ignored, resulting in a certain clock deviation.

[0067] In this regard, the compensation cycle calculation circuit 310 is further configured to: when the calculated number of cycles to be compensated Y of the real-time clock is a decimal, update the number of cycles to be compensated Y to Y*P, where P is a positive integer. Figure 3 This compensation method is described in detail. Figure 3 : is a flow chart of clock accuracy compensation in an embodiment of the present invention, which is particularly aimed at the case where the number of cycles to be compensated Y is a decimal, and includes the following steps:

[0068] Step S310: Calculate the number of cycles Y to be compensated of the real-time clock based on the real-time clock calibration circuit.

[0069] Step S320, within a preset multiple P of time, updating the number of compensation cycles to S=Y*P.

[0070] For example, the unit precision is, for example, the precision per second. Since the RTC counter uses a clock of M (e.g., 32768) Hz for counting, if the precision per second needs to be compensated, it can only be compensated according to an integer cycle of M (e.g., 32768) Hz, and the minimum compensation unit per second is 1 / M (corresponding to 1 / 32768). The embodiment of the present invention is expected to achieve higher clock compensation under the RTC clock under the same conditions, thereby expanding the maximum compensation cycle by P times (such as an integer multiple of 2, 4), and the compensation unit per second becomes 1 / (M*P). Taking the previous M as 32768 and P as 4 as an example, 1 / (M*P)=(1 / 131072). In this way, for example, when Y=1.25, the number of compensation cycles can be changed to S=Y*P=1.25*4=5 within P(4) seconds, that is, the compensation cycle is increased, and S=Y*P=5 makes the maximum compensation cycle become an integer cycle, thereby better improving the compensation precision. It should be noted that even if, for example, Y=1.2 and P=4, the compensation cycle number S=1.2*4=4.8 does not become an integer number of cycles, it can be compensated by rounding off to compensate 5 cycles within 4 seconds; compared with the original number of cycles Y=1.2, the maximum compensation cycle is also expanded by 4 times, and the error of the new compensation method within 4 seconds is 5-4.8=0.2 cycles, and the error per second is 0.05 cycles; compared with the original error per second of 1.2-1=0.2, it is significantly improved. This compensation method makes the compensation unit per second become 1 / (M*P), and the compensation unit per second becomes smaller than 1 / M, and the compensation accuracy is improved.

[0071] Preferably, the preset multiple P (eg, 4) is 2 K (For example, K = 2), where K is a positive integer. Through the RTL (Register Transfer Level) code, it is assumed that the value of S is stored in a 32-bit binary register S[31:0] = 32'b0000_0000_0000_0000_0000_0000_0000_0101. Through the register shift method, it can be known that: within P seconds, the integer part of the compensation cycle per second is S[31:K] = S[31:2] = 30'b00_0000_0000_0000_0000_0000_0000_0001, and the remaining fractional part S[K-1:0] = [1:0] = 2'b01 represents the 1st second to S[K-1:0] = 2'b01 seconds, and one more compensation cycle. That is, from the 1st second to the S[K-1:0]th second, the compensation period per second is S[31:K]+1=2; from S[K-1:0]+1=2 seconds to 2 K =4 seconds, the compensation period per second is S[31:K]=1.

[0072] Therefore, the real-time clock calibration circuit of the embodiment of the present invention can convert the number of compensation cycles of the real-time clock with a decimal frequency error into an integer number of cycles by expanding the maximum compensation cycle, thereby improving the minimum compensation accuracy. In addition, the compensation method implemented in step S310 and step S320 can be implemented by a digital hardware circuit, which is simple in design and can improve the minimum compensation accuracy.

[0073] Figure 4 FIG. 1 is a flow chart of a real-time clock calibration method according to an embodiment of the present invention. Figure 4 As shown, the method includes:

[0074] Step S410: When the system clock, the real-time clock and the reference clock are in clock synchronization, counting the number of cycles of the real-time clock and the reference clock, wherein the reference clock is configured to have a fixed frequency.

[0075] Among them, counting the number of cycles of the real-time clock and the reference clock may preferably include: counting the number of cycles of the real-time clock and the reference clock in a clock synchronization process relative to the system clock; and when the system clock, the real-time clock and the reference clock are in clock synchronization, counting the number of cycles of the real-time clock and the reference clock based on the synchronization clock.

[0076] Step S420: calibrate the real-time clock according to the respective frequencies and the number of cycles of the real-time clock and the reference clock.

[0077] For more implementation details and effects of the real-time clock calibration method of the embodiment of the present invention, reference may be made to the above-mentioned embodiment of the real-time clock calibration circuit, which will not be described in detail here.

[0078] Another embodiment of the present invention further provides a chip structure, including: a system clock, a real-time clock and a reference clock; and the real-time clock calibration circuit described in the above embodiment, for calibrating the real-time clock. The chip structure is, for example, a main control chip, such as a microcontroller.

[0079] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0080] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0081] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0082] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0083] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0084] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0085] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0086] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0087] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A real-time clock calibration circuit, characterized in that: include: A clock module, comprising a system clock, a real-time clock and a reference clock, wherein the reference clock is configured to have a fixed frequency without frequency error, and the system clock is a clock source with an arbitrary clock frequency; A statistics module, used for counting the number of cycles of the real-time clock and the reference clock when the system clock, the real-time clock and the reference clock are in clock synchronization; as well as A calibration module, configured to calibrate the real-time clock according to the respective frequencies and the number of cycles of the real-time clock and the reference clock; Wherein, the statistical module includes: A counting unit, used for counting the number of cycles of the real-time clock and the reference clock respectively in a clock synchronization process relative to the system clock, wherein the counting unit comprises: a first counting circuit that uses the real-time clock as a clock and starts counting the number of cycles of the real-time clock in response to a start signal from the system clock; and a second counting circuit that uses the reference clock as a clock and starts counting the number of cycles of the reference clock in response to a start signal from the system clock; and A synchronization unit, configured to realize clock synchronization between the system clock, the real-time clock and the reference clock independently of each other, so that the counting unit counts the number of cycles of the real-time clock and the reference clock based on the synchronization clock, wherein the synchronization unit comprises: A first clock synchronization unit is arranged between the system clock and the first counting circuit, and is used to achieve clock synchronization between the system clock and the real-time clock; a second clock synchronization unit is arranged between the system clock and the second counting circuit, and is used to achieve clock synchronization between the system clock and the reference clock; and a third clock synchronization unit is arranged between the first counting circuit and the second counting circuit, and is used to achieve clock synchronization between the real-time clock and the reference clock.

2. The real-time clock calibration circuit according to claim 1, characterized in that: The first counting circuit is configured to perform subtraction counting starting from a preset number of cycles, and the second counting circuit is configured to perform addition counting starting from zero; Furthermore, when the first counting circuit counts down to zero, it generates a stop signal, and sends the stop signal to the second counting circuit via the third clock synchronization unit. The second counting circuit stops counting in response to receiving the stop signal.

3. The real-time clock calibration circuit according to claim 1, characterized in that: The system clock generates the start signal using a control register, sends the start signal to the first counting circuit through the first clock synchronization unit, and sends the start signal to the second counting circuit through the second clock synchronization unit.

4. The real-time clock calibration circuit according to claim 1, characterized in that: The calibration module comprises: a compensation cycle calculation circuit, configured to calculate the number of cycles to be compensated of the real-time clock according to an ideal frequency division ratio of the real-time clock and the reference clock and the number of cycles; and The clock compensation circuit is used to calibrate the real-time clock according to the calculated number of cycles to be compensated.

5. The real-time clock calibration circuit according to claim 4, characterized in that: The compensation cycle calculation circuit uses the following formula to calculate the number of cycles Y to be compensated for the real-time clock: Wherein, C2 and C1 are the cycle numbers corresponding to the reference clock and the real-time clock, respectively. is the ideal frequency division ratio between the reference clock and the real-time clock, N is the fixed frequency of the reference clock, and M is the initial frequency of the real-time clock with a frequency error.

6. The real-time clock calibration circuit according to claim 5, characterized in that: When the statistical module performs subtraction counting on the real-time clock to count the corresponding number of cycles, C1 is the preset number of cycles of the real-time clock in one clock synchronization count; Furthermore, the compensation cycle calculation circuit is further configured to improve the accuracy of the calculated number of cycles to be compensated of the real-time clock by increasing C1.

7. The real-time clock calibration circuit according to claim 5, characterized in that: The clock compensation circuit calibrates the real-time clock according to the calculated number of cycles to be compensated, including: Based on the number of cycles to be compensated Y and the initial frequency M of the real-time clock, determining a frequency error X=Y*M of the real-time clock; If the number of cycles to be compensated Y is greater than zero, when the real-time clock is in the timing phase, the number of cycles of the real-time clock is increased so that the real-time clock compensates for the existing frequency error by timing M+X cycles; and If the number of cycles to be compensated Y is less than zero, then when the real-time clock is in the timing phase, the number of cycles of the real-time clock is reduced so that the real-time clock compensates for the existing frequency error by timing MX cycles.

8. The real-time clock calibration circuit according to claim 5, characterized in that: The compensation cycle calculation circuit is further used for: when the calculated number of cycles to be compensated Y of the real-time clock is a decimal, updating the number of cycles to be compensated Y to Y*P, wherein P is a positive integer.

9. A real-time clock calibration method, characterized in that: include: When a system clock, a real-time clock and a reference clock are in clock synchronization, counting the number of cycles of the real-time clock and the reference clock, wherein the reference clock is configured to have a fixed frequency without frequency error, and the system clock is a clock source with an arbitrary clock frequency; as well as Calibrate the real-time clock according to the respective frequencies and the number of cycles of the real-time clock and the reference clock; The counting of the number of cycles of the real-time clock and the reference clock comprises: Counting the number of cycles of the real-time clock and the reference clock in a clock synchronization process relative to the system clock, comprising: setting a first counting circuit, which uses the real-time clock as a clock and starts counting the number of cycles of the real-time clock in response to a start signal from the system clock; and setting a second counting circuit, which uses the reference clock as a clock and starts counting the number of cycles of the reference clock in response to a start signal from the system clock; and In the case of realizing independent clock synchronization between the system clock, the real-time clock and the reference clock, counting the number of cycles of the real-time clock and the reference clock is performed based on the synchronization clock, including: setting a first clock synchronization unit between the system clock and the first counting circuit to realize clock synchronization between the system clock and the real-time clock; setting a second clock synchronization unit between the system clock and the second counting circuit to realize clock synchronization between the system clock and the reference clock; and setting a third clock synchronization unit between the first counting circuit and the second counting circuit to realize clock synchronization between the real-time clock and the reference clock.

10. A chip structure, characterized in that: The chip structure comprises: System clock, real-time clock, and reference clock; and The real-time clock calibration circuit described in any one of claims 1 to 8 is used to calibrate the real-time clock.

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