Integrated circuit, cross-clock domain data transmission method, electronic equipment and storage medium

Abstract

The invention discloses an integrated circuit, a cross-clock domain data transmission method, electronic equipment and a storage medium. The integrated circuit comprises a first clock domain and a second clock domain, the first clock domain comprises a first pointer control module, the second clock domain comprises a second pointer control module, the first pointer control module comprises a first synchronous pointer control module, and the second pointer control module comprises a second synchronous pointer control module. The first synchronous pointer control module is configured to respond to the fact that the frequency of the first clock signal is larger than the frequency of the second clock signal, and determine the phase relation between the first clock signal and the second clock signal according to the second clock phase and the second clock period of the second clock domain, the first clock signal and the first clock phase of the first clock domain, determining a first pointer control signal based on the phase relation; and in response to the fact that the frequency of the first clock signal is smaller than that of the second clock signal, determining that the first pointer control signal is a first value, so that the first read pointer and the first write pointer increase the first value in each clock period of the first clock signal.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an integrated circuit, a data transmission method across clock domains, an electronic device, and a non-transitory computer-readable storage medium. Background Art

[0002] Processors typically use one or more clock signals to synchronize logical operations at modules of the processor, thereby preventing errors such as setup errors, race conditions, etc. Typical processors use different clock signals for different parts of the processor, where each processor part is called a clock domain. By using different clock domains, the processor operates different parts at different frequencies, and also operates different parts relatively independently with respect to the timing of logical operations. For example, the processor can synchronize different clock domains with clock signals of different frequencies, thereby improving processing efficiency. In addition, the processor can provide different clock signals to different clock domains without synchronizing the different clock signals, thereby simplifying clock management and signal routing at the processor. Summary of the invention

[0003] At least one embodiment of the present disclosure provides an integrated circuit, comprising a first clock domain determined based on a first clock signal and a second clock domain determined based on a second clock signal, wherein the first clock signal and the second clock signal are homologous clock signals, the frequency of the first clock signal is greater than the frequency of the second clock signal, or the frequency of the first clock signal is less than the clock frequency of the second clock signal, the first clock domain comprises a first pointer control module, the second clock domain comprises a second pointer control module, the first pointer control module is configured to generate a first pointer control signal for the first clock domain, so that a first read pointer and a first write pointer in the first clock domain are adjusted according to the first pointer control signal, wherein the first pointer control signal is used to indicate an update time point of the first read pointer and the first write pointer; the second pointer control module is configured to generate a second pointer control signal for the second clock domain, so that a second read pointer and a second write pointer in the second clock domain are adjusted according to the second pointer control signal, wherein the second pointer control signal is used to indicate an update time point of the second read pointer and the second write pointer a new time point; the integrated circuit also includes a first first-in-first-out buffer and a second first-in-first-out buffer, the first first-in-first-out buffer is configured to perform data transmission from the first clock domain to the second clock domain based on the first write pointer and the second read pointer, and the second first-in-first-out buffer is configured to perform data transmission from the second clock domain to the first clock domain based on the first read pointer and the second write pointer; the first pointer control module includes a first synchronization pointer control module, and the first synchronization pointer control module is configured to: in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, determine the phase relationship between the first clock signal and the second clock signal according to the second clock phase and the second clock cycle of the second clock domain, the first clock signal, and the first clock phase of the first clock domain, and determine the first pointer control signal based on the phase relationship; in response to the frequency of the first clock signal being less than the frequency of the second clock signal, determine the first pointer control signal to be a first value, so that the first read pointer and the first write pointer increase by the first value in each clock cycle of the first clock signal.

[0004] For example, in the integrated circuit provided by at least one embodiment of the present disclosure, the first synchronization pointer control module and the second synchronization pointer control module included in the second synchronization pointer control module have the same structure, and both include a first sub-module and a second sub-module, the first sub-module of the first synchronization pointer control module is configured to determine the first clock phase according to the first clock cycle of the first clock domain, wherein the first clock phase is used to indicate the phase value of each clock cycle of the first clock signal; the second sub-module of the first synchronization pointer control module is configured to determine the first pointer control signal, wherein, in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, the first pointer control signal being the first value indicates that the rising edge of the second clock signal is located in the current clock cycle of the first clock signal, and the first pointer control signal being the second value indicates that there is no rising edge of the second clock signal in the current clock cycle of the first clock signal.

[0005] For example, in the integrated circuit provided by at least one embodiment of the present disclosure, the second submodule includes a phase synchronization detection unit, a phase estimation unit and a phase tracking unit, the phase synchronization detection unit is configured to determine the target clock phase in the second clock signal based on the second clock phase and the first clock signal, wherein the target clock phase is a phase value of a clock cycle selected in the second clock signal; the phase estimation unit is configured to determine the target clock cycle corresponding to the target clock phase in the first clock signal based on the first clock phase and the second clock cycle, wherein the target clock phase is located in a phase interval corresponding to the target clock cycle, and the phase interval is determined by the phase value of the target clock cycle and the phase value of the next clock cycle of the target clock cycle; the phase tracking unit is configured to continuously estimate the first pointer control signal output in each current clock cycle of the first clock signal based on the target clock phase and the target clock cycle.

[0006] For example, in the integrated circuit provided by at least one embodiment of the present disclosure, the phase synchronization detection unit includes a multi-stage trigger group and an AND gate, the multi-stage trigger group is configured to use the first clock signal as a clock to synchronize a transition edge selected in the second clock signal; the AND gate is configured to perform AND processing on the synchronized transition edge and the second clock phase to obtain the phase value of the clock cycle in which the selected transition edge is located as the target clock phase.

[0007] For example, in the integrated circuit provided by at least one embodiment of the present disclosure, the phase estimation unit is configured to compare the target clock phase with phase intervals corresponding to multiple clock cycles respectively to determine the target clock cycle corresponding to the target clock phase, wherein the multiple clock cycles are multiple clock cycles in the first clock signal before the transition edge after the synchronization.

[0008] For example, in the integrated circuit provided by at least one embodiment of the present disclosure, the phase estimation unit is further configured to estimate a phase change of the second clock signal measured by a clock period of the first clock signal.

[0009] For example, in the integrated circuit provided by at least one embodiment of the present disclosure, when the phase tracking unit performs continuous estimation of the first pointer control signal output in each current clock cycle of the first clock signal based on the target clock phase and the target clock cycle, the following steps are included: determining the clock phase to be estimated based on the target clock phase and the second clock cycle; in the current clock cycle: determining whether the clock phase to be estimated is located in the phase interval corresponding to the current clock cycle based on the clock phase to be estimated; in response to the clock phase to be estimated being located in the phase interval corresponding to the current clock cycle, determining that the first pointer control signal output in the current clock cycle is the first value, and updating the clock phase to be estimated based on the second clock cycle; in response to the clock phase to be estimated not being located in the phase interval corresponding to the current clock cycle, determining that the first pointer control signal output in the current clock cycle is the second value.

[0010] For example, in the integrated circuit provided by at least one embodiment of the present disclosure, the first read pointer and the first write pointer are adjusted according to the first pointer control signal in each clock cycle of the first clock signal, and the second read pointer and the second write pointer are adjusted according to the second pointer control signal in each clock cycle of the second clock signal; in response to a data write operation being generated in a write clock cycle in the first clock domain, a data read operation is performed in a read clock cycle corresponding to the write clock cycle in the second clock signal, wherein, in response to the clock frequency of the first clock signal being greater than the clock frequency of the second clock signal, a rising edge of the second clock signal that differs from a rising edge of the read clock cycle by a+1 second clock cycles is located in a clock cycle before the write clock cycle in the first clock signal, and in response to the clock frequency of the first clock signal being less than the clock frequency of the second clock signal, a rising edge that differs from a rising edge of the write clock cycle by a first clock cycle is located in a clock cycle before the read clock cycle in the second clock signal, and a is a positive integer.

[0011] For example, in the integrated circuit provided by at least one embodiment of the present disclosure, the first pointer control module also includes a first state machine and a first asynchronous pointer control module, the second pointer control module also includes a second state machine and a second asynchronous pointer control module, the first asynchronous pointer control module and the second asynchronous pointer control module each include a multi-stage trigger, and the first asynchronous pointer control module and the second asynchronous pointer control module synchronize the first write pointer, the first read pointer, the second write pointer, and the second read pointer in different clock domains through the multi-stage triggers respectively included; the first state machine is configured to control the first clock domain to use the first asynchronous pointer control module to perform cross-clock domain data transmission when frequency switching occurs, and after the frequency switching is completed and the phase estimation is completed, control the first clock domain to use the first synchronous pointer control module to perform cross-clock domain data transmission; the second state machine is configured to control the second clock domain to use the second asynchronous pointer control module to perform cross-clock domain data transmission when frequency switching occurs, and after the frequency switching is completed and the phase estimation is completed, control the second clock domain to use the second synchronous pointer control module to perform cross-clock domain data transmission.

[0012] For example, in the integrated circuit provided by at least one embodiment of the present disclosure, the first state machine and the second state machine are also configured to receive first indication information indicating whether the frequency switching is completed, and second indication information indicating the frequency magnitude relationship between the first clock signal and the second clock signal. In response to the first indication information indicating that the frequency switching has occurred, the first state machine controls the first clock domain to use the first asynchronous pointer control module to perform cross-clock domain data transmission, and the second state machine controls the second clock domain to use the second asynchronous pointer control module to perform cross-clock domain data transmission; the first state machine and the second state machine are also configured to determine whether the frequency switching is completed and the phase estimation is completed based on the first indication information and the second indication information.

[0013] For example, in the integrated circuit provided by at least one embodiment of the present disclosure, when the first state machine determines whether the frequency switching is completed and the phase estimation is completed according to the first indication information and the second indication information, the following operations are performed: in response to the first indication information indicating that the frequency switching is completed, and the second indication information indicating that the clock frequency of the first clock signal is greater than the clock frequency of the second clock signal: the first state machine controls the first synchronization pointer control module to perform phase estimation to obtain the phase relationship and determines the first pointer control signal based on the phase relationship; in response to the first synchronization pointer control module completing the phase estimation, it is determined that the frequency switching is completed and the phase estimation is completed, and the first state machine is also configured to perform a synchronous handshake with the second state machine so that the second state machine controls the second clock domain to use the second synchronization pointer control module to perform data transmission across clock domains; in response to the first indication information indicating that the frequency switching is completed, and the second indication information indicating that the clock frequency of the first clock signal is less than the clock frequency of the second clock signal: after completing the synchronous handshake with the second state machine, it is determined that the frequency switching is completed and the phase estimation is completed.

[0014] At least one embodiment of the present disclosure provides a method for data transmission across clock domains, which is applied to a first clock domain determined based on a first clock signal and a second clock domain determined based on a second clock signal, wherein the first clock domain includes a first first-in-first-out buffer, and the second clock domain includes a second first-in-first-out buffer, the first clock signal and the second clock signal are homologous clock signals, and the frequency of the first clock signal is greater than the frequency of the second clock signal, or the frequency of the first clock signal is less than the clock frequency of the second clock signal, and the data transmission method includes: in the first clock domain, determining a first pointer control signal, and adjusting a first read pointer and a first write pointer of the first clock domain according to the first pointer control signal, wherein the first pointer control signal is used to indicate an update time point of the first read pointer and the first write pointer; in the second clock domain, determining a second pointer control signal, and adjusting a second read pointer and a second write pointer of the second clock domain according to the second pointer control signal, wherein the second pointer control signal is used to indicate The update time point of the second read pointer and the second write pointer; based on the first write pointer and the second read pointer, using the first first-in-first-out buffer to transfer data from the first clock domain to the second clock domain, and based on the first read pointer and the second write pointer, using the second first-in-first-out buffer to transfer data from the second clock domain to the first clock domain; wherein, determining the first pointer control signal includes: in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, according to the second clock phase and second clock cycle of the second clock domain, the first clock signal, and the first clock phase of the first clock domain, determining the phase relationship between the first clock signal and the second clock signal, and determining the first pointer control signal based on the phase relationship; in response to the frequency of the first clock signal being less than the frequency of the second clock signal, determining the first pointer control signal to be a first value, so that the first read pointer and the first write pointer increase by the first value in each clock cycle of the first clock signal.

[0015] For example, in the data transmission method provided by at least one embodiment of the present disclosure, determining the first pointer control signal also includes: determining the first clock phase according to the first clock cycle of the first clock domain, wherein the first clock phase is used to indicate the phase value of each clock cycle of the first clock signal; wherein, in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, the first pointer control signal is a first value indicating that a rising edge of the second clock signal is located in the current clock cycle of the first clock signal, and the first pointer control signal is a second value indicating that no rising edge of the second clock signal is located in the current clock cycle.

[0016] For example, in the data transmission method provided by at least one embodiment of the present disclosure, the phase relationship between the first clock signal and the second clock signal is determined according to the second clock phase and the second clock cycle of the second clock domain, the first clock signal, and the first clock phase, and the first pointer control signal is determined based on the phase relationship, including: determining the target clock phase in the second clock signal based on the second clock phase and the first clock signal, wherein the target clock phase is a phase value of a clock cycle selected in the second clock signal; determining the target clock cycle corresponding to the target clock phase in the first clock signal based on the first clock phase and the second clock cycle, wherein the target clock phase is located in the phase interval corresponding to the target clock cycle, and the phase interval is determined by the phase value of the target clock cycle and the phase value of the next clock cycle of the target clock cycle; based on the target clock phase and the target clock cycle, continuously estimating the first pointer control signal output in each current clock cycle of the first clock signal.

[0017] For example, the data transmission method provided in at least one embodiment of the present disclosure also includes: when frequency switching occurs, controlling the first clock domain and the second clock domain to use asynchronous pointer control logic to perform cross-clock domain data transmission; after the frequency switching is completed and the phase estimation is completed, controlling the first clock domain and the second clock domain to use synchronous pointer control logic to perform cross-clock domain data transmission, wherein the asynchronous pointer control logic includes synchronizing the first write pointer, the first read pointer, the second write pointer, and the second read pointer in different clock domains through a multi-stage trigger, and the synchronous pointer control logic includes obtaining the phase relationship and performing cross-clock domain data transmission based on the phase relationship.

[0018] At least one embodiment of the present disclosure provides an electronic device, comprising: a memory, which non-transiently stores computer-executable instructions; and a processor, which is configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the processor, implement the method for data transmission across clock domains according to any embodiment of the present disclosure.

[0019] At least one embodiment of the present disclosure provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the method for transmitting data across clock domains according to any embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0021] Figure 1 is a schematic structural diagram of a multi-core chip system;

[0022] Figure 2 A schematic block diagram of an integrated circuit provided for at least one embodiment of the present disclosure;

[0023] Figure 3 A schematic diagram of clock phases provided in an embodiment of the present disclosure;

[0024] Figure 4 A schematic diagram of the phase relationship between a first clock domain and a second clock domain provided in an embodiment of the present disclosure;

[0025] Figure 5 A schematic diagram of a first synchronization pointer control module provided by an embodiment of the present disclosure;

[0026] Figure 6 A schematic structural diagram of a second submodule provided for at least one embodiment of the present disclosure;

[0027] Fig. 7A A schematic structural diagram of a phase synchronization detection unit provided in an embodiment of the present disclosure;

[0028] Figure 7B An embodiment of the present disclosure provides Fig. 7A A timing diagram of a phase synchronization detection unit shown;

[0029] Fig. 8A A timing diagram of a data transmission process across clock domains is provided for an embodiment of the present disclosure;

[0030] Figure 8B A timing diagram of a data transmission process across clock domains is provided for another embodiment of the present disclosure;

[0031] Fig. 9 A schematic diagram of state switching of a state machine provided in an embodiment of the present disclosure;

[0032] Fig.10 A schematic block diagram of a first pointer control module provided in an embodiment of the present disclosure;

[0033] Fig.11 A schematic flow chart of a method for data transmission across clock domains provided for at least one embodiment of the present disclosure;

[0034] Fig.12 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure;

[0035] Fig.13 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0037] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0038] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components.

[0039] Figure 1 Figure 1 is a schematic diagram of the structure of a multi-core chip system. Figure 1 As shown in the figure, the system is a typical 4-core system on chip, including 4 processing cores (Core), three-level caches (L1 cache, L2 cache and L3 cache) corresponding to the 4 processing cores, on-chip interconnect network, dynamic random access memory and other intellectual property cores (Intellectual PropertyCore). I-L1$ is the private instruction L1 cache of each processing core, D-L1$ is the private data L1 cache of each processing core, every two processing cores share an L2 cache, and four processing cores share an L3 cache. L3 cache and other intellectual property cores (for example, direct memory access / video / display, etc.) access dynamic random access memory through the on-chip interconnect network.

[0040] like Figure 1 As shown in the figure, in the design of high-performance processor chips, multiple processing cores may usually share the L3 cache. In order to save power and improve processor performance, DVFS (Dynamic Voltage and Frequency Scaling) technology is often used. The processing core has different operating voltages and frequencies under different load scenarios, so the processing core will switch frequencies continuously. Since the frequency of the processing core will change, the clock frequencies of the processing core and the L3 cache can be different, so the interface signal between the processing core and the L3 cache is an asynchronous clock signal.

[0041] When data is transmitted across clock domains, metastability errors may occur. Therefore, signals across clock domains must be processed by cross-clock domain circuits. This technology is called synchronous processing technology for asynchronous clock signals.

[0042] These errors can be mitigated by including metastable circuits (e.g., groups of flip-flops) between clock domains to implement data transfers. However, such metastable circuits can increase latency and require additional circuitry (such as additional entries in a buffer) to account for control signal delays.

[0043] These errors can also be reduced by using an asynchronous first-in-first-out buffer (FIFO) to transfer data across clock domains, but the delay of using an asynchronous FIFO is also large, which will affect the performance of the processor. Specifically, the asynchronous FIFO circuit determines whether the FIFO is empty or full by comparing the write pointer of one clock domain with the read pointer of another clock domain. Therefore, the asynchronous FIFO needs to synchronize the read pointer (pointing to the next location in the FIFO where data is to be read) or the write pointer (pointing to the next location in the FIFO where data is to be written) from one clock domain to another. Traditional synchronization circuits are implemented using more than two levels of triggers (DFFs). The delay generated by the synchronization circuit will be greater than two clock cycles of the destination clock domain, which is also the overall data transmission delay of the traditional asynchronous FIFO circuit. For example, when data is transmitted from a fast clock to a slow clock, because the synchronization delay of the pointer from the fast clock domain to the slow clock domain requires more than two clock cycles of the slow clock domain, the data transmission delay is large.

[0044] In addition, as mentioned earlier, multiple processing cores in high-performance processors often share the L3 cache. The processing core is a single-clock domain digital logic, and the frequency can often be increased to a very high level with the improvement of the process and the optimization of the circuit timing. The cache in the L3 cache is a customized analog circuit with a large area. The physical routing of the L3 cache is longer, and the frequency increase convergence of the L3 cache will be more difficult than that of the processing core. Therefore, it is very likely that the operating frequency of the processing core will be higher than the frequency of the L3 cache in some high-performance scenarios. Due to the use of DVFS technology, the frequency of the processing core will be higher than the L3 frequency, and the frequency of the processing core will be lower than the frequency of the L3 cache. Current cross-clock domain signal processing usually only supports one frequency relationship, such as only supporting the scenario where the frequency of the processing core is lower than the frequency of the L3 cache, but does not support arbitrary switching of the frequencies of the two clock domains.

[0045] At least one embodiment of the present disclosure provides an integrated circuit, a method for data transmission across clock domains, an electronic device, and a non-transitory computer-readable storage medium.

[0046] In at least one embodiment, the integrated circuit includes a first clock domain determined based on a first clock signal and a second clock domain determined based on a second clock signal, the first clock signal and the second clock signal are homologous clock signals, the frequency of the first clock signal is greater than the frequency of the second clock signal, or the frequency of the first clock signal is less than the clock frequency of the second clock signal, the first clock domain includes a first pointer control module, the second clock domain includes a second pointer control module, the first pointer control module is configured to generate a first pointer control signal for the first clock domain, so that the first read pointer and the first write pointer in the first clock domain are adjusted according to the first pointer control signal, wherein the first pointer control signal is used to indicate the update time point of the first read pointer and the first write pointer; the second pointer control module is configured to generate a second pointer control signal for the second clock domain, so that the second read pointer and the second write pointer in the second clock domain are adjusted according to the second pointer control signal, wherein the second pointer control signal is used to indicate the update time point of the second read pointer and the first write pointer. The integrated circuit also includes a first first-in-first-out buffer and a second first-in-first-out buffer, the first first-in-first-out buffer is configured to perform data transmission from the first clock domain to the second clock domain based on the first write pointer and the second read pointer, and the second first-in-first-out buffer is configured to perform data transmission from the second clock domain to the first clock domain based on the first read pointer and the second write pointer; the first pointer control module includes a first synchronization pointer control module, and the first synchronization pointer control module is configured to: in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, determine the phase relationship between the first clock signal and the second clock signal according to the second clock phase and the second clock cycle of the second clock domain, the first clock signal, and the first clock phase of the first clock domain, and determine the first pointer control signal based on the phase relationship; in response to the frequency of the first clock signal being less than the frequency of the second clock signal, determine the first pointer control signal to be a first value, so that the first read pointer and the first write pointer increase by the first value in each clock cycle of the first clock signal.

[0047] At least one embodiment of the present disclosure also provides a method for data transmission across clock domains, which is applied to a first clock domain determined based on a first clock signal and a second clock domain determined based on a second clock signal, wherein the first clock domain includes a first first-in-first-out buffer, and the second clock domain includes a second first-in-first-out buffer, the first clock signal and the second clock signal are homologous clock signals, and the frequency of the first clock signal is greater than the frequency of the second clock signal, or the frequency of the first clock signal is less than the clock frequency of the second clock signal, and the data transmission method includes: in the first clock domain, determining a first pointer control signal, and adjusting a first read pointer and a first write pointer of the first clock domain according to the first pointer control signal, wherein the first pointer control signal is used to indicate an update time point of the first read pointer and the first write pointer; in the second clock domain, determining a second pointer control signal, and adjusting a second read pointer and a second write pointer of the second clock domain according to the second pointer control signal, wherein the second The pointer control signal is used to indicate the update time point of the second read pointer and the second write pointer; based on the first write pointer and the second read pointer, the first first-in-first-out buffer is used to transfer data from the first clock domain to the second clock domain, and based on the first read pointer and the second write pointer, the second first-in-first-out buffer is used to transfer data from the second clock domain to the first clock domain; wherein, determining the first pointer control signal includes: in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, according to the second clock phase and the second clock cycle of the second clock domain, the first clock signal, and the first clock phase of the first clock domain, determining the phase relationship between the first clock signal and the second clock signal, and determining the first pointer control signal based on the phase relationship; in response to the frequency of the first clock signal being less than the frequency of the second clock signal, determining the first pointer control signal to be a first value, so that the first read pointer and the first write pointer increase by the first value in each clock cycle of the first clock signal.

[0048] The integrated circuit and the cross-clock domain data transmission method provided by at least one embodiment of the present disclosure can support any switching of the clock frequencies of two asynchronous clock domains, such as switching from a scenario where the frequency of the first clock domain (e.g., the clock domain of the processing core, etc.) is higher than the frequency of the second clock domain (e.g., the clock domain of the L3 cache, etc.) to a scenario where the frequency of the first clock domain is lower than the frequency of the second clock domain, and vice versa, it also supports switching from a scenario where the frequency of the first clock domain is lower than the frequency of the second clock domain to a scenario where the frequency of the first clock domain is higher than the frequency of the second clock domain. Therefore, the integrated circuit provided by at least one embodiment of the present disclosure supports the DVFS technology, has no restrictions on the relationship between the clock frequencies of the two asynchronous clock domains, is more flexible, and has wider applicability.

[0049] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0050] Figure 2A schematic block diagram of an integrated circuit provided for at least one embodiment of the present disclosure.

[0051] For example, the integrated circuit 100 may be in the form, structure or function of a chip, a processor, etc. The integrated circuit may be any circuit structure that requires cross-clock domain data transmission, and the present disclosure does not impose any specific limitation on this.

[0052] like Figure 2 As shown, the integrated circuit 100 includes a first clock domain 101 determined based on a first clock signal and a second clock domain 102 determined based on a second clock signal. The first clock signal and the second clock signal are co-source clock signals, that is, they are obtained by dividing the same clock source, and the two clock signals have different frequency division coefficients. Therefore, the phase relationship between the first clock signal and the second clock signal can be completely determined by the frequency division coefficients of the two clock domains, and thus, when the clock phases of the first clock domain and the second clock domain are known, it can be known at what time the read pointer and the write pointer of the fast clock signal increase.

[0053] It should be noted that the integrated circuit 100 may also include a third clock domain, a fourth clock domain, etc., that is, the integrated circuit may include more clock domains. When data is transmitted across clock domains, two clock domains controlled by asynchronous clocks are selected from multiple clock domains as the first clock domain and the second clock domain.

[0054] In the present disclosure, the clock phase is used to indicate the phase value of the clock signal in each clock cycle. For example, the phase value may be a specific value that increases according to the frequency division coefficient, and returns to 0 and continues to increase after reaching the upper limit.

[0055] Figure 3 A schematic diagram of clock phases provided in accordance with an embodiment of the present disclosure.

[0056] like Figure 3 As shown, the first clock signal is Figure 3 The frequency switching occurs at the frequency switching moment in the frequency switching, the frequency division factor increases from 8 to 12, and the frequency decreases. Figure 3 As shown, before the frequency switching, the first clock cycle is represented by a frequency division factor of 8, and after the frequency switching, the first clock cycle is represented by a frequency division factor of 12. The number corresponding to each clock cycle in the first clock phase represents the phase value of each clock cycle. The first clock phase starts from 0, and the frequency division factor increases by 8 in each clock cycle. After the frequency switching occurs, the frequency division factor increases by 12 in each clock cycle.

[0057] Of course, the above method is an example of expressing the clock phase, and the present disclosure is not limited thereto, and other similar methods may also be used to express the phase value of the clock signal in each clock cycle. For example, since the clock phases need to be compared in the present disclosure, the first clock phase and the second clock phase may be set to have the same value range, for example, both are expressed with an 8-bit width.

[0058] For example, in at least one embodiment of the present disclosure, the frequency of the first clock signal may be greater than the frequency of the second clock signal, or the frequency of the first clock signal may be less than the frequency of the second clock signal. That is, the present disclosure does not limit the frequency relationship between the two clock domains.

[0059] like Figure 2 As shown, the first clock domain includes a first pointer control module 103 , and the second clock domain includes a second pointer control module 104 .

[0060] The first pointer control module 103 is configured to generate a first pointer control signal for the first clock domain 101 , so that the first read pointer and the first write pointer in the first clock domain 101 are adjusted according to the first pointer control signal.

[0061] For example, the first write pointer adjustment module and the first read pointer adjustment module are used to adjust the first read pointer and the first write pointer according to the first pointer control signal. For example, the first read pointer and the first write pointer can accumulate the first pointer control signal currently output in each clock cycle. Of course, other feasible methods can also be used to adjust the first read pointer and the first write pointer according to the first pointer control signal to reflect the change of the first pointer control signal, and the present disclosure does not make specific restrictions.

[0062] The second pointer control module 104 is configured to generate a second pointer control signal for the second clock domain 102 , so that the second read pointer and the second write pointer in the second clock domain 102 are adjusted according to the second pointer control signal.

[0063] For example, the second write pointer adjustment module and the second read pointer adjustment module are used to adjust the second read pointer and the second write pointer according to the second pointer control signal. For example, the second read pointer and the second write pointer can accumulate the second pointer control signal in each clock cycle. Of course, other feasible ways can also be used to adjust the second read pointer and the second write pointer according to the second pointer control signal to reflect the change of the second pointer control signal, and the present disclosure does not make specific limitations.

[0064] like Figure 2 As shown, the integrated circuit 100 further includes a first first-in-first-out buffer (FIFO) 105 and a second first-in-first-out buffer (FIFO) 106 .

[0065] The first FIFO buffer 105 is configured to perform data transmission from the first clock domain to the second clock domain based on the first write pointer and the second read pointer.

[0066] like Figure 2 As shown, the first FIFO buffer 105 includes a first buffer and a second read selector. The first buffer area is configured to cache data to be sent to the second clock domain, and the write position of the data is indicated by the first write pointer. The second read selector is configured to select and output the data in the read address indicated by the second read pointer from the data transmitted from the first buffer area of ​​the first clock domain to the second clock domain based on the second read pointer. Thus, the data transmission from the first clock domain to the second clock domain is completed through the first write pointer and the second read pointer.

[0067] The second FIFO buffer 106 is configured to perform data transmission from the second clock domain to the first clock domain based on the first read pointer and the second write pointer.

[0068] like Figure 2 As shown, the second FIFO buffer 106 includes a second buffer and a first read selector. The second buffer area is configured to cache data that needs to be sent to the first clock domain, and the write position of the data is indicated by the second write pointer. The first read selector is configured to select and output the data in the read address indicated by the first read pointer from the data transmitted from the second buffer area of ​​the second clock domain to the first clock domain based on the first read pointer. Thus, the data transmission from the second clock domain to the first clock domain is completed through the second write pointer and the first read pointer.

[0069] For example, a plurality of cache entries of the first buffer are connected to a plurality of channels of the second read selector correspondingly, and a plurality of cache entries of the second buffer are connected to a plurality of channels of the first read selector correspondingly.

[0070] Of course, the integrated circuit may include more other modules, and the present disclosure does not impose any specific limitation on this.

[0071] For example, the first pointer control module includes a first synchronization pointer control module, and the first synchronization pointer control module is configured to: in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, determine the phase relationship between the first clock signal and the second clock signal according to the second clock phase and the second clock cycle of the second clock domain, the first clock signal, and the first clock phase of the first clock domain, and determine the first pointer control signal based on the phase relationship; in response to the frequency of the first clock signal being less than the frequency of the second clock signal, determine the first pointer control signal to be a first value so that the first read pointer and the first write pointer increase by the first value in each clock cycle of the first clock signal.

[0072] For example, the first pointer control signal is used to determine the update time point of the first read pointer and the first write pointer. For example, if the frequency of the first clock signal is greater than the frequency of the second clock signal, the first pointer control signal is used to indicate whether the rising edge of the second clock signal is located in the current clock cycle of the first clock signal.

[0073] The first pointer control module and the second pointer control module have similar functions and structures, the difference being that one is used to generate a first pointer control signal, and the other uses similar logic to generate a second pointer control signal.

[0074] For example, the second pointer control module includes a second synchronization pointer control module configured as: in response to the frequency of the second clock signal being greater than the frequency of the first clock signal, determining the phase relationship between the first clock signal and the second clock signal according to the first clock phase and the first clock cycle of the first clock domain, the second clock signal, and the second clock phase of the second clock domain, and determining the second pointer control signal based on the phase relationship; in response to the frequency of the second clock signal being less than the frequency of the first clock signal, determining the second pointer control signal to be a first value so that the second read pointer and the second write pointer increase by the first value in each clock cycle of the second clock signal.

[0075] For example, the second pointer control signal is used to determine the update time point of the second read pointer and the second write pointer. For example, if the frequency of the second clock signal is greater than the frequency of the first clock signal, the second pointer control signal is used to indicate whether the rising edge of the first clock signal is located in the current clock cycle of the second clock signal.

[0076] The first synchronous pointer control module and the second synchronous pointer control module determine corresponding pointer control values ​​based on the phase relationship between the first clock signal and the second clock signal.

[0077] Figure 4 A schematic diagram of the phase relationship between a first clock domain and a second clock domain provided in an embodiment of the present disclosure.

[0078] like Figure 4 As shown, assuming that the first clock signal is divided by 3 and the second clock signal is divided by 5. Then the phase of the first clock signal in each clock cycle (first clock phase) can be expressed as 0-3-6-9-12..., and the phase of the second clock signal in each clock cycle (second clock phase) can be expressed as 0-5-10-15... Based on the phase relationship, it can be determined that, for example, the second rising edge of the second clock signal is located at the second clock cycle ( Figure 4 The third rising edge of the second clock signal is located in the fourth clock cycle of the first clock signal (cycle1). Figure 4For example, the second read pointer and the second write pointer of the second clock domain can be set to increase in each clock cycle, and the first read pointer and the first write pointer of the first clock domain can be set to increase only in cycle 1, cycle 2, cycle 4, etc. (after the rising edge of the slow clock is judged to appear). In this way, the cross-clock domain signal synchronization of the two clock domains is achieved to avoid data loss on the asynchronous interface.

[0079] In at least one embodiment of the present disclosure, the first synchronous pointer control module can determine the phase relationship between the first clock signal and the second clock signal according to the second clock phase, the second clock cycle, the first clock signal, and the first clock phase when the frequency of the first clock signal is greater than the frequency of the second clock signal, and determine the first pointer control signal based on the phase relationship to estimate the clock phase of the slower clock domain in the faster clock domain; when the frequency of the first clock signal is less than the frequency of the second clock signal, the first value is accumulated in each clock cycle of the first clock signal, thereby increasing the first read pointer and the first write pointer at each rising edge of the first clock signal. Thus, even if the frequency changes, the updated phase relationship can be obtained through the first pointer control module, thereby controlling the read pointer and the write pointer, and there is no restriction on the frequency size relationship of the two asynchronous clock domains, so that the integrated circuit supports DVFS technology, does not limit frequency changes, has greater flexibility, and is more widely applicable.

[0080] Similarly, the second synchronization pointer control module can also use similar logic to obtain the phase relationship, and determine the second read pointer and the second write pointer according to the updated phase relationship when the frequency switching occurs. In addition, the acquisition of the phase relationship occurs in the faster frequency clock domain, and the slower frequency clock domain only needs to accumulate the first value in each clock cycle.

[0081] For example, the first synchronous pointer control module and the second synchronous pointer control module have the same structure, and both include a first submodule and a second submodule.

[0082] Figure 5 A schematic diagram of a first synchronization pointer control module provided in accordance with an embodiment of the present disclosure.

[0083] The first submodule 1031 of the first synchronization pointer control module is configured to determine a first clock phase according to a first clock period of the first clock domain, wherein the first clock phase is used to indicate a phase value of each clock cycle of the first clock signal.

[0084] For a description of the first clock phase, please refer to Figure 3 The relevant content will not be repeated here.

[0085] The second submodule 1032 of the first synchronous pointer control module is configured as follows: in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, determining the phase relationship between the first clock signal and the second clock signal according to the second clock phase and the second clock cycle of the second clock domain, the first clock signal, and the first clock phase of the first clock domain, and determining the first pointer control signal based on the phase relationship; in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, the first pointer control signal being a first value indicates that a rising edge of the second clock signal is located in the current clock cycle of the first clock signal, and the first pointer control signal being a second value indicates that no rising edge of the second clock signal is located in the current clock cycle; in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, determining the first pointer control signal to be the first value.

[0086] For example, in the present disclosure, the clock phase of the slower clock domain is estimated in the faster clock domain. Therefore, when the frequency of the first clock signal is greater than the frequency of the second clock signal, the second submodule estimates the phase of the slower second clock signal to determine the phase relationship between the first clock signal and the second clock signal, and determines the first pointer control signal based on the phase relationship.

[0087] For example, the first pointer control signal at this time may output the first value or the second value in each clock cycle of the first clock signal. If the first value is output, it indicates that the rising edge of the second clock signal is in the current clock cycle, for example Figure 4 In cycle1, if the second value is output, it means that there is no rising edge of the second clock signal in the current clock cycle, for example Figure 4 For example, the first value may be 1 and the second value may be 0.

[0088] For example, if the frequency of the first clock signal is greater than the frequency of the second clock signal, the first value can be output in each clock cycle of the first clock signal. For example, at the rising edge of each slow clock signal, the first read pointer and the first write pointer both accumulate the first value, for example, 1.

[0089] The second synchronization pointer control module also includes a first submodule and a second submodule.

[0090] For example, the first submodule of the second synchronization pointer control module is configured to determine a second clock phase according to a second clock cycle of the second clock domain, wherein the second clock phase is used to indicate a phase value of each clock cycle of the second clock signal.

[0091] For a description of the second clock phase, please refer to Figure 3 The relevant content will not be repeated here.

[0092] The second submodule of the second synchronization pointer control module is configured as follows: in response to the frequency of the second clock signal being greater than the frequency of the first clock signal, determining the phase relationship between the first clock signal and the second clock signal according to the first clock phase and the first clock cycle of the first clock domain, the second clock signal, and the second clock phase of the second clock domain, and determining the second pointer control signal based on the phase relationship; in response to the frequency of the second clock signal being greater than the frequency of the first clock signal, the second pointer control signal being a first value indicates that a rising edge of the first clock signal is located in a current clock cycle of the second clock signal, and the second pointer control signal being a second value indicates that no rising edge of the first clock signal is located in the current clock cycle; in response to the frequency of the second clock signal being greater than the frequency of the first clock signal, determining the second pointer control signal to be the first value.

[0093] Figure 6 A schematic structural diagram of a second submodule provided for at least one embodiment of the present disclosure.

[0094] The structure and function of the second submodule are described below by taking the first synchronous pointer control module as an example. The same is true for the second submodule of the second synchronous pointer control module, which will not be described again here.

[0095] like Figure 6 As shown, the second submodule 1032 includes a phase synchronization detection unit, a phase estimation unit, and a phase tracking unit.

[0096] The phase synchronization detection unit is configured to determine a target clock phase in the second clock signal based on the second clock phase and the first clock signal. For example, the target clock phase is a phase value of a clock cycle selected in the second clock signal.

[0097] Fig. 7A A schematic structural diagram of a phase synchronization detection unit provided in one embodiment of the present disclosure.

[0098] like Fig. 7A As shown, the phase synchronization detection unit includes a multi-stage trigger group and an AND gate. The multi-stage trigger group is configured to use the first clock signal as a clock to synchronize a jump edge selected in the second clock signal to transfer the phase jump signal (the selected jump edge) from the slow clock domain to the fast clock domain to avoid metastable state in the synchronization process. The AND gate is configured to perform AND processing on the synchronized jump edge and the second clock phase to obtain the phase value of the clock cycle where the selected jump edge is located as the target clock phase, and the target clock phase is a phase value in the second clock phase.

[0099] Figure 7B An embodiment of the present disclosure provides Fig. 7A The timing diagram of the phase synchronization detection unit is shown.

[0100] like Figure 7BAs shown, the phase value of the clock cycle where the selected jump edge is located is phase A. After the jump edge passes through the multi-stage trigger group, the synchronized jump edge is output. The AND gate performs AND processing on the synchronized jump edge and the second clock phase to obtain the target clock phase, that is, phase A.

[0101] It should be noted that in the phase synchronization detection unit, starting from the selected transition edge, the second clock phase in the subsequent clock cycles is phase A, so that the target clock phase can be obtained. Afterwards, when the next transition edge is selected to perform the above process, the second clock phase is updated to the phase value of the transition edge.

[0102] For example, the phase estimation unit is configured to determine a target clock cycle corresponding to the target clock phase in the first clock signal based on the first clock phase and the second clock cycle, wherein the target clock phase is located in a phase interval corresponding to the target clock cycle, and the phase interval is determined by the phase value of the target clock cycle and the phase value of the next clock cycle of the target clock cycle.

[0103] For example, the phase estimation unit is configured to compare the target clock phase with phase intervals corresponding to multiple clock cycles to determine the target clock cycle corresponding to the target clock phase, wherein the multiple clock cycles are multiple clock cycles before the jump edge after synchronization in the first clock signal.

[0104] For example, Figure 7B For example, multiple clock cycles include 4 clock cycles before the transition edge after synchronization, including Figure 7B The number of clock cycles selected may be related to the number of stages of the flip-flop in the multi-stage flip-flop group.

[0105] For example, first determine whether the target clock phase is in the phase interval corresponding to period 0. For example, the phase interval corresponding to period 0 is [phase1, phase1+period1]. Here, Phase1 represents the phase value corresponding to period 0, and period1 is the clock period of the first clock signal, for example, represented by a frequency division coefficient.

[0106] If phase A falls into the phase interval corresponding to cycle 0, the target clock cycle corresponding to the target clock phase is determined to be cycle 0. If phase A does not fall into the phase interval corresponding to cycle 0, it is further determined whether phase A falls into the phase interval corresponding to cycle 1. If phase A falls into the phase interval corresponding to cycle 1, the target clock cycle corresponding to the target clock phase is determined to be cycle 1. If phase A does not fall into the phase interval corresponding to cycle 1, it is further determined whether phase A falls into the phase interval corresponding to cycle 2, and so on. Thus, the target clock cycle corresponding to the target clock phase in the first clock signal can be determined. At the same time, the rising edge corresponding to the jump edge in the first clock signal, that is, the rising edge of the target clock cycle, can also be determined.

[0107] Therefore, in the present disclosure, the corresponding relationship between the rising edges of the first clock signal and the second clock signal is indirectly obtained through phase comparison, thereby obtaining the phase relationship, and obtaining the pointer control signal through the phase relationship to adjust the read pointer and the write pointer.

[0108] For example, the phase estimation unit is further configured to estimate the phase change of the second clock signal measured by the clock cycle of the first clock signal. For example, the phase estimation unit can also estimate the target phases corresponding to multiple clock cycles in the first clock signal after the target clock cycle, wherein each target phase is a phase value in the second clock signal.

[0109] For example, Figure 7B For example, assuming that the target clock cycle corresponding to phase A is determined to be cycle 0, then continue to add phase A to the second clock cycle to obtain the phase B of the object to be determined, and compare phase B with the phase interval corresponding to cycle 1. If phase B is in the phase interval corresponding to cycle 1, then the target phase corresponding to cycle 1 is determined to be phase B. If phase B is not in the phase interval corresponding to cycle 1, then the target phase corresponding to cycle 1 is determined to be phase A, and so on. In this way, the phase change of the second clock signal measured by the clock cycle of the first clock signal can be obtained. For example, it can be estimated that phase A lasts for several first clock cycles, phase B lasts for several first clock cycles, etc.

[0110] The phase tracking unit is configured to continuously estimate the first pointer control signal output in each current clock cycle of the first clock signal based on the target clock phase and the target clock cycle. For example, the phase tracking unit can continuously determine the first pointer control signal output in each clock cycle after the synchronization jump edge.

[0111] After obtaining the target clock phase and its corresponding target clock cycle, it is possible to continuously estimate whether the rising edge of the second clock signal falls into the current clock cycle of the first clock signal based on the corresponding relationship. This method can derive the first pointer control signal in real time with minimal computing resources without repeatedly using the above method to determine the pointer control signal.

[0112] For example, when the phase tracking unit performs continuous estimation of the first pointer control signal output in each current clock cycle of the first clock signal based on the target clock phase and the target clock cycle, the following steps are included: determining the clock phase to be estimated based on the target clock phase and the second clock cycle; in the current clock cycle: determining whether the clock phase to be estimated is located in the phase interval corresponding to the current clock cycle based on the clock phase to be estimated; in response to the clock phase to be estimated being located in the phase interval corresponding to the current clock cycle, determining that the first pointer control signal is a first value, and updating the clock phase to be estimated based on the second clock cycle; in response to the clock phase to be estimated not being located in the phase interval corresponding to the current clock cycle, determining that the first pointer control signal is a second value.

[0113] For example, the target clock phase and the second clock cycle are added to obtain the clock phase to be estimated B. For example, if the clock cycle corresponding to the clock phase B has been determined through the above process, the clock phase B and the second clock cycle can be added to obtain the clock phase C to be estimated.

[0114] For example, suppose the current clock cycle is Figure 7B For cycle 5 in the figure, for the clock phase C to be estimated, determine whether the clock phase C to be estimated is located in the phase interval corresponding to cycle 5. For example, the phase interval corresponding to cycle 5 is determined by the phase value of cycle 5 and the phase value of the next clock cycle of cycle 5.

[0115] If the clock phase C to be estimated is in the phase interval corresponding to cycle 5, the first pointer control signal is determined to be the first value, and the second submodule outputs the first value in cycle 5, indicating that the rising edge of the second clock signal is located in cycle 5, and the second clock cycle is added to the clock phase C to be estimated, and the clock phase to be estimated is updated to phase D, and subsequent judgments are continued.

[0116] If the clock phase C to be estimated is not located in the phase interval corresponding to cycle 5, the first pointer control signal is determined to be the second value, indicating that no rising edge of the second clock signal falls into cycle 5. The above process is continued in the next clock cycle to determine whether the clock phase C to be estimated is located in the phase interval corresponding to the next clock cycle, which will not be repeated here.

[0117] Therefore, phase tracking can be performed based on the target clock phase in the second clock signal and the target clock cycle in the first clock signal corresponding to the target clock phase, and the corresponding relationship can be used to determine the update time points of the subsequent read pointer and write pointer, so that in the subsequent clock cycles, a pointer control signal can be continuously output to indicate whether the rising edge of the second clock signal falls into the current clock cycle, so as to continuously update and adjust the read pointer and write pointer.

[0118] In the present disclosure, after frequency switching occurs, the phase relationship between the first clock signal and the second clock signal after the updated frequency can be determined based on the above process, thereby determining the update time point of the read pointer and the write pointer. There is no restriction on the frequency relationship between the two clock domains. The clock frequency of the first clock domain can be higher than the clock frequency of the second clock domain, and the clock frequency of the first clock domain can also be lower than the clock frequency of the second clock domain.

[0119] For example, the first read pointer and the first write pointer are adjusted according to the first pointer control signal in each clock cycle of the first clock signal, and the second read pointer and the second write pointer are adjusted according to the second pointer control signal in each clock cycle of the second clock signal.

[0120] In response to a data write operation being generated in a write clock cycle in the first clock domain, a data read operation is performed in a read clock cycle corresponding to the write clock cycle in the second clock signal. For example, the data write operation includes writing data to the first first-in-first-out buffer according to the first write pointer, and the data read operation includes reading the written data according to the second read pointer.

[0121] For example, in response to the clock frequency of the first clock signal being greater than the clock frequency of the second clock signal, a rising edge of the second clock signal that is a second clock cycle away from a rising edge of the read clock cycle is located in a clock cycle before a write clock cycle in the first clock signal.

[0122] For example, in response to the clock frequency of the first clock signal being lower than the clock frequency of the second clock signal, a rising edge of the write clock cycle that is a number of first clock cycles away from the rising edge of the write clock cycle is located one clock cycle before the read clock cycle in the second clock signal.

[0123] For example, a is a positive integer and is related to the depth of the first FIFO buffer. For example, if the depth of the first FIFO buffer is 3, a may be 1.

[0124] In the present disclosure, the read pointer and the write pointer are adjusted in each clock cycle, and the read pointer and the write pointer are in an increasing cycle state. To ensure that there is no conflict between reading and writing, in at least one embodiment of the present disclosure, it is arranged that when a data write operation occurs at a rising edge (rising edge m) of a slower clock domain, a data read operation is performed in a read clock cycle of a faster clock signal, and a rising edge that is a clock cycle of a slower clock signal different from the rising edge m is located in the clock cycle before the read clock cycle.

[0125] Fig. 8A A timing diagram of a data transmission process across clock domains is provided for an embodiment of the present disclosure.

[0126] like Fig. 8A As shown, assuming that the frequency of the first clock signal is less than the frequency of the second clock signal, the depth of the first FIFO buffer is 3, the first pointer control signal outputs 1 in each clock cycle, and the first read pointer and the first write pointer increase by 1 in each clock cycle, as shown in FIG. Fig. 8A As shown, the first read pointer and the first write pointer cycle through 0, 1, and 2.

[0127] like Fig. 8A As shown, the rising edge 0 of the first clock signal is located in the cycle 0 of the second clock signal, so the second pointer control signal 1 is output in the cycle 0 of the second clock signal, and the second read pointer and the second write pointer are increased by 1 in the cycle 1 of the second clock signal, changing from 2 to 0. The rising edge 1 of the first clock signal is located in the cycle 2 of the second clock signal, so the second pointer control signal 1 is output in the cycle 2 of the second clock signal, and the second read pointer and the second write pointer are increased by 1 in the cycle 3 of the second clock signal, changing from 0 to 1. The rising edge 2 of the first clock signal is located in the cycle 5 of the second clock signal, so the second pointer control signal 1 is output in the cycle 5 of the second clock signal, and the second read pointer and the second write pointer are increased by 1 in the cycle 6 of the second clock signal, changing from 1 to 2. The subsequent process is analogous and will not be repeated here.

[0128] Therefore, if Fig. 8A As shown, assuming that a data write operation occurs at rising edge 0, the data at write position 1 needs to be read out at cycle 3 of the second clock signal. Assuming that a data write operation occurs at rising edge 1, the data at write position 2 needs to be read out at cycle 6 of the second clock signal, thereby avoiding data read and write conflicts, and the read pointer and the write pointer can change according to the pointer control signal in each clock cycle regardless of the data write and read requests.

[0129] In addition, if Fig. 8AAs shown, the delay caused by the above-mentioned cross-clock domain data transmission is less than the clock cycles of 2 slow clock domains. Compared with the traditional data transmission method using multi-stage triggers for synchronization, the synchronization processing delay of the asynchronous clock signal can be reduced.

[0130] In at least one embodiment of the present disclosure, it is configured that when a data write operation occurs at a certain rising edge (rising edge n) of the faster clock domain, a data read operation is performed in a read clock cycle in a slower clock signal, and a rising edge in the slower clock signal that differs from the rising edge of the read clock cycle by a+1 slower clock cycles is located in a clock cycle before the write clock cycle in the faster clock signal.

[0131] Figure 8B A timing diagram of a data transmission process across clock domains is provided for another embodiment of the present disclosure.

[0132] like Figure 8B As shown, assuming that the frequency of the first clock signal is greater than the frequency of the second clock signal, the depth of the first FIFO buffer is 3, the second pointer control signal outputs 1 in each clock cycle, and the second read pointer and the second write pointer increase by 1 in each clock cycle, such as Figure 8B As shown, the second read pointer and the second write pointer cycle through 0, 1, and 2.

[0133] like Figure 8B As shown, the rising edge 0 of the second clock signal is located in the cycle 0 of the first clock signal, so the first pointer control signal 1 is output in the cycle 0 of the first clock signal, and the first read pointer and the first write pointer increase by 1 in the cycle 1 of the first clock signal, changing from 1 to 2. The rising edge 1 of the second clock signal is located in the cycle 2 of the first clock signal, so the first pointer control signal 1 is output in the cycle 2 of the first clock signal, and the first read pointer and the first write pointer increase by 1 in the cycle 3 of the first clock signal, changing from 2 to 0. The rising edge 2 of the second clock signal is located in the cycle 5 of the first clock signal, so the first pointer control signal 1 is output in the cycle 5 of the first clock signal, and the first read pointer and the first write pointer increase by 1 in the cycle 6 of the first clock signal, changing from 0 to 1. The subsequent process is analogous and will not be repeated here.

[0134] Therefore, if Figure 8B As shown, assuming that a data write operation occurs in cycle 1 of the first clock signal, the data in write position 2 needs to be read out at the rising edge 2 of the second clock signal. Assuming that a data write operation occurs in cycle 3 of the first clock signal, the data in write position 0 needs to be read out at the rising edge 3 of the second clock signal, thereby avoiding data read and write conflicts, and the read pointer and the write pointer can be changed according to the pointer control signal in each clock cycle without considering the data write and read requests.

[0135] like Figure 8B As shown, the delay caused by the above-mentioned data transmission across clock domains is less than the clock cycles of two slow clock domains. Compared with the traditional data transmission method using multi-stage triggers for synchronization (at least because the synchronizer brings more than two clock cycles of the destination clock domains), the synchronization processing delay of the asynchronous clock signal can be reduced.

[0136] Of course, it should be noted that the above pointer adjustment process is described by taking the write operation occurring in the first clock domain and the read operation occurring in the second clock domain as an example. The pointer adjustment logic for the write operation occurring in the second clock domain and the read operation occurring in the first clock domain is similar and will not be repeated here.

[0137] In the present disclosure, the clock signal adopts the same source clock signal, so the phase relationship between the two clock domains can be determined by the frequency division coefficient, thereby determining the update time points of the read pointers and write pointers of the two clock domains, reducing the synchronization processing delay of the asynchronous clock signal.

[0138] As mentioned above, high-performance processors use DVFS technology. The processing core will use different voltages and frequencies according to different loads during operation. For example, when the workload of a processing core is small, the voltage and frequency can be reduced to a very low level to save power. When the workload of a processing core is large, its voltage and frequency can be increased. Cross-clock data processing is prone to errors during frequency switching. Currently, data transmission is usually stopped during frequency switching. However, if data transmission is stopped during frequency switching, the performance of high-performance processors will be affected.

[0139] In the integrated circuit provided by at least one embodiment of the present disclosure, the first clock domain further includes a first state machine and a first asynchronous pointer control module, and the second clock domain further includes a second state machine and a second asynchronous pointer control module.

[0140] For example, the first asynchronous pointer control module and the second asynchronous pointer control module each include a multi-stage trigger, and the first asynchronous pointer control module and the second asynchronous pointer control module synchronize the first write pointer, the first read pointer, the second write pointer, and the second read pointer in different clock domains through the multi-stage triggers they include.

[0141] For example, the first asynchronous pointer control module and the second asynchronous pointer control module determine whether the first FIFO buffer or the second FIFO buffer is empty or full by comparing the write pointer of one clock domain with the read pointer of another clock domain. Therefore, the asynchronous pointer control module needs to synchronize the read pointer (pointing to the next position in the FIFO buffer where data is to be read) or the write pointer (pointing to the next position in the FIFO buffer where data is to be written) from one clock domain to another clock domain. Unlike the synchronous pointer control module, in the asynchronous pointer control module, the synchronization of the pointer is realized by a synchronizer, which usually includes a multi-stage trigger. By using the multi-stage trigger to stably reflect the pointer value of another clock domain, the metastable problem is avoided. When comparing pointers, these stable register values ​​are used instead of directly comparing the pointers across clock domains. Although the asynchronous pointer control module may bring more delays, the asynchronous pointer control module can still maintain data transmission across clock domains during the frequency switching process.

[0142] For example, the asynchronous pointer control module may adopt a conventional structure that utilizes an asynchronous FIFO to perform cross-clock domain data transmission, which will not be described in detail here.

[0143] For example, the first state machine is configured to control the first clock domain to use the first asynchronous pointer control module to perform data transmission across clock domains when frequency switching occurs, and to control the first clock domain to use the first synchronous pointer control module to perform data transmission across clock domains after the frequency switching is completed and the phase estimation is completed.

[0144] The second state machine is configured to control the second clock domain to use the second asynchronous pointer control module to perform cross-clock domain data transmission when frequency switching occurs, and to control the second clock domain to use the second synchronous pointer control module to perform cross-clock domain data transmission after the frequency switching is completed and the phase estimation is completed.

[0145] Fig. 9 A schematic diagram of state machine state switching provided by an embodiment of the present disclosure.

[0146] like Fig. 9 As shown, the integrated circuit is in a reset state when it is reset or initially powered on, and enters the first state. At this time, the frequency is changing and has not yet stabilized. In the first state, the first asynchronous pointer control module, the second asynchronous pointer control module, the first first-in-first-out buffer, and the second first-in-first-out buffer are used to transmit data across clock domains.

[0147] After the frequency switching is completed and the phase estimation is completed, for example, when the clock is stable and the first pointer control module or the second pointer control module completes the phase estimation and outputs the first pointer control signal or the second pointer control signal, it enters the second state, at which time the first synchronization pointer control module, the second synchronization pointer control module, the first first-in-first-out buffer, and the second first-in-first-out buffer are used to perform data transmission across clock domains.

[0148] When frequency switching occurs again, the second state is exited, the third state is entered, and finally the first state is returned. At this time, the first asynchronous pointer control module, the second asynchronous pointer control module, the first first-in-first-out buffer, and the second first-in-first-out buffer are used to perform data transmission across clock domains, and the above process is repeated.

[0149] The first state machine and the second state machine are also configured to receive first indication information indicating whether the frequency switching is completed, and second indication information indicating the frequency size relationship between the first clock signal and the second clock signal. In response to the first indication information indicating that the frequency switching has occurred, the first state machine controls the first clock domain to use the first asynchronous pointer control module to perform cross-clock domain data transmission, and the second state machine controls the second clock domain to use the second asynchronous pointer control module to perform cross-clock domain data transmission; the first state machine and the second state machine are also configured to determine whether the frequency switching is completed and the phase estimation is completed based on the first indication information and the second indication information.

[0150] For example, when the first state machine determines whether the frequency switching is completed and the phase estimation is completed according to the first indication information and the second indication information, it includes performing the following operations: in response to the first indication information indicating that the frequency switching is completed, and the second indication information indicating that the clock frequency of the first clock signal is greater than the clock frequency of the second clock signal: the first state machine controls the first synchronization pointer control module to perform phase estimation to obtain the phase relationship and determine the first pointer control signal based on the phase relationship, in response to the first synchronization pointer control module completing the phase estimation, it is determined that the frequency switching is completed and the phase estimation is completed, and the first state machine is also configured to perform a synchronous handshake with the second state machine so that the second state machine controls the second clock domain to use the second synchronization pointer control module to perform data transmission across clock domains; in response to the first indication information indicating that the frequency switching is completed, and the second indication information indicating that the clock frequency of the first clock signal is less than the clock frequency of the second clock signal: after completing the synchronous handshake with the second state machine, it is determined that the frequency switching is completed and the phase estimation is completed.

[0151] Fig.10 A schematic block diagram of a first pointer control module provided in accordance with an embodiment of the present disclosure.

[0152] It should be noted that the second pointer control module also has a similar structure, for example, including a second state machine and a second asynchronous pointer control module and a second synchronous pointer control module, and the specific contents will not be repeated.

[0153] like Fig.10 As shown, the first state machine receives the first indication information and the second indication information, determines whether the state needs to be switched according to the first indication information and the second indication information, and outputs different control signals to switch between using the first synchronous control module or the first asynchronous pointer control module to generate the first pointer control signal.

[0154] For example, when the chip is reset or the frequency is unstable, the first indication information indicates that the frequency switching has not been completed. At this time, it is in the first state, and the first state machine outputs a control signal 1, and uses the first pointer control signal output by the first asynchronous pointer control module to adjust the first read pointer and the first write pointer. For example, when the first asynchronous pointer control module is used, the first pointer control signal includes a control signal for the first read pointer and a control signal for the first write pointer, and the first read pointer and the first write pointer are adjusted respectively.

[0155] When the first indication information indicates that the chip frequency switching is completed, it is determined according to the second indication information whether the clock frequency of the first clock domain is greater than the clock frequency of the second clock domain.

[0156] If the clock frequency of the first clock domain is greater than the clock frequency of the second clock domain, the first state machine controls the first synchronization pointer control module to perform phase estimation according to the above process, including determining the phase relationship and determining the first pointer control signal based on the phase relationship. The specific process refers to the relevant description of the above-mentioned first synchronization pointer control module, which will not be repeated here. After the first synchronization pointer control module completes the phase estimation, it is determined that the frequency switching is completed and the phase estimation is completed, and the second state is entered. At this time, the first state machine outputs the control signal 0, and uses the first pointer control signal output by the first synchronization pointer control module to adjust the first read pointer and the first write pointer. In addition, the first state machine is also configured to perform a synchronous handshake with the second state machine, so that the second state machine controls the second clock domain to use the second synchronization pointer control module to perform data transmission across clock domains. For the second synchronization pointer control module, the second pointer control signal output by the second synchronization pointer control module is the first value. As a result, both clock domains enter the synchronization pointer control logic.

[0157] When the first indication information indicates that the chip frequency switching is completed, if the clock frequency of the first clock domain is less than the clock frequency of the second clock domain, the first state machine waits for the handshake signal of the second state machine. At this time, the second state machine controls the second synchronization pointer control module to perform phase estimation according to the above process. Specifically, the second state machine also determines that the frequency switching is completed and the frequency of the second clock signal is greater than the frequency of the first clock signal according to the received first indication information and the second indication information. The second state machine controls the second synchronization pointer control module to perform phase estimation, including determining the phase relationship and determining the second pointer control signal based on the phase relationship. After the second synchronization pointer control module completes the phase estimation, it is determined that the frequency switching is completed and the phase estimation is completed, and enters the second state. At this time, the second state machine outputs the control signal 0, and uses the second pointer control signal output by the second synchronization pointer control module to adjust the second read pointer and the second write pointer. In addition, the second state machine is also configured to perform synchronous handshake with the first state machine. After the first state machine completes the synchronous handshake with the second state machine, the first state machine determines that the frequency switching is completed and the phase estimation is completed, and controls the first clock domain to use the first synchronization pointer control module to perform cross-clock domain data transmission. For the first synchronization pointer control module, the first pointer control signal output by it is the first value. Thus, both clock domains enter the synchronization pointer control logic.

[0158] When the first indication information indicates that the chip frequency switches again, the first state machine and the second state machine both exit the second state and enter the third state, and finally return to the first state. The first state machine and the second state machine both output control signal 1 to switch to their respective asynchronous pointer control modules, and continue to use the asynchronous pointer control module to adjust the read pointer and the write pointer until entering the second state again.

[0159] The integrated circuit provided by at least one embodiment of the present disclosure can switch the synchronous pointer control module to the asynchronous pointer control module during the dynamic frequency switching process, and use the asynchronous pointer control module to achieve clock signal synchronization during the frequency switching process. When the frequency switching is completed and the phase estimation is completed, the synchronous pointer control module can be used together again through the synchronous handshake mechanism, thereby maintaining data transmission during the dynamic frequency switching process, maintaining low-latency cross-clock processing after the frequency is stable, and data transmission can be performed throughout the entire operating period of the integrated circuit, thereby improving the performance of the processor without pausing data transmission due to switching frequencies.

[0160] Fig.11 A schematic flowchart of a method for data transmission across clock domains is provided for at least one embodiment of the present disclosure.

[0161] For example, the data transmission method across clock domains is applied to a first clock domain determined based on a first clock signal and a second clock domain determined based on a second clock signal, the first clock domain includes a first first-in-first-out buffer, the second clock domain includes a second first-in-first-out buffer, the first clock signal and the second clock signal are homologous clock signals, the frequency of the first clock signal is greater than the frequency of the second clock signal, or the frequency of the first clock signal is less than the clock frequency of the second clock signal.

[0162] For example, the cross-clock domain data transmission method can be applied to an integrated circuit including different clock domains. For the description of the clock domains and the integrated circuit, reference can be made to the aforementioned related parts and will not be repeated here.

[0163] For example, Fig.11 As shown, the cross-clock domain data transmission method provided by the embodiment of the present disclosure includes steps S110 to S130.

[0164] In step S110, a first pointer control signal is determined in a first clock domain, and a first read pointer and a first write pointer in the first clock domain are adjusted according to the first pointer control signal.

[0165] For example, the first pointer control signal is used to indicate an update time point of the first read pointer and the first write pointer.

[0166] For the specific process of using the first pointer control signal to adjust the first read pointer and the first write pointer, reference may be made to the relevant description in the aforementioned integrated circuit, and the repeated parts will not be repeated here.

[0167] In step S120, a second pointer control signal is determined in the second clock domain, and a second read pointer and a second write pointer in the second clock domain are adjusted according to the second pointer control signal.

[0168] For example, the second pointer control signal is used to indicate an update time point of the second read pointer and the second write pointer.

[0169] For the specific process of adjusting the second read pointer and the second write pointer using the second pointer control signal, reference may be made to the relevant description in the aforementioned integrated circuit, and the repeated parts will not be repeated here.

[0170] In step S130, based on the first write pointer and the second read pointer, a first first-in-first-out buffer is used to perform data transmission from the first clock domain to the second clock domain, and based on the first read pointer and the second write pointer, a second first-in-first-out buffer is used to perform data transmission from the second clock domain to the first clock domain.

[0171] For example, in some embodiments, determining the first pointer control signal may include: in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, determining the phase relationship between the first clock signal and the second clock signal according to the second clock phase and the second clock cycle of the second clock domain, the first clock signal, and the first clock phase of the first clock domain, and determining the first pointer control signal based on the phase relationship; in response to the frequency of the first clock signal being less than the frequency of the second clock signal, determining the first pointer control signal to be a first value so that the first read pointer and the first write pointer increase by the first value in each clock cycle of the first clock signal.

[0172] For example, in some embodiments, determining the second pointer control signal may include: in response to the frequency of the second clock signal being greater than the frequency of the first clock signal, determining the phase relationship between the first clock signal and the second clock signal according to the first clock phase and the first clock cycle of the first clock domain, the second clock signal, and the second clock phase of the second clock domain, and determining the second pointer control signal based on the phase relationship; in response to the frequency of the second clock signal being less than the frequency of the first clock signal, determining the second pointer control signal to be a first value so that the second read pointer and the second write pointer increase by the first value in each clock cycle of the second clock signal.

[0173] The method for determining the second pointer control signal is similar to the method for determining the first pointer control signal. The following takes the first pointer control signal as an example to specifically describe the process of determining the first pointer control signal. For the process of the second pointer control signal, reference can be made to the adaptive adjustment object of the determination process of the first pointer control signal, which will not be repeated here.

[0174] For example, determining the first pointer control signal may further include: determining a first clock phase according to a first clock cycle of the first clock domain, wherein the first clock phase is used to indicate a phase value of each clock cycle of the first clock signal.

[0175] For example, in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, the first pointer control signal is a first value indicating that a rising edge of the second clock signal is in the current clock cycle of the first clock signal, and the first pointer control signal is a second value indicating that no rising edge of the second clock signal is in the current clock cycle.

[0176] For example, determining the phase relationship between the first clock signal and the second clock signal according to the second clock phase and the second clock cycle of the second clock domain, the first clock signal, and the first clock phase, and determining the first pointer control signal based on the phase relationship may include: determining the target clock phase in the second clock signal based on the second clock phase and the first clock signal, wherein the target clock phase is a phase value of a clock cycle selected in the second clock signal; determining the target clock cycle corresponding to the target clock phase in the first clock signal based on the first clock phase and the second clock cycle, wherein the target clock phase is located in the phase interval corresponding to the target clock cycle, and the phase interval is determined by the phase value of the target clock cycle and the phase value of the next clock cycle of the target clock cycle; and continuously estimating the first pointer control signal output in each current clock cycle of the first clock signal based on the target clock phase and the target clock cycle.

[0177] For example, the process of determining the target clock phase may refer to the related description of the aforementioned phase estimation unit, which will not be repeated here.

[0178] For example, according to the second clock phase and the second clock cycle of the second clock domain, the first clock signal, and the first clock phase, the phase relationship between the first clock signal and the second clock signal is determined, and the first pointer control signal is determined based on the phase relationship. It can also include: estimating the phase change of the second clock signal measured by the clock cycle of the first clock signal.

[0179] For the specific implementation process of estimating the phase change, reference may be made to the related description of the aforementioned phase estimation unit, which will not be repeated here.

[0180] For example, in some embodiments, based on the target clock phase and the target clock cycle, continuously estimating the first pointer control signal output in each current clock cycle of the first clock signal can include: determining the clock phase to be estimated based on the target clock phase and the second clock cycle; in the current clock cycle: determining whether the clock phase to be estimated is located in the phase interval corresponding to the current clock cycle based on the clock phase to be estimated; in response to the clock phase to be estimated being located in the phase interval corresponding to the current clock cycle, determining that the first pointer control signal output in the current clock cycle is a first value, and updating the clock phase to be estimated based on the second clock cycle; in response to the clock phase to be estimated not being located in the phase interval corresponding to the current clock cycle, determining that the first pointer control signal output in the current clock cycle is a second value.

[0181] For the specific process of continuously estimating the first pointer control signal, reference may be made to the related description of the aforementioned phase tracking unit, and the repeated parts will not be repeated here.

[0182] For example, the first read pointer and the first write pointer are adjusted according to the first pointer control signal in each clock cycle of the first clock signal, and the second read pointer and the second write pointer are adjusted according to the second pointer control signal in each clock cycle of the second clock signal; in response to a write clock cycle in the first clock domain, a data write operation is generated, and a data read operation is performed in a read clock cycle corresponding to the write clock cycle in the second clock signal, wherein, in response to the clock frequency of the first clock signal being greater than the clock frequency of the second clock signal, a rising edge of the second clock signal that is a+1 second clock cycles different from a rising edge of the read clock cycle is located in a clock cycle before the write clock cycle in the first clock signal, and in response to the clock frequency of the first clock signal being less than the clock frequency of the second clock signal, a rising edge that is a first clock cycle different from a rising edge of the write clock cycle is located in a clock cycle before the read clock cycle, and a is a positive integer.

[0183] In the present disclosure, after the frequency switching occurs, the phase relationship between the first clock signal and the second clock signal after the frequency is updated can be determined based on the above process, thereby determining the update time point of the read pointer and the write pointer, and there is no restriction on the frequency size relationship between the two clock domains. The clock frequency of the first clock domain can be higher than the clock frequency of the second clock domain, and the clock frequency of the first clock domain can also be lower than the clock frequency of the second clock domain. In addition, the clock signal uses a homologous clock signal, so the phase relationship between the two clock domains can be determined by the frequency division coefficient, thereby determining the update time point of the read pointer and the write pointer of the two clock domains, reducing the synchronization processing delay of the asynchronous clock signal.

[0184] For example, in at least one embodiment of the present disclosure, the method for data transmission across clock domains also includes: when frequency switching occurs, controlling the first clock domain to use asynchronous pointer control logic to perform data transmission across clock domains, and after the frequency switching is completed and the phase estimation is completed, controlling the first clock domain to use synchronous pointer control logic to perform data transmission across clock domains, wherein the asynchronous pointer control logic includes synchronizing a first write pointer, a first read pointer, a second write pointer, and a second read pointer in different clock domains through a multi-stage trigger, and the synchronous pointer control logic includes obtaining a phase relationship and performing data transmission across clock domains based on the phase relationship.

[0185] For example, the asynchronous pointer control logic can refer to the relevant description of the aforementioned asynchronous pointer control module, and the asynchronous pointer control logic can implement the relevant functions of the asynchronous pointer control module. The synchronous pointer control logic can refer to the relevant description of the aforementioned synchronous pointer control module, and the synchronous pointer control logic can implement the relevant functions of the synchronous pointer control module.

[0186] For example, in some embodiments, when a frequency switch occurs, controlling the first clock domain to use asynchronous pointer control logic to perform data transmission across clock domains may include: in response to received first indication information indicating that a frequency switch has occurred, controlling the first clock domain to use asynchronous pointer control logic to perform data transmission across clock domains.

[0187] For example, in some embodiments, the data transmission method further includes: determining whether the frequency switching is completed and the phase estimation is completed according to the first indication information and the second indication information, wherein the second indication information is used to indicate the frequency magnitude relationship between the first clock signal and the second clock signal.

[0188] For example, in some embodiments, determining whether the frequency switching is completed and the phase estimation is completed based on the first indication information and the second indication information may include: in response to the first indication information indicating that the frequency switching is completed, and the second indication information indicating that the clock frequency of the first clock signal is greater than the clock frequency of the second clock signal: performing phase estimation to obtain the phase relationship and determining the first pointer control signal based on the phase relationship, in response to determining the first pointer control signal, determining that the frequency switching is completed and the phase estimation is completed, and performing state synchronization with the second clock domain, so that the second clock domain performs a pointer adjustment according to the determined second pointer control signal for data transmission across clock domains; in response to the first indication information indicating that the frequency switching is completed, and the second indication information indicating that the clock frequency of the first clock signal is less than the clock frequency of the second clock signal: after performing state synchronization with the second clock domain, determining that the frequency switching is completed and the phase estimation is completed, and performing a pointer adjustment according to the determined first pointer control signal for data transmission across clock domains.

[0189] For a detailed description of the above process, please refer to the relevant content of the aforementioned integrated circuit, which will not be repeated here.

[0190] The cross-clock domain data transmission method provided by at least one embodiment of the present disclosure can switch the synchronous pointer control module to the asynchronous pointer control module during the dynamic frequency switching process, and use the asynchronous pointer control module to achieve clock signal synchronization during the frequency switching process. When the frequency switching is completed and the phase estimation is completed, the synchronous pointer control module can be used again through the synchronous handshake mechanism, thereby maintaining data transmission during the dynamic frequency switching process and maintaining low-latency cross-clock processing after the frequency is stable.

[0191] At least one embodiment of the present disclosure further provides an electronic device, Fig.12 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0192] For example, Fig.12As shown, the electronic device includes a processor 201, a communication interface 202, a memory 203 and a communication bus 204. The processor 201, the communication interface 202, and the memory 203 communicate with each other through the communication bus 204, and the components such as the processor 201, the communication interface 202, and the memory 203 can also communicate through a network connection. The present disclosure does not limit the type and function of the network.

[0193] For example, the memory 203 is used to store computer executable instructions non-transiently. When the processor 201 is used to execute the computer executable instructions, the computer executable instructions are executed by the processor 201 to implement the cross-clock domain data transmission method according to any of the above embodiments. The specific implementation of each step of the cross-clock domain data transmission method and the related explanation content can be referred to the embodiment of the cross-clock domain data transmission method above, which will not be repeated here.

[0194] For example, the processor 201 executes the program stored in the memory 203 to implement the cross-clock domain data transmission method, which is the same as the implementation method mentioned in the embodiment of the cross-clock domain data transmission method, and will not be repeated here.

[0195] For example, the communication bus 204 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industrial Standard Architecture (EISA) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0196] For example, the communication interface 202 is used to implement communication between the electronic device and other devices.

[0197] For example, the processor 201 can control other components in the electronic device to perform the desired functions. The processor 201 can be a central processing unit (CPU), a network processor (NP), etc., and can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The central processing unit (CPU) can be an X86 or ARM architecture, etc.

[0198] For example, the memory 203 may include any combination of one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer executable instructions may be stored on the computer-readable storage medium, and the processor 201 may execute the computer executable instructions to implement various functions of the electronic device. Various applications and various data may also be stored in the storage medium.

[0199] For example, for a detailed description of the process of an electronic device performing cross-clock domain data transmission, reference may be made to the relevant description in the embodiment of the cross-clock domain data transmission method, and repeated parts will not be repeated.

[0200] Fig.13 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. Fig.13 As shown, one or more computer executable instructions 301 may be non-temporarily stored on the storage medium 300. For example, when the computer executable instructions 301 are executed by a processor, one or more steps in the cross-clock domain data transmission method described above may be executed.

[0201] For example, the storage medium 300 may be applied to the above electronic device. For example, the storage medium 300 may include the memory 203 in the electronic device.

[0202] For example, the description of the storage medium 300 may refer to the description of the memory in the embodiment of the electronic device, and the repeated parts will not be repeated.

[0203] There are a few points to note about this disclosure:

[0204] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0205] (2) For the sake of clarity, the thickness and size of layers or structures are exaggerated in the drawings used to describe the embodiments of the present invention. It is understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or there may be intervening elements.

[0206] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0207] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. An integrated circuit, comprising a first clock domain determined based on a first clock signal and a second clock domain determined based on a second clock signal, wherein the first clock signal and the second clock signal are homologous clock signals, and a frequency of the first clock signal is greater than a frequency of the second clock signal, or a frequency of the first clock signal is less than a clock frequency of the second clock signal, The first clock domain includes a first pointer control module, the second clock domain includes a second pointer control module, The first pointer control module is configured to generate a first pointer control signal for the first clock domain, so that the first read pointer and the first write pointer in the first clock domain are adjusted according to the first pointer control signal, wherein: The first pointer control signal is used to indicate an update time point of the first read pointer and the first write pointer; The second pointer control module is configured to generate a second pointer control signal for the second clock domain, so that the second read pointer and the second write pointer in the second clock domain are adjusted according to the second pointer control signal, wherein the second pointer control signal is used to indicate an update time point of the second read pointer and the second write pointer; The integrated circuit further includes a first first-in-first-out buffer and a second first-in-first-out buffer, The first FIFO buffer is configured to perform data transmission from the first clock domain to the second clock domain based on the first write pointer and the second read pointer, The second FIFO buffer is configured to perform data transmission from the second clock domain to the first clock domain based on the first read pointer and the second write pointer; The first pointer control module includes a first synchronous pointer control module, and the first synchronous pointer control module is configured as follows: In response to the frequency of the first clock signal being greater than the frequency of the second clock signal, determining a phase relationship between the first clock signal and the second clock signal according to a second clock phase and a second clock cycle of the second clock domain, the first clock signal, and a first clock phase of the first clock domain, and determining the first pointer control signal based on the phase relationship; In response to the frequency of the first clock signal being less than the frequency of the second clock signal, the first pointer control signal is determined to be a first value, so that the first read pointer and the first write pointer increase by the first value in each clock cycle of the first clock signal.

2. The integrated circuit according to claim 1, wherein: The first synchronous pointer control module and the second synchronous pointer control module include the same structure as the second synchronous pointer control module, and both include a first submodule and a second submodule. The first submodule of the first synchronization pointer control module is configured to determine the first clock phase according to the first clock cycle of the first clock domain, wherein the first clock phase is used to indicate the phase value of each clock cycle of the first clock signal; The second submodule of the first synchronous pointer control module is configured to determine the first pointer control signal, wherein, in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, the first pointer control signal being the first value indicates that the rising edge of the second clock signal is located in the current clock cycle of the first clock signal, and the first pointer control signal being the second value indicates that there is no rising edge of the second clock signal in the current clock cycle of the first clock signal.

3. The integrated circuit according to claim 2, wherein: The second submodule includes a phase synchronization detection unit, a phase estimation unit and a phase tracking unit. The phase synchronization detection unit is configured to determine a target clock phase in the second clock signal based on the second clock phase and the first clock signal, wherein the target clock phase is a phase value of a clock cycle selected in the second clock signal; The phase estimation unit is configured to determine a target clock cycle corresponding to the target clock phase in the first clock signal based on the first clock phase and the second clock cycle, wherein the target clock phase is located in a phase interval corresponding to the target clock cycle, and the phase interval is determined by a phase value of the target clock cycle and a phase value of a clock cycle next to the target clock cycle; The phase tracking unit is configured to continuously estimate the first pointer control signal output in each current clock cycle of the first clock signal based on the target clock phase and the target clock cycle.

4. The integrated circuit according to claim 3, wherein: The phase synchronization detection unit includes a multi-stage trigger group and an AND gate. The multi-stage flip-flop group is configured to use the first clock signal as a clock to synchronize a transition edge selected in the second clock signal; The AND gate is configured to perform AND processing on the synchronized transition edge and the second clock phase to obtain a phase value of the clock cycle where the selected transition edge is located as the target clock phase.

5. The integrated circuit according to claim 4, wherein: The phase estimation unit is configured to compare the target clock phase with phase intervals corresponding to multiple clock cycles to determine a target clock cycle corresponding to the target clock phase, wherein the multiple clock cycles are multiple clock cycles in the first clock signal before the transition edge after the synchronization.

6. The integrated circuit according to claim 5, wherein: The phase estimation unit is further configured to estimate a phase change of the second clock signal measured in terms of a clock period of the first clock signal.

7. The integrated circuit according to claim 3, wherein: When the phase tracking unit continuously estimates the first pointer control signal output in each current clock cycle of the first clock signal based on the target clock phase and the target clock cycle, the following steps are performed: Determining a clock phase to be estimated based on the target clock phase and the second clock period; In the current clock cycle: Based on the clock phase to be estimated, determining whether the clock phase to be estimated is within a phase interval corresponding to the current clock cycle; In response to the clock phase to be estimated being located in the phase interval corresponding to the current clock cycle, determining that the first pointer control signal output in the current clock cycle is the first value, and updating the clock phase to be estimated based on the second clock cycle; In response to the fact that the clock phase to be estimated is not located in the phase interval corresponding to the current clock cycle, it is determined that the first pointer control signal output in the current clock cycle is the second value.

8. The integrated circuit of claim 1, wherein: The first read pointer and the first write pointer are adjusted according to the first pointer control signal in each clock cycle of the first clock signal, and the second read pointer and the second write pointer are adjusted according to the second pointer control signal in each clock cycle of the second clock signal; In response to a data write operation being generated in a write clock cycle of the first clock domain, a data read operation is performed in a read clock cycle corresponding to the write clock cycle in the second clock signal, In response to the clock frequency of the first clock signal being greater than the clock frequency of the second clock signal, a rising edge of the second clock signal that is a+1 second clock cycles away from a rising edge of the read clock cycle is located in a clock cycle before the write clock cycle in the first clock signal, In response to the clock frequency of the first clock signal being less than the clock frequency of the second clock signal, a rising edge that is a first clock cycle away from a rising edge of the write clock cycle is located in a clock cycle before the read clock cycle in the second clock signal, and a is a positive integer.

9. The integrated circuit according to any one of claims 1 to 8, wherein: The first pointer control module further includes a first state machine and a first asynchronous pointer control module, and the second pointer control module further includes a second state machine and a second asynchronous pointer control module. The first asynchronous pointer control module and the second asynchronous pointer control module each include a multi-stage trigger, and the first asynchronous pointer control module and the second asynchronous pointer control module synchronize the first write pointer, the first read pointer, the second write pointer, and the second read pointer in different clock domains through the multi-stage triggers respectively included; The first state machine is configured to control the first clock domain to use the first asynchronous pointer control module to perform cross-clock domain data transmission when frequency switching occurs, and control the first clock domain to use the first synchronous pointer control module to perform cross-clock domain data transmission after frequency switching is completed and phase estimation is completed; The second state machine is configured to control the second clock domain to use the second asynchronous pointer control module to transmit data across clock domains when frequency switching occurs, and to control the second clock domain to use the second synchronous pointer control module to transmit data across clock domains after the frequency switching is completed and the phase estimation is completed.

10. The integrated circuit of claim 9, wherein: The first state machine and the second state machine are further configured to receive first indication information indicating whether the frequency switching is completed, and second indication information indicating the frequency magnitude relationship between the first clock signal and the second clock signal, In response to the first indication information indicating that frequency switching occurs, the first state machine controls the first clock domain to use the first asynchronous pointer control module to perform cross-clock domain data transmission, and the second state machine controls the second clock domain to use the second asynchronous pointer control module to perform cross-clock domain data transmission; The first state machine and the second state machine are further configured to determine whether the frequency switching is completed and the phase estimation is completed according to the first indication information and the second indication information.

11. The integrated circuit of claim 10, wherein: When the first state machine determines whether the frequency switching is completed and the phase estimation is completed according to the first indication information and the second indication information, the first state machine includes performing the following operations: In response to the first indication information indicating that the frequency switching is completed, and the second indication information indicating that the clock frequency of the first clock signal is greater than the clock frequency of the second clock signal: The first state machine controls the first synchronous pointer control module to perform phase estimation to obtain the phase relationship and determines the first pointer control signal based on the phase relationship. In response to the first synchronization pointer control module completing the phase estimation, determining that the frequency switching is completed and the phase estimation is completed, and The first state machine is further configured to perform a synchronous handshake with the second state machine, so that the second state machine controls the second clock domain to use the second synchronization pointer control module to perform data transmission across clock domains; In response to the first indication information indicating that the frequency switching is completed, and the second indication information indicating that the clock frequency of the first clock signal is less than the clock frequency of the second clock signal: After completing the synchronization handshake with the second state machine, it is determined that the frequency switching is completed and the phase estimation is completed.

12. A method for data transmission across clock domains, applied to a first clock domain determined based on a first clock signal and a second clock domain determined based on a second clock signal, wherein the first clock domain includes a first first-in-first-out buffer, the second clock domain includes a second first-in-first-out buffer, the first clock signal and the second clock signal are homologous clock signals, the frequency of the first clock signal is greater than the frequency of the second clock signal, or the frequency of the first clock signal is less than the clock frequency of the second clock signal, The data transmission method comprises: In the first clock domain, determining a first pointer control signal, and adjusting a first read pointer and a first write pointer in the first clock domain according to the first pointer control signal, wherein the first pointer control signal is used to indicate an update time point of the first read pointer and the first write pointer; In the second clock domain, determining a second pointer control signal, and adjusting a second read pointer and a second write pointer of the second clock domain according to the second pointer control signal, wherein the second pointer control signal is used to indicate an update time point of the second read pointer and the second write pointer; Based on the first write pointer and the second read pointer, using the first first-in-first-out buffer to perform data transmission from the first clock domain to the second clock domain, and based on the first read pointer and the second write pointer, using the second first-in-first-out buffer to perform data transmission from the second clock domain to the first clock domain; Wherein, determining the first pointer control signal includes: In response to the frequency of the first clock signal being greater than the frequency of the second clock signal, determining a phase relationship between the first clock signal and the second clock signal according to a second clock phase and a second clock cycle of the second clock domain, the first clock signal, and a first clock phase of the first clock domain, and determining the first pointer control signal based on the phase relationship; In response to the frequency of the first clock signal being less than the frequency of the second clock signal, the first pointer control signal is determined to be a first value, so that the first read pointer and the first write pointer increase by the first value in each clock cycle of the first clock signal.

13. The data transmission method according to claim 12, wherein: Determining a first pointer control signal also includes: Determine the first clock phase according to a first clock cycle of the first clock domain, wherein the first clock phase is used to indicate a phase value of each clock cycle of the first clock signal; In which, in response to the frequency of the first clock signal being greater than the frequency of the second clock signal, the first pointer control signal is a first value indicating that a rising edge of the second clock signal is located in a current clock cycle of the first clock signal, and the first pointer control signal is a second value indicating that no rising edge of the second clock signal is located in the current clock cycle.

14. The data transmission method according to claim 12, wherein: Determining a phase relationship between the first clock signal and the second clock signal according to a second clock phase and a second clock cycle of the second clock domain, the first clock signal, and the first clock phase, and determining the first pointer control signal based on the phase relationship, including: Determine a target clock phase in the second clock signal based on the second clock phase and the first clock signal, wherein the target clock phase is a phase value of a clock cycle selected in the second clock signal; Determine a target clock cycle corresponding to the target clock phase in the first clock signal based on the first clock phase and the second clock cycle, wherein the target clock phase is located in a phase interval corresponding to the target clock cycle, and the phase interval is determined by a phase value of the target clock cycle and a phase value of a clock cycle next to the target clock cycle; Based on the target clock phase and the target clock period, a first pointer control signal output in each current clock period of the first clock signal is continuously estimated.

15. The data transmission method according to claim 12, further comprising: When frequency switching occurs, the first clock domain and the second clock domain are controlled to use asynchronous pointer control logic to perform cross-clock domain data transmission; after the frequency switching is completed and the phase estimation is completed, the first clock domain and the second clock domain are controlled to use synchronous pointer control logic to perform cross-clock domain data transmission, Among them, the asynchronous pointer control logic includes synchronizing the first write pointer, the first read pointer, the second write pointer, and the second read pointer in different clock domains through a multi-stage trigger, and the synchronous pointer control logic includes obtaining the phase relationship and performing data transmission across clock domains based on the phase relationship.

16. An electronic device, comprising: A memory non-transitorily stores computer executable instructions; a processor configured to execute the computer executable instructions, Wherein, when the computer executable instructions are executed by the processor, the method for data transmission across clock domains according to any one of claims 12-15 is implemented.

17. A non-transitory computer-readable storage medium, wherein: The non-transitory computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the method for data transmission across clock domains according to any one of claims 12 to 15 is implemented.

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