Processing equipment and processing method

Abstract

The invention provides a processing device and a processing method, and the processing device is provided with a frequency modulation processing part connected with a system clock part, and obtains the system clock frequency of the operation of the processing device and the execution information of a to-be-executed instruction, and the execution information can represent the working data of the processing device executing the corresponding to-be-executed instruction. According to the technical scheme, when it is determined that the system clock frequency and the execution information of the to-be-executed target instruction meet the preset frequency modulation condition, the currently output system clock frequency can be gradually adjusted to the target working frequency according to the corresponding frequency modulation mode, so that the processing equipment operates at the target working frequency to execute the corresponding to-be-executed target instruction.

Description

Technical Field

[0001] The present application mainly relates to the field of computer applications, and more specifically to a processing device and a processing method. Background Art

[0002] In actual applications of processing devices such as processors, current surges may occur when their loads change. This is a violent pulse generated in a very short time, which causes a sudden drop in the voltage of the processing device and affects its circuit function.

[0003] In this regard, one or more combinations of increasing the circuit voltage of the processing equipment, reducing the circuit transmission impedance, etc. are proposed to solve the above problems, but this requires adding high-cost devices to achieve this, thereby increasing the hardware cost of the processing equipment and may also reduce processing performance and reliability. Summary of the invention

[0004] In order to solve the above problems, this application provides the following technical solutions:

[0005] The present application proposes a processing device, the processing device comprising: a system clock component and a frequency modulation processing component, wherein:

[0006] The system clock component is used to sample the clock signal and output the system clock frequency of the processing device;

[0007] The frequency modulation processing component is connected to the system clock component, and is used to obtain the system clock frequency and the execution information of the instruction to be executed, determine that the system clock frequency and the execution information of the target instruction to be executed meet the preset frequency modulation condition, and gradually adjust the system clock frequency to the target operating frequency output according to the corresponding frequency modulation mode, so that the processing device runs at the target operating frequency and executes the corresponding target instruction to be executed;

[0008] The execution information can represent the working data of the processing device executing the corresponding instruction to be executed, and the target instruction to be executed is at least one instruction to be executed;

[0009] In different frequency modulation modes, the change process of the output operating frequency from the clock frequency to the target operating frequency is different.

[0010] Optionally, the instruction to be executed is read by a control component of the processing device and executed by a corresponding execution component in the processing device, and the system clock frequency of the processing device and the execution information of the instruction to be executed are stored in a storage component of the processing device;

[0011] The frequency modulation processing component includes: a frequency regulator and a performance monitor, wherein:

[0012] The performance monitor is connected to the frequency regulator and the storage component respectively, and is used to obtain the system clock frequency and the execution information of each of the to-be-executed instructions stored in the storage component, determine whether the system clock frequency and the execution information of the to-be-executed target instructions meet the preset frequency modulation condition, and send a corresponding frequency modulation instruction to the frequency regulator;

[0013] The frequency regulator is respectively connected to the control component, the storage component, the execution component and the system clock component, and is used to gradually adjust the system clock frequency output by the system clock component in real time to the target operating frequency output according to the frequency modulation mode corresponding to the frequency modulation instruction.

[0014] Optionally, satisfying the preset frequency modulation condition includes: predicting that the instantaneous change current caused by the processing device running at the system clock frequency switching to execute any one of the target instructions to be executed is greater than a current change threshold;

[0015] The frequency modulation parameters of the frequency regulator in different frequency modulation modes are different, and the frequency modulation parameters include at least one frequency modulation coefficient of the system clock frequency and a corresponding effective frequency modulation duration.

[0016] Optionally, the performance monitor remains powered on and running, and acquires in real time the operating frequency of the processing device and the execution information of each of the stored instructions to be executed;

[0017] The frequency regulator is also used for:

[0018] Receive a frequency modulation end instruction sent by the performance monitor, or determine that the system time exceeds the effective frequency modulation duration in the frequency modulation mode, trigger the frequency regulator to switch from the frequency modulation mode to the non-frequency modulation mode, and output the system clock frequency from the system clock component.

[0019] The present application also proposes a processing method, which comprises:

[0020] Acquire the system clock frequency currently running on the processing device and the execution information of the instruction to be executed; the system clock frequency is obtained by sampling the clock signal, and the execution information can represent the working data of the processing device executing the corresponding instruction to be executed;

[0021] Determine that the system clock frequency and the execution information of the target instruction to be executed meet a preset frequency modulation condition, and gradually adjust the system clock frequency to a target operating frequency according to a corresponding frequency modulation mode; the target instruction to be executed is at least one instruction to be executed, and under different frequency modulation modes, the operating frequency change process output from the system clock frequency to the target operating frequency is different;

[0022] At the target operating frequency, the corresponding target instruction to be executed is executed.

[0023] Optionally, the determining that the system clock frequency and the execution information of the target instruction to be executed meet a preset frequency modulation condition includes:

[0024] Comparing the target operating frequency included in the operating data of the to-be-executed instruction with the system clock frequency to obtain a corresponding comparison result;

[0025] It is determined that the comparison result meets a preset frequency modulation condition, the to-be-executed instruction corresponding to the comparison result is determined as a to-be-executed target instruction, and the processing device is triggered to enter a corresponding frequency modulation mode.

[0026] Optionally, the obtaining execution information of the instruction to be executed includes:

[0027] Acquire execution information of a dynamic voltage and frequency adjustment instruction from a target application; the execution information includes a target operating frequency required for the target application to execute the dynamic voltage and frequency adjustment instruction.

[0028] Optionally, determining that the system clock frequency and the execution information of the target instruction to be executed meet a preset frequency modulation condition includes:

[0029] According to the system clock frequency and the execution information of each of the to-be-executed instructions, predict whether the work change data generated when the corresponding to-be-executed instruction is executed meets a preset frequency modulation condition, and obtain a corresponding prediction result;

[0030] Determine the instruction to be executed corresponding to the prediction result that satisfies the preset frequency modulation condition as the target instruction to be executed;

[0031] The processing device is triggered to enter a corresponding frequency modulation mode based on the system clock frequency and the target operating frequency represented by the execution information of the target instruction to be executed.

[0032] Optionally, the determining that the system clock frequency and the execution information of the target instruction to be executed meet a preset frequency modulation condition includes:

[0033] According to the system clock frequency and the execution information, predicting the instantaneous change current generated when the corresponding instruction to be executed is executed;

[0034] Determining that at least one of the instantaneous change currents is greater than a current change threshold, and determining the corresponding instruction to be executed as a target instruction to be executed;

[0035] Based on a first difference between the system clock frequency and the target operating frequency of the target instruction to be executed, or a second difference between the instantaneous change current and a current change threshold, the processing device is triggered to enter a corresponding frequency modulation mode.

[0036] Optionally, gradually adjusting the system clock frequency to a target operating frequency according to a corresponding frequency modulation mode includes:

[0037] According to at least one frequency modulation coefficient in the frequency modulation mode, within a corresponding effective frequency modulation duration, the system clock frequency is reduced to gradually adjust the currently running system clock frequency to a target operating frequency;

[0038] The frequency modulation coefficient includes a frequency division coefficient of a frequency divider in the processing device, and the smaller the frequency division coefficient is, the smaller the operating frequency output by the frequency divider is. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0040] Figure 1 This is a schematic structural diagram of an optional embodiment 1 of the processing device proposed in this application;

[0041] Figure 2 This is a schematic diagram of the structure of the optional embodiment 2 of the processing device proposed in this application;

[0042] Figure 3 This is a flow chart of an optional embodiment 1 of the processing method proposed in this application;

[0043] Figure 4 This is a flow chart of an optional second embodiment of the processing method proposed in this application;

[0044] Figure 5 This is a flow chart of optional embodiment 3 of the processing method proposed in this application. DETAILED DESCRIPTION

[0045] Regarding the content described in the background technology section, when the circuit load suddenly increases, a current surge may occur, causing a sudden voltage drop, such as the voltage drop V = L*D i / D t , L is the inductance, D i / D tThe instantaneous change current generated when the load is switched. If the instantaneous change current generated when the circuit load of the processing device is switched is large, a large voltage drop will be generated, which can easily cause circuit failure. In order to solve this problem and ensure the safety of the processing device components, if the circuit is designed to operate at an operating frequency below the maximum frequency, the processing performance needs to be sacrificed; if the system is designed to operate at a higher voltage, this requires sacrificing processing reliability and will also increase power consumption; if the power supply network is strengthened to reduce the circuit transmission impedance, the cost will increase; if the voltage regulator is integrated, the voltage is increased before executing high-power instructions, which requires that the system itself does not have the conditions for high-load execution, and the cost is sacrificed to introduce an on-chip voltage regulator. If the system itself can support high-load operation, it just cannot bear the voltage drop when the load is switched. At other times, the introduced on-chip voltage regulator will not be able to meet the working requirements. In other words, the cost of introducing the on-chip voltage regulator is too high.

[0046] In order to improve the above problem, through the simulation of different load switching of the processing equipment, it is known that the voltage drop peak duration is very short, that is, transient voltage drop. This application hopes to avoid this problem. Combined with the above voltage drop formula, in order to avoid excessive D i / D t The excessive voltage drop can avoid current surge. For this, the power consumption of the processing equipment can be gradually increased, that is, the circuit is slowly started. However, how to make adjustments in a short time (such as the order of magnitude of a dozen system clock cycles) becomes the consideration direction of this application.

[0047] Since the various types of working data in the processing equipment have P = C × F × V 2 In this operation relationship, the voltage V is not adjustable, and the capacitor C is also not easy to adjust in some processing devices, such as ARM processing devices. The power regulation mechanism such as PDP (Parallel Distributed Processing) / MPMM (Maximum Power Mitigation Mechanism) / DT (Scheduling Throttling) is a closed-loop feedback mechanism and cannot be used actively. Therefore, the present application proposes to implement an action on the frequency F, that is, to achieve slow start by reducing the frequency, so as to solve the above problem.

[0048] Among them, in the process of achieving slow start by frequency reduction, the present application needs to be able to quickly identify the scenario requiring slow start at the circuit level without interfering with the normal scheduling of DVFS (Dynamic voltage and frequency scaling) by the operating system and without causing timing violations affecting circuit functions during frequency switching, that is, to start the frequency reduction work in time to effectively solve the transient voltage drop problem caused by load switching.

[0049] Taking the above problems into consideration, the present application proposes to add a small amount of on-chip circuits, that is, to add a frequency modulation processing component connected to the system clock component in the processing device, which has the function of adjusting the system clock frequency output by the system clock component. The frequency modulation processing component can be composed of low-cost devices to reduce hardware costs. Moreover, the present application executes the frequency modulation instruction through hardware to directly adjust the starting frequency of the system clock signal, so as to quickly change the operating frequency of the processing device to meet the processing requirements. Compared with the frequency modulation processing method of the system software, the frequency modulation processing component of the hardware circuit structure proposed in the present application can directly respond to the received instructions without the participation of the system processor CPU, thereby improving the response speed and thus improving the processing efficiency of the processing method proposed in the present application.

[0050] Based on this, the frequency modulation processing component added in the present application can obtain the system clock frequency of the processing device currently running and the execution information corresponding to each instruction to be executed, and determine whether the system clock frequency and the execution information of the instruction to be executed meet the preset frequency modulation conditions. If so, the system clock frequency will be gradually adjusted to the corresponding target operating frequency in a timely manner according to the corresponding frequency modulation mode, so that the processing device runs at the target operating frequency to execute the corresponding target instruction to be executed, while satisfying the normal processing of the target instruction to be executed, and realizing frequency reduction and slow start, and the operating frequency adjustment process will not cause system timing violations to affect the circuit function, effectively avoiding the transient voltage drop problem.

[0051] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0052] It should be noted that in this application, words such as "exemplary", "for example" or "such as" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplarily", "for example" or "such as" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. In other words, the use of words such as "exemplary", "for example" or "such as" is intended to present related concepts in a specific way.

[0053] Reference Figure 1 , which is a schematic diagram of the structure of an optional embodiment 1 of the processing device proposed in this application. The processing device may be a processor, such as a central processing unit CPU or other processor with active D i / D t This application does not limit the product type of processing equipment. This application only takes the CPU processor as an example. Figure 1 As shown, the processing device may include: a system clock component 110 and a frequency modulation processing component 120, wherein:

[0054] The system clock component 110 can be used to sample the clock signal and output the system clock frequency of the processing device so that the components included in the processing device can operate at the received system clock frequency. This application does not limit the value of the system clock frequency and its sampling method.

[0055] Optionally, the system clock component 110 may be a phase-locked loop (PLL), i.e., a negative feedback control system that uses a voltage generated by phase synchronization to tune a voltage-controlled oscillator to generate a target frequency. In the embodiment of the present application, the clock signal output by the timing circuit may be sampled by the phase-locked loop (PLL) to obtain the system clock frequency required for the operation of the processing device. The working principle of the phase-locked loop (PLL) is not described in detail in the present application, and it should be noted that the composition structure of the system clock component 110 includes but is not limited to a phase-locked loop.

[0056] The frequency modulation processing component 120 can be connected to the system clock component 110, and can obtain the system clock frequency of the processing device currently running and the execution information of each instruction to be executed. After determining that the system clock frequency and the execution information of the target instruction to be executed meet the preset frequency modulation conditions, the system constant frequency can be gradually adjusted to the target operating frequency output according to the corresponding frequency modulation mode, so that the processing device runs at the target operating frequency and executes the corresponding target instruction to be executed.

[0057] Among them, since the execution information can represent the working data of the processing device executing the corresponding instruction to be executed, such as one or more of the working current, working voltage, working frequency, and power consumption / power, etc. In practical applications, the instructions to be executed by the processing device can be used to implement different power instructions for various application processing requirements, such as DVFS instructions from upper-level application software, and / or processing instructions for implementing various operations (such as arithmetic operations, logical operations such as AND, OR, and negation, arithmetic and logical shift operations, comparison of numerical values, etc.), etc. This application does not limit the content of the instructions to be executed and the content of the working data required, which can be determined according to the circumstances.

[0058] In this way, the frequency modulation processing component combines the current system clock frequency of the processing device and the working data of each instruction to be executed to predict whether directly switching the system clock frequency to the working frequency of the instruction to be executed meets the preset frequency modulation conditions, such as predicting whether sending the instruction to be executed to the corresponding execution component will cause unacceptable D under the current system clock frequency. i / D t, that is, predicting whether a current surge phenomenon will occur. If the preset frequency modulation condition is met, that is, it is predicted that a current surge phenomenon will occur, the adjustment processing component 120 will switch to the corresponding frequency modulation mode in time, and gradually adjust the current system clock frequency to the target operating frequency, so that the processing device runs at the target operating frequency and switches to execute the corresponding target instructions to be executed. While meeting the corresponding processing requirements, it avoids directly adjusting the system clock frequency to the corresponding target operating frequency, causing transient voltage drops and damaging components in the processing device, thereby ensuring the working reliability and safety of the processing device.

[0059] It should be noted that the frequency modulation processing component added to the processing device of the present application can have multiple frequency modulation modes, such as reducing the received system clock frequency to different degrees, outputting frequency modulation gears of corresponding working frequencies, etc. In this way, in different frequency modulation modes, the working frequency output by the frequency modulation processing component 120 changes from the current system clock frequency to the target working frequency in different processes. The present application can consider the differences in working data required or generated by different target instructions to be executed, and determine to enter a frequency modulation mode that is compatible with the current prediction result from the multiple frequency modulation modes of the frequency modulation processing mode to solve the transient voltage drop problem. The present application does not limit the control implementation method of each frequency modulation mode, which can be determined according to the situation.

[0060] It can be seen that the frequency modulation processing component 120 can combine the current frequency state of the processing device and the working data required by the instruction to be executed to predict in advance whether the execution of the instruction to be executed meets the preset frequency modulation condition, that is, to pre-identify whether the execution scenario of each instruction to be executed is a scenario that requires frequency reduction and slow start. If so, the system clock frequency sampled by the system clock component 110 is gradually adjusted to gradually switch the currently running system clock frequency to the target working frequency, so that when switching to execute the corresponding target instruction to be executed (that is, the instruction to be executed corresponding to the preset frequency modulation condition), it is not directly switched from the currently running system clock frequency to the target working frequency, but is switched from a certain working frequency in the adjustment process to the target working frequency. In this way, the D generated by the instruction switching, that is, the load switching, is i / D t It will not cause excessive instantaneous voltage drop, which effectively solves the voltage drop problem. In addition, the processing process does not need to change the system clock signal, nor will it hinder the normal scheduling of the instructions to be executed, thereby ensuring the normal processing work of the processing equipment.

[0061] In the practical application of the present application, combined with the above description of the working content of the frequency modulation processing component 120, as shown in FIG. Figure 2As shown, the above-mentioned instructions to be executed can be read by the control component 130 in the processing device, and at least one instruction to be executed each time is written into the storage component 140 for storage. For each stored instruction to be executed, it can be sent to the corresponding execution component 150 in the processing device for execution according to the processing requirements of the processing device. In the process of operation of the processing device, in order to avoid excessive transient voltage drop caused by load switching, i.e. switching to execute the instructions to be executed, the control component 130 can obtain the current system clock frequency and the execution information of each instruction to be executed, and write it into the storage component 140 for storage. The implementation process is not described in detail in this application.

[0062] In some embodiments, for each instruction to be executed that is read, an instruction queue can be used for caching, but it is not limited to this caching implementation method. Each time a plurality of instructions to be cached can be read, and they are written into the instruction queue for caching. For each instruction to be executed, execution information that can guarantee the working data when it is executed is obtained in advance, and the execution information and the current working frequency of the processing device are written into the storage component for storage, so that the frequency modulation processing device 120 can monitor whether to enter the frequency modulation mode accordingly.

[0063] Optionally, the control component 130 may be one or more controllers, i.e., a component that controls the various components of the computer where the processing device is located to coordinate their work according to the functional requirements of the instruction, and may generate corresponding types of operation control signals based on the read opcodes and timing signals of the instructions to be executed, so as to correctly establish a data path and complete the control of fetching and executing instructions.

[0064] The storage unit 140 may include multiple registers or other types of memory to achieve the storage of the above different contents so that they can be quickly executed later to improve processing efficiency. The present application does not limit the type of storage unit used to store contents such as instructions to be executed and their execution information, current working state information of the processing device (such as the current operating frequency, etc.), and operands of instructions, etc., which can be determined according to the circumstances.

[0065] The execution unit 150 for executing the above-mentioned instructions to be executed may include an operator, that is, a component in a computer that performs various arithmetic and logical operations to complete the processing of various data. The working process of the operator is not described in detail in this application. It should be noted that other types of execution units can also be used according to the processing requirements of the instructions to be executed. This application does not limit the component types and working principles of the control unit 130, storage unit 140 and execution unit 150 in the processing device.

[0066] In some embodiments, the frequency modulation processing component 120 may include: a frequency regulator 121 connected to the control component 130, the storage component 140, the execution component 150 and the system clock component 110 respectively, and a performance monitor 122 connected to the frequency regulator 121 and the storage component 140 respectively, wherein:

[0067] The performance monitor 122 can be used to obtain the system clock frequency and execution information of each instruction to be executed stored in the storage component 140, and determine whether the system clock frequency and the execution information of the target instruction to be executed meet the preset frequency modulation conditions, that is, directly switch to execute the target instruction to be executed according to the current frequency state, and predict that a large instantaneous voltage drop will occur. The corresponding frequency modulation instruction can be sent to the frequency regulator 121 to promptly trigger the frequency regulator 121 to perform the corresponding frequency modulation mode.

[0068] The frequency regulator 121 can be used to gradually adjust the system clock frequency output in real time by the system clock component 110 to the target operating frequency output according to the frequency modulation mode corresponding to the frequency modulation instruction after receiving the frequency modulation instruction, and transmit the target operating frequency to other components connected to the frequency regulator 121, so that the control component 130 can send the corresponding target instruction to be executed stored in the storage component 140 to the corresponding execution component 150 for execution, that is, when switching to the target instruction to be executed, it is gradually adjusted from the current running system clock frequency (that is, the operating frequency when predicting whether it meets the preset frequency modulation condition) to the target operating frequency, rather than directly switching from the system clock frequency to the target operating frequency, so as to ensure that the processing method of gradually adjusting the operating frequency proposed in the present application does not cause D caused by switching the high-power target instruction to be executed. i / D t Will not cause excessive instantaneous pressure drop.

[0069] In the practical application of the present application, combined with the above description of the current surge phenomenon, the preset frequency modulation condition described in the context embodiment may include: predicting the instantaneous change current (such as the above D i / D t ) is greater than the current change threshold (which can be determined by determining the working data that produces the current surge phenomenon through experiments or simulations on the processing equipment, and this application does not impose any limitation on its value).

[0070] Based on this, the performance monitor 122 can predict in real time or periodically the instantaneous change current caused by the processing device running at the system clock frequency switching to execute each instruction to be executed, and determine whether at least one instantaneous change current is greater than the current change threshold. If so, it is determined that the prediction result of the corresponding instruction to be executed meets the preset frequency modulation condition, and the corresponding instruction to be executed can be determined as the target instruction to be executed. Combined with the prediction result, the corresponding frequency modulation instruction is generated, that is, the adjustment instruction that triggers the frequency regulator 121 to enter the corresponding frequency modulation mode. For different frequency modulation modes, the frequency modulation instructions generated at this time can be different, and this application does not limit the content of the frequency modulation instructions.

[0071] Among them, the multiple frequency modulation modes of the frequency regulator 121 can have different frequency modulation parameters, that is, the frequency modulation parameters of the frequency regulator in different frequency modulation modes are different, so that after the frequency regulator 121 enters the frequency modulation mode corresponding to the received frequency modulation instruction, it can gradually adjust the system clock frequency received from the system clock component 110 according to the corresponding frequency modulation parameters, so that the output adjusted operating frequency gradually changes to the required target operating frequency. This application does not limit the content of the frequency modulation parameters.

[0072] In actual applications, during the working frequency adjustment process described above, the performance of the processing equipment will be lost to a certain extent. In order to avoid excessive performance loss, it is necessary to restore the frequency required by the system in a timely manner. The processing method executed by the designed processing equipment can be simulated, and the execution time of different frequency modulation modes triggered in different processing scenarios can be determined based on the simulation results, that is, the effective frequency modulation time. This application does not limit the value of the effective frequency modulation time under different frequency modulation modes, which can be determined according to the situation.

[0073] Among them, for multiple frequency modulation modes of the frequency regulator 121, that is, different frequency modulation gears, when the input system clock frequency is the same, the frequency regulator 121 with different frequency modulation gears can output different operating frequencies. These multiple frequency modulation modes can be divided according to their frequency modulation ranges or according to the above simulation results. This application does not limit the frequency modulation granularity of different frequency modulation modes for the same system clock frequency, which can be achieved by configuring the frequency modulation coefficients corresponding to different frequency modulation modes.

[0074] Therefore, the frequency modulation parameters under different frequency modulation modes may include: at least one frequency modulation coefficient for the system clock frequency and its corresponding effective frequency modulation duration, etc. In any frequency modulation mode, the effective frequency modulation duration of each frequency modulation system executed may be different, or partially the same, etc. The present application does not limit the frequency modulation coefficients and their corresponding effective frequency modulation durations, which may be determined according to the circumstances. Optionally, if the frequency regulator 121 is a frequency divider, its frequency modulation coefficients under different frequency modulation modes may be frequency division coefficients, which are used to reduce the frequency of the received system clock frequency, and gradually adjust to the desired target operating frequency by executing different frequency division coefficients. Among them, as the frequency division coefficient executed by the frequency divider is smaller, the output operating frequency after adjustment is smaller, and the present application does not elaborate on the working principle of the frequency divider.

[0075] In the embodiment of the present application, when the frequency regulator 121 enters any frequency modulation mode, in order to avoid directly switching the currently running system clock frequency to the target operating frequency, causing excessive instantaneous voltage drop, the frequency modulation coefficients of the corresponding order can be executed in sequence according to the order of multiple frequency modulation coefficients in the frequency modulation mode, and each frequency modulation coefficient executes the corresponding effective frequency modulation duration. When its execution duration reaches the effective frequency modulation duration, it automatically switches to the frequency modulation coefficient of the next order and executes the corresponding effective frequency modulation duration, etc., until all frequency modulation coefficients in the frequency modulation mode are executed. The process of switching the output operating frequency based on different frequency modulation coefficients realizes the process of gradually adjusting from the currently running system clock frequency to the target operating frequency, avoiding excessive voltage drop.

[0076] In some other embodiments proposed in the present application, in order to achieve a gradual adjustment from the currently running system clock frequency to the target operating frequency, if a frequency modulation mode corresponds to a frequency modulation coefficient, the frequency modulation instruction generated by the performance monitor 122 can be an instruction to trigger the frequency adjuster 121 to enter multiple frequency modulation modes in sequence, and the triggering order of these multiple frequency modulation modes can be determined according to the order of the corresponding frequency modulation coefficients and the size relationship between the target operating frequency and the system clock frequency.

[0077] In this way, during the frequency modulation process of the processing device for any target instruction to be executed, the frequency regulator 121 can be controlled to trigger the frequency regulator 121 in sequence according to the triggering order of multiple frequency modulation modes corresponding to the received frequency modulation instruction and their effective frequency modulation duration, and enter the corresponding frequency modulation mode, and adjust the received system constant frequency within the corresponding effective frequency modulation duration according to the frequency modulation coefficient under the frequency modulation mode, and output the adjusted operating frequency until the frequency modulation processing under the last frequency modulation mode is completed and the target operating frequency is output.

[0078] Of course, in some embodiments, the performance monitor 122 determines that any target instruction to be executed satisfies the preset frequency modulation condition. After determining the multiple frequency modulation modes that the frequency regulator 121 needs to enter, the performance monitor 122 can generate frequency modulation instructions for triggering the frequency modulation modes of the corresponding order in sequence according to the triggering order of the multiple frequency modulation modes, and send the frequency modulation instructions to the frequency regulator 121 to trigger the frequency regulator 121 to enter the corresponding frequency modulation mode. At the same time, the performance monitor 122 can also record the execution time of each frequency modulation instruction, such as starting from the generation time. After determining that the execution time reaches the corresponding effective frequency modulation time, a frequency modulation instruction for triggering the next frequency modulation mode can be generated, and the frequency regulator 121 can continue to be controlled to adjust the current system clock frequency accordingly, so that the system clock frequency of the processing device currently running is gradually adjusted to the target operating frequency.

[0079] Optionally, the performance monitor 122 may also send frequency modulation instructions corresponding to different adjustment modes to the frequency regulator 121, and the frequency regulator 121 may gradually adjust the clock frequency of the currently running system to the target operating frequency according to the execution order of different adjustment systems in each frequency modulation instruction and the effective frequency modulation duration. The implementation process is not described in detail in this application.

[0080] It should be noted that, in the implementation process of how the frequency regulator 121 and the performance monitor 122 gradually adjust the currently running system clock frequency to the target operating frequency, the present application controls the frequency regulator 121 to enter different frequency modulation modes, and follows the corresponding frequency modulation parameters under the frequency modulation mode, that is, there is no restriction on at least one frequency modulation coefficient of the system clock frequency and the corresponding effective frequency modulation duration, including but not embodied in the implementation method described above.

[0081] For example, if the instruction to be executed is a DVFS instruction, i.e., a dynamic voltage and frequency adjustment instruction, from a target application, its execution information may include the values ​​to which the DVFS instruction needs to adjust the operating data of the processing device, such as the operating voltage and operating frequency, which are currently running, i.e., the target operating data, such as the target operating voltage and the target operating frequency, thereby determining the state in which the processing device needs to be adjusted to operate.

[0082] According to the method described above, if the current system frequency is always 1GHz, and the target operating frequency of the DVFS instruction is 3GHz, the instantaneous change current generated by directly executing the DVFS instruction from the current 1GHz to 3GHz will be greater than the current change threshold, and a current surge will occur, which will cause excessive voltage drop. In order to avoid this problem, the present application can adjust the current 1GHz to 2GHz first, and then further adjust from 2GHz to 3GHz according to the method described above, but it is not limited to this adjustment change process.

[0083] Optionally, in combination with the above example content, the above performance monitor 122 may include a signal comparator, which may include a first input port, a second input port, a comparison circuit, and an output port. The first input port and the second input port may be connected to the storage component 140, and are used to respectively receive the system clock frequency of the current operation of the storage processing device and the target operating frequency of any instruction to be executed from the storage component 140, so as to compare the system clock frequency and the target operating frequency through the comparison circuit connected to the first input port and the second input port, and determine based on the comparison result that the preset frequency modulation condition is met, and output a frequency modulation instruction for triggering the frequency regulator 121 to enter the corresponding frequency modulation mode, and send the frequency modulation instruction to the frequency regulator 121 through the connected output port, so that the frequency regulator 121 performs frequency modulation according to the method described in the context, and the implementation process is not described in detail in this application.

[0084] It should be noted that the circuit composition structure of the above-mentioned performance monitor 122 includes but is not limited to the signal comparator described above. The corresponding circuit structure can be determined in combination with the prediction principle for determining whether the preset frequency modulation conditions are met. This application does not give detailed examples one by one.

[0085] Optionally, the performance monitor 122 may also include a searcher connected to the storage component 140 and the above-mentioned signal comparator, for searching the execution information of each instruction to be executed stored in the storage component 140, so as to determine whether there is a target instruction to be executed that meets the preset frequency modulation condition according to the method described in the context, and if so, the target operating frequency of the target instruction to be executed and the system clock frequency of the processing device currently running are sent to the signal comparator for processing. Of course, the searcher can also directly generate the corresponding frequency modulation instruction and send it to the frequency regulator 121 for frequency modulation processing. The frequency modulation implementation process can refer to the description of the corresponding part of the context embodiment, and this application will not repeat it.

[0086] Based on this, in an optional example, the searcher can search the instructions to be executed in the instruction queue to predict whether there are target instructions to be executed that meet the preset frequency modulation conditions, that is, whether the instantaneous change current generated by switching the current system clock frequency to the target operating frequency corresponding to the instruction to be executed is greater than the current threshold, that is, whether the current surge phenomenon will cause excessive voltage drop. If the prediction result of one or more instructions to be executed is yes, in order to avoid the voltage drop, the system clock frequency can be gradually adjusted according to the method described in the context.

[0087] For example, if the system frequency currently running is always 1 GHz, according to the prediction method described in the context, it is predicted that there will be no current surge when switching to each instruction to be executed in the instruction queue, and there is no need to perform frequency modulation, such as controlling the division coefficient of the divider to be 1; if the system frequency currently running is always 3 GHz, according to the prediction method described in the context, it is predicted that there will be a current surge when switching to a certain instruction to be executed in the instruction queue, and the instruction to be executed is determined as the target instruction to be executed. In order to avoid excessive voltage drop, the frequency reduction processing method described in the context can be used to reduce the frequency from 3 GHz to 2 GHz (a division coefficient of 2 / 3), and then reduce the frequency to 1 GHz (a division coefficient of 1 / 3), and then switch to execute the target instruction to be executed, but it is not limited to the frequency modulation implementation method described in this embodiment.

[0088] Based on the processing device described in the above embodiment, the above-mentioned performance monitor 122 can maintain a powered-on running state, and obtain the operating frequency of the processing device and the execution information of each stored instruction to be executed in real time, so that it can be combined with the method described above to determine in real time whether the preset frequency modulation conditions are met, so that the frequency modulation slow start process can be entered in time when necessary. The implementation process is not described in detail in this application. Optionally, the performance monitor 122 can be connected to the auxiliary power supply of the computer where the processing device is located. No matter what state the computer and the processing device are in, the auxiliary power supply always supplies power to the performance monitor 122 to ensure that the performance monitor 122 is always in a working state. This application does not limit the working principle of the auxiliary power supply.

[0089] Based on the above analysis, the above-mentioned frequency regulator 121 can also be used to receive the frequency modulation end instruction sent by the performance monitor 122, or determine that the system time exceeds the effective frequency modulation time in the frequency modulation mode, triggering the frequency regulator 121 to switch from the frequency modulation mode to the non-frequency modulation mode, and output the system clock frequency from the system clock component, that is, to restore the required frequency in time to avoid excessive performance loss.

[0090] The frequency modulation end instruction may be generated when it is determined that the preset frequency modulation condition is not met according to the processing method described above, or when the statistical system time exceeds the effective frequency modulation duration in the frequency modulation mode (such as a frequency modulation mode including multiple frequency modulation coefficients, or a frequency modulation mode that can be switched to the last one among multiple frequency modulation modes with different frequency modulation coefficients, etc.). Of course, as analyzed above, when it is determined that the execution duration of the frequency modulation mode, that is, the statistical system time, exceeds the corresponding effective frequency modulation duration, it is directly switched to the non-frequency modulation mode, and the system clock frequency from the system clock component is directly output as the current working frequency.

[0091] As for the components of the frequency modulation processing component described in the above embodiment, ordinary devices can be used to implement the processing method proposed in the present application, without introducing high-cost devices such as voltage regulators. In addition, the present application reads the current working status of the processing device (such as the currently executed system clock frequency mentioned above) and the target working frequency required for the execution of the instruction to be executed through the introduced hardware, and processes them through hardware circuits such as the above-mentioned comparator, and sends frequency modulation instructions to the divider in a timely and accurate manner, so that the divider directly divides the input system clock frequency to quickly implement frequency modulation. In this way, frequency modulation is performed once every one or fewer system clock cycles, and the current system clock frequency of other components of the frequency processing component to the processing device can be sent to gradually adjust to the target working frequency, that is, frequency slow start can be implemented, and the target working frequency can be achieved within a very short time (such as a dozen system clock cycles) through two or three times or other reduced times of frequency modulation, thereby avoiding the rapid voltage drop in the frequency modulation process of the processing device and causing circuit failure.

[0092] In combination with the composition structure of the processing device described in the above embodiments, the implementation process of the processing method proposed in this application will be described below, but it is not limited to the execution steps and their order of the embodiments described below, and can be adaptively adjusted according to actual conditions.

[0093] Reference Figure 3 , which is a flow chart of an optional embodiment 1 of the processing method proposed in this application, the method can be applied to a processing device, the composition structure of the processing device can refer to but is not limited to the description of the above processing device embodiment, such as Figure 3 As shown, the processing method may include:

[0094] Step S31, obtaining the system clock frequency of the processing device currently running and the execution information of the instruction to be executed;

[0095] Combined with the above description of the composition structure of the processing device and its working principle, the above-mentioned system clock frequency can be obtained by the system clock component through sampling the input clock signal. It can be seen that the size of the system clock frequency depends on the sampling frequency of the system clock component. This application does not limit its value, which can be determined according to processing requirements.

[0096] In practical applications, in order to improve processing efficiency, the processing device can read at least one instruction to be executed, write it into the instruction queue for caching, and wait for the processing demand to be directly sent from the instruction queue to the corresponding execution component for execution. The implementation process is not described in detail in this application. In the embodiment of the present application, for each cached instruction to be executed, in order to accurately and timely predict whether a current surge phenomenon will occur during its execution, the execution information of each instruction to be executed can be obtained in time, that is, the working data that can characterize the execution of the corresponding instruction to be executed by the processing device. This application does not limit the content of the working data, which can be determined according to the circumstances.

[0097] Step S32, determining that the system clock frequency and the execution information of the target instruction to be executed meet the preset frequency modulation condition, and gradually adjusting the system clock frequency to the target operating frequency according to the corresponding frequency modulation mode; the target instruction to be executed is at least one instruction to be executed;

[0098] Combined with the description of the corresponding part of the context embodiment, in the implementation process of step S32, it is possible to predict whether a current surge phenomenon will occur when switching from the currently running system clock frequency to each cached instruction to be executed, and the prediction implementation process is not limited in this application. For a certain instruction to be executed, it is predicted that a current surge phenomenon will occur when switching execution, and the instruction to be executed is determined as a target instruction to be executed. The frequency modulation mode to be entered can be determined in combination with the required working data and the current system clock frequency of the processing device. After that, the current system clock frequency can be gradually adjusted to the target working frequency according to the corresponding frequency modulation mode. The implementation process is not described in detail in this application.

[0099] In the embodiment of the present application, in different frequency modulation modes, the process of changing the output operating frequency from the system clock frequency to the target operating frequency is different, that is, the system clock frequency output by the system clock component is adjusted to the value of the operating frequency and the adjustment amount in sequence without limitation, which can be determined according to the situation. As described in the corresponding part of the above embodiment, the frequency regulator 121 can be controlled to enter a corresponding frequency modulation mode, and the corresponding frequency modulation parameters are executed in sequence to adjust the received system clock frequency so that the output adjusted operating frequency gradually changes from the current running system clock frequency to the target operating frequency. The adjustment implementation process is not described in detail in this application.

[0100] Step S33, executing the corresponding target instruction to be executed at the target operating frequency.

[0101] As described above for the processing device, after the frequency modulation processing component gradually adjusts its output operating frequency to the target operating frequency as described above, the target operating frequency can be transmitted to other components connected thereto so that other components operate at the target operating frequency, such as reading instructions to be executed, writing instructions to be executed into the instruction object cache, sending the cached instructions to be executed to the execution component for execution, etc. For different types of target instructions to be executed, the type of execution component and its composition structure are not limited in this application.

[0102] Reference Figure 4 , which is a flow chart of an optional embodiment 2 of the processing method proposed in this application. This embodiment can describe an optional detailed implementation of the processing method proposed above, such as Figure 4 As shown, the processing method may include:

[0103] Step S41, obtaining the system clock frequency of the processing device currently running and the execution information of the instruction to be executed;

[0104] Regarding the implementation process of step S41, reference may be made to the description of the corresponding part of the above embodiment, and this embodiment will not be described in detail here.

[0105] Step S42, comparing the target operating frequency included in the operating data of the instruction to be executed with the system clock frequency to obtain a corresponding comparison result;

[0106] Step S43, determining that the comparison result satisfies the preset frequency modulation condition, determining the to-be-executed instruction corresponding to the comparison result as the to-be-executed target instruction, and triggering the processing device to enter the corresponding frequency modulation mode;

[0107] In an embodiment of the present application, before executing each instruction to be executed, it is first predicted according to the method described above whether a current surge problem will occur when switching to the execution of the instruction to be executed. If so, it is determined that the preset frequency modulation conditions are met. This embodiment does not limit the prediction implementation method.

[0108] Optionally, according to the prediction implementation method described in step S42 above, the difference between the target operating frequency and the system clock frequency can be determined as the comparison result. If the difference is greater than the frequency threshold, it can be determined that the preset frequency modulation condition is met. Otherwise, it means that the preset frequency modulation condition is not met. The target operating frequency can be the operating frequency to which the dynamic voltage frequency adjustment instruction is required to be adjusted.

[0109] It should be noted that the implementation method of step S42 includes but is not limited to this difference comparison method. In addition, based on the comparison result, determining whether the preset frequency modulation condition is met may also include predicting, based on the comparison result, directly switching from the system clock frequency to the target operating frequency, or executing the instruction switch corresponding to the to-be-executed instruction at the currently running system clock frequency, whether the instantaneous change current caused by the execution is greater than the current change threshold, etc., thereby determining whether the preset frequency modulation condition is met. The present application does not impose any restrictions on the implementation method of step S42 and step S43, which may be determined according to the circumstances.

[0110] In some other embodiments, for any instruction to be executed that has been obtained, the power change / power consumption change caused by the processing device switching to the instruction to be executed can also be predicted. Based on the power change, whether a current surge will occur when the instruction to be executed is executed, that is, whether the instantaneous change current caused is greater than the current change threshold. If so, it is determined that the preset frequency modulation condition is met, and the frequency modulation mode for the instruction to be executed can be triggered.

[0111] Step S44, according to at least one frequency modulation coefficient in the frequency modulation mode, within the corresponding effective frequency modulation duration, the system clock frequency is down-converted to gradually adjust the current system clock frequency to the target operating frequency;

[0112] Step S45, executing the corresponding target instruction to be executed at the target operating frequency.

[0113] Combined with the frequency modulation implementation method described in the above embodiment, since the frequency modulation parameters in different frequency modulation modes are different, the frequency modulation parameters include at least one frequency modulation coefficient for the system clock frequency and the corresponding effective frequency modulation duration. In this way, according to the above method, in order to actively avoid excessive instantaneous change current, when predicting that the instantaneous change current caused by the execution of a target instruction to be executed is greater than the current change threshold, the frequency modulation mode to be entered can be determined, and the currently running system clock frequency can be adjusted according to the corresponding adjustment parameters to gradually adjust from the currently running system clock frequency to the target operating frequency, ensuring that there will be no current surge when switching from the previous operating frequency that is directly switched to the target operating frequency to the target operating frequency.

[0114] In practical applications, as analyzed above, the execution order of multiple frequency modulation coefficients under the same frequency modulation mode can be determined based on the size relationship between the target operating frequency required for the target instruction to be executed and the currently running system clock frequency, as well as the adjustment relationship between the frequency modulation coefficient and the system clock frequency. Afterwards, after entering the frequency modulation mode, the multiple frequency modulation coefficients can be executed in sequence according to the execution order, and when the execution time of each frequency modulation coefficient reaches the effective frequency modulation time, it will automatically switch to the frequency modulation coefficient of the next sequence, thereby realizing multiple adjustments to the system clock frequency, gradually adjusting from the currently running operating frequency to the target operating frequency, realizing slow start of frequency modulation, and the frequency modulation process will not affect the sampling of the system clock signal, and the frequency modulation can be terminated in time to reduce the loss of processing performance.

[0115] It should be noted that during the frequency modulation process in the frequency modulation mode, as in the example above, when the target operating frequency is greater than the current operating frequency, the frequency modulation coefficient can also be used to adjust the system clock frequency to gradually increase the current operating frequency to the target operating frequency. The implementation process is not described in detail in this application.

[0116] Optionally, in a scenario where the processing device uses a frequency divider to adjust the system clock frequency, the frequency division coefficients of the frequency divider can be determined as the above-mentioned frequency modulation coefficients. In this way, after the frequency divider enters the frequency modulation mode, the corresponding frequency division coefficient can be selected to divide the system clock frequency from the coefficient clock component (such as a phase-locked loop) to gradually obtain the required target operating frequency, etc.

[0117] Reference Figure 5 , which is a flow chart of an optional embodiment 3 of the processing method proposed in this application. This embodiment can describe another optional detailed implementation of the processing method proposed above, such as Figure 5 As shown, the processing method may include:

[0118] Step S51, obtaining the system clock frequency of the processing device currently running and the execution information of the instruction to be executed;

[0119] In actual applications, in some embodiments, the execution information of the dynamic voltage and frequency adjustment instructions from the target application can be obtained; in other embodiments, the execution information of each operation instruction can also be obtained, such as the execution information of each instruction to be executed cached in the instruction queue as mentioned above. The present application does not limit the type of instructions to be executed and the content of their execution information, which can be determined according to the circumstances.

[0120] As analyzed above, when the processing device is in non-frequency modulation mode, it can run at the system clock frequency, and this application does not limit its value. And according to the system processing requirements, the system clock frequency can be changed by adjusting the sampling parameters such as the sampling frequency of the clock signal, and this application does not limit the implementation process.

[0121] Since the present application needs to predict whether a current surge will occur when the processing device switches the load, i.e., switches the instructions to be executed, if so, the system clock frequency is directly adjusted through the frequency modulation slow start method, so that the current operating frequency of the processing device is gradually adjusted to the target operating frequency, thereby actively avoiding the problem of excessive instantaneous current change caused by switching the corresponding target instructions to be executed, resulting in excessive voltage drop. Therefore, in order to obtain the prediction results of each instruction to be executed in a timely manner, the execution information of each currently existing instruction to be executed can be obtained in real time or periodically.

[0122] It should be understood that as the processing device progresses, some of the currently cached instructions to be executed are executed and new caches of instructions to be executed are read. After obtaining the new instructions to be executed, the present application can obtain the corresponding execution information in a timely manner to obtain the predicted results of the corresponding instructions to be executed according to the method described below.

[0123] Step S52, predicting whether the work change data generated when the corresponding instruction to be executed satisfies the preset frequency modulation condition based on the system clock frequency and the execution information of each instruction to be executed, and obtaining a corresponding prediction result;

[0124] Step S53, determining the corresponding to-be-executed instruction that meets the preset frequency modulation condition as the to-be-executed target instruction;

[0125] In the embodiment of the present application, the working change data may be an instantaneous change current. Therefore, step S52 may include predicting whether the instantaneous change current generated when each instruction to be executed is executed is greater than the current change threshold. If at least one instantaneous change current is greater than the current change threshold, it means that the preset frequency modulation condition is met. The corresponding instruction to be executed may be determined as the target instruction to be executed. At this time, it is necessary to start the frequency modulation slow start processing in time, and gradually adjust the current operating frequency according to the method described below. On the contrary, if each instantaneous change current is less than or equal to the current change threshold, it means that the preset frequency modulation condition is not met, and the current operation state can continue to work without switching to the frequency modulation mode.

[0126] It should be noted that, as analyzed above, during the implementation of the above step S52, the predicted work change data can also be power consumption / power changes, based on which it is determined whether the predicted frequency modulation conditions are met and the corresponding prediction results are obtained. This application does not limit the content of the work change data.

[0127] Step S54, triggering the processing device to enter a corresponding frequency modulation mode based on the system clock frequency and the target operating frequency represented by the execution information of the target instruction to be executed;

[0128] Since different working data are different when different instructions to be executed are executed, the change process of adjusting to the corresponding target working frequency may be different under the currently running system clock frequency, and the required adjustment parameters may be different. In this way, for different target instructions to be executed, the processing device can be triggered to enter different frequency modulation modes. This application does not limit the trigger correspondence between different target instructions to be executed and different frequency modulation modes.

[0129] Among them, in this embodiment, each of the above-mentioned frequency modulation modes can correspond to multiple frequency modulation systems, and different frequency modulation coefficients can correspond to the same or different effective frequency modulation durations. In this way, after determining any target instruction to be executed, it is possible to determine which frequency modulation mode the processing device enters based on the first difference between the system clock frequency and the target operating frequency of the target instruction to be executed, or based on the second difference between the corresponding instantaneous change current and the current change threshold, so as to actively avoid the current surge phenomenon caused by switching to execute the target instruction to be executed. The present application does not limit the implementation method of step S54.

[0130] In other embodiments, if each frequency modulation mode corresponds to a frequency modulation coefficient and a corresponding effective frequency modulation duration, according to the method described above, it is possible to determine multiple frequency modulation modes that need to be triggered for the target instruction to be executed, as well as the triggering order of these multiple frequency modulation modes, and generate corresponding frequency modulation instructions. By responding to the frequency modulation instructions, these multiple frequency modulation modes are sequentially switched for execution to achieve frequency modulation slow start according to the steps described below.

[0131] Step S55, processing the system clock frequency according to the multiple frequency modulation coefficients in the frequency modulation mode within the corresponding effective frequency modulation duration, so as to gradually adjust the current system clock frequency to the target operating frequency;

[0132] In the embodiment of the present application, for the multiple frequency modulation modes of the processing device, as well as the frequency modulation coefficients and effective frequency modulation durations in different frequency modulation modes, the frequency modulation parameters of the different frequency modulation modes can be obtained by simulating the switching control process of various instructions after designing the circuit structure of the processing device as described in the above embodiment. According to the obtained simulation results, the above preset frequency modulation conditions can also be adjusted according to actual needs, and the present application does not limit the simulation implementation method of the processing device.

[0133] It should be noted that, in the process of gradually adjusting the current system clock frequency to the target operating frequency in step S55, when the processing device runs at the operating frequency after each adjustment, that is, the operating frequency between the current system clock frequency and the target operating frequency, can be determined based on the corresponding frequency modulation coefficient, and the instructions to be executed can continue to be executed at the adjusted operating frequency. In other words, in the frequency modulation slow start process proposed in the present application, the normal execution of other instructions to be executed is not affected.

[0134] Step S56, executing the corresponding target instruction to be executed at the target operating frequency;

[0135] As mentioned above, Enxi, in the process of gradually adjusting the operating frequency of the processing equipment, after the operating frequency is obtained after the penultimate adjustment, another adjustment can be performed to directly switch the operating frequency to the target operating frequency, and the corresponding target instruction to be executed can be directly switched to execute. The instantaneous change current caused by the instruction switching will not be greater than the current change threshold, and there will be no current surge phenomenon, that is, it will not cause excessive voltage drop, thereby ensuring the circuit safety of the processing equipment.

[0136] Step S57, determining that the system time exceeds the effective frequency modulation duration in the frequency modulation mode, triggering the processing device to switch from the frequency modulation mode to the non-frequency modulation mode, and executing the current instruction to be executed at the system clock frequency.

[0137] In order to minimize the performance loss of the processing equipment, the above-mentioned frequency modulation slow start processing can be terminated in time and the working frequency required by the processing equipment can be restored in time. Therefore, in the above-mentioned frequency modulation process, the coefficient time of the frequency modulation process, that is, the actual frequency modulation duration, can be counted. When it exceeds the effective frequency modulation duration of the executed frequency modulation mode, the frequency regulator of the processing equipment can be timely controlled to switch from the frequency modulation mode to the non-frequency modulation mode, so that the frequency regulator directly outputs the system clock frequency output from the system clock component, and each component in the processing equipment can be controlled to work under the system clock frequency.

[0138] Optionally, if the above-mentioned frequency regulator is a frequency divider, the frequency modulation coefficient in the above-mentioned frequency modulation mode can be a frequency division coefficient, and the frequency division coefficients in different frequency modulation modes are different, such as 1 / 4, 2 / 4, 3 / 4, etc., and the system clock edge jump frequency is controlled accordingly, and the original system clock frequency is changed. The frequency division process is not described in detail in this application. When switching to non-frequency modulation mode, its frequency division coefficient can be controlled to 1, that is, the input system clock frequency is not divided, so that the processing device runs at the original system clock frequency. It should be noted that for other types of frequency regulators, other processing methods can be used to adjust the system clock frequency, and the implementation process is not described in detail in this application.

[0139] The present application also provides a computer-readable storage medium, on which at least one computer instruction set can be stored. The processing device implements the processing method proposed in the present application by executing the computer instruction. Regarding the implementation process of the processing method, reference can be made to the description of the corresponding part of the method embodiment above, and the present application will not give detailed examples one by one here.

[0140] Finally, it should be noted that, with respect to the above embodiments, unless the context clearly indicates an exception, the words "a", "an", "a kind" and / or "the" do not specifically refer to the singular, but may also include the plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of clearly identified steps and elements, and these steps and elements do not constitute an exclusive list, and the method or device may also include other steps or elements. The elements defined by the sentence "includes a..." do not exclude the existence of other identical elements in the process, method, commodity or device that includes the elements.

[0141] In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0142] The terms such as "first", "second", etc. used in this application are only used for descriptive purposes to distinguish one operation, unit or module from another operation, unit or module, and do not necessarily require or imply any actual relationship or order between these units, operations or modules. They cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include one or more of the features.

[0143] In addition, the various embodiments in this specification are described in a progressive or parallel manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0144] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A processing device, comprising: System clock component and frequency modulation processing component, including: The system clock component is used to sample the clock signal and output the system clock frequency of the processing device; The frequency modulation processing component is connected to the system clock component, and is used to obtain the system clock frequency and the execution information of the instruction to be executed, determine that the system clock frequency and the execution information of the target instruction to be executed meet the preset frequency modulation condition, and gradually adjust the system clock frequency to the target operating frequency output according to the corresponding frequency modulation mode, so that the processing device runs at the target operating frequency and executes the corresponding target instruction to be executed; The execution information can represent the working data of the processing device executing the corresponding instruction to be executed, and the target instruction to be executed is at least one instruction to be executed; In different frequency modulation modes, the change process of the output operating frequency from the clock frequency to the target operating frequency is different.

2. The processing device according to claim 1, wherein the instruction to be executed is read by a control unit of the processing device and executed by a corresponding execution unit in the processing device, and the system clock frequency of the processing device and the execution information of the instruction to be executed are stored in a storage unit of the processing device; The frequency modulation processing component includes: a frequency regulator and a performance monitor, wherein: The performance monitor is connected to the frequency regulator and the storage component respectively, and is used to obtain the system clock frequency and the execution information of each of the to-be-executed instructions stored in the storage component, determine whether the system clock frequency and the execution information of the to-be-executed target instructions meet the preset frequency modulation condition, and send a corresponding frequency modulation instruction to the frequency regulator; The frequency regulator is respectively connected to the control component, the storage component, the execution component and the system clock component, and is used to gradually adjust the system clock frequency output by the system clock component in real time to the target operating frequency output according to the frequency modulation mode corresponding to the frequency modulation instruction.

3. The processing device according to claim 2, wherein satisfying the preset frequency modulation condition comprises: Predicting that the instantaneous change current caused by the processing device running at the system clock frequency switching to execute any one of the target instructions to be executed is greater than a current change threshold; The frequency modulation parameters of the frequency regulator in different frequency modulation modes are different, and the frequency modulation parameters include at least one frequency modulation coefficient of the system clock frequency and a corresponding effective frequency modulation duration.

4. The processing device according to claim 2, wherein the performance monitor is powered on and operates to obtain the operating frequency of the processing device and the execution information of each of the stored instructions to be executed in real time; The frequency regulator is also used for: Receive a frequency modulation end instruction sent by the performance monitor, or determine that the system time exceeds the effective frequency modulation duration in the frequency modulation mode, trigger the frequency regulator to switch from the frequency modulation mode to the non-frequency modulation mode, and output the system clock frequency from the system clock component.

5. A processing method, comprising: Obtain the system clock frequency currently running on the processing device and the execution information of the instructions to be executed; The system clock frequency is obtained by sampling the clock signal, and the execution information can represent the working data of the processing device executing the corresponding instruction to be executed; Determine that the system clock frequency and the execution information of the target instruction to be executed meet a preset frequency modulation condition, and gradually adjust the system clock frequency to a target operating frequency according to a corresponding frequency modulation mode; the target instruction to be executed is at least one instruction to be executed, and under different frequency modulation modes, the operating frequency change process output from the system clock frequency to the target operating frequency is different; At the target operating frequency, the corresponding target instruction to be executed is executed.

6. The processing method according to claim 5, wherein determining that the system clock frequency and the execution information of the target instruction to be executed meet a preset frequency modulation condition comprises: Comparing the target operating frequency included in the operating data of the instruction to be executed with the system clock frequency to obtain a corresponding comparison result; It is determined that the comparison result meets a preset frequency modulation condition, the to-be-executed instruction corresponding to the comparison result is determined as a to-be-executed target instruction, and the processing device is triggered to enter a corresponding frequency modulation mode.

7. The processing method according to claim 6, wherein obtaining execution information of the instruction to be executed comprises: Obtaining execution information of a dynamic voltage and frequency adjustment instruction from a target application; The execution information includes a target operating frequency required by the target application to execute the dynamic voltage and frequency adjustment instruction.

8. The processing method according to claim 5, wherein the system clock frequency and the execution information of the target instruction to be executed satisfy the preset frequency modulation condition, comprising: According to the system clock frequency and the execution information of each of the to-be-executed instructions, predict whether the work change data generated when the corresponding to-be-executed instruction is executed meets a preset frequency modulation condition, and obtain a corresponding prediction result; Determine the instruction to be executed corresponding to the prediction result that satisfies the preset frequency modulation condition as the target instruction to be executed; The processing device is triggered to enter a corresponding frequency modulation mode based on the system clock frequency and the target operating frequency represented by the execution information of the target instruction to be executed.

9. The processing method according to claim 5, wherein determining that the system clock frequency and the execution information of the target instruction to be executed meet a preset frequency modulation condition comprises: According to the system clock frequency and the execution information, predicting the instantaneous change current generated when the corresponding instruction to be executed is executed; Determining that at least one of the instantaneous change currents is greater than a current change threshold, and determining the corresponding instruction to be executed as a target instruction to be executed; Based on a first difference between the system clock frequency and the target operating frequency of the target instruction to be executed, or a second difference between the instantaneous change current and a current change threshold, the processing device is triggered to enter a corresponding frequency modulation mode.

10. The processing method according to any one of claims 5 to 9, wherein gradually adjusting the system clock frequency to a target operating frequency according to a corresponding frequency modulation mode comprises: According to at least one frequency modulation coefficient in the frequency modulation mode, within a corresponding effective frequency modulation duration, the system clock frequency is reduced to gradually adjust the currently running system clock frequency to a target operating frequency; The frequency modulation coefficient includes a frequency division coefficient of a frequency divider in the processing device, and the smaller the frequency division coefficient is, the smaller the operating frequency output by the frequency divider is.

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